November 1983
Revised January 1999
CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiple xer/Dem ultiple xer • Dual 4-Channel Analog
Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
© 1999 Fairchild Semicond uctor Corpor ation DS005662.prf www.fairchild semi.com
CD4051BC • CD4052BC • CD4053BC
Single 8-Channel Analog Multiplexer/Demultiplexer •
Dual 4-Channel Analog Multiplexer/Demultiplexer •
Triple 2-Channel Analog Multiplex er/Demultiplexer
General Descript ion
The CD40 51BC, CD4052BC, and CD 4053BC analog mul-
tiplexers/demultiplexers are digitally controlled analog
switches having low “ON” impedance and very low “OFF”
leakage currents. Control of analog signals up to 15Vp-p
can be achieved by digital signal amplitudes of 3 − 15V. For
example, if VDD = 5V, V SS = 0V and VEE = −5V, an al og s ig-
nals from −5V to +5V c an b e co nt r olled by dig it a l inp u t s of 0
− 5V. The multiplexer circuits dissipate extremely low qui-
escent power over the full VDD−VSS and VDD−VEE supply
voltage ranges, independent of the logic state of the control
signals. When a logical “1” is present at the inhibit input ter-
minal all channels are “OFF”.
CD4051BC is a single 8-channel multiplexer having three
binary contr ol in pu ts. A, B, and C, and an inhib i t inp ut. T he
three binary signals select 1 of 8 channels to be turned
“ON” and connect the input to the output.
CD4052BC is a differential 4-channel multiplexer having
two binary contro l inputs, A and B, and an i nhibit input . The
two binar y input signals select 1 or 4 pairs of channels to
be turned on and connect the differential analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole double-throw configu-
ration.
Features
■Wide range of digital and analog signal levels:
digital 3 – 15V, analog to 15Vp-p
■Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p
signal-input range for VDD − VEE = 15V
■High “OFF” resistance:
channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
■Logic level conversion for digital addressing signals of
3 – 15V (VDD − VSS = 3 – 1 5V) to switch analog si gnals
to 15 Vp-p (VDD − VEE = 15V)
■Matched switch characteristics:
∆RON = 5Ω (typ.) for VDD − VEE = 15V
■Very low quiescent power dissipation under all digital-
control input and supply conditions:
1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V
■Binar y add re ss decod i ng on chip
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix lett er “X” to the order ing code.
Order Number Package Number Package Description
CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide