REVISION - STMicroelectronics

1/4February 2002

1 - DESCRIPTION

This errata sheet describes the functional and electrical problems known in the revision AB of the

ST 10F2 80-AB engi neering sampl es.

The ST10F280-AB engineering samples marked as EAB-xxxx are not completely tested in all electrical

and functional characteristics and should be used for functional ev aluation only.

Test conditions for these engineering samples are:

– TA Room Temperature (25°C)

– Vcc 5.0V ±10%

– Fosc 40MHz, PLL disabled, direct drive (fCPU = 40MHz)

2 - FUNCTIONAL PROBLEMS

The following malfunctions are kn own in this step:

2.1 - PWRDN.1 - Execution of PWRDN Instruction

When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in

SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRD-

CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the

PWRDN instruction is ignored.

However, under the conditions described below, the PWRDN instruction is not ignored, and no further

instr uctions are fetc hed from exter nal memory, i.e. the CPU is in a quasi-idle state.

This problem only occurs in the following situations:

a) The instructions following the PWRDN instruction are located in an external memory, and a multi-

plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used.

b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral

(XRAM,CAN), and the instructions following the PWRDN instruction are located in exter nal memor y.

In t his case, the problem occurs for any bus configuration.

Note: The on-chip peri pherals are st ill working correctly, in particular the Watchdog Timer, if not disabled,

resets the dev ice upon an overf low. Interrupts and PEC transfers, howe ver, cannot be processed. In case

NMI is asser t ed low while the device is in this quasi-idle state, power-down mode is entered.

No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all P2 pins used to ex it from power-down

mode are at inact i ve le v e l (if PWRDCFG = 1): the chip normally enters powerdown mode.

Workaround:

Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN

instruction, otherwise inser t a N OP instruction in front of PWRDN. When a multiplexed bus with memor y

tristate wait state is used, t he PWRDN i nstructi on must be execut ed from internal RAM or XRAM .

ST10F280-AB

16- Bi t MCU wi th 5 12K Byt e FLASH and 18K Byte RAM Memories

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notic e.

ERRATA SHEET

ST10F280-AB

2/4

2.2 - MAC.9 - CoCMP Instruction I nverted Op erands

The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a 40-bit signed

operand from th 40-bit accumulator content (acc - op2\op1), and updates the N, Z and C fl ags in the MSW

been implemented in the Mac Unit. Therefore, the N and C flags are set according to the reverse

operation (Z flag is not affected).

Workaround:

Change interpretation of the N and C flags in the MSW register.

Example:

MO V R12, #07h

MO V R13, #06h

MO V R14, #0

CoLOAD R14, R12 ; Accum ul ator = 70000h

CoCMP R14, R13 ; Compares 70000h to 60000h

Here the content of MSW is 0500h, i.e. C = 1, Z = 0 and N = 1.

To test if the Accumulator was greater t han or equal the c omp ared value, the "normal" test, according t o

the descr i ption in the ST10 Programming Ma nual, would be:

JNB MSW. 10, Greater ; If C flag cleared, then greater than or equal

Wi th the i mplementati on, this test does not provide the ex pected resul t.

To obtain the correct comparison, use instead:

JB MSW.10, Greater ; C flag set: 60000h < 70000h (60000h-70000h implemented)

; i.e. the accumulator is greater than or equal co mpared value

2.3 - MA C.10 - E Flag Ev aluation for CoSHR and C oASHR Instructions when Saturation Mode is Enabled

The Logical and the Arithmet ic Right Shif t ins truc tions (CoS HR/CoASHR) are specifif ed not to be affected

by the saturation mode (MS bit of the MCW register): the shift operation is always made on the 40 bits of

the ac cumulator. The result shifted i n the accumulator i s nev er sat urated. Only when the saturation mode

is enabled, the evaluation of the E Flag (in the MSW register) is erroneous.

Comment to the example:

In the example below (Table 1), t he E F lag is kep t c leared however MAE is used: bi t 0 of MAE has be en

shifted into bit 15 of MAH. The MAE part has been used and it contents significant bits but the E Flag has

not been set .

The content of the flags i s given after t he execution of the instruction.

Workaround:

If the MAE flag is used, the saturation mode must be disabled before running Logical and/or Arihmetic

Right Shift instruction s and re-enable just after.

Table 1 : MA C. 10 Example

MS Bit is Set, Saturation Mode is Enabled Status of Flags After Instruction Execution

Code Accu mulator Value

(Hexa.) SL E SV C Z N Remark

MOV R5, #5555h -- ---- ---- -------

CoLOAD R5, R5 00 5555 5555 000000Right

NOP 00 5555 5555 000000Right

MOV MSW, #007Fh 7F 5555 5555 000000Right

NOP 7F 5555 5555 000000Right

CoSHR #1 3F AAAA AAAA 00*0000*E is wrong

ST10F280-AB

3/4

2.4 - ST_XTIMER.01 - XADCINJ Signal Output Too Short for ADC Channel Injection

The duration of the XADCINJ output lasts two cycles (50ns at 40MHz) but to ensure that a signal

transition is properl y recognized, an e xternal c apture input signal should be held for at least 8 CPU clock

cycles before it changes its level so the duration of the XADCINJ signal is too short.

Workaround:

The falling edge of the XADCINJ signal must be delayed up t o 8 CPU clock cycles.

Histo ry of Fixed Functional Problems of the ST10F280

Summa ry of Rem a i ni n g Functio nal Problems K nown on the ST10F280-AB

Fi gure 1 : XADCINJ Ti ming

Fi gure 2 : External Connection for ADC Channe l Injection

Name Short Description Fixed in Step

ST_XADCMUX.01 Erroneous Conversion Result in Overload Condition AB

Name Short Description

PWRDN.1 Execution of PWRDN Instruction

MAC.9 CoCMP Instruction Inverted Operands

MAC.10 E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled

ST_XTIMER.01 XADCINJ Signal Output Too Short for ADC Channel Injection

XCLK

XADCINJ

4 TCL = 50ns

Input

Latch

XTIMER

Clock

P7.7/CC31

XADCINJ

CAPCOM2 UNIT

Output trigger for ADC

channel injection

Typical value:

R = 10KΩ C = 47pF at 40MHz

ST10F280-AB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

conseque nces of use of such i nformation nor for any infringement of patents or ot her rights of third parties which may result from

its use. No licens e is gra n te d by implication or otherwise under any patent or patent rights of STMicroelectron ics. S pec ific at ions

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems with out expres s written approval of STMicroelec tronics .

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4/4

3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION

DC Parameters

Engineering data are not completly collected yet.

AC Timing s

Engineering data are not completly collected yet.

No t e on On - C hi p Oscillato r

The X TAL2 output is not designed to provide a val id signal when XTAL1 is supplied by an ex ter nal clock

signal. It may happen, if the ex ternal clock signal is not perfe ctly symetr ical and cente red on VDD / 2, that

XTAL2 signal is not equal to XTAL1.

This is due to the design of the oscillator, which ha s a aut o-adaptat ion ga in cont rol de dicat ed to external

crystal.

If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin disconnected to

a ch ieve the lowes t cons u m p t ion of the on -c h ip o s c illator.

4 - ERRATA SHEET V ERSION INFORMATION

This document has been released on the 6th of February 2002. It reflects t he current silicon stat us of the

ST10F280-AB.

F280-AB.REF