BU-61703/61705 SIMPLE SYSTEM RT (SSRT) FEATURES DESCRIPTION * Complete Integrated Remote The BU-61703/5 Simple System RT (SSRT) MIL-STD-1553 terminals provide a complete interface between a simple system and a MIL-STD-1553 bus. These terminals integrate dual transceiver, protocol logic, and a FIFO memory for received messages in a 1.0 inch square ceramic package. The SSRT provides multi-protocol support of MIL-STD-1553A/B, MIL-STD-1760, McAir, and STANAG-3838. The SSRT's transceivers are completely monolithic, require only a +5V supply, and consume low power. There are versions of the simple system RT available with transceivers trimmed for MILSTD-1760 compliance, or compatible to McAir standards. As a means of further reducing power consumption, the SSRT is available in versions with its logic powered by +3.3V, or +5V. The SSRT can operate with a choice of clock frequencies of 10, 12, 16, or 20 MHz. The SSRT is ideal for stores and other simple systems that do not require a microprocessor. To streamline the interface to simple systems, the SSRT Note: Transformers are external. 55 includes an internal 32-word FIFO for received data words. This serves to ensure that only complete, consistent blocks of validated data words are transferred to a system. The SSRT incorporates a built-in selftest (BIT). This BIT, which is processed following power turn-on or after receipt of an Initiate self-test mode command, provides a comprehensive test of the SSRT's encoders, decoders, protocol, transmitter watchdog timer, and protocol. The result of the built-in test may be conveyed to the bus controller by means of the SSRT's Terminal Flag bit and/or its RT BIT word. The SSRT includes an auto-configuration feature. This may be used to enable the SSRT to run (or not run) its BIT at power turn-on, to select between MIL-STD-1553A or -1553B protocol, to transfer received data words to a system either individually or by means of a burst transfer, to implement wraparound for subaddress 30 (per MILSTD-1553B Notice 2), along with options involving the reporting of selftest failures and loopback errors. B-3226 B-3227 TRANSMITTER INHIBIT TX/RX A * 1.0 X 1.0 Inch, 72-pin Package * Choice of 5V or 3.3V Logic Power * Meets 1553A/McAir Response Time Requirements * Internal FIFO for Burst Mode Capability on Receive Data * 16-bit DMA Interface * Auto Configuration Capability * Comprehensive Built-in Self-test * Direct Interface to Simple (Processorless) Systems * Selectable Input Clock: 10, 12, 16, or 20 MHz BUS B TX/RX B D15-D0 DMA HANDSAKE AND TRANDFER CONTROL LOGIC TRANSCEIVER B DTGRT DTACK MSTCLR AUTO_CFG BRO_ENA MEMWR DUAL ENCODER DECODER AND RT STATE LOGIC DMA HANDSAKE CONTROL HS FAIL MEMOE B-3226 B-3227 CONTROL INPUTS SYSTEM DATA DTREQ TX/RX B 55 STANAG-3838 RT, and MIL-STD-1760 Stores Management DATA BUFFERS TRANSCEIVER A TX_INH 55 * Supports MIL-STD-1553A/B Notice 2, TX/RX A BUS A 55 Terminal Including: Dual Low-Power 5V Only Transceiver Complete RT Protocol Logic DATA TRANSFER CONTROL COMMAND ADDRESS BUS L_BRO, T/R, SA4-SA0 WC/MC/CWC4-0 ILLEGAL RTAD4-RTAD0 RT ADDRESS RTADP RT_AD_LAT SRV_RQST SSFLAG BUSY RT WORD INPUTS RT_AD_ERR RTACTIVE INCMD CLK_IN CLOCK FEQUENCEY SELECTION CLK_SEL1 CLK_SEL0 GBR MSG_ERR RTFAIL FIGURE 1. BU-61703/5 BLOCK DIAGRAM (c) 2000 Data Device Corporation RT MESSAGE STATUS TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage ! Logic +5V or +3.3V ! RAM +5V ! Transceiver +5V ! Voltage Input Range for +5V Powered Logic (BU-61705) ! Voltage Input Range for +3.3V Powered Logic (BU-61703) RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage ! Direct Coupled Across 35 , Measured on Bus ! Transformer Coupled Across 70 , Measured on Bus BU-61573(5)XX-XX0 (Note 8) BU-61573(5)XX-XX2 (Note 8, 9,13) Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time BU-61703(5)X3 BU-61703(5)X4 LOGIC VIH All signals except CLK_IN CLK_IN VIL All signals except CLK_IN CLK_IN Schmidt Hysteresis All signals except CLK_IN CLK_IN IIH (Vcc=5.5V, VIN=Vcc) IIH (Vcc=5.5V, VIN=2.7V) IIH (Vcc=3.6V, VIN=Vcc) IIH (Vcc=3.6V, VIH=2.7V) IIL (Vcc=5.5V, VIH=0.4V) IIL (Vcc=3.6V, VIH=0.4V) VOH (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOH=max) VOH (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) VOL (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOL=max) IOL IOH CI (Input Capacitance) CIO (Bi-directional signal input capacitance) MIN TYP MAX TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont'd) UNITS -0.3 -0.3 -0.3 6.0 6.0 7.0 V V V -0.3 6.0 V -0.3 6.0 V 2.5 POWER SUPPLY REQUIREMENTS Voltages/Tolerances ! +5V Logic (BU-61705) (Note 10) ! +3.3V Logic (BU-61703) (Note 10) ! +5V Ch. A, +5, Ch. B (Note 10) Current Drain ! BU-61705XX-XX0 ! +5V (Logic, CH A, CH B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61705XX-XX2 ! +5V (Logic, CH A, CH B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61703XX-XX0 ! +5V (CH A, CH B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! 3.3V (Logic) ! BU-61703XX-XX2 ! +5V (CH A, CH B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! 3.3V (Logic) K 0.200 5 pF 0.860 Vp-p 10 Vpeak 6 7 9 Vp-p 18 20 20 22 27 27 Vp-p Vp-p 10 MVP-P -250 150 250 mVpeak 100 200 150 250 300 300 nsec nsec 2.1 0.8*Vcc 0.4 1.0 -10 -350 -10 -350 -350 -350 PARAMETER POWER DISSIPATION Total Hybrid (Note 11) ! BU-61705XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61705XX-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61703XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-61703XX-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Hottest Die (Note 11) ! BU-6170XXX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle ! BU-6170XXX-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle V V 0.7 0.2*Vcc V V 10 -50 10 -33 -50 -33 V V A A A A A A 2.4 V 2.4 V 0.4 V 0.4 V mA mA pF pF 3.4 -3.4 50 50 2 MIN TYP 4.5 3.0 4.75 5.0 3.3 5.0 MAX UNITS 5.5 3.6 5.5 V V V 160 265 370 580 mA mA mA mA 160 276 392 625 mA mA mA mA 100 205 310 520 40 mA mA mA mA mA 100 216 332 565 40 mA mA mA mA mA 0.88 1.11 1.33 1.79 W W W W 0.88 1.17 1.46 2.05 W W W W 0.69 0.92 1.15 1.60 W W W W 0.69 0.98 1.28 1.86 W W W W 0.28 0.51 0.75 1.22 W W W W 0.28 0.58 0.88 1.48 W W W W NOTES: (Cont'd) TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont'd) PARAMETER CLOCK INPUT Frequency ! Nominal Value * Default * Option * Option * Option ! Long Term Tolerance * 1553A Compliance * 1553B Compliance ! Short Term Tolerance, 1 second * 1553A Compliance * 1553B Compliance ! Duty Cycle 1553 MESSAGE TIMING RT-to-RT Response Timeout (Note 12) RT Response Time (mid-parity to mid-sync) (Note 12) Transmitter Watchdog Timeout THERMAL Thermal Resistance, Junction-to-Case, Hottest Die (JC) Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 sec.) MIN TYP MAX UNITS ground. Transformer must be a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. 16.0 12.0 10.0 20.0 MHz MHz MHz MHz -0.01 -0.10 0.01 0.1 % % 0.001 -0.01 40 0.001 0.01 60 % % % 19.5 s 7 s s 20 150 150 +300 C/W C C C 1.0 X 1.0 X 0.155 (25.4 x 25.4 x 3.94) in. (mm) 0.6 (17) oz (g) 17.5 18.5 4 660.5 -55 -65 (13) MIL-STD-1760 compliant output voltage not available for BU-61703/5X4 versions. Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications: Impedance parameters are specified directly between pins TX/RX A(B) and TX / RX A(B) of the SSRT hybrid. (3) It is assumed that all power and ground inputs to the hybrid are connected. (4) The specifications are applicable for both unpowered and powered conditions. (5) The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz. (6) Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. (7) Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to the pins of the isolation transformer on the stub side (either direct or transformer coupled), and referenced to hybrid MIL-STD-1760 requires an output of 20 Vp-p minimum on the stub connection. (12) Measured from mid-parity crossing of command word to mid-sync crossing of RT's status word. NOTES: (2) (9) (11) Power dissipation specifications assume a transformer coupled configuration, with external dissipation (while transmitting) of 0.14 watts for the active isolation transformer, 0.08 watts for the active bus coupling transformer, 0.45 watts for each of the two bus isolation resistors, and 0.15 watts for each of the two bus termination resistors. Weight Specifications include both transmitter and receiver (tied together internally). An "X" in one or more of the product type fields indicates that the reference is applicable to all available product options. (10) External 10 F tantalum and 0.1 F capacitors to ground should be located as close as possible to Pins 20 and 72, and a 0.1 F capacitor at pin 37. PHYSICAL CHARACTERISTICS Size (1) (8) 3 INTRODUCTION The BU-61703/5 includes a hardwired R.T. address input. This includes 5 address lines, an address parity input, and an address parity error output. The RT address can also be latched by means of a latching input signal. GENERAL The BU-61703/5 Simple System RT (SSRT) is a complete MILSTD-1553 Remote Terminal (RT) bus interface unit. Contained in this hybrid are a dual transceiver and Manchester II encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) protocol logic. Also included are built-in self-test capability and a parallel subsystem interface. The subsystem interface includes a 12bit address bus and a 16-bit data bus that operates in a 16-bit DMA handshake transfer configuration. The local bus and associated control signals may be operated from either +5 volt or +3.3 volt power. The BU-61703/5 supports command illegalization. Commands may be illegalized by asserting the input signal ILLEGAL active low within approximately 2 s after the mid-parity bit zero-crossing of the received command word. Command words may be illegalized as a function of broadcast, T / R bit, subaddress, word count, and/or mode code. An internal Built-in-Test (BIT) Word register is updated at the end of each message. The contents of the BIT Word Register are transmitted in response to a Transmit BIT Word Mode Command. The BU-61703/5 provides a number of real-time output signals. These various signals provide indications of message in progress, valid received message, message error, handshake fail, loop-test fail or transmitter timeout. The transceiver front end of the BU-61703/5 is implemented by means of low-power monolithic technology. The transceiver requires only a single +5 V voltage source. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making the BU-61703/5 suitable for MIL-STD-1760 applications. The BU-61703/5 includes standard DMA handshake signals (Request, Grant, and Acknowledge) as well as transfer control outputs ( MEMOE and MEMWR ). The DMA interface operates in a 16-bit mode, supporting word-wide transfers. The receiver sections of the BU-61703/5 are fully compliant with MIL-STD-1553B in terms of front-end overvoltage protection, threshold, and bit-error rate. The SSRT's system interface allows the BU-61703/5 to be interfaced directly to a simple system that doesn't include a microprocessor. This provides a low-cost 1553 interface for A/D and D/A converters, switch closures, actuators, and other discrete I/O signals. The BU-61703/5 implements all MIL-STD-1553 message formats, including all 13 MIL-STD 1553 dual redundant mode codes. Any subset of the possible 1553 commands (broadcast, T/R bit, subaddress, word count/mode code) may be optionally illegalized by means of an external PROM, PLD, or RAM. An extensive amount of message validation is performed for each message received. Each word received is validated for correct sync type and sync encoding, Manchester II encoding, parity, and bit count. All messages are verified to contain a legal, defined command word and correct word count. If the BU-61703/5 is the receiving RT in an RTto-RT transfer, it verifies that the T/R bit of the transmit command word is logic "1" and that the transmitting RT responds in time and contains the correct RT address in its Status Word. The BU-61703/5 has an internal FIFO for received data words. This 32-word deep FIFO may be used to allow the BU-61703/5 to transfer its data words to the local system in burst mode. Burst mode utilizes the FIFO by transferring data to the local bus at a rate of one data word every three clock cycles. Burst mode negotiates only once for use of the subsystem bus. Negotiation is performed only after all 1553 data words have been received and validated. In non-burst mode, the BU-61703/5 will negotiate for the local bus after every received data word. The data word transfer period is three clock cycles for each received 1553 data word. The BU-61703/5 may also be used in a shared RAM interface configuration. By means of tri-state buffers and a small amount of "glue" logic, the BU-61703/5 will store Command Words and access Data Words to/from dedicated "mailbox" areas in a shared RAM for each broadcast / T/R bit / subaddress / mode code. The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz clock input. For any clock frequency, the decoder samples incoming data on both edges of the clock input. This oversampling, in effect, provides for a sampling rate of twice the input clocks' frequency. Benefits of the higher sampling rate include a wider tolerance for zero-crossing distortion and improved bit error rate performance. 4 ADDRESS MAPPING: DMA READ OPERATION A typical addressing scheme for the BU-61703/5 12-bit address bus could be as follows: In response to a transmit command, the BU-61703/5 needs to read data words from the external subsystem. To initiate a data word read transfer, the SSRT asserts the signal DTREQ low. Assuming that the subsystem asserts DTGRT in time, the SSRT will then assert the appropriate values of L_BRO (logic "0"), T / R (high), SA4-0, and MC/CWC4-0; MEMWR high, along with DTACK low and MEMOE low to enable data to be read from the subsystem. A11: BROADCAST / OWNADDRESS A10: TRANSMIT/ RECEIVE A9-A5: SUBADDRESS 4-0 A4-A0: WORD COUNT/MODE CODE 4-0 After the transfer of each Data Word has been completed, the value of the address bus outputs CWC4 through CWC0 is incremented. This method of address mapping provides for a "mailbox" allocation scheme for the storage of data words. The 12 address outputs may be used to map into 4K words of processor address space. The BU-61703/5's addressing scheme maps messages in terms of broadcast/own address, transmit/receive, subaddress, and word/count mode code. A 32-word message block is allocated for each T/R-subaddress. DMA WRITE OPERATION In response to a receive command, the BU-61703/5 will need to transfer data to the subsystem. There are two options for doing this, the burst mode and the non-burst mode. In burst mode, all received data words are transferred from the SSRT to the subsystem in a contiguous burst, only following the reception of the correct number of valid data words. In the non-burst mode, single data words are written to the external subsystem immediately following the reception of each individual data word. For non-mode code messages, the Data Words to be transmitted or received are accessed from (to) relative locations 0 through 31 within the respective message block. For the MIL-STD-1553B Synchronize with data, Selected transmitter shutdown, Override selected transmitter shutdown, and Transmit vector word mode commands which involve a single data word transfer, the address for the data word is offset from location 0 of the message block for subaddresses 0 and 31 by the value of the mode code field of the received command word. To initiate a DMA write cycle, the SSRT asserts DTREQ low. The subsystem must then respond with DTGRT low. Assuming that DTGRT was asserted in time, the BU-61703/5 will then assert DTACK low. The BU-61703/5 will then assert the appropriate value of L_BRO, T / R , SA4-0, and MC/CWC4-0, MEMOE high, and MEMWR low. MEMWR will be asserted low for one clock cycle. The subsystem may then use either the falling or rising edge of MEMWR to latch the data. Similar to the DMA read operation, the address outputs CWC4 through CWC0 are incremented after the completion of a DMA write operation. The data words transmitted in response to the Transmit last command or Transmit BIT word mode commands are accessed from a pair of internal registers. DMA INTERFACE HANDSHAKE FAIL A 16-bit data bus, a 12-bit address bus, and six control signals are provided to facilitate communication with the parallel subsystem. The data bus D15-D0 consists of bi-directional tri-state signals. The address bus L_BRO, T / R , SA4-SA0, and WC/MC/CWC4-0; along with the data transfer control signals MEMOE and MEMWR are two-state output signals. Following the assertion of DTREQ low by the SSRT, the external subsystem has 10 s to respond by asserting DTACK to logic "0". If the BU-61703/5 (SSRT) asserts DTREQ and the subsystem does not respond with DTGRT in time for the BU-61703/5 to complete a data word transfer, the HSFAIL output will be asserted low to inform the subsystem of the handshake failure, and bit 12 in the internal Built-In-Test (BIT) word will be set to logic "1." If the handshake failure occurs on a data word read transfer (for a transmit command), the SSRT will abort the current message transmission. In the case of a handshake failure on a write transfer (received command) the SSRT will set the handshake failure output and BIT word bit, and abort processing the current message. The control signals include the standard DMA handshake signals DTREQ , DTGRT , DTACK , as well as the transfer control outputs MEMOE and MEMWR . HS _ FAIL provides an indication to the subsystem of a handshake failure condition. Data transfers between the subsystem and the BU-61703/5 are performed by means of a DMA handshake, initiated by the BU-61703/5. A data read operation is defined to be the transfer of data from the subsystem to the BU-61703/5. Conversely, a data write operation transfers data from the BU-61703/5 to the subsystem. Data is transferred as a single 16-bit word 5 MESSAGE PROCESSING OPERATION COMMAND ILLEGALIZATION Following the receipt and transfer of a valid Command Word, the BU-61703/5 will attempt to perform one of the following operations: (1) transfer received 1553 data to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly the last command word or RT BIT word) on the 1553 bus, and/or (4) set status word conditions. The BU-61703/5 includes a provision for command illegalization. If a command is illegalized, the BU-61703/5 will set the Message error bit and transmit its status word to the Bus Controller. No data words will be transmitted in response to an illegalized transmit command. However, data words associated with an illegalized receive command will be written to the external subsystem (although these transfers may be blocked using external logic). The BU-61703/5 responds to all non-broadcast messages to its RT address with a 1553 Status Word. ILLEGAL is sampled approximately 2 s following the mid-parity bit zero crossing of the received command word. A low on ILLEGAL will illegalize a particular command word and cause the SSRT to respond with its Message error bit set in its status word. Command illegalization based on broadcast, T / R bit, subaddress, and/or word count/mode code may be implemented by means of an external PROM, PLD, or RAM device, as shown in FIGURE 2. RT ADDRESS RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity (RT_AD_P) should be programmed for a unique RT address and reflect an odd parity sum. The BU-61703/5 will not respond to any MIL-STD-1553 commands or transfer received data from any nonbroadcast messages if an odd parity sum is not presented by RT_AD_4-0 and RT_AD_P. An address parity error will be indicated by a low output on the RT_AD_ERR pin. The input signal RT_AD_LAT operates a transparent latch for RTAD4-RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch tracks the value presented on the input pins. If RT_AD_LAT is high, the output of the internal latch becomes latched to the values presented at the time of a low-to-high transition of RT_AD_LAT. The external device may be used to define the legality of specific commands. Any subset of the possible 1553 commands may be illegalized as a function of broadcast, T / R bit, subaddress, word count, and/or mode code. The output of the illegalization device should be tied directly to the BU-61703/5's ILLEGAL signal input. The maximum access time of the external illegalizing device is 400 ns. If illegalization is not used, ILLEGAL should be hardwired to logic "1". RT address and RT Address Parity must be presented valid before the mid-parity crossing of the 1553 command and held, at least, until following the first received data word. L-BRO A 11 T/R A 10 SA4 A9 SA3 A8 SA2 A7 SA1 A6 SA0 A5 WC/MC/CWC4 A4 WC/MC/CWC3 A3 WC/MC/CWC2 A2 WC/MC/CWC1 A1 WC/MC/CWC0 A0 PROM / RAM / PLD (4Kx1) (400ns max) BU - 61703 / 5 "SSRT" IL L E G A L FIGURE 2. BU-61703/6 ILLEGALIZATION 6 D0 BUSY In burst mode, a DMA handshake will not be initiated until after all data words have been received over the 1553 data bus and stored into the SSRT's internal FIFO. After the handshake has been negotiated, the SSRT will burst the contents of the FIFO to the local bus (D0-D15). After the reception of a valid non-mode code receive command word followed by the correct number of valid data words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the output Good Block Received ( GBR ). The width of this pulse is two clock cycles. The external subsystem may control the SSRT's Busy RT status word bit by means of the BUSY input signal. The SSRT samples BUSY approximately 2 s following the mid-parity bit zero crossing of the received Command Word. If BUSY is sampled low for a particular message, the value of the busy bit transmitted in the SSRT's status word will be logic "1". If BUSY is sampled high for a particular message, the value of the busy bit transmitted in the SSRT's status word will be logic "0". RT-TO-RT TRANSFER ERRORS If the RT responds to a transmit command with a busy bit of logic "1", the status word will be transmitted, but no data words will be transmitted by the SSRT. If the SSRT responds to a receive command with a busy bit of logic "1", data words will be transferred to the external subsystem (although these may be blocked by means of external logic). For the case where the SSRT is the receiving RT of an RT-to-RT transfer, if the transmitting RT does not respond within the specified time period, the SSRT will determine that a timeout condition has occurred. The value of the SSRT's RT-to-RT timeout timer is in the range from 17.5 to 18.5 s, and is specified from the mid-parity bit crossing of the transmit command word to the mid-sync crossing of the transmitting RT's status word. In the case of an RTto-RT timeout, the SSRT will not respond and the RT-TO-RT NO TRANSFER TIMEOUT bit (bit 2) of the SSRT's BIT Word will be set to logic "1". Similar to ILLEGAL , it is possible to cause the SSRT to respond with Busy for specific command words (only), by means of an external PROM, RAM, or PLD device. TRANSMIT COMMAND (RT-TO-BC TRANSFER) Also, if the SSRT is the receiving RT for an RT-to-RT transfer, and the T / R bit of the second command word is logic "0", or the RT address field for the transmit command is the same as for the receive command, or the subaddress for the transmit command is 00000 or 11111, the BU-61703/5 will not respond, and will set the RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT word to logic "1". If the BU-61703/5 receives a valid Transmit command word that the subsystem determines is legal (input signal ILLEGAL is high) and the subsystem is not BUSY (input signal BUSY is high), the BU-61703/5 will initiate a transmit data response following transmission of its status word. This entails a handshake/read cycle for each data word transmitted, with the number of data words to be transmitted specified by the word count field of the transmit command word. RT STATUS, ERROR HANDLING, AND MESSAGE TIMING SIGNALS If ILLEGAL is sampled low, the Message Error bit will be set in the SSRT's status word. No data words will be transmitted following transmission of the status word to an illegalized transmit command. A low on the BUSY input will set the busy bit in the Status Word; in this instance, only the status word will be transmitted, with no data words. Message transfers and transfer errors are indicated by means of the INCMD , HS _ FAIL , MSG_ ERR , and RTFAIL error indication outputs. Additional error detection and indication mechanisms include updating of the internal command, RT status and BIT word registers. RECEIVE COMMAND (BC-TO-RT TRANSFER) The BU-61703/5 provides a number of timing signals during the processing of 1553 messages. INCMD is asserted low when a new command is received. At the end of a message (either valid or invalid), INCMD transitions from low to high. In non-burst mode, a DMA handshake will be initiated for each data word received from the 1553 data bus. If successful, the respective handshake will be followed by a corresponding write cycle. A handshake timeout will not terminate transfer attempts for the remaining data words, error flagging or Status Word transmission. After the reception of a valid non-mode code receive Command Word followed by the correct number of valid Data Words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the Good Block Received ( GBR ) output. The width of this pulse is two clock cycles. As discussed above, HS _ FAIL will be asserted low if the subsystem fails to respond to DTREQ within the maximum amount of time (10 s). Following the last data word transfer for a valid non-mode code receive message (for either non-burst mode or burst mode), GBR will be asserted low for two clock cycles. 7 PROTOCOL SELF-TEST MSG_ ERR is asserted as a low output level following any detected error in a received message, except for an error in the command word. If an error is detected in a received command word, the rest of the message will be ignored. The SSRT includes a comprehensive, autonomous off-line selftest of its internal protocol logic. The test includes a comprehensive test of all registers, Manchester encoder and decoders, transmitter failsafe timer, protocol logic, and the internal FIFO. If MSG_ ERR and/or HS _ FAIL have been asserted (low), they will be cleared to logic "1" following receipt of a subsequent valid command word. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. LOOPBACK TEST The BU-61703/5 performs a loopback self-test at the end of each non-broadcast message processed. The loopback test consists of the following verifications: (1) The received version of every transmitted word is verified for validity (encoding, bit count, parity) and correct sync type; and (2) The received version of the last transmitted word is verified by means of a bit-by-bit comparison to the transmitted version of this word. If there is a transmitter timeout (660.5 s) and/or if the loopback test fails for one or more transmitted words, the Terminal flag status word bit will be set in response to the next non-broadcast message. Unless disabled by means of the SSRT's Auto-Config feature, the protocol self-test will be performed following the SSRT's power turn-on (i.e., when MSTCLR is released high). If the Auto-Config feature is used and Auto-Config bit 5 is set to logic "0", then a failure of the protocol self-test following power turn-on will result in the SSRT not going online. If bit 5 is set to logic "0" and the protocol self-test passes following power turn-on, the SSRT will go online. The protocol self-test will also be performed following receipt of an Initiate self-test mode command from the 1553 bus. If an Initiate self-test mode command is received by the SSRT, and AutoConfig bit 5 is set to logic "0", then a failure of the protocol self-test following will result in the SSRT going offline. Note that the setting of the Terminal flag status bit following a loop test failure may be disabled by means of the Auto-Config feature; i.e., by setting Auto-Config bit 4 to logic "0". STATUS WORD If the protocol self-test fails: (1) the Terminal Flag bit will be set to logic "1" in the SSRT status word; (2) bit 8 in the SSRT's BIT word, BIT Test Fail, will be set to logic "1"; (3) the SSRT's RTFAIL output will be asserted to logic "0". The Broadcast Command Received bit is formulated internally by the SSRT. The Message Error Status bit will be set if the current command is a Transmit Status Word or Transmit Last Command mode command if there was an error in the data portion of the previous receive message. Message Error will also be set if ILLEGAL has been sampled low by the SSRT for the current message. ILLEGAL , SRV_RQST , BUSY , and SSFLAG (Subsystem Flag) will be sampled from their respective Status input pins approximately 2 s following the mid-parity bit zero crossing of the received Command Word. This time is 400 ns maximum following after the L_BRO, T / R , SA4-0, and WC/MC/CWC4-0 outputs have been presented valid. 8 AUTO-CONFIGURATION TABLE 2. AUTO-CONFIGURATION PARAMETERS BIT The SSRT includes an auto-configuration feature, which allows various optional features to be enabled or disabled. Auto-configuration may be enabled or disabled by means of the input signal AUTO _ CFG. If AUTO _ CFG is connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values. Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, 1553B is the default). If AUTO _ CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 by means of a DMA read data transfer. The transfer occurs during the time that the RTACTIVE and DTACK outputs are logic "0", following MSTCLR transitioning from logic "0" to logic "1" and a successful DT _ REQ -to- DTGRT handshake. FUNCTION 5 RT GOES ONLINE IF SELF-TEST FAILS If logic "0", the RT will become enabled only if the self-test passes. If auto-config is not used, or if this bit is logic "1", or if the power-up self-test passes, then the RT will go online following self-test. 4 RTFAIL-to-TERMINAL FLAG AUTO-WRAP If the loop test fails for a particular message, the Terminal flag bit will be set in the SSRT's status response for the subsequent non-broadcast message. MIL-STD-1553A*/B (-B is logic "1", or the default). In MIL-STD-1553B mode, subaddress 31 is a mode code subaddress, and mode codes are implemented in full accordance with MIL-STD-1553B. In MIL-STD-1553A mode, subaddress 31 is a non-mode code subaddress, and no data words are transmitted or anticipated to be received for mode code messages. SUBADDRESS 30 WRAPAROUND Subaddress 30 wraparound is enabled. That is, the data words for a receive message to subaddress 30 are stored in the internal FIFO, and not transferred to the external system. For a subsequent transmit message to subaddress 30, the transmitted data words are read from the internal FIFO, rather than from the external system. 1 BURST MODE Enables burst mode (using the internal FIFO) for received data words. In burst mode, for a receive message, all data words are transferred to the external system in a contiguous burst following reception of the last data word. 0 POWER-UP SELFTEST ENABLE If enabled, the SSRT will perform selftest following the rising edge of MSTCLR*. 3 Note that if DTGRT is hardwired to logic "0", the handshake process is not necessary (i.e., DTACK and RTACTIVE will both be asserted to logic "0" one clock cycle following DT _ REQ ). Each of the configuration parameters is enabled if the SSRT reads a value of logic "1" for the respective data bit. 2 The auto-configuration parameters are defined by Table 2. The timing signals pertaining to Auto-Configuration mode are illustrated in FIGURE 12. CLOCK INPUT The SSRT may be operated from one of four clock frequencies: 10, 12, 16, or 20 MHz. The selected clock frequency must be designated by means of the input signals CLK_SEL_1 and CLK_SEL_0, as shown in Table 3. TABLE 3. CLOCK FREQUENCY SELECTION CLK_SEL_1 CLK_SEL_0 CLOCK FREQUENCY 0 0 10 MHz 0 1 20 MHz 1 0 12 MHz 1 1 16 MHz 9 DESCRIPTION MID-PARITY MID-PARITY MID-PARITY MID-PARITY MID-SYNC t9 1553 BUS RX COMMAND DATA #1 STATUS DATA #2 t1 L-BRO, T/R, SA4-SA0 t10 t7 WC/MC/CWC WC / MC PREVIOUS MSG CWC = 0 CWC = 1 t8 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY 1F cwc t13 WC / MC VALID t5 INCMD t6 t15 NOTE 1 t2 t14 GBR t11 DTREQ DTGRT DTACK BURST DATA WRITE TRANSFER D15-D0 (Refer to FIGURE 9 on page 22) MEMWR MEMOE t12 RT_FAIL t3 MSG_ERR HS_FAIL RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. FIGURE 3. RT RECEIVE COMMAND (BURST MODE) TIMING 10 TABLE FOR FIGURE 3. RT RECEIVE COMMAND TIMING (BURST MODE) REF DESCRIPTION CLOCK FREQUENCY RESPONSE TIME MIN TYP UNITS MAX t1 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL 1.5 s t2 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t3 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t7 Mid-parity crossing of first data word to WC/CWC valid data of 1Fh ALL t8 Duration of WC/CWC data value of 1Fh ALL t9 RT Response time. ALL t10 CWC transition to next word following mid-parity of subsequent received data words. ALL t11 Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) ALL t12 Mid-Sync crossing of Status response to RT_FAIL rising ALL t13 CWC valid following falling edge of DTREQ ALL t14 GBR pulse width (see Note 1) t15 Mid-parity crossing of status word to INCMD rising 11 400 s 1 200 4 6.5 ns 7 4.5 s s 1 4 ns 5.25 s 30 ns s 1.5 20 MHz 100 ns 16 MHz 125 ns 12 MHz 167 ns 10 MHz 200 ns ALL 3 s MID-PARITY MID-PARITY MID-PARITY MID-PARITY MID-SYNC t11 1553 BUS RX COMMAND DATA #1 STATUS DATA #2 t1 L-BRO, T/R, SA4-SA0 t15 t7 WC/MC/CWC WC / MC PREVIOUS MSG CWC = 0 CWC = 1 WC / MC t9 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY 1F VALID t6 t5 INCMD t17 t10 t2 t12 t14 GBR t8 t13 DTREQ DTGRT DTACK SINGLE WORD WRITE SINGLE WORD WRITE D15-D0 DATA WORD #1 DATA WORD #2 MEMWR (Refer to FIGURE 10 on page 24) MEMOE RT_FAIL t16 t3 MSG_ERR HS_FAIL RT RECEIVE COMMAND (NON-BURST MODE) FIGURE 4. RT RECEIVE COMMAND (NON-BURST MODE) TIMING 12 TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (NON-BURST MODE) REF DESCRIPTION CLOCK FREQUENCY RESPONSE TIME MIN TYP UNITS MAX t1 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL 1.5 s t2 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t3 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD ALL 300 ns t7 Mid-parity crossing to WC/CWC value of 1Fh t8 Mid-parity crossing of first data word to DTREQ falling edge t9 WC/CWC data value of 1Fh held 400 ns ALL 1 s 20 MHz 1.2 s 16 MHz 1.25 s 12 MHz 1.33 s 10 MHz 1.4 s 20 MHz 200 ns 16 MHz 250 ns 12 MHz 333 ns 10 MHz 400 ns t10 CWC valid following falling edge of DTREQ ALL t11 RT Response time. ALL 4 t12 Delay from following mid-parity of last received data word to GBR low. (see Notes 1, 2) ALL 4 t13 Mid-parity crossing of all data words, except first data word, to DTREQ falling edge ALL 1 s t14 GBR pulse width 20 MHz 100 ns 16 MHz 125 ns 12 MHz 167 ns 10 MHz 200 ns 20 MHz 75 ns 16 MHz 94 ns 12 MHz 125 ns 10 MHz 150 ns t15 CWC transition to WC prior to Mid-Sync crossing of Status response. 30 6.5 7 ns s s t16 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 s t17 Mid Parity crossing of status word to INCMD rising ALL 3.0 s Notes: 1. Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT(low) - to - DTGRT(low) delay. 2. The transceiver delays are measured at a range of 150 ns to 450 ns for the receiver and 100 ns to 250 ns for the transmitter. 13 MID-PARITY MID-SYNC MID-SYNC MID-SYNC MID-PARITY t1 1553 BUS TX COMMAND STATUS DATA #1 DATA #2 t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC 1F WC PREVIOUS MSG t14 cwc = 1 WC t11 t5 ILLEGAL, SRV_RQST SSFLAG, BUSY VALID t7 t6 INCMD CWC = 0 t15 t12 t3 GBR DTREQ t13 t9 DTGRT DTACK D15-D0 MEMWR SINGLE WORD READ SINGLE WORD READ MEMOE DATA WORD #1 DATA WORD #2 (Refer to FIGURE 11 on page 26) t10 RT_FAIL MSG_ERR t4 HS_FAIL RT TRANSMIT COMMAND FIGURE 5. RT TRANSMIT COMMAND TIMING 14 TABLE FOR FIGURE 5. RT TRANSMIT COMMAND TIMING REF DESCRIPTION CLOCK FREQUENCY VALUE UNITS MIN TYP MAX 4 6.5 7 s t1 RT Response time. ALL t2 Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid ALL 1.5 s t3 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t4 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh t9 Mid-Sync crossing of status word to DTREQ falling edge t10 Mid-Sync crossing of Status response to RT_FAIL rising (see Note 1) t11 Duration of WC/CWC value of 1Fh t12 CWC valid following falling edge of DTREQ t13 Mid-Sync crossing of received data word to DTREQ falling edge t14 t15 400 ALL 6.5 s 20 MHz 6.75 s 16 MHz 6.81 s 12 MHz 6.92 s 10 MHz 7 s ALL 1.5 s 20 MHz 200 ns 16 MHz 250 ns 12 MHz 333 ns 10 MHz 400 ns ALL Mid-Sync crossing of last received data word for CWC to transition to WC Mid Parity crossing of status word to INCMD rising NOTE1: Assuming that RTFAIL was previously low. 15 ns 30 ns 20 MHz 1.75 s 16 MHz 1.81 s 12 MHz 1.92 s 10 MHz 2 s 20 MHz 1.55 s 16 MHz 1.56 s 12 MHz 1.59 s 10 MHz 1.6 s ALL 3 s MID-SYNC MID-PARITY MID-SYNC MID-SYNC MID-PARITY t1 1553 BUS RX COMMAND TX COMMAND DATA #1 STATUS DATA #2 STATUS t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC 1F WC PREVIOUS MSG WC t11 t5 ILLEGAL, SRV_RQST SSFLAG, BUSY VALID t7 t6 INCMD t14 cwc = 1 CWC = 0 t15 t12 t3 GBR DTREQ t13 t9 DTGRT DTACK D15-D0 MEMWR SINGLE WORD READ SINGLE WORD READ MEMOE DATA WORD #1 DATA WORD #2 t10 RT_FAIL MSG_ERR t4 HS_FAIL RT - RT TRANSMIT COMMAND FIGURE 6. RT - RT TRANSMIT TIMING 16 (Refer to FIGURE 11 on page 26) TABLE FOR FIGURE 6. RT-RT TRANSMIT COMMAND TIMING REF DESCRIPTION CLOCK FREQUENCY MIN VALUE TYP MAX UNITS 17.5 18.5 19.5 s t1 RT - RT response timeout for transmitting RT. ALL t2 Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid ALL 1.5 s t3 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t4 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh t9 Mid-Sync crossing of status word to DTREQ falling edge t10 Mid-Sync crossing of Status response to RT_FAIL rising t11 Duration of WC/CWC value of 1Fh t12 CWC valid following falling edge of DTREQ t13 Mid-Sync crossing of received data word to DTREQ falling edge t14 t15 400 ALL 6.5 s 20 MHz 6.75 s 16 MHz 6.81 s 12 MHz 6.92 s 10 MHz 7 s ALL 1.5 20 MHz 200 s ns 16 MHz 250 ns 12 MHz 333 ns 10 MHz 400 ns ALL Mid-Sync crossing of last received data word for CWC to transition to WC Mid Parity crossing of status word to INCMD rising 17 ns 30 ns 20 MHz 1.75 s 16 MHz 1.81 s 12 MHz 1.92 s 10 MHz 2 s 20 MHz 1.55 s 16 MHz 1.56 s 12 MHz 1.59 s 10 MHz 1.6 s ALL 3 s MID-SYNC MID-PARITY MID-PARITY MID-PARITY 1553 BUS RX COMMAND TX COMMAND MID-SYNC MID-PARITY t7 MID-PARITY t10 STATUS DATA #1 DATA #2 STATUS t1 L-BRO, T/R, SA4-SA0 WC/MC/CWC t11 t8 1F WC / MC PREVIOUS MSG CWC = 1 t9 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY CWC = 0 cwc t14 WC / MC VALID t5 INCMD t6 t16 NOTE 1 t2 t15 GBR t12 DTREQ DTGRT DTACK BURST DATA WRITE TRANSFER D15-D0 MEMWR (Refer to FIGURE 9 on page 22) MEMOE t13 RT_FAIL t3 MSG_ERR HS_FAIL RT - RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR. FIGURE 7. RT - RT RECEIVE (BURST-MODE) TIMING 18 TABLE FOR FIGURE 7. RT-RT RECEIVE COMMAND TIMING (BURST MODE) REF DESCRIPTION CLOCK FREQUENCY RESPONSE TIME MIN TYP UNITS MAX t1 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL 1.5 s t2 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t3 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD ALL 300 ns t7 RT - RT response timeout for transmitting RT. ALL 17.5 t8 Mid-parity crossing of first data word to WC/CWC valid data of 1Fh ALL t9 Duration of WC/CWC data value of 1Fh ALL t10 RT Response time. ALL t11 CWC transition to next word following mid-parity of subsequent received data words. ALL t12 Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) ALL t13 Mid-Sync crossing of Status response to RT_FAIL rising ALL t14 CWC valid following falling edge of DTREQ ALL t15 GBR pulse width (see Note 1) t16 Mid-parity crossing of status word to INCMD rising 19 400 18.5 19.5 200 6.5 ns 7 4.5 s s 1 4 s s 1 4 ns 5.25 s 30 ns s 1.5 20 MHz 100 ns 16 MHz 125 ns 12 MHz 167 ns 10 MHz 200 ns ALL 3 s MID-SYNC MID-PARITY MID-PARITY MID-PARITY MID-SYNC MID-PARITY t7 1553 BUS RX COMMAND TX COMMAND MID-PARITY t12 STATUS DATA #1 DATA #2 STATUS t1 L-BRO, T/R, SA4-SA0 WC/MC/CWC t16 t8 1F WC / MC PREVIOUS MSG WC / MC t10 t4 ILLEGAL, SRV_RQST SSFLAG, BUSY CWC = 1 CWC = 0 VALID t6 t5 INCMD t18 t11 t2 t13 t15 GBR t9 t14 DTREQ DTGRT DTACK SINGLE WORD WRITE SINGLE WORD WRITE D15-D0 DATA WORD #1 DATA WORD #2 MEMWR (Refer to FIGURE 10 on page 24) MEMOE RT_FAIL t17 t3 MSG_ERR HS_FAIL RT - RT RECEIVE COMMAND (NON-BURST MODE) FIGURE 8. RT - RT RECEIVE (NON-BURST-MODE) TIMING 20 TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE) REF DESCRIPTION CLOCK FREQUENCY RESPONSE TIME MIN TYP UNITS MAX t1 Mid-parity crossing of received command word delay to SA4-SA0, LBRO, T/R Bit, and WC/MC valid ALL 1.5 s t2 Mid-parity crossing of received command word delay to falling edge of INCMD ALL 2 s t3 Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ALL 1.5 s t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4SA0, L-BRO, T/R, and CWC/MC valid ALL t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD ALL 300 ns t7 RT - RT response timeout for transmitting RT. ALL 17.5 t8 Mid-parity crossing to WC/CWC value of 1Fh ALL 1 s t9 Mid-parity crossing of first data word to DTREQ falling edge 20 MHz 1.2 s 16 MHz 1.25 s 12 MHz 1.33 s 10 MHz 1.4 s 20 MHz 200 ns 16 MHz 250 ns 12 MHz 333 ns 10 MHz 400 t10 WC/CWC data value of 1Fh held 400 18.5 19.5 ns s ns t11 CWC valid following falling edge of DTREQ ALL t12 RT Response time. ALL 4 t13 Delay from following mid-parity of last received data word to GBR low. (see notes 1, 2) ALL 4 t14 Mid-parity crossing of all data words, except first data word, to DTREQ falling edge ALL 1 s t15 GBR pulse width 20 MHz 100 ns 16 MHz 125 ns 12 MHz 167 ns 10 MHz 200 ns 20 MHz 75 ns 16 MHz 94 ns 12 MHz 125 ns 10 MHz 150 ns t16 CWC transition to WC prior to Mid-Sync crossing of Status response. 6.5 30 ns 7 s s t17 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 s t18 Mid Parity crossing of status word to INCMD rising ALL 3.0 s Notes: 1. Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT(low) - to - DTGRT(low) delay. 2. The transceiver delays are measured at a range of 150 ns to 450 ns for the receiver and 100 ns to 250 ns for the transmitter. 21 CLOCK IN t1 t2 DTREQ t17 t4 t8 DTGRT t6 t9 DTACK t5 t11 t13 t11 t12 t13 t12 MEMWR MEMOE L-BRO, T/R, SA4-SA0 VALID t3 t7 t15 WC/MC/CWC CWC = 0 CWC = 1 t14 t7 t16 DATA VALID D15-D0 WC t14 DATA VALID t10 t10 t18 t21 t19 t20 GBR 1 INCMD DMA WRITE - BURST MODE (SHOWN FOR TWO DATA WORDS) 1 INCMD rising edge is shown for the case of a RX Broadcast command message. For the non-Broadcast case, INCMD rising edge is after the Mid-Parity crossing of the RT STATUS response. FIGURE 9. DMA WRITE TRANSFER (BURST-MODE) TIMING 22 REF t1 t2 TABLE FOR FIGURE 9. SSRT DMA WRITE (BURST MODE) TIMING DESCRIPTION CLOCK VALUE @ 5 Volts VALUE @ 3.3 Volts FREQUENCY MIN TYP MAX MIN TYP MAX CLOCK IN rising to DTREQ low ALL 40 40 DTREQ falling to DTGRT low ALL 10 10 t3 CWC setup time prior to MEMWR falling for first word of burst transfer (see Note 1) t4 t5 DTGRT low setup prior to CLOCK IN rising edge DTGRT falling to DTACK low t6 t7 t8 t9 CLOCK IN rising to DTACK low Data output valid following CLOCK IN DTGRT hold time following DTACK falling DTACK low pulse width (based on a two data word transfer) (see Note 2) t10 Data output setup time prior to MEMWR low t11 t12 CLOCK IN rising to MEMWR low MEMWR low pulse width t13 t14 CLOCK IN rising to MEMWR high Data output and CWC hold time following MEMWR high t15 t16 Data output hold time following CLOCK IN rising CWC (all but first data word) setup time prior to MEMWR low t17 t18 CLOCK IN rising to DTREQ and DTACK high Data output signal Tri-State following CLOCK IN rising CLOCK IN rising to GBR falling edge GBR low pulse width t19 t20 t21 INCMD rising following CLOCK IN rising (see Note 3) 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL ALL ALL 20 MHz 16 MHz 12 MHz 10 MHz 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL ALL ALL 20 MHz 16 MHz 12 MHz 10 MHz ALL 60 85 127 160 10 60 85 127 160 15 100 113 133 150 40 40 30 290 365 490 590 10 22 43 60 300 375 500 600 40 52.5 73.3 90 50 62.5 83.3 100 105 118 138 155 40 40 30 290 365 490 590 10 22 43 60 300 375 500 600 40 52.5 73.3 90 50 62.5 83.3 100 40 40 30 20 33 53 70 10 10 23 43 60 40 10 23 43 60 15 10 23 43 60 30 40 40 40 40 90 115 157 190 100 125 167 200 40 90 115 157 190 100 125 167 200 30 40 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Assume DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ(low)-to-DTGRT(low) delay. 2. DTACK pulse width is 3 clock cycles per data word transfer 3. Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 s at 10 MHz, 8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz. 23 CLOCK IN t1 t2 DTREQ t15 t4 t8 DTGRT t6 t9 DTACK t5 t11 t13 t12 MEMWR MEMOE L-BRO, T/R, SA4-SA0 VALID t16 t3 WC/MC/CWC t17 CWC = 0 t14 t7 DATA D15-D0 VALID t10 NON-BURST DMA WRITE NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle. FIGURE 10. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING 24 REF t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 TABLE FOR FIGURE 10. SSRT DMA WRITE TIMING (NON-BURST) DESCRIPTION CLOCK VALUE @ 5 Volts VALUE @ 3.3 Volts FREQUENCY MIN TYP MAX MIN TYP MAX CLOCK IN rising to DTREQ low ALL 40 40 DTREQ (low)-to-DTGRT (low) delay time ALL 10 10 CWC setup time prior to MEMWR falling 20 MHz 110 110 (see Note) 16 MHz 148 148 12 MHz 210 210 10 MHz 260 260 DTGRT low setup prior to CLOCK IN rising ALL 10 15 DTGRT falling to DTACK low 20 MHz 100 105 16 MHz 113 118 12 MHz 133 138 10 MHz 150 155 CLOCK IN rising to DTACK low ALL 40 40 Data output valid following CLOCK IN rising ALL 40 40 DTGRT hold time following DTACK falling ALL 30 30 DTACK low pulse width 20 MHz 200 200 16 MHz 250 250 12 MHz 333 333 10 MHz 400 400 Data output setup time prior to MEMWR low 20 MHz 60 60 16 MHz 85 85 12 MHz 127 127 10 MHz 160 160 CLOCK IN rising to MEMWR low ALL 40 40 MEMWR low pulse width 20 MHz 40 50 40 50 16 MHz 52.5 62.5 52.5 62.5 12 MHz 73.3 83.3 73.3 83.3 10 MHz 90 100 90 100 CLOCK IN rising to MEMWR high ALL 40 40 Data output hold time following MEMWR high 20 MHz 20 10 16 MHz 33 23 12 MHz 53 43 10 MHz 70 60 CLOCK IN rising to DTREQ and DTACK high ALL 30 40 Data output hold time following CLOCK IN rising ALL 10 15 Data output signal Tri-State following CLOCK IN ALL 40 40 rising Note: Assume that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time from DTREQ (low) to DTGRT (low). 25 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLOCK IN t1 t13 t2 DTREQ t4 t7 DTGRT t6 t8 DTACK t5 MEMWR t9 t10 MEMOE L-BRO, T/R, SA4-SA0 WC/CWC VALID t3 CWC = 0 t12 t11 DATA VALID D15-D0 DMA SINGLE WORD READ FIGURE 11. DMA READ TRANSFER TIMING 26 REF t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 TABLE FOR FIGURE 11. SSRT DMA READ TIMING CLOCK VALUE @ 5 Volts FREQUENCY MIN TYP MAX CLOCK IN rising to DTREQ low ALL 40 DTREQ (low)-to-DTGRT delay time ALL 10 CWC setup time prior to MEMOE falling 20 MHz 60 16 MHz 85 12 MHz 127 10 MHz 160 DTGRT low setup prior to CLOCK IN rising ALL 10 DTGRT falling to DTACK low 20 MHz 100 16 MHz 113 12 MHz 133 10 MHz 150 CLOCK IN rising to DTACK low ALL 40 DTGRT hold time following DTACK falling ALL 30 DTACK low pulse width 20 MHz 200 16 MHz 250 12 MHz 333 10 MHz 400 CLOCK IN rising to MEMOE low ALL 40 MEMOE low pulse width 20 MHz 150 16 MHz 188 12 MHz 250 10 MHz 300 Time for input data to become valid 20 MHz 80 following falling edge of MEMOE 16 MHz 105 12 MHz 146 10 MHz 180 Data input hold time following CLOCK IN ALL 30 rising (see Note) CLOCK IN rising to DTREQ, DTACK, and ALL 30 MEMOE high DESCRIPTION Note: The SSRT's data sampling time occurs one clock cycle prior to the rising edge of MEMOE. 27 VALUE @ 3.3 Volts MIN TYP MAX 40 10 60 85 127 160 10 105 118 138 155 40 30 200 250 333 400 40 150 188 250 300 70 95 136 170 30 40 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLOCK IN MSTCLR t2 t11 t3 DTREQ t1 t4 t7 DTGRT t6 t8 DTACK t13 t12 t5 RTACTIVE note1 MEMWR MEMOE t9 D15-D0 t10 DATA VALID AUTO-CONFIGURATION - DMA SINGLE WORD READ Note1: RTACTIVE asserted high 1 clock following DTACK high asumming self-test is not enabled. When self-test is enabled RTACTIVE is delayed inthe amount of 't12'. See the table reference for details. FIGURE 12. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING 28 REF t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 TABLE FOR FIGURE 12. AUTO-CONFIGURATION - DMA READ TIMING DESCRIPTION CLOCK VALUE @ 5 Volts VALUE @ 3.3 Volts FREQUENCY MIN TYP MAX MIN TYP MAX 35 65 35 MSTCLR high delay to DTREQ low 20 MHz 50 50 65 47.5 77.5 47.5 16 MHz 62.5 62.5 77.5 68.3 98.3 68.3 12 MHz 83.3 83.3 98.3 85 115 85 10 MHz 100 100 115 CLOCK IN rising to DTREQ low ALL 40 40 DTREQ (low)-to-DTGRT delay time ALL 10 10 DTGRT low setup prior to CLOCK IN rising ALL 10 10 DTGRT falling to DTACK low 20 MHz 100 105 16 MHz 113 118 12 MHz 133 138 10 MHz 150 155 CLOCK IN rising to DTACK low ALL 40 40 DTGRT hold time following DTACK falling ALL 30 30 215 185 185 DTACK low pulse width 20 MHz 200 200 215 265 235 235 16 MHz 250 250 265 348 318 318 12 MHz 333 333 348 415 385 385 10 MHz 400 400 415 20 MHz 120 120 Time for input data to become valid 16 MHz 157 157 following falling edge of DTACK 12 MHz 220 220 10 MHz 270 270 Data input hold time following sampling time ALL 30 30 (see Note 1) CLOCK IN rising to DTREQ, DTACK, and ALL 30 40 MEMOE high t12 RTACTIVE high delayed from DTACK high (see Note 2) t13 CLOCK IN rising to RTACTIVE high 20 MHz 16 MHz 12 MHz 10 MHz ALL 1.6 2.0 2.7 3.2 1.6 2.0 2.7 3.2 30 Notes: 1: During Auto-Configuration the SSRT samples data three clock cycles following the falling edge of DTACK. 2: If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK. If self-test is enabled then RTACTIVE will be delayed from going active high in accordance with `t12'. 29 40 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ns CLOCK IN t1 SIGNAL IN t2 SIGNAL OUT HIGH TO LOW t3 SIGNAL OUT LOW TO HIGH CLOCK EDGE TO SIGNAL IN / OUT TIMING FIGURE 13. CLOCK EDGE SIGNAL TIMING REF t1 t2 t3 TABLE FOR FIGURE 13. SSRT CLOCK EDGE TO SIGNAL IN / OUT VALID TIMING DESCRIPTION VALUE @ 5 Volts VALUE @ 3.3 Volts MIN TYP MAX MIN TYP MAX SIGNAL INPUT setup time prior to CLOCK IN rising edge 10 15 CLOCK IN rising edge to SIGNAL OUTPUT driven low 40 40 (see Note) CLOCK IN rising edge to SIGNAL OUTPUT driven high 30 40 (see Note) Note: Assumes a 50pf external load. For loading above 50 pf, the validity of output signals is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 30 UNITS ns ns ns INTERFACE TO MIL-STD-1553 BUS FIGURE 14 illustrates the interface between the BU-61703/5 SSRT and a MIL-STD-1553 bus. Connections for both direct (short stub) coupling and transformer (long stub) coupling, as well as the peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. DATA BUS Z0 SHORT STUB (DIRECT COUPLED) (1:2.5) 55 BU-61703/5 11.6 Vpp 1 FT MAX 28 Vpp 55 SSRT ISOLATION TRANSFORMER OR (1:1.79) LONG STUB (TRANSFORMER COUPLED) (1:1.41) 0.75 Z0 20 FT MAX 28 Vpp 20 Vpp 11.6 Vpp 0.75 Z0 COUPLING TRANSFORMER ISOLATION TRANSFORMER Z0 NOTE: Z 0 = 70 TO 85 OHMS NOTES: 1. Shown for one of two redundant buses that interface to the BU-61703/5 hybrid. 2. Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal, 9 Vp-p max. 3. Transmitted voltage for a transformer-coupled stub is 18 Vp-p min, 27 Vp-p max for MIL-STD-1553B; 20 Vp-p min, 27 Vp-p max for MIL-STD-1760. 4. Required tolerance on isolation resistors is 2%. Instantaneous power dissipation (when transmitting) is approximately 0.45 W typ, 0.8 W (max) for each isolation resistor. FIGURE 14. SSRT INTERFACE TO MIL-STD-1553 BUS. 31 PULSE TRANSFORMERS In selecting isolation transformers to be used with the Simple System RT, there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MIL-STD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. ry center-tap, the inductance measured across the "secondary" (stub side) winding must also be less than 6.0 H. The difference between these two measurements is the "differential" leakage inductance. This value must be less than 1.0 H. Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct coupled, and 1:1.79 transformer coupled. TABLE 4 provides a listing of many of these transformers. The maximum allowable leakage inductance is 6.0 H, and is measured as follows: The side of the transformer that connects to the Simple System RT is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance must be less than 6.0 H. Similarly, if the other side of the primary is shorted to the prima- For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com. NOTES: 1. For McAIR version of the Simple System RT (BU-6170XX4), only the B-3818 or B-3819 transformers (shown in bold in the table) may be used. 2. For all other applications, any of the other transformers listed may be used. TABLE 4. RECOMMENDED BETA TRANSFORMERS FOR USE WITH SSRT TRANSFORMER CONFIGURATION BTTC PART NO. Single epoxy transformer, through-hole, 0.625 X 0.625, 0.250" max height B-3226 Single epoxy transformer, through-hole, 0.625 X 0.625, 0.220" max height. (May be used with BU-6170XX4 version of SSRT) B-3818 Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height B-3231 Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height B-3227 Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height. (May be used with BU-6170XX4 version of SSRT) B-3819 Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height LPB-5014 Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height LPB-5015 Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height TST-9007 Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height TST-9017 Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height TST-9027 Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155 max height B-3300 Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155 max height B-3261 Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155 max height B-3310 Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height HLP-6014 Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height HLP-6015 32 P.C. BOARD LAYOUT GUIDELINES for transformer (stub) coupled terminals. If there are ground planes under the analog bus signal traces, it is likely that the terminal will not meet this requirement. GROUND PLANES As is the rule in all high-speed digital circuits, it is good practice to use ground and power supply planes under the SSRT hybrid as well as the associated digital components. POWER AND GROUND DISTRIBUTION Another important consideration is power and ground distribution. Refer to FIGURE 16. For the SSRT hybrid/transformer combination, the high current path when the SSRT is transmitting will be from the +5 volt power supply, through the transmitter output stage, through one leg of the isolation transformer to the transformer center tap. It is important to realize that the high current return path is through the transformer center tap and not through the SSRT GROUND pins. However, it is very important that there be NO ground and/or power supply planes underneath the analog bus signal traces. This applies to the TX/RX signals running between the SSRT and the isolation transformers as well as the traces between the transformers to any connectors or cables leaving the board. Another important layout consideration is to minimize the power supply distribution impedance along this path. Any resistance will result in voltage drops for the power supply input voltage, and can ultimately lower the transmitter output voltage, possibly below the minimum level required by MIL-STD-1553 or MIL-STD-1760. The reason for not using supply or ground planes under the analog signal traces is that the effect of the distributed capacitance will be to lower the input impedance of the terminal, as seen from the 1553 bus. MIL-STD-1553 requires a minimum input impedance of 2000 ohms for direct coupled terminals and 1000 ohms +5 V A/B +5 V or +3.3 V LOGIC HIGH LEVEL CURRENTS SSRT TX TRANSCEIVER LOGIC RX LOW / MEDIUM LEVEL CURRENTS LOGIC GND GND A/B LOW LEVEL CURRENTS FIGURE 16. POWER - GROUND DISTRIBUTION 33 1553 BUS CONNECTIONS despite the fact that the MIL-STD-1553B requirement is for it to be measured looking directly in from the bus side of the isolation transformer. The isolation transformers should be placed as physically close as possible to the respective TX/RX pins on the SSRT. In addition, the distance from the isolation transformers to any connectors or cables leaving the board should be as short as possible. In addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and transformer-to-connector spacing serves to minimize crosstalk from other signals on the board. The effect of a relatively long stub cable will be to reduce the measured impedance (looking in from the bus). In order to keep the impedance above the required level of 1000 ohms (for transformer-coupled stubs), the length of any cable between the 1553 RT and the system connector should be minimized. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS The general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. This minimizes impedance discontinuities. The decision of whether to isolate or make connections between the center tap of the isolation transformer's secondary, the stub shield, the bus shield, and/or chassis ground must be made on a system basis, as determined by an analysis of EMI/RFI and lightning considerations. For purposes of software development and system integration, it is generally not necessary to integrate the required couplers, terminators, etc., that comprise a complete MIL-STD-1553B bus. In most instances, a simplified electrical configuration will suffice. The three connection methods illustrated in FIGURE 17 allow the SSRT to be interfaced over a "simulated bus" to simulation and test equipment. It is important to note that the termination resistors indicated are necessary in order to ensure reliable communications between the SSRT and the simulation/test equipment. In most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. This is ISOLATION TRANSFORMER STUB COUPLING STUB COUPLING SSRT HYBRID TEST/ SIMULATION EQUIPMENT 78 1.5W (A) ISOLATION TRANSFORMER DIRECT COUPLING DIRECT COUPLING 55 1W SSRT HYBRID 55 TEST/ SIMULATION EQUIPMENT 39 0.5W 55 1W 55 (B) ISOLATION TRANSFORMER DIRECT COUPLING SSRT HYBRID STUB COUPLING 20 0.5W 55 1W TEST/ SIMULATION EQUIPMENT 39 0.5W 55 1W 20S 0.5W (C) (A) TRANSFORMER COUPLED TO TRANSFORMER COUPLED (B) DIRECT COUPLED TO DIRECT COUPLED (C) DIRECT COUPLED TO TRANSFORMER COUPLED FIGURE 17. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS 34 SIMPLE SYSTEM INTERFACE FIGURE 15 illustrates the capability of the SSRT to interface to a system with no host processor in burst mode. In this example, only one set of external latches is needed to buffer the data words written by the SSRT to the external system. In burst mode, all received data words are stored in the internal FIFO until the last word is received. At this point, the SSRT will transfer the entire contents of the FIFO to the system if the message is validated. In this case, GBR will be driven low for two clock cycles following the burst transfer cycle. If the received message is not valid, the FIFO data will not be transferred to the external system and GBR will remain high. LATCH D15-D0 BUS A Write Address Decoder DISCRETE DIGITAL OUTPUTS LATCH BUS B EN MEMWR RT ADDRESS TRI-STATE BUFFER RTAD4-0, RTADP BU-61703/5 SSRT Clock Oscillator EN L-BRO, T/R, SA4-0, WC/CWC4-0 Read Address Decoder CLK-IN EN MEMOE +5V DISCRETE DIGITAL INPUTS TRI-STATE BUFFER EN +5V AUTO_CFG MSTCLR DTGRT TRI-STATE BUFFER EN RTACTIVE DTACK FIGURE 15. SSRT-TO-SIMPLE SYSTEM INTERFACE (Shown for BURST MODE) 35 AUTOCONFIGURATION (OPTIONAL) BIT WORD The BU-61703/5 provides an internally formulated Built-In-Test word (BIT word). This word is transmitted to the BC in response to a Transmit BIT Word Mode Code Command. The BIT word bit functions and descriptions are provided in Table 5. TABLE 5. INTERNAL BUILT-IN-TEST (BIT) WORD DEFINITION BIT FUNCTION DESCRIPTION 15 (MSB) TRANSMITTER TIMEOUT Set if the SSRT's failsafe timer detected a fault condition. The transmitter timeout circuit will automatically shut down the CH. A or CH. B transmitter if it transmits for longer than 660.5 s. 14 13 CH. B LOOP TEST FAILURE CH. A LOOP TEST FAILURE A loopback test is performed on the transmitted portion of every non-broadcast message. A validity check is performed on the received version of every word transmitted by the SSRT. In addition, a bitby-bit comparison is performed on the last word transmitted by the RT for each message. If either the received version of the last word does not match the transmitted version and/or the received version of any transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective bus channel will be set. 12 HANDSHAKE FAILURE 11 10 If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input DTGRT* asserted within 10 s after the SSRT has asserted DTREQ*. TRANSMITTER SHUTDOWN B If either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut TRANSMITTER SHUTDOWN A down by means of a Transmitter shutdown mode command. 9 TERMINAL FLAG INHIBITED Set to logic "1" if the SSRT's Terminal flag RT status bit has been disabled by an Inhibit terminal flag mode code command. Will revert to logic "0" if an Override inhibit terminal flag mode code command is received. 8 BIT TEST FAIL Set to logic "1" to denote that the SSRT has failed its off-line protocol self-test. This bit will be logic "0" if the self-test passed or had not been performed. 7 HIGH WORD COUNT Set to logic "1" if the previous message had a high word count error. 6 LOW WORD COUNT Set to logic "1" if the previous message had a low word count error. 5 INCORRECT SYNC TYPE RECEIVED If set, indicates that the SSRT detected a Command sync in a received Data Word. 4 INVALID WORD Indicates that the SSRT received one or more words containing one or more of the following error MANCHESTER/PARITY ERROR types: sync field error, Manchester encoding error, parity error, and/or bit count error. RECEIVED 3 RT-RT TRANSFER RESPONSE This bit is set if the SSRT is the receiving RT for an RT-to-RT transfer and one or more of the following ERROR (no gap, data, sync, errors occurs: (1) If the transmitting RT responds with a response time of less than 4 s, per MILaddress mismatch) STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 s dead time; and/or (2) There is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT Status Word; and/or (3) The RT address field of the transmitting RT Status Word does not match the RT address in the transmit Command Word. 2 RT-RT TRANSFER NO RESPONSE TIMEOUT If set, indicates that, for the previous message, the SSRT was the receiving RT for an RT-to-RT transfer and that the transmitting RT either did not respond or responded later than the SSRT RT-to-RT timeout time. The SSRT's RT-to-RT response timeout time is defined as the time from the mid-bit crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the transmitting RT status word. The value of the SSRT's RT-to-RT response timeout time is in the range from 17.5 to 19.5 s. 1 RT-RT TRANSFER T/R ERROR ON SECOND COMMAND OR INVALID ADDRESS If the SSRT is the receiving RT for an RT-to-RT transfer, if this bit is set, it indicates one or more of the following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) subaddress = 00000 or 11111; (3) same RT Address field as the receive Command Word. 0 (LSB) COMMAND WORD CONTENTS ERROR Indicates that a received command word is not defined in accordance with MIL-STD-1553B. This includes the following undefined Command Words: (1) The Command Word is a non-mode code, broadcast, transmit command; (2) a message with a T/R bit of "0", a subaddress/mode field of 00000 or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111. Note: Bits 15 through 9 are cleared only following a RESET input or receipt of a Reset Remote Terminal mode command. Bits 8 through 0 are updated as a result of every message processed. 36 MODE CODES The BU-61703/5 fully implements all 13 of the dual redundant MIL-STD-1553B mode codes. Four mode codes, Transmit vector word, Synchronize (with data), Selected transmitter shutdown, and Override transmitter shutdown, involve data transfers with the subsystem. For the Transmit last command mode command, the data word transmitted is from the SSRT's last command internal register. For the Transmit BIT word mode command, the SSRT's internally formulated BIT Word is transmitted. Table 6 provides a summary of the 1553B mode codes supported by the BU-61703/5. SUMMARY OF RESPONSES TO MODE CODE MESSAGES The SSRT's responses to mode codes, including responses to various error conditions, are summarized in Table 6. TABLE 6. MODE CODE SUMMARY T/R BIT MODE CODE FUNCTION DATA WORD BROADCAST ALLOWED 0 00000-01111 Undefined No No 1 00000 Dynamic Bus Control No No 1 00001 Synchronize No Yes 1 00010 Transmit Status Word No No 1 00011 Initiate Self Test No Yes 1 00100 Transmitter Shutdown No Yes 1 00101 Override Transmitter Shutdown No Yes 1 00110 Inhibit Terminal Flag No Yes 1 00111 Override Inhibit Terminal Flag No Yes 1 01000 Reset Remote Terminal No Yes 1 01001-01111 RESERVED No TBD 1 10000 Transmit Vector Word From Subsystem No 0 10001 Synchronize with Data To Subsystem Yes 1 10010 Transmit Last Command From Internal Register No 1 10011 Transmit BIT Word From Internal Register No 0 10100 Selected Transmitter Shutdown (see Note) To Subsystem Yes 0 10101 Override Selected Transmitter Shutdown (see Note) To Subsystem Yes 1 10110-11111 RESERVED From Subsystem TBD 0 10110-11111 RESERVED To Subsystem TBD Note: For the Selected transmitter shutdown and Override transmitter shutdown mode commands, the SSRT responds with Clear Status but no action is taken. 37 DETAILED MODE CODES FUNCTIONAL DESCRIPTION The applicable Mode Codes for the SSRT are described below: DYNAMIC BUS CONTROL ( T/R = 1; 00000) MESSAGE SEQUENCE = DBC + STATUS The SSRT responds with Status showing non-acceptance of the mode code command. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). SYNCHRONIZE WITHOUT DATA WORD ( T/R = 1; 00001) MESSAGE SEQUENCE = SYNC + STATUS The SSRT responds with Status. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). TRANSMIT STATUS WORD ( T/R = 1; 00010) MESSAGE SEQUENCE = TRANSMIT STATUS + STATUS The Status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was not a Transmit status or Transmit last command mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word) 3. T/R bit Set to Zero .No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Contents Error (BIT Word). INITIATE SELF-TEST ( T/R = 1; 00011) MESSAGE SEQUENCE = SELF TEST + STATUS If the command was non-broadcast, the SSRT responds with Status. If the command was either non-broadcast or broadcast, the SSRT will go offline and perform its internal off-line protocol self-test. The self-test exercises the SSRT's encoder and decoders, registers, transmitter watchdog timer, and protocol logic. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. The bus controller may determine the result of the self-test be means of a Transmit BIT word mode command. If the self-test passes, bit 8 of the SSRT's BIT word (BIT Test Fail) will be logic "0"; if the self-test fails, this bit will be logic "1". In addition, if self-test fails, the terminal flag status word bit will be set to logic "1" in response to the next non-broadcast message. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). 5. Loopback Test Failure. Set Terminal Flag bit in internal Status register (Status Word for next non-broadcast command), Current Channel (A or B) Loop Test Failure and CH A/B Loop Test Failure (BIT Word), assert RTFAIL output. 38 TRANSMITTER SHUTDOWN ( T/R = 1; 00100) MESSAGE SEQUENCE =SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT responds with Status. Following the Status transmission, the SSRT inhibits any further transmission from the alternate redundant channel. Once shutdown, the transmitter can only be reactivated by an Override Transmitter Shutdown or Reset RT mode command, or Hardware Reset (MSTRCLR input). Note that the receivers on both channels are always active, even when the transmitters are inhibited. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). OVERRIDE TRANSMITTER SHUTDOWN ( T/R = 1; 00101) MESSAGE SEQUENCE = OVERRIDE SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT responds with Status. At the end of the Status transmission, the SSRT reactivates the transmitter of the alternate redundant bus. If the command was broadcast, the Broadcast Command Received Status Word bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00110) MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG + STATUS The SSRT responds with Status and inhibits further setting of the Terminal Flag bit in its internal Status Word register. Once the Terminal Flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT mode code commands, or by Reset. If the command was broadcast, the Broadcast Received bit is set, the state of the Terminal Flag bit in the internal Status Word register remains unchanged and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). OVERRIDE INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00111) MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG + STATUS The SSRT responds with Status and re-enables the Terminal Flag bit in its internal Status register. If the command was a broadcast, the Broadcast Command Received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). 39 RESET REMOTE TERMINAL ( T/R = 1; 01000) MESSAGE SEQUENCE = RESET REMOTE TERMINAL + STATUS The SSRT responds with Status and internally resets. The Message Error and Broadcast Command Received bits of the internal Status register are reset to 0. The internal BIT Word Register is reset to 0. If either of the 1553 transmitters has been shut down, the shutdown condition is overridden. If the Terminal Flag bit has been inhibited, the inhibit is overridden. If the command is received as a broadcast, the Broadcast Command Received bit is set and the Status Word is suppressed. Also, if the command is received as a broadcast and the Terminal Flag bit had been set as a result of the Loopback test of the previous message, the Terminal Flag bit is not reset to zero. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). RESERVED MODE CODES ( T/R = 1; 01001 - 01111) MESSAGE SEQUENCE = RESERVED MODE COMMAND + STATUS The SSRT responds with status. If the command has been illegalized by means of the illegalization table, the Message Error Status Word bit will be set. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). TRANSMIT VECTOR WORD ( T/R = 1; 10000) MESSAGE SEQUENCE = TRANSMIT VECTOR WORD + STATUS VECTOR WORD The SSRT transmits a Status Word followed by a vector word. The vector word is read from the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 4. T/R bit Set to Zero plus one Data Word. The SSRT will respond with Status 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Low Word Count (BIT word). 6. Zero T/R bit and Broadcast Address, plus one Data Word. No Status response. Set Broadcast Command Received bits (Status Word) 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT word). SYNCHRONIZE WITH DATA WORD ( T/R = 0; 10001) MESSAGE SEQUENCE = SYNCHRONIZE COMMAND/DATA WORD + STATUS The SSRT will write the received 16 bit data word to the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Correct Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word) 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), High Word Count (BIT word). 4. Command T/R bit set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit set to One not followed by Data Word. he SSRT replies with Status plus one Data Word. The Data Word is read from the subsystem (or single-word data block for subaddress 0000 or 1111). 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word); Set Command Word Contents Error (BIT word). 40 TRANSMIT LAST COMMAND ( T/R = 1; 10010) MESSAGE SEQUENCE = TRANSMIT LAST COMMAND + STATUS/LAST COMMAND The Status register is not updated before transmission. It contains the Status from the previous command. The Data Word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND or TRANSMIT STATUS WORD mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT will respond with Status. The Data Word is transferred to the internal register. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error(BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to the internal register. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT Word). TRANSMIT BIT WORD ( T/R = 1; 10011) MESSAGE SEQUENCE = TRANSMIT BIT WORD + STATUS/BIT WORD The SSRT responds with Status followed by the Built-in Test (BIT) word. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word.No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT will respond with Status. The Data Word is transferred to internal registers. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error (BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to internal registers. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command received bits (Status Word), Command Word contents Error (BIT Word). SELECTED TRANSMITER SHUTDOWN ( T/R = 0; 10100) MESSAGE SEQUENCE = TRANSMITER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem and Status is transmitted. No other action is taken by the SSRT. No transmitters are shut down as a result of this mode command. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count Bit (BIT Word). No status response. Bits Set: message error (SW), High Word Count, Illegal Mode Code (BIT Word) 3. Command Followed by too many Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count Bit (BIT Word). 4. Command T/R bit Set to One followed by one Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word). 41 OVERRIDE SELECTED TRANSMITER SHUTDOWN ( T/R = 0; 10101) MESSAGE SEQUENCE = TRANSMITER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem. No transmitters that have been previously shut down are reactivated as a result of this command. No other action is taken by the SSRT. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command Followed by too many Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count bit (BIT Word). 4. Command T/R bit Set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word). RESERVED MODE CODES ( T/R = 1; 11111) MESSAGE SEQUENCE (when T/R = 1) = RESERVED MODE CODE STATUS/DATA (when T/R = 0) = RESERVED MODE CODE DATA + STATUS For a RESERVED receive Command, the SSRT stores the Data Word to the subsystem. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. For a RESERVED transmit Command Word, the SSRT responds with Status plus a single Data Word. The Data Word is read from the subsystem. ERROR CONDITIONS (T/R = 1) 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. Broadcast Command. No Status response. Set Message Error bit (status word), and Command Word Contents Error (BIT Word). ERROR CONDITIONS (T/R = 0) 1. Invalid Command. No response, command ignored. 2. Command not followed by Contiguous Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command followed by to many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT word). 42 TABLE 7. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS POWER AND GROUND SIGNAL NAME PIN DESCRIPTION +5V Vcc CH A 72 Channel A transceiver power. +5V Vcc CH B 20 Channel B transceiver power. +5V / +3.3V Logic 37 Logic power. For BU-61703 this pin must be connected to +3.3V. For BU-61705 this pin must be connected to +5V. GROUND 17 18 19 Ground. 26 65 67 71 MIL-STD-1553 ISOLATION TRANSFORMER INTERFACE SIGNAL NAME PIN TX/RX-A (I/O) 5 TX/RX-A (I/O) 7 TX/RX-B (I/O) 13 TX/RX-B (I/O) 16 DESCRIPTION Analog transmit/receive signals. Connect directly to 1553 isolation transformers. DATA BUS (16) SIGNAL NAME D15 (I/O) (MSB) PIN DESCRIPTION D14 (I/O) 53 Bi-directional data bus. When the SSRT is writing data to the external system, these signals are active outputs. At all other times, these signals are high impedance inputs. 50 D13 (I/O) 48 D12 (I/O) 49 D11 (I/O) 52 D10 (I/O) 54 D9 (I/O) 51 D8 (I/O) 46 D7 (I/O) 47 D6 (I/O) 36 D5 (I/O) 45 D4 (I/O) 39 D3 (I/O) 44 D2 (I/O) 43 D1 (I/O) 38 D0 (I/O) (LSB) 42 43 COMMAND / ADDRESS BUS SIGNAL PIN DESCRIPTION L_BRO (0) 3 Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a broadcast command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will output logic "0". T/R 4 Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a transmit message, this signal will output a value of logic "1". For a receive message, this signal will output logic "0". SA4 (0) 69 Subaddress. These five two-state output signals are latched following receipt of a new command word. They provide the subaddress field of the received command word. SA3 (0) 6 SA2 (0) 11 SA1 (0) 22 SA0 (0) 68 WC / MC / CWC4 (O) (MSB) 9 WC / MC / CWC3 (O) 10 WC / MC / CWC2 (O) 12 WC / MC / CWC1 (O) 27 WC / MC / CWC0 (O) (LSB) 15 Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state output signals provide the contents of the command word's Word Count/Mode Code field. For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the value of the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in burst mode). CWC increments from 0 to the value of the Word Count field - 1 during the message. At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from 0 to the value of the word count field -1, as each word is transferred from the internal FIFO to the external system over D15-D0. In burst mode, it takes three clock cycles to transfer each word to the external system. For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word Count - 1, as each word is read from the external system and transferred to the SSRT. For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched through the end of the message (until receipt of a subsequent command word). DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS SIGNAL PIN DESCRIPTION DTREQ (O) 24 Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0). DTGRT (I) 64 Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT asserting DTREQ low in order to enable the SSRT to read data from or write data to the external subsystem. The maximum allowable time from DTREQ to DTGRT is 10 s. If the SSRT's DMA handshake isn't required, DTGRT may be hardwired to logic "0". DTACK (O) 29 Data Transfer Acknowledge. Active low output signal used to indicate the SSRT's acceptance of the system data bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT's data transfers over D15-D0 will be framed by the time that DTACK is asserted low. If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to enable configuration data to be read from an external tri-state buffer. For transmit massages, or a receive messages in non-burst mode, or for receive messages to subaddress 30 assuming that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words between the external system and the SSRT. For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQ-to-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA burst write transfer from the SSRT to the external system. The total time for a burst write transfer is three clock cycles times the number of data words. HS_FAIL (O) 57 Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not respond with a DTGRT in time, following the SSRT's assertion of DTREQ. MEMOE (O) 14 Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The SSRT latches the data one clock cycle prior to the rising edge of MEMOE. MEMWR (O) 23 Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT write cycles. Used to transfer data from the SSRT to the external system. The external system may latch data on either the falling or rising edge of MEMWR. 44 RT ADDRESS SIGNAL PIN DESCRIPTION RTAD4 (i) (MSB) 35 RT Address inputs. RTAD3 (i) 34 RTAD2 (i) 21 RTAD1 (i) 41 RTAD0 (i) (LSB) 33 RTADP (I) 40 Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD-4-RTAD0 and RTADP. RT_AD_LAT (I) 31 RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT is configured to accept a hardwired RT address from RTAD4-RTAD and RTADP. If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP will be latched internally by the SSRT on the rising edge of RT_AD_LAT. RT_AD_ERR (O) 1 Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity. Note, if RT_AD_ERR is low, then the SSRT will not recognize any valid Command Word received to its own RT address. RT STATUS WORD INPUTS SIGNAL PIN DESCRIPTION ILLEGAL (I) 62 Illegal. Input to the SSRT that is sampled after the Command Word transfer. A logic "0" will cause the Message Error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the Message Error bit. SRV_RQST (I) 61 Service Request. When this input is logic "0", the Service request bit in the SSRT's status word will be logic "1". When this input is logic "1", the Service request bit in the SSRT's status word will be logic "0". SSFLAG (I) 32 Subsystem Flag. If this input is asserted low, the Subsystem Flag bit will be set in the SSRT's Status Word. BUSY (I) 55 Busy. If this input is asserted low, the Busy bit will be set to logic "1" in the SSRT's Status Word. If the Busy bit in the status word is logic "1", the SSRT will not transmit any data words, except for a Transmit last command or Transmit BIT word mode command. For a receive command, if the SSRT is Busy, it will still transfer data words to the external system (although these transfers may be blocked by means of external logic). 45 RT ACTIVITY AND MESSAGE STATUS INDICATORS SIGNAL RTACTIVE PIN DESCRIPTION 56 RT Active. This signal will be low (logic "0") following power turn-on, and when the SSRT is reading its Autoconfigure word or is performing its internal self-test. After the self-test passes, or if the Auto-configure option is not used, or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to always go online), RTACTIVE will then transition to logic "1". When this occurs, the SSRT will begin processing messages over the 1553 bus. If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTACTIVE will remain at logic "0". In this case, the SSRT will remain offline and not process any 1553 messages. A failed self test will cause RTFAIL_L to be asserted low (logic "0"). If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when RTACTIVE and DTACK are both outputting logic "0". INCMD 25 In-command. This two-state output is asserted low whenever a message is being processed by the SSRT. GBR (O) 60 Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the external system that a valid, legal, non-mode receive command with the correct number of valid data words has been received and transferred to the external system. For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT time of 0, this will be approximately 4 s following the mid-parity bit crossing of the last received data word. For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst write transfer. MSG_ERR (O) 28 Message Error. Active low level two-state output signal used to flag to the external system that there was a message error on the 1553 bus communication (word, gap, or word count error) for a particular message. This output goes low upon detecting the error and is reset following the receipt of the next valid command word (to the RT) from the 1553 bus, or if MSTCLR is asserted low. If this output goes low, all further servicing of the current message is aborted. RTFAIL (O) 58 Remote Terminal Fail. This two-state output signal will be asserted low following a failure of the built-in self-test performed following power turn-on or as the result of the receipt of an Initiate self-test mode command. The built-in off-line self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and RT protocol logic. In addition, RTFAIL will be asserted low following a failure of the on-line loop test for any non-broadcast message. The on-line loop test verifies the validity of the received version of all transmitted words (sync, Manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last transmitted word. If asserted to logic "0", RTFAIL will clear to logic "1" when the SSRT begins transmission of its status word in response to a subsequent valid non-broadcast message. CONTROL INPUTS SIGNAL PIN DESCRIPTION MSTCLR (I) 2 Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a "reset" condition, note that the risetime of MSTCLR must be less than 10 s. AUTO_CFG (I) 70 Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values as listed in Table 2. Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default). If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a DMA read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic "0" to logic "1". Each of the configuration parameters is enabled if the SSRT reads a value of logic "1" for the respective data bit. BRO_ENA (I) 63 Broadcast Enable. If this input is logic "1", the SSRT will recognize RT address 31 as the broadcast address. If this input is logic "0", the SSRT will not recognize RT ad dress 31 as the broadcast address; however, in this configuration, RT address 31 may be used as a standard RT address. TX_INH (I) 59 Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connected to logic "0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should be applied to this input. 46 CLOCK INPUT SIGNAL PIN DESCRIPTION CLK_IN (I) 30 Clock Input. The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs. CLK_SEL_1 (I) 66 These two inputs are used to designate the SSRT's clock frequency, as follows: CLK_SEL_1 CLK_SEL_0 (I) CLK_SEL_0 Clock Frequency 0 0 10 MHz 0 1 20 MHz 1 0 12 MHz 1 1 16 MHz 8 FACTORY TEST SIGNAL PIN XCVR_TP (ZAP VOLTA) P1(*) XCVR_TP (READOUTB) P2(*) XCVR_TP (READOUTA) P3(*) XCVR_TP (CLOCK) P4(*) XCVR_TP (RESET*) P5(*) XCVR_TP (ZAP VOLTB) P6(*) DESCRIPTION For factory test only. Do not connect for normal operation. (*) Note that the Test Output pins are pads located on the bottom of the package. 47 TABLE 8. NUMERICAL PIN LISTING BU-61703 (3.3V / 5V) BU-61703 (3.3V / 5V) PIN PIN BU-61703 (3.3V / 5V) PIN BU-61705 (5V) BU-61705 (5V) BU-61705 (5V) P1 ** XCVR TP (ZAP VOLTA) P2 ** XCVR TP (READOUTB) P3 ** XCVR TP (READOUTA) P4 ** XCVR TP (CLOCK) P5 ** XCVR TP (RESET_L) P6 ** XCVR TP (ZAP VOLTB) D8 N/A GND 47 D7 N/A GND WC2 48 D13 N/A GND 13 TX/RX_B 49 D12 14 MEMOE 50 D14 15 WC0 51 D9 16 TX/RX-B 52 D11 17 GROUND 53 D15 18 GROUND 54 D10 19 GROUND 55 BUSY 20 +5V Vcc-CH. B 56 RTACTIVE 21 RTAD2 57 HS_FAIL 22 SA1 58 RT_FAIL 23 MEMWR 59 TX_INH 24 DTREQ 60 GBR 25 INCMD 61 SRV_RQST 26 GROUND 62 ILLEGAL 27 WC1 63 BRO_ENA 28 MSG_ERR 64 DTGRT 29 DTACK 65 GROUND 30 CLOCK_IN 66 CLK_SEL_1 31 RT_AD_LAT 67 GROUND 32 SSFLAG 68 SA0 33 RTAD0 69 SA4 34 RTAD3 70 AUTO_CFG 35 RTAD4 71 GROUND 36 D6 72 +5V Vcc-CH. A 1 RT_AD_ERR 37 +5V/3.3V-LOGIC 2 MSTCLR 38 D1 3 L_BRO 39 D4 4 T/R 40 RTADP 5 TX/RX_A 41 RTAD1 6 SA3 42 D0 7 TX/RX_A 43 D2 8 CLK_SEL_0 44 D3 9 WC4 45 D5 10 WC3 46 11 SA2 12 48 ** Note that the Test Output pins on the flat pack are pads which are located on the bottom of the package. 2.000 0.015 (50.800 0.381) 1.000 SQ 0.010 (25.400 0.254) 0.500 0.005 (12.70 0.127) 0.200 0.005 (5.080 0.127) 0.100 DIA. (2.540) (see note 4) P6 P5 P4 P2 P1 P3 72 1 0.018 0.002 0.050 0.005 (0.457 0.051) (1.270 0.127) VIEW "B" INDEX DENOTES PIN NO. 1 VIEW "B" 0.850 0.008 (21.590 0.203) BOTTOM VIEW VIEW "A" 0.010 0.002 (0.254 0.051) 0.035 0.005 (0.889 0.127) VIEW "A" 0.155 MAX (3.94) 1.024 0.014 NOM. (26.010 0.356) 0.050 0.005 (1.270 0.127) 0.040 0.004 (1.016 0.102) 0.090 0.010 (2.286 0.254) SIDE VIEW Notes: 1) Dimensions are in inches (mm). 2) Package Material: Alumina (AL2O3) 3) Lead Material: Kovar, Plated by 50 in. minimum nickel under 60 in. minimum gold. 4) There are 6 test pads located on the bottom of the package. These pads are recessed so as not to interfere when mounting the hybrid There are no user connections to these pads. FIGURE 16. MECHANICAL OUTLINE DRAWING 49 1.38 0.02 (35.05 0.51) 1.00 SQ 0.01 (25.40 0.25) 0.19 0.01 (4.83 0.25) 0.100 DIA. (2.540) (see note 4) P6 P5 P4 P2 P1 P3 72 Notes: 1) Dimensions are in inches (mm). 2) Package Material: Alumina (AL2O3) 3) Lead Material: Kovar, Plated by 50 in. minimum nickel under 60 in. minimum gold. 4) There are 6 test pads located on the bottom of the package. These pads are recessed so as not to interfere when mounting the hybrid. There are no user connections to these pads. 1 VIEW "B" 0.850 0.008 (21.590 0.203) 0.018 0.002 0.050 0.005 (0.457 0.051) (1.270 0.127) BOTTOM VIEW VIEW "B" 0.08 MIN FLAT (2.03) INDEX DENOTES PIN NO. 1 0.012 R. MAX (0.305 R.) 0.155 MAX (3.94) 0.010 0.002 (0.254 0.051) 1.024 0.014 NOM. (26.010 0.356) VIEW "A" 0.05 MIN FLAT (1.27) SIDE VIEW 0.050 0.005 (1.27 0.127) 0.006 -0.004,+0.010 (0.152 -0.100,+ 0.254) VIEW "A" FIGURE 17. MECHANICAL OUTLINE DRAWING 50 ORDERING INFORMATION BU-61705F3-120X Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Test Criteria: 0 = Standard Testing 2 = MIL-STD-1760 Amplitude Compliant Process Requirements: 0 = Standard DDC practices, no Burn-In (See table below.) 1 = MIL-PRF-38534 Compliant 2 = B* 3 = MIL-PRF-38534 Compliant with PIND Testing 4 = MIL-PRF-38534 Compliant with Solder Dip 5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In Temperature Range/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 6 = Custom Part (Reserved) 7 = Custom Part (Reserved) 8 = 0C to +70C with Variables Test Data Voltage/Transceiver Option: 3 = +5 Volts rise/fall times = 100 to 300 ns 4 = +5 Volts rise/fall times = 200 to 300 ns ( McAir compatible) Package Type: F = Flat Pack G = "Gull Wing" (Formed Lead) Logic Voltage 3 = 3.3 Volt 5 = 5 Volt Product Type: BU-6170 = RT only with simple (non-processor) interface STANDARD DDC PROCESSING MIL-STD-883 TEST METHOD(S) CONDITION(S) INSPECTION 2009, 2010, 2017, and 2032 -- SEAL 1014 A and C TEMPERATURE CYCLE 1010 C CONSTANT ACCELERATION 2001 A BURN-IN 1015, Table 1 -- 51 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7382 or 7234 Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Sweden - Tel: +46-(0)8-54490044, Fax +46-(0)8-7550570 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com RM (R) I FI REG U ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 B-08/00-500 PRINTED IN THE U.S.A. 52