BU-61703G4-162K - Data Device Corporation (DDC)

BU-61703/61705

SIMPLE SYSTEM RT (SSRT)

COMMAND

ADDRESS

BUS

MESSAGE

STATUS

WORD

INPUTS

DATA

TRANSFER

CONTROL

DMA

HANDSAKE

CONTROL

DMA

HANDSAKE

AND

TRANDFER

CONTROL

LOGIC

SYSTEM

DATA

BUFFERS

DTREQ

D15-D0

DTGRT

DTACK

HS FAIL

MEMOE

MEMWR

L_BRO, T/R, SA4-SA0

WC/MC/CWC4-0

ILLEGAL

SRV_RQST

SSFLAG

BUSY

RTACTIVE

INCMD

RTAD4-RTAD0

RT_AD_LAT

RT_AD_ERR

GBR

CLK_IN

CLK_SEL1

CLK_SEL0

MSG_ERR

RTFAIL

DUAL

ENCODER

DECODER

AND

RT STATE

LOGIC

BRO_ENA

AUTO_CFG

MSTCLR

CONTROL

INPUTS

ADDRESS

CLOCK

FEQUENCEY

SELECTION

55Ω

TX/RX A

TX/RX B

TRANSCEIVER

B-3226

B-3227

B-3226

B-3227

TX_INH

BUS A

BUS B

TRANSMITTER

INHIBIT

RTADP

Note: Transformers are external.

FEATURES

• Complete Integrated Remote

Terminal Including:

Dual Low-Power 5V Only Transceiver

Complete RT Protocol Logic

• Suppor ts MIL-STD-1553A/B Notice 2,

STANAG-3838 RT, and

MIL-STD-1760 Stores Management

• 1.0 X 1.0 Inch, 72-pin Package

• Choice of 5V or 3.3V Logic Power

• Meets 1553A/McAir Response Time

Requirements

• Internal FIFO for Burst Mode

Capability on Receive Data

• 16-bit DMA Interface

• Auto Configuration Capability

• Comprehensive Built-in Self-test

• Direct Interface to Simple

(Processorless) Systems

• Selectable Input Clock:

10, 12, 16, or 20 MHz

DESCRIPTION

The BU-61703/5 Simple System RT

(SSRT) MIL-STD-1553 terminals pro-

vide a complete interface between a

simple system and a MIL-STD-1553

bus. These terminals integrate dual

transceiver, protocol logic, and a FIFO

memory for received messages in a

1.0 inch square ceramic package. The

SSRT provides multi-protocol support

of MIL-STD-1553A/B, MIL-STD-1760,

McAir, and STANAG-3838.

The SSR T's transceivers are complete-

ly monolithic, require only a +5V sup-

ply, and consume lo w po wer.There are

versions of the simple system RT a v ail-

able with transceivers trimmed for MIL-

STD-1760 compliance, or compatible

to McAir standards. As a means of fur-

ther reducing power consumption, the

SSRT is available in versions with its

logic powered by +3.3V, or +5V. The

SSRT can operate with a choice of

clock frequencies of 10, 12, 16, or 20

MHz.

The SSRT is ideal for stores and other

simple systems that do not require a

microprocessor .To streamline the inter-

face to simple systems, the SSRT

includes an internal 32-word FIFO for

received data words. This serves to

ensure that only complete, consistent

blocks of validated data words are

transferred to a system.

The SSRT incorporates a built-in self-

test (BIT).This BIT, which is processed

following power turn-on or after receipt

of an Initiate self-test mode command,

provides a comprehensive test of the

SSRT's encoders, decoders, protocol,

transmitter watchdog timer, and proto-

col.The result of the built-in test ma y be

conveyed to the bus controller by

means of the SSRT's Ter minal Flag bit

and/or its RT BIT word.

The SSRT includes an auto-configura-

tion feature. This may be used to

enable the SSRT to run (or not run) its

BIT at power turn-on, to select between

MIL-STD-1553A or -1553B protocol, to

transfer received data words to a sys-

tem either individually or by means of a

burst transfer, to implement wrap-

around for subaddress 30 (per MIL-

STD-1553B Notice 2), along with

options involving the reporting of self-

test failures and loopback errors.

µA

0.7

0.2•Vcc

-50

-33

-50

-33

0.4

-3.4

2.1

0.8•Vcc

0.4

1.0

-10

-350

-10

-350

2.4

3.4

LOGIC

VIH

All signals except CLK_IN

CLK_IN

VIL

All signals except CLK_IN

CLK_IN

Schmidt Hysteresis

All signals except CLK_IN

CLK_IN

IIH (Vcc=5.5V, VIN=Vcc)

IIH (Vcc=5.5V, VIN=2.7V)

IIH (Vcc=3.6V, VIN=Vcc)

IIH (Vcc=3.6V, VIH=2.7V)

IIL (Vcc=5.5V, VIH=0.4V)

IIL (Vcc=3.6V, VIH=0.4V)

VOH (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOH=max)

VOH (Vcc=3.0V, VIH=2.7V,

VIL=0.2V, IOH=max)

VOL (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOL=max)

VOL (Vcc=3.0V, VIH=2.7V,

VIL=0.2V, IOL=max)

IOL

IOH

CI(Input Capacitance)

CIO (Bi-directional signal input

capacitance)

Vp-p

MVP-P

mVpeak

nsec

250

300

150

250

-250

100

200

TRANSMITTER

Differential Output Voltage

!Direct Coupled Across 35 Ω,

Measured on Bus

!Transformer Coupled Across

70 Ω, Measured on Bus

BU-61573(5)XX-XX0 (Note 8)

BU-61573(5)XX-XX2

(Note 8, 9,13)

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Transformer

Coupled Across 70 ohms

Rise/F all Time

BU-61703(5)X3

BU-61703(5)X4

KΩ

Vp-p

Vpeak

0.860

2.5

0.200

RECEIVER

Differential Input Resistance

(Notes 1-6)

Differential Input Capacitance

(Notes 1-6)

Threshold Voltage, Tr ansf ormer

Coupled,

Common Mode Voltage (Note 7)

6.0

7.0

6.0

-0.3

ABSOLUTE MAXIMUM RATING

Supply Voltage

!Logic +5V or +3.3V

!RAM +5V

!Transceiver +5V

!Voltage Input Range for +5V

Powered Logic (BU-61705)

!Voltage Input Range for +3.3V

Powered Logic (BU-61703)

UNITSMAXTYPMINPARAMETER

TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS

UNITSMAXTYPMINPARAMETER

0.88

1.11

1.33

1.79

0.88

1.17

1.46

2.05

0.69

0.92

1.15

1.60

0.69

0.98

1.28

1.86

0.28

0.51

0.75

1.22

0.28

0.58

0.88

1.48

5.5

3.6

5.5

160

265

370

580

160

276

392

625

100

205

310

520

100

216

332

565

5.0

3.3

5.0

4.5

3.0

4.75

POWER DISSIPATION

Total Hybrid (Note 11)

!BU-61705XX-XX0

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61705XX-XX2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61703XX-XX0

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61703XX-XX2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Hottest Die (Note 11)

!BU-6170XXX-XX0

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-6170XXX-XX2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances

!+5V Logic (BU-61705) (Note 10)

!+3.3V Logic (BU-61703) (Note 10)

!+5V Ch. A, +5, Ch. B (Note 10)

Current Drain

!BU-61705XX-XX0

!+5V (Logic, CH A, CH B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61705XX-XX2

!+5V (Logic, CH A, CH B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61703XX-XX0

!+5V (CH A, CH B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!3.3V (Logic)

!BU-61703XX-XX2

!+5V (CH A, CH B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!3.3V (Logic)

TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont’d)

(g)

in.

(mm)

°C/W

°C

150

+300

-55

-65

Weight

PHYSICAL CHARACTERISTICS

Size

THERMAL

Thermal Resistance, Junction-to-Case,

Hottest Die (θJC)

Operating Junction Temperature

Storage Temperature

Lead Temperature (solder ing, 10 sec.)

µs

19.5

18.5

660.5

17.5

1553 MESSAGE TIMING

RT-to-RT Response Timeout

(Note 12)

RT Response Time

(mid-parity to mid-sync) (Note 12)

Tr ansmitter Watchdog Timeout

MHz

0.01

0.1

0.001

0.01

16.0

12.0

10.0

20.0

-0.01

-0.10

0.001

-0.01

CLOCK INPUT

Frequency

!Nominal Value

• Default

• Option

!Long Term Toler ance

• 1553A Compliance

• 1553B Compliance

!Short Term Toler ance , 1 second

• 1553A Compliance

• 1553B Compliance

!Duty Cycle

UNITSMAXTYPMINPARAMETER

TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont’d)

0.6

(17)

1.0 X 1.0 X 0.155

(25.4 x 25.4 x 3.94)

NOTES:

Notes 1 through 6 are applicable to the Receiver Differential Resistance

and Differential Capacitance specifications:

(1) Specifications include both transmitter and receiver (tied together

internally).

(2) Impedance parameters are specified directly between pins

TX/RX A(B) and of the SSRT hybrid.

(3) It is assumed that all power and g round inputs to the hybrid are con-

nected.

(4) The specifications are applicable for both unpowered and powered

conditions.

(5) The specifications assume a 2 volt rms balanced, differential, sinu-

soidal input. The applicable frequency range is 75 kHz to 1 MHz.

(6) Minimum resistance and maximum capacitance parameters are

guaranteed over the operating range, but are not tested.

(7) Assumes a common mode voltage within the frequency range of dc

to 2 MHz, applied to the pins of the isolation transformer on the stub

side (either direct or transformer coupled), and referenced to hybrid

)B(A RX/TX

ground. Transformer must be a DDC recommended transformer or

other transformer that provides an equivalent minimum CMRR.

(8) An "X" in one or more of the product type fields indicates that the ref-

erence is applicable to all available product options.

(9) MIL-STD-1760 requires an output of 20 Vp-p minimum on the stub

connection.

(10) External 10 µF tantalum and 0.1 µF capacitors to ground should be

located as close as possible to Pins 20 and 72, and a 0.1 µF capac-

itor at pin 37.

(11) Power dissipation specifications assume a transformer coupled con-

figuration, with external dissipation (while transmitting) of 0.14 watts

for the active isolation transformer , 0.08 watts f or the active b us cou-

pling transformer, 0.45 watts for each of the two bus isolation resis-

tors, and 0.15 watts for each of the two bus termination resistors.

(12) Measured from mid-parity crossing of command word to mid-sync

crossing of RT's status word.

(13) MIL-STD-1760 compliant output voltage not available for

BU-61703/5X4 versions.

NOTES: (Cont’d)

The BU-61703/5 includes a hardwired R.T. address input. This

includes 5 address lines, an address parity input, and an address

parity error output.The RT address can also be latched by means

of a latching input signal.

The BU-61703/5 supports command illegalization. Commands

may be illegalized by asserting the input signal active

low within appro ximately 2 µs after the mid-parity bit zero-crossing

of the received command word. Command words may be illegal-

ized as a function of broadcast, bit, subaddress, word count,

and/or mode code.

An internal Built-in-Test (BIT) Word register is updated at the end

of each message. The contents of the BIT Word Register are

transmitted in response to a Transmit BIT Word Mode Command.

The BU-61703/5 provides a number of real-time output signals.

These various signals provide indications of message in prog ress ,

valid received message, message error, handshake fail, loop-test

fail or transmitter timeout.

The BU-61703/5 includes standard DMA handshake signals

(Request, Grant, and Ac knowledge) as well as transf er control out-

puts ( and ). The DMA interface operates in a

16-bit mode, supporting word-wide transfers.

The SSRT's system interface allows the BU-61703/5 to be inter-

faced directly to a simple system that doesn't include a micro-

processor .This provides a lo w-cost 1553 interface f or A/D and D/A

conver ters, switch closures, actuators, and other discrete I/O sig-

nals.

The BU-61703/5 has an internal FIFO for received data words.

This 32-word deep FIFO may be used to allow the BU-61703/5 to

transfer its data words to the local system in burst mode. Burst

mode utilizes the FIFO by transferring data to the local bus at a

rate of one data word every three clock cycles. Burst mode nego-

tiates only once for use of the subsystem bus. Negotiation is per-

f ormed only after all 1553 data words hav e been receiv ed and v a l-

idated. In non-burst mode, the BU-61703/5 will negotiate for the

local bus after every received data word. The data word transfer

period is three clock cycles for each received 1553 data word.

The BU-61703/5 ma y also be used in a shared RAM interface con-

figuration. By means of tri-state buffers and a small amount of

"glue" logic, the BU-61703/5 will store Command Words and

access Data Words to/from dedicated "mailbo x" areas in a shared

RAM for each broadcast / T/R bit / subaddress / mode code.

MEMWR

MEMOE

R/T

ILLEGAL

INTRODUCTION

GENERAL

The BU-61703/5 Simple System RT (SSRT) is a complete MIL-

STD-1553 Remote Ter minal (RT) bus interface unit. Contained in

this hybrid are a dual transceiver and Manchester II

encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) pro-

tocol logic. Also included are built-in self-test capability and a par-

allel subsystem interface.The subsystem interface includes a 12-

bit address bus and a 16-bit data bus that operates in a 16-bit

DMA handshake transfer configuration.The local bus and associ-

ated control signals may be operated from either +5 volt or +3.3

volt power.

The transceiver front end of the BU-61703/5 is implemented by

means of low-power monolithic technology. The transceiver

requires only a single +5 V voltage source. The voltage source

transmitters provide superior line driving capability for long cables

and heavy amounts of bus loading. In addition, the monolithic

transceivers provide a minimum stub voltage level of 20 volts

peak-to-peak transformer coupled, making the BU-61703/5 suit-

able for MIL-STD-1760 applications.

The receiver sections of the BU-61703/5 are fully compliant with

MIL-STD-1553B in terms of front-end overvoltage protection,

threshold, and bit-error rate.

The BU-61703/5 implements all MIL-STD-1553 message f ormats,

including all 13 MIL-STD 1553 dual redundant mode codes. Any

subset of the possible 1553 commands (broadcast, T/R bit, sub-

address, word count/mode code) may be optionally illegalized by

means of an exter nal PROM, PLD, or RAM. An extensive amount

of message validation is performed for each message received.

Each word received is validated for correct sync type and sync

encoding, Manchester II encoding, parity, and bit count. All mes-

sages are verified to contain a legal, defined command word and

correct word count.If the BU-61703/5 is the receiving RT in an R T-

to-RT transfer, it verifies that the T/R bit of the transmit command

word is logic "1" and that the transmitting RT responds in time and

contains the correct RT address in its Status Word.

The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz

clock input. For any clock frequency, the decoder samples incom-

ing data on both edges of the clock input. This oversampling, in

effect, provides for a sampling rate of twice the input clocks' fre-

quency. Benefits of the higher sampling rate include a wider toler-

ance for zero-crossing distortion and improved bit error rate per-

formance.

ADDRESS MAPPING:

A typical addressing scheme for the BU-61703/5 12-bit address

bus could be as follows:

A11:

A10:

A9-A5: SUBADDRESS 4-0

A4-A0: WORD COUNT/MODE CODE 4-0

This method of address mapping provides for a "mailbox" alloca-

tion scheme f or the storage of data words .The 12 address outputs

may be used to map into 4K words of processor address space.

The BU-61703/5's addressing scheme maps messages in terms

of broadcast/own address, transmit/receive, subaddress, and

word/count mode code. A 32-word message block is allocated for

each T/R-subaddress.

For non-mode code messages, the Data Words to be transmitted

or received are accessed from (to) relative locations

0 through 31 within the respective message block. For the

MIL-STD-1553B Synchronize with data, Selected transmitter shut-

down, Override selected transmitter shutdown, and Transmit vec-

tor word mode commands which involve a single data word trans-

fer, the address for the data word is offset from location 0

of the message block for subaddresses 0 and 31 by the value of

the mode code field of the received command word.

The data words transmitted in response to the Transmit last com-

mand or Transmit BIT word mode commands are accessed from

a pair of internal registers.

DMA INTERFACE

A 16-bit data bus , a 12-bit address b us , and six control signals are

provided to facilitate communication with the parallel subsystem.

The data bus D15-D0 consists of bi-directional tri-state signals.

The address bus L_BRO, , SA4-SA0, and WC/MC/CWC4-0;

along with the data transf er control signals and

are two-state output signals.

The control signals include the standard DMA handshake signals

, , , as well as the transf er control outputs

and . provides an indication to the

subsystem of a handshake failure condition.

Data transfers between the subsystem and the BU-61703/5 are

performed by means of a DMA handshake, initiated by

the BU-61703/5. A data read operation is defined to be the trans-

fer of data from the subsystem to the BU-61703/5. Conversely, a

data write operation transfers data from the BU-61703/5 to the

subsystem. Data is transferred as a single 16-bit word

FAIL_HS

MEMWR

MEMOE

DTACK

DTGRT

DTREQ

MEMWR

MEMOE

R/T

RECEIVE/TRANSMIT

OWNADDRESS/BROADCAST

DMA READ OPERATION

In response to a transmit command, the BU-61703/5 needs to

read data words from the external subsystem. To initiate a data

word read transfer, the SSRT asserts the signal low.

Assuming that the subsystem asser ts in time, the SSRT

will then asser t the appropr iate values of L_BRO (logic "0"),

(high), SA4-0, and MC/CWC4-0; high, along with

low and low to enable data to be read from the

subsystem.

After the transfer of each Data Word has been completed, the

value of the address bus outputs CWC4 through CWC0 is incre-

mented.

DMA WRITE OPERA TION

In response to a receive command, the BU-61703/5 will need to

transfer data to the subsystem. There are two options for doing

this, the burst mode and the non-burst mode. In burst mode, all

received data w ords are tr ansferred from the SSRT to the subsys-

tem in a contiguous burst, only following the reception of the cor-

rect number of valid data words. In the non-burst mode,

single data words are written to the external subsystem immedi-

ately following the reception of each individual data word.

To initiate a DMA wr ite cycle, the SSRT asser ts low.The

subsystem must then respond with low. Assuming that

was asserted in time, the BU-61703/5 will then assert

low. The BU-61703/5 will then assert the appropriate

value of L_BRO, , SA4-0, and MC/CWC4-0, high,

and low. will be asserted low for one clock

cycle.The subsystem ma y then use either the falling or rising edge

of to latch the data. Similar to the DMA read operation,

the address outputs CWC4 through CWC0 are incremented after

the completion of a DMA write operation.

HANDSHAKE FAIL

Following the asser tion of low by the SSRT, the external

subsystem has 10 µs to respond by asserting to

logic "0".

If the BU-61703/5 (SSRT) asserts and the subsystem

does not respond with in time f or the B U-61703/5 to com-

plete a data word transf er, the output will be asserted low

to inf orm the subsystem of the handshake f ailure , and bit 12 in the

internal Built-In-Test (BIT) word will be set to logic "1." If the hand-

shake failure occurs on a data word read transfer (for a transmit

command), the SSRT will abort the current message transmis-

sion. In the case of a handshake failure on a write transfer

(received command) the SSRT will set the handshake failure out-

put and BIT word bit, and abor t processing the current message.

HSFAIL

DTGRT

DTREQ

DTACK

DTREQ

MEMWR

MEMOE

R/T

DTACK

DTGRT

DTREQ

MEMOE

DTACK

MEMWR

R/T

DTGRT

DTREQ

L-BRO

T/R

A11

A10

PROM / RAM / PLD

(4Kx1)

SA1

WC/MC/CWC3

WC/MC/CWC2

SA0

WC/MC/CWC4

WC/MC/CWC1

SA4

SA3

SA2

WC/MC/CWC0

ILLEGAL

BU - 61703 / 5

"SSRT"

(400ns max)

FIGURE 2. BU-61703/6 ILLEGALIZATION

MESSAGE PROCESSING OPERATION

Following the receipt and transfer of a valid Command Word, the

BU-61703/5 will attempt to perform one of the following opera-

tions: (1) transfer received 1553 data to the subsystem, (2) read

data from the subsystem for transmission on the 1553 bus, (3)

transmit status (and possibly the last command word or RT BIT

word) on the 1553 bus, and/or (4) set status word conditions.

The BU-61703/5 responds to all non-broadcast messages to its

RT address with a 1553 Status Word.

RT ADDRESS

RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity

(RT_AD_P) should be programmed for a unique RT address and

reflect an odd parity sum.The BU-61703/5 will not respond to any

MIL-STD-1553 commands or transf er receiv ed data from any non-

broadcast messages if an odd parity sum is not presented by

R T_AD_4-0 and RT_AD_P. An address parity error will be indicat-

ed by a low output on the pin. The input signal

RT_AD_LAT operates a transparent latch for

R TAD4-RTAD0 and RTADP.If RT_AD_LAT is low, the output of the

latch tracks the value presented on the input pins. If RT_AD_LAT

is high, the output of the internal latch becomes latched to the val-

ues presented at the time of a low-to-high transition of

RT_AD_LAT.

RT address and RT Address Parity must be presented valid

before the mid-parity crossing of the 1553 command and held, at

least, until following the first received data word.

RT_AD_ERR

COMMAND ILLEGALIZATION

The BU-61703/5 includes a provision f or command illegalization.If

a command is illegalized, the BU-61703/5 will set the Message

error bit and transmit its status word to the Bus Controller. No data

words will be transmitted in response to an illegalized transmit

command. However, data words associated with an illegalized

receive command will be written to the external subsystem

(although these transfers may be blocked using external logic).

is sampled appro ximately 2 µs following the mid-parity bit

zero crossing of the received command word. A low on

will illegalize a particular command word and cause the SSRT to

respond with its Message error bit set in its status word.Command

illegalization based on broadcast, bit, subaddress, and/or

word count/mode code may be implemented by means of an

exter nal PROM, PLD, or RAM device, as shown in FIGURE 2.

The exter nal device may be used to define the legality of specific

commands. Any subset of the possible 1553 commands may be

illegalized as a function of broadcast, bit, subaddress, word

count, and/or mode code. The output of the illegalization device

should be tied directly to the BU-61703/5's signal input.

The maximum access time of the e xternal illegalizing de vice is 400

ns.

If illegalization is not used, should be hardwired to logic

"1".

ILLEGAL

R/T

ILLEGAL

In burst mode , a DMA handshake will not be initiated until after all

data words ha ve been receiv ed o v er the 1553 data bus and stored

into the SSRT's internal FIFO. After the handshake has been

negotiated, the SSRT will burst the contents of the FIFO to the

local bus (D0-D15). After the reception of a valid non-mode code

receive command word followed by the correct number of valid

data words and assuming that all words are successfully trans-

ferred to the subsystem, a negative pulse will be asserted on the

output Good Block Receiv ed ( ).The width of this pulse is two

clock cycles.

RT-TO-RT TRANSFER ERRORS

For the case where the SSRT is the receiving RT of an RT-to-RT

transfer, if the transmitting RT does not respond within the speci-

fied time period, the SSRT will determine that a timeout condition

has occurred.The value of the SSR T's R T-to-R T timeout timer is in

the range from 17.5 to 18.5 µs, and is specified from the mid-par-

ity bit crossing of the transmit command word to the mid-sync

crossing of the transmitting R T's status word.In the case of an RT-

to-RT timeout, the SSRT will not respond and the RT-TO-RT NO

TRANSFER TIMEOUT bit (bit 2) of the SSRT's BIT Word will be

set to logic "1".

Also, if the SSRT is the receiving RT for an RT-to-RT transfer, and

the bit of the second command word is logic "0", or the RT

address field for the transmit command is the same as for the

receive command, or the subaddress for the transmit command is

00000 or 11111, the BU-61703/5 will not respond, and will set the

RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT

word to logic "1".

RT STATUS, ERROR HANDLING, AND MESSAGE

TIMING SIGNALS

Message transfers and transfer errors are indicated by means of

the , , , and error indication

outputs. Additional error detection and indication mechanisms

include updating of the internal command, RT status and BIT word

registers.

The BU-61703/5 provides a number of timing signals during the

processing of 1553 messages. is asserted low when a

new command is received. At the end of a message (either valid

or invalid), transitions from low to high.

As discussed above, will be asserted low if the subsys-

tem fails to respond to within the maximum amount of

time (10 µs).

Following the last data word transfer for a valid non-mode code

receive message (for either non-b urst mode or b urst mode),

will be asser ted low for two clock cycles.

GBR

DTREQ

FAIL_HS

INCMD

RTFAIL

ERR_MSG

FAIL_HS

INCMD

R/T

GBR

BUSY

The external subsystem may control the SSRT's Busy RT status

word bit by means of the input signal. The SSRT samples

approximately 2 µs following the mid-parity bit zero cross-

ing of the received Command Word. If is sampled low for a

particular message, the value of the busy bit transmitted in the

SSRT's status word will be logic "1". If is sampled high for

a par ticular message, the value of the busy bit transmitted in the

SSRT's status word will be logic "0".

If the RT responds to a transmit command with a busy bit of logic

"1", the status word will be transmitted, but no data words will be

transmitted by the SSRT. If the SSRT responds to a receive com-

mand with a busy bit of logic "1", data w ords will be transferred to

the e xternal subsystem (although these may be bloc k ed by means

of exter nal logic).

Similar to , it is possible to cause the SSRT to respond

with Busy for specific command words (only), by means of an

exter nal PROM, RAM, or PLD device.

TRANSMIT COMMAND (RT-TO-BC TRANSFER)

If the BU-61703/5 receives a valid Transmit command word that

the subsystem determines is legal (input signal is high)

and the subsystem is not BUSY (input signal is high), the

BU-61703/5 will initiate a transmit data response following trans-

mission of its status word.This entails a handshake/read cycle for

each data word transmitted, with the number of data words to be

transmitted specified by the word count field of the transmit com-

mand word.

If is sampled lo w, the Message Error bit will be set in the

SSRT's status word. No data words will be transmitted following

transmission of the status word to an illegalized transmit com-

mand. A low on the input will set the busy bit in the Status

W ord;in this instance, only the status word will be tr ansmitted, with

no data words.

RECEIVE COMMAND (BC-TO-RT TRANSFER)

In non-burst mode, a DMA handshake will be initiated for each

data word received from the 1553 data bus. If successful, the

respective handshake will be followed by a corresponding write

cycle.A handshake timeout will not terminate transf er attempts for

the remaining data words, error flagging or Status Word transmis-

sion. After the reception of a valid non-mode code receive

Command Word followed by the correct number of valid Data

W ords and assuming that all words are successfully tr ansferred to

the subsystem, a negative pulse will be asserted on the Good

Block Received ( ) output.The width of this pulse is two clock

cycles.

GBR

BUSY

ILLEGAL

BUSY

ILLEGAL

BUSY

is asserted as a low output level f ollowing any detect-

ed error in a received message, except for an error in the com-

mand word. If an error is detected in a received command word,

the rest of the message will be ignored.

If and/or have been asserted (low), they will

be cleared to logic "1" f ollowing receipt of a subsequent v alid com-

mand word.

LOOPBACK TEST

The BU-61703/5 performs a loopback self-test at the end of each

non-broadcast message processed.The loopback test consists of

the following verifications: (1) The received version of every trans-

mitted word is verified for validity (encoding, bit count, parity) and

correct sync type; and (2) The received version of the last trans-

mitted word is verified by means of a bit-by-bit comparison to the

transmitted version of this word. If there is a transmitter timeout

(660.5 µs) and/or if the loopback test fails for one or more trans-

mitted words, the Terminal flag status word bit will be set in

response to the next non-broadcast message.

Note that the setting of the Terminal flag status bit following a loop

test failure may be disabled by means of the Auto-Config feature;

i.e., by setting Auto-Config bit 4 to logic "0".

STATUS WORD

The Broadcast Command Received bit is formulated internally by

the SSRT. The Message Error Status bit will be set if the current

command is a Transmit Status Word or Transmit Last Command

mode command if there was an error in the data portion of the pre-

vious receive message .Message Error will also be set if

has been sampled low by the SSRT for the current message.

, , , and (Subsystem Flag)

will be sampled from their respective Status input pins approxi-

mately 2 µs following the mid-parity bit zero crossing of the

received Command Word.This time is 400 ns maximum following

after the L_BRO, , SA4-0, and WC/MC/CWC4-0 outputs ha v e

been presented valid.

R/T

SSFLAG

BUSY

SRV_RQST

ILLEGAL

FAIL_HS

ERR_MSG

PROTOCOL SELF-TEST

The SSRT includes a comprehensive, autonomous off-line self-

test of its internal protocol logic. The test includes a comprehen-

sive test of all registers , Manchester encoder and decoders , trans-

mitter failsafe timer, protocol logic, and the internal FIFO.

This test is completed in approximately 32,000 clock cycles. That

is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms

at 12 MHz, and 3.2 ms at 10 MHz.While the SSRT is performing

its off-line self-test, it will ignore (and therefore not respond to) all

messages received from the 1553 bus.

Unless disabled by means of the SSRT's Auto-Config feature, the

protocol self-test will be performed following the SSRT's power

turn-on (i.e., when is released high). If the Auto-Config

feature is used and Auto-Config bit 5 is set to logic "0", then a fail-

ure of the protocol self-test f ollowing power turn-on will result in the

SSR T not going online. If bit 5 is set to logic "0" and the protocol

self-test passes following power turn-on, the SSRT will go online.

The protocol self-test will also be perf ormed following receipt of an

Initiate self-test mode command from the 1553 bus. If an Initiate

self-test mode command is received by the SSRT, and Auto-

Config bit 5 is set to logic "0", then a f ailure of the protocol self-test

following will result in the SSRT going offline.

If the protocol self-test fails: (1) the Ter minal Flag bit will be set to

logic "1" in the SSR T status word;(2) bit 8 in the SSRT's BIT word,

BIT Test Fail, will be set to logic "1"; (3) the SSRT's out-

put will be asser ted to logic "0".

RTFAIL

MSTCLR

MIL-STD-1553A*/B

(-B is logic "1", or the

default).

POWER-UP SELF-

TEST ENABLE

BURST MODE

SUBADDRESS 30

WRAPAROUND

RTFAIL-to-TERMINAL

FLAG AUTO-WRAP

RT GOES ONLINE IF

SELF-TEST FAILS

FUNCTION

In MIL-STD-1553B mode, subaddress

31 is a mode code subaddress, and

mode codes are implemented in full

accordance with MIL-STD-1553B. In

MIL-STD-1553A mode, subaddress 31

is a non-mode code subaddress, and no

data words are transmitted or anticipat-

ed to be received for mode code mes-

sages.

If enabled, the SSRT will perform self-

test following the rising edge of MST-

CLR*.

Enables burst mode (using the internal

FIFO) for received data words. In burst

mode, for a receive message, all data

words are transferred to the external

system in a contiguous burst following

reception of the last data word.

Subaddress 30 wraparound is enabled.

That is, the data words for a receive

message to subaddress 30 are stored in

the internal FIFO, and not transferred to

the external system. For a subsequent

transmit message to subaddress 30, the

transmitted data words are read from

the internal FIFO, rather than from the

external system.

If the loop test fails for a particular mes-

sage, the Terminal flag bit will be set in

the SSRT's status response for the sub-

sequent non-broadcast message.

If logic "0", the RT will become enabled

only if the self-test passes. If auto-config

is not used, or if this bit is logic "1", or if

the power-up self-test passes, then the

RT will go online following self-test.

DESCRIPTIONBIT

TABLE 2. AUTO-CONFIGURATION PARAMETERS

CLK_SEL_0

12 MHz

16 MHz1

20 MHz010 MHz0

CLOCK FREQUENCYCLK_SEL_1

TABLE 3. CLOCK FREQUENCY SELECTION

CLOCK INPUT

The SSRT may be operated from one of four clock frequencies:

10, 12, 16, or 20 MHz.The selected clock frequency m ust be des-

ignated by means of the input signals CLK_SEL_1 and

CLK_SEL_0, as shown in Table 3.

AUTO-CONFIGURATION

The SSRT includes an auto-configuration feature, which allows

various optional features to be enabled or disabled. Auto-configu-

ration may be enabled or disabled by means of the input signal

. If is connected to logic "1", then the

auto-configure option is disabled, and the six configuration para-

meters revert to their default values.

Note that the default condition for each configuration para-

meter is enabled (for the MIL-STD-1553A/B protocol selection, -

1553Bis the default).

If is connected to logic "0", then the configuration

parameters are transferred over D5-D0 by means of a DMA read

data transfer. The transfer occurs during the time that the

RTACTIVE and outputs are logic "0", following

transitioning from logic "0" to logic "1" and a successful

-to- handshake.

Note that if is hardwired to logic "0", the handshake

process is not necessary (i.e., and RTACTIVE will both

be asser ted to logic "0" one clock cycle following ).

Each of the configuration parameters is enabled if the SSRT

reads a value of logic "1" for the respective data bit.

The auto-configuration parameters are defined by Table 2.

The timing signals pertaining to Auto-Configuration mode are

illustrated in FIGURE 12.

REQ_DT

DTACK

DTGRT

REQ_DT

MSTCLR

DTACK

CFG_AUTO

FIGURE 3. RT RECEIVE COMMAND (BURST MODE) TIMING

1553 BUS RX COMMAND DATA #2DATA #1 STATUS

L-BRO, T/R, SA4-SA0

WC/MC/CWC

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

MID-PARITY MID-PARITY

MID-PARITY MID-PARITY MID-SYNC

BURST

DATA

WRITE

TRANSFER

t11

t12

t15

PREVIOUS MSG cwc

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t4 t8

WC / MC WC / MCCWC = 0 CWC = 1

RT RECEIVE COMMAND (BURST MODE)

t14

t13

t10

NOTE 1

NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD

is referenced from the rising edge of GBR.

(Refer to FIGURE 9 on page 22)

TABLE FOR FIGURE 3. RT RECEIVE COMMAND TIMING (BURST MODE)

RESPONSE TIMEREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX UNITS

t1 Mid-parity crossing of received command word delay to

SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL 1.5 µs

t2 Mid-parity crossing of received command word delay to

falling edge of INCMD ALL 2 µs

t3 Mid-Parity crossing of receive command word delay to

MSG_ERR and HS_FAIL rising ALL 1.5 µs

t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time

from SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL 400 ns

t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD

low. ALL 500 ns

t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following

falling edge of INCMD ALL 300 ns

t7 Mid-parity crossing of first data word to WC/CWC valid data

of 1Fh ALL 1 µs

t8 Duration of WC/CWC data value of 1Fh ALL 200 ns

t9 RT Response time. ALL 4 6.5 7 µs

t10 CWC transition to next word following mid-parity of

subsequent received data words. ALL 1 µs

t11 Mid-parity crossing of last data word to DTREQ falling edge

(requesting data word burst write transfer) ALL 4 4.5 5.25 µs

t12 Mid-Sync crossing of Status response to RT_FAIL rising ALL 1.5 µs

t13 CWC valid following falling edge of DTREQ ALL 30 ns

20 MHz 100 ns

16 MHz 125 ns

12 MHz 167 ns

t14 GBR pulse width (see Note 1)

10 MHz 200 ns

t15 Mid-parity crossing of status word to INCMD rising ALL 3 µs

FIGURE 4. RT RECEIVE COMMAND (NON-BURST MODE) TIMING

1553 BUS RX COMMAND DATA #2DATA #1 STATUS

L-BRO, T/R, SA4-SA0

WC/MC/CWC

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

MID-PARITY MID-PARITY

MID-PARITY MID-PARITY MID-SYNC

t13

t16

t2 t12

t17

t11

PREVIOUS MSG CWC = 1 WC / MC

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t4 t9

t10

WC / MC CWC = 0

RT RECEIVE COMMAND (NON-BURST MODE)

t14

t15

SINGLE

WORD

WRITE

DATA WORD

SINGLE

WORD

WRITE

DATA WORD

(Refer to FIGURE 10 on page 24)

TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (NON-BURST MODE)

RESPONSE TIME UNITSREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX

t1 Mid-parity crossing of received command word delay to SA4-SA0, L-BRO,

T/R Bit, and WC/MC valid ALL 1.5 µs

t2 Mid-parity crossing of received command word delay to falling edge of

INCMD ALL 2 µs

t3 Mid-Parity crossing of receive command word delay to MSG_ERR and

HS_FAIL rising ALL 1.5 µs

t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0,

L-BRO, T/R, and CWC/MC valid ALL 400 ns

t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns

t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge

of INCMD ALL 300 ns

t7 Mid-parity crossing to WC/CWC value of 1Fh ALL 1 µs

20 MHz 1.2 µs

16 MHz 1.25 µs

12 MHz 1.33 µs

t8 Mid-parity crossing of first data word to DTREQ falling edge

10 MHz 1.4 µs

20 MHz 200 ns

16 MHz 250 ns

12 MHz 333 ns

t9 WC/CWC data value of 1Fh held

10 MHz 400 ns

t10 CWC valid following falling edge of DTREQ ALL 30 ns

t11 RT Response time. ALL 4 6.5 7 µs

t12 Delay from following mid-parity of last received data word to GBR low.

(see Notes 1, 2) ALL 4 µs

t13 Mid-parity crossing of all data words, except first data word, to DTREQ

falling edge ALL 1 µs

20 MHz 100 ns

16 MHz 125 ns

12 MHz 167 ns

t14 GBR pulse width

10 MHz 200 ns

20 MHz 75 ns

16 MHz 94 ns

12 MHz 125 ns

t15 CWC transition to WC prior to Mid-Sync crossing of Status response.

10 MHz 150 ns

t16 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 µs

t17 Mid Parity crossing of status word to INCMD rising ALL 3.0 µs

Notes:

1. Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low

will increase by the amount of the DTGRT(low) - to - DTGRT(low) delay.

2. The transceiver delays are measured at a range of 150 ns to 450 ns for the receiver

and 100 ns to 250 ns for the transmitter.

FIGURE 5. RT TRANSMIT COMMAND TIMING

1553 BUS TX COMMAND DATA #2DATA #1

STATUS

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

MID-PARITY MID-SYNC MID-PARITYMID-SYNC MID-SYNC

SINGLE

WORD

READ

DATA WORD

SINGLE

WORD

READ

DATA WORD

t15

t10

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t13

t14

RT TRANSMIT COMMAND

L-BRO, T/R, SA4-SA0

WC/MC/CWC

PREVIOUS MSG cwc = 1

t11

t12

WC WCCWC = 0

(Refer to FIGURE 11 on page 26)

TABLE FOR FIGURE 5. RT TRANSMIT COMMAND TIMING VALUEREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX UNITS

t1 RT Response time. ALL 4 6.5 7 µs

t2 Mid-parity crossing of received command word delay to L-BRO,

T/R Bit, SA4-SA0, and WC/MC valid ALL 1.5 µs

t3 Mid-parity crossing of received command word delay to falling

edge of INCMD ALL 2 µs

t4 Mid-Parity crossing of receive command word delay to

MSG_ERR and HS_FAIL rising ALL 1.5 µs

t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from

SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL 400 ns

t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD

low ALL 500 ns

t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following

falling edge of INCMD ALL 300 ns

t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh ALL 6.5 µs

20 MHz 6.75 µs

16 MHz 6.81 µs

12 MHz 6.92 µs

t9 Mid-Sync crossing of status word to DTREQ falling edge

10 MHz 7 µs

t10 Mid-Sync crossing of Status response to RT_FAIL rising (see

Note 1) ALL 1.5 µs

20 MHz 200 ns

16 MHz 250 ns

12 MHz 333 ns

t11 Duration of WC/CWC value of 1Fh

10 MHz 400 ns

t12 CWC valid following falling edge of DTREQ ALL 30 ns

20 MHz 1.75 µs

16 MHz 1.81 µs

12 MHz 1.92 µs

t13 Mid-Sync crossing of received data word to DTREQ falling edge

10 MHz 2 µs

20 MHz 1.55 µs

16 MHz 1.56 µs

12 MHz 1.59 µs

t14 Mid-Sync crossing of last received data word for CWC to

transition to WC

10 MHz 1.6 µs

t15 Mid Parity crossing of status word to INCMD rising ALL 3 µs

NOTE1: Assuming that RTFAIL was previously low.

FIGURE 6. RT - RT TRANSMIT TIMING

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

SINGLE

WORD

READ

DATA WORD

SINGLE

WORD

READ

DATA WORD

t15

t10

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t13

t14

RT - RT TRANSMIT COMMAND

L-BRO, T/R, SA4-SA0

WC/MC/CWC

PREVIOUS MSG cwc = 1

t11

t12

WC WCCWC = 0

1553 BUS RX COMMAND STATUS

TX COMMAND DATA #1

MID-PARITY MID-PARITY

MID-SYNC MID-SYNC MID-SYNC

DATA #2 STATUS

(Refer to FIGURE 11 on page 26)

TABLE FOR FIGURE 6. RT–RT TRANSMIT COMMAND TIMING VALUEREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX UNITS

t1 RT – RT response timeout for transmitting RT. ALL 17.5 18.5 19.5 µs

t2 Mid-parity crossing of received command word delay to L-BRO,

T/R Bit, SA4-SA0, and WC/MC valid ALL 1.5 µs

t3 Mid-parity crossing of received command word delay to falling

edge of INCMD ALL 2 µs

t4 Mid-Parity crossing of receive command word delay to

MSG_ERR and HS_FAIL rising ALL 1.5 µs

t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from

SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL 400 ns

t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD

low ALL 500 ns

t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following

falling edge of INCMD ALL 300 ns

t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh ALL 6.5 µs

20 MHz 6.75 µs

16 MHz 6.81 µs

12 MHz 6.92 µs

t9 Mid-Sync crossing of status word to DTREQ falling edge

10 MHz 7 µs

t10 Mid-Sync crossing of Status response to RT_FAIL rising ALL 1.5 µs

20 MHz 200 ns

16 MHz 250 ns

12 MHz 333 ns

t11 Duration of WC/CWC value of 1Fh

10 MHz 400 ns

t12 CWC valid following falling edge of DTREQ ALL 30 ns

20 MHz 1.75 µs

16 MHz 1.81 µs

12 MHz 1.92 µs

t13 Mid-Sync crossing of received data word to DTREQ falling edge

10 MHz 2 µs

20 MHz 1.55 µs

16 MHz 1.56 µs

12 MHz 1.59 µs

t14 Mid-Sync crossing of last received data word for CWC to

transition to WC

10 MHz 1.6 µs

t15 Mid Parity crossing of status word to INCMD rising ALL 3 µs

FIGURE 7. RT - RT RECEIVE (BURST-MODE) TIMING

L-BRO, T/R,

SA4-SA0

WC/MC/CWC

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

MID-PARITY MID-PARITY

MID-PARITY MID-PARITY MID-SYNC

BURST

DATA

WRITE

TRANSFER

t12

t13

t16

t10

PREVIOUS MSG cwc

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t4 t9

WC / MC WC / MC

CWC = 0 CWC = 1

RT - RT RECEIVE COMMAND (BURST MODE)

t15

t14

t11

NOTE 1

NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD

is referenced from the rising edge of GBR.

1553 BUS RX COMMAND STATUSTX COMMAND DATA #1

MID-PARITY MID-SYNC

t7 DATA #2 STATUS

(Refer to FIGURE 9 on page 22)

TABLE FOR FIGURE 7. RT-RT RECEIVE COMMAND TIMING (BURST MODE)

RESPONSE TIMEREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX UNITS

t1 Mid-parity crossing of received command word delay to SA4-SA0,

L-BRO, T/R Bit, and WC/MC valid ALL 1.5 µs

t2 Mid-parity crossing of received command word delay to falling

edge of INCMD ALL 2 µs

t3 Mid-Parity crossing of receive command word delay to

MSG_ERR and HS_FAIL rising ALL 1.5 µs

t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from

SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL 400 ns

t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns

t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following

falling edge of INCMD ALL 300 ns

t7 RT – RT response timeout for transmitting RT. ALL 17.5 18.5 19.5 µs

t8 Mid-parity crossing of first data word to WC/CWC valid data of

1Fh ALL 1 µs

t9 Duration of WC/CWC data value of 1Fh ALL 200 ns

t10 RT Response time. ALL 4 6.5 7 µs

t11 CWC transition to next word following mid-parity of subsequent

received data words. ALL 1 µs

t12 Mid-parity crossing of last data word to DTREQ falling edge

(requesting data word burst write transfer) ALL 4 4.5 5.25 µs

t13 Mid-Sync crossing of Status response to RT_FAIL rising ALL 1.5 µs

t14 CWC valid following falling edge of DTREQ ALL 30 ns

20 MHz 100 ns

16 MHz 125 ns

12 MHz 167 ns

t15 GBR pulse width (see Note 1)

10 MHz 200 ns

t16 Mid-parity crossing of status word to INCMD rising ALL 3 µs

FIGURE 8. RT - RT RECEIVE (NON-BURST-MODE) TIMING

L-BRO, T/R,

SA4-SA0

WC/MC/CWC

INCMD

DTREQ

DTGRT

DTACK

GBR

MEMWR

MEMOE

D15-D0

RT_FAIL

MSG_ERR

HS_FAIL

t14

t17

t2 t13

t18

PREVIOUS MSG CWC = 1 WC / MC

ILLEGAL, SRV_RQST

SSFLAG, BUSY VALID

t4 t10

t11

WC / MC CWC = 0

RT - RT RECEIVE COMMAND (NON-BURST MODE)

t15

t16

SINGLE

WORD

WRITE

DATA WORD

SINGLE

WORD

WRITE

DATA WORD

MID-PARITY MID-PARITY

MID-PARITY MID-PARITY MID-SYNC

t12

1553 BUS RX COMMAND STATUS

TX COMMAND DATA #1

MID-PARITY MID-SYNC

t7 DATA #2 STATUS

(Refer to FIGURE 10 on page 24)

TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE)

RESPONSE TIMEREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX UNITS

t1 Mid-parity crossing of received command word delay to SA4-SA0, L-

BRO, T/R Bit, and WC/MC valid ALL 1.5 µs

t2 Mid-parity crossing of received command word delay to falling edge of

INCMD ALL 2 µs

t3 Mid-Parity crossing of receive command word delay to MSG_ERR and

HS_FAIL rising ALL 1.5 µs

t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-

SA0, L-BRO, T/R, and CWC/MC valid ALL 400 ns

t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns

t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge

of INCMD ALL 300 ns

t7 RT – RT response timeout for transmitting RT. ALL 17.5 18.5 19.5 µs

t8 Mid-parity crossing to WC/CWC value of 1Fh ALL 1 µs

20 MHz 1.2 µs

16 MHz 1.25 µs

12 MHz 1.33 µs

t9 Mid-parity crossing of first data word to DTREQ falling edge

10 MHz 1.4 µs

20 MHz 200 ns

16 MHz 250 ns

12 MHz 333 ns

t10 WC/CWC data value of 1Fh held

10 MHz 400 ns

t11 CWC valid following falling edge of DTREQ ALL 30 ns

t12 RT Response time. ALL 4 6.5 7 µs

t13 Delay from following mid-parity of last received data word to GBR low.

(see notes 1, 2) ALL 4 µs

t14 Mid-parity crossing of all data words, except first data word, to DTREQ

falling edge ALL 1 µs

20 MHz 100 ns

16 MHz 125 ns

12 MHz 167 ns

t15 GBR pulse width

10 MHz 200 ns

20 MHz 75 ns

16 MHz 94 ns

12 MHz 125 ns

t16 CWC transition to WC prior to Mid-Sync crossing of Status response.

10 MHz 150 ns

t17 Mid-Sync crossing of status response to RT_FAIL rising ALL 1.5 µs

t18 Mid Parity crossing of status word to INCMD rising ALL 3.0 µs

Notes:

1. Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low

will increase by the amount of the DTGRT(low) - to - DTGRT(low) delay.

2. The transceiver delays are measured at a range of 150 ns to 450 ns for the receiver

and 100 ns to 250 ns for the transmitter.

FIGURE 9. DMA WRITE TRANSFER (BURST-MODE) TIMING

CLOCK IN

DTREQ

DTGRT

DTACK

MEMWR

MEMOE

WC/MC/CWC

D15-D0 DATA VALIDDATA VALID

t1 t2

t4 t8

t11 t12 t13

t15

t10

t14 t16

t10

t14

t19 t20

t17

L-BRO, T/R,

SA4-SA0 VALID

GBR

INCMD

CWC = 0 CWC = 1 WC

t18 t21

DMA WRITE - BURST MODE

(SHOWN FOR TWO DATA WORDS)

1 INCMD rising edge is shown for the case of a RX Broadcast command message.

For the non-Broadcast case, INCMD rising edge is after the Mid-Parity crossing of the RT STATUS response.

TABLE FOR FIGURE 9. SSRT DMA WRITE (BURST MODE) TIMING

VALUE @ 5 Volts VALUE @ 3.3 Volts UNITSREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX MIN TYP MAX

t1 CLOCK IN rising to DTREQ low ALL 40 40 ns

t2 DTREQ falling to DTGRT low ALL 10 10 µs

20 MHz 60 60 ns

16 MHz 85 85 ns

12 MHz 127 127 ns

t3 CWC setup time prior to MEMWR falling for first

word of burst transfer (see Note 1)

10 MHz 160 160 ns

t4 DTGRT low setup prior to CLOCK IN rising edge ALL 10 15 ns

20 MHz 100 105 ns

16 MHz 113 118 ns

12 MHz 133 138 ns

t5 DTGRT falling to DTACK low

10 MHz 150 155 ns

t6 CLOCK IN rising to DTACK low ALL 40 40 ns

t7 Data output valid following CLOCK IN ALL 40 40 ns

t8 DTGRT hold time following DTACK falling ALL 30 30 ns

20 MHz 290 300 290 300 ns

16 MHz 365 375 365 375 ns

12 MHz 490 500 490 500 ns

t9 DTACK low pulse width (based on a two data

word transfer) (see Note 2)

10 MHz 590 600 590 600 ns

20 MHz 10 10 ns

16 MHz 22 22 ns

12 MHz 43 43 ns

t10 Data output setup time prior to MEMWR low

10 MHz 60 60 ns

t11 CLOCK IN rising to MEMWR low ALL 40 40 ns

20 MHz 40 50 40 50 ns

16 MHz 52.5 62.5 52.5 62.5 ns

12 MHz 73.3 83.3 73.3 83.3 ns

t12 MEMWR low pulse width

10 MHz 90 100 90 100 ns

t13 CLOCK IN rising to MEMWR high ALL 30 40 ns

20 MHz 20 10 ns

16 MHz 33 23 ns

12 MHz 53 43 ns

t14 Data output and CWC hold time following

MEMWR high

10 MHz 70 60 ns

t15 Data output hold time following CLOCK IN rising ALL 10 15 ns

20 MHz 10 10 ns

16 MHz 23 23 ns

12 MHz 43 43 ns

t16 CWC (all but first data word) setup time prior to

MEMWR low

10 MHz 60 60 ns

t17 CLOCK IN rising to DTREQ and DTACK high ALL 30 40 ns

t18 Data output signal Tri-State following CLOCK IN

rising ALL 40 40 ns

t19 CLOCK IN rising to GBR falling edge ALL 40 40 ns

20 MHz 90 100 90 100 ns

16 MHz 115 125 115 125 ns

12 MHz 157 167 157 167 ns

t20 GBR low pulse width

10 MHz 190 200 190 200 ns

t21 INCMD rising following CLOCK IN rising

(see Note 3) ALL 30 40 ns

Notes:

1. Assume DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of

the DTREQ(low)-to-DTGRT(low) delay.

2. DTACK pulse width is 3 clock cycles per data word transfer

3. Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising

edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock

cycles: 9.6 µs at 10 MHz, 8 µs at 12 MHz, 6.0 µs at 16 MHz, or 4.8 µs at 20 MHz.

FIGURE 10. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING

CLOCK IN

DTREQ

DTGRT

DTACK

MEMWR

MEMOE

WC/MC/CWC

D15-D0 DATA VALID

t1t2

t4 t8

t11 t12 t13

t17

t16

t7 t14

t10

t15

L-BRO, T/R,

SA4-SA0 VALID

CWC = 0

NON-BURST DMA WRITE

NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle.

TABLE FOR FIGURE 10. SSRT DMA WRITE TIMING (NON-BURST)

VALUE @ 5 Volts VALUE @ 3.3 Volts UNITSREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX MIN TYP MAX

t1 CLOCK IN rising to DTREQ low ALL 40 40 ns

t2 DTREQ (low)-to-DTGRT (low) delay time ALL 10 10 µs

20 MHz 110 110 ns

16 MHz 148 148 ns

12 MHz 210 210 ns

t3 CWC setup time prior to MEMWR falling

(see Note)

10 MHz 260 260 ns

t4 DTGRT low setup prior to CLOCK IN rising ALL 10 15 ns

20 MHz 100 105 ns

16 MHz 113 118 ns

12 MHz 133 138 ns

t5 DTGRT falling to DTACK low

10 MHz 150 155 ns

t6 CLOCK IN rising to DTACK low ALL 40 40 ns

t7 Data output valid following CLOCK IN rising ALL 40 40 ns

t8 DTGRT hold time following DTACK falling ALL 30 30 ns

20 MHz 200 200 ns

16 MHz 250 250 ns

12 MHz 333 333 ns

t9 DTACK low pulse width

10 MHz 400 400 ns

20 MHz 60 60 ns

16 MHz 85 85 ns

12 MHz 127 127 ns

t10 Data output setup time prior to MEMWR low

10 MHz 160 160 ns

t11 CLOCK IN rising to MEMWR low ALL 40 40 ns

20 MHz 40 50 40 50 ns

16 MHz 52.5 62.5 52.5 62.5 ns

12 MHz 73.3 83.3 73.3 83.3 ns

t12 MEMWR low pulse width

10 MHz 90 100 90 100 ns

t13 CLOCK IN rising to MEMWR high ALL 40 40 ns

20 MHz 20 10 ns

16 MHz 33 23 ns

12 MHz 53 43 ns

t14 Data output hold time following MEMWR high

10 MHz 70 60 ns

t15 CLOCK IN rising to DTREQ and DTACK high ALL 30 40 ns

t16 Data output hold time following CLOCK IN rising ALL 10 15 ns

t17 Data output signal Tri-State following CLOCK IN

rising ALL 40 40 ns

Note:

Assume that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time

from DTREQ (low) to DTGRT (low).

FIGURE 11. DMA READ TRANSFER TIMING

CLOCK IN

DTREQ

DTGRT

DTACK

MEMWR

MEMOE

WC/CWC

D15-D0 DATA VALID

t1 t2

t4 t7

t10

t11

t13

t12

L-BRO, T/R,

SA4-SA0 VALID

CWC = 0

DMA SINGLE WORD READ

TABLE FOR FIGURE 11. SSRT DMA READ TIMING

VALUE @ 5 Volts VALUE @ 3.3 VoltsREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX MIN TYP MAX UNITS

t1 CLOCK IN rising to DTREQ low ALL 40 40 ns

t2 DTREQ (low)-to-DTGRT delay time ALL 10 10 µs

20 MHz 60 60 ns

16 MHz 85 85 ns

12 MHz 127 127 ns

t3 CWC setup time prior to MEMOE falling

10 MHz 160 160 ns

t4 DTGRT low setup prior to CLOCK IN rising ALL 10 10 ns

20 MHz 100 105 ns

16 MHz 113 118 ns

12 MHz 133 138 ns

t5 DTGRT falling to DTACK low

10 MHz 150 155 ns

t6 CLOCK IN rising to DTACK low ALL 40 40 ns

t7 DTGRT hold time following DTACK falling ALL 30 30 ns

20 MHz 200 200 ns

16 MHz 250 250 ns

12 MHz 333 333 ns

t8 DTACK low pulse width

10 MHz 400 400 ns

t9 CLOCK IN rising to MEMOE low ALL 40 40 ns

20 MHz 150 150 ns

16 MHz 188 188 ns

12 MHz 250 250 ns

t10 MEMOE low pulse width

10 MHz 300 300 ns

20 MHz 80 70 ns

16 MHz 105 95 ns

12 MHz 146 136 ns

t11 Time for input data to become valid

following falling edge of MEMOE

10 MHz 180 170 ns

t12 Data input hold time following CLOCK IN

rising (see Note) ALL 30 30 ns

t13 CLOCK IN rising to DTREQ, DTACK, and

MEMOE high ALL 30 40 ns

Note:

The SSRT’s data sampling time occurs one clock cycle prior to the rising edge of MEMOE.

FIGURE 12. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING

CLOCK IN

DTREQ

DTGRT

DTACK

MEMWR

MEMOE

D15-D0

MSTCLR

RTACTIVE

DATA VALID

t2 t3

t4 t7

t11

t13

note1

t10

t12

AUTO-CONFIGURATION - DMA SINGLE WORD READ

Note1: RTACTIVE asserted high 1 clock following DTACK high asumming self-test is not enabled.

When self-test is enabled RTACTIVE is delayed inthe amount of 't12'.

See the table reference for details.

TABLE FOR FIGURE 12. AUTO-CONFIGURATION – DMA READ TIMING

VALUE @ 5 Volts VALUE @ 3.3 VoltsREF DESCRIPTION CLOCK

FREQUENCY MIN TYP MAX MIN TYP MAX UNITS

20 MHz 50 50 ns

16 MHz 62.5 62.5 ns

12 MHz 83.3 83.3 ns

t1 MSTCLR high delay to DTREQ low

10 MHz 100 100 ns

t2 CLOCK IN rising to DTREQ low ALL 40 40 ns

t3 DTREQ (low)-to-DTGRT delay time ALL 10 10 µs

t4 DTGRT low setup prior to CLOCK IN rising ALL 10 10 ns

20 MHz 100 105 ns

16 MHz 113 118 ns

12 MHz 133 138 ns

t5 DTGRT falling to DTACK low

10 MHz 150 155 ns

t6 CLOCK IN rising to DTACK low ALL 40 40 ns

t7 DTGRT hold time following DTACK falling ALL 30 30 ns

20 MHz 200 200 ns

16 MHz 250 250 ns

12 MHz 333 333 ns

t8 DTACK low pulse width

10 MHz 400 400 ns

20 MHz 120 120 ns

16 MHz 157 157 ns

12 MHz 220 220 ns

10 MHz 270 270 ns

t10 Data input hold time following sampling time

(see Note 1) ALL 30 30 ns

t11 CLOCK IN rising to DTREQ, DTACK, and

MEMOE high ALL 30 40 ns

20 MHz 1.6 1.6 ms

16 MHz 2.0 2.0 ms

12 MHz 2.7 2.7 ms

t12 RTACTIVE high delayed from DTACK high

(see Note 2)

10 MHz 3.2 3.2 ms

t13 CLOCK IN rising to RTACTIVE high ALL 30 40 ns

Notes:

1: During Auto-Configuration the SSRT samples data three clock cycles following the falling edge of DTACK.

2: If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK.

If self-test is enabled then RTACTIVE will be delayed from going active high in accordance with ‘t12’.

47.5

68.3

77.5

98.3

115

47.5

68.3

77.5

98.3

115

Time for input data to become valid

following falling edge of DTACK

185

235

318

385

215

265

348

415

215

265

348

415

185

235

318

385

FIGURE 13. CLOCK EDGE SIGNAL TIMING

CLOCK IN

SIGNAL IN

SIGNAL OUT

HIGH TO LOW

SIGNAL OUT

LOW TO HIGH

CLOCK EDGE TO SIGNAL IN / OUT TIMING

TABLE FOR FIGURE 13. SSRT CLOCK EDGE TO SI GNAL I N / OUT VALI D TIMING

VALUE @ 5 Volts VALUE @ 3.3 VoltsREF DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t1 SIGNAL INPUT setup time prior to CLOCK IN rising edge 10 15 ns

t2 CLOCK IN rising edge to SIGNAL OUTPUT driven low

(see Note) 40 40 ns

t3 CLOCK IN rising edge to SIGNAL OUTPUT driven high

(see Note) 30 40 ns

Note:

Assumes a 50pf external load. For loading above 50 pf, the validity of output signals is del ayed by

an additional 0.14 ns/pf typ, 0.28 ns/pf max.

INTERFACE TO MIL-STD-1553 BUS

FIGURE 14 illustrates the interface between the BU-61703/5

SSRT and a MIL-STD-1553 bus. Connections for both direct

(short stub) coupling and transformer (long stub) coupling, as

well as the peak-to-peak voltage levels at various points (when

transmitting), are indicated in the diagram.

BU-61703/5

SSRT

DATA

BUS

55 Ω

(1:2.5)

11.6 Vpp 28 Vpp

1 FT MAX

(1:1.79)

11.6 Vpp 20 Vpp

(1:1.41)

COUPLING

TRANSFORMER

0.75 Z0

LONG STUB

(TRANSFORMER

COUPLED)

20 FT MAX

28Vpp

SHORT STUB

(DIRECT COUPLED)

NOTE: Z0= 70 TO 85 OHMS

ISOLATION

TRANSFORMER

ISOLATION

TRANSFORMER

NOTES:

1. Shown for one of two redundant buses that interface to the BU-61703/5 hybrid.

2. Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal, 9 Vp-p max.

3. Transmitted voltage for a transformer-coupled stub is 18 Vp-p min, 27 Vp-p max for

MIL-STD-1553B; 20 Vp-p min, 27 Vp-p max for MIL-STD-1760.

4. Required tolerance on isolation resistors is 2%. Instantaneous power dissipation

(when transmitting) is approximately 0.45 W typ, 0.8 W (max) for each isolation resistor.

FIGURE 14. SSRT INTERFACE TO MIL-STD-1553 BUS.

PULSE TRANSFORMERS

In selecting isolation transformers to be used with the Simple

System R T, there is a limitation on the maximum amount of leak-

age inductance. If this limit is exceeded, the transmitter rise and

f all times may increase , possibly causing the b us amplitude to fall

below the minimum level required by MIL-STD-1553.In addition,

an excessive leakage imbalance may result in a transformer

dynamic offset that exceeds 1553 specifications.

The maximum allowable leakage inductance is 6.0 µH, and

is measured as follows:

The side of the transformer that connects to the

Simple System RT is defined as the “primary”winding. If one

side of the primary is shorted to the primary center-tap, the

inductance should be measured across the “secondary”(stub

side) winding. This inductance must be less than 6.0 µH.

Similarly, if the other side of the primar y is shorted to the pr ima-

ry center-tap, the inductance measured across the “secondary”

(stub side) winding must also be less than 6.0 µH.

The difference between these two measurements is the

“differential”leakage inductance. This value must be less than

1.0 µH.

Beta Transformer Technology Corporation (BTTC), a subsidiary

of DDC, manufactures transformers in a variety of mechanical

configurations with the required turns ratios of 1:2.5 direct cou-

pled, and 1:1.79 transformer coupled. TABLE 4 provides a listing

of many of these transformers.

For further information, contact BTTC at 631-244-7393 or at

www.bttc-beta.com.

NOTES:

1. F or McAIR v ersion of the Simple System R T (BU-6170XX4), only the B-3818 or B-3819 transf ormers (shown in bold in the table) ma y be used.

2. For all other applications, any of the other transfor mers listed may be used.

TABLE 4. RECOMMENDED BETA TRANSFORMERS FOR USE WITH SSRT

B-3819

Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height.

(May be used with BU-6170XX4 version of SSRT)

B-3310Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155 max height

B-3261Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155 max height

B-3300

LPB-5015

Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155 max height

B-3818

HLP-6015Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height

HLP-6014Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height

TST-9027Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height

TST-9017Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height

TST-9007Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height

LPB-5014Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height

B-3227Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height

B-3231Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height

B-3226Single epoxy transformer, through-hole, 0.625 X 0.625, 0.250" max height

BTTC PART NO.TRANSFORMER CONFIGURATION

Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height

Single epoxy transformer, through-hole, 0.625 X 0.625, 0.220" max height.

(May be used with BU-6170XX4 version of SSRT)

P.C. BOARD LAYOUT GUIDELINES

GROUND PLANES

As is the rule in all high-speed digital circuits, it is good practice

to use ground and power supply planes under the SSRT hybrid

as well as the associated digital components.

The reason f or not using supply or ground planes under the ana-

log signal traces is that the effect of the distributed capacitance

will be to lower the input impedance of the terminal, as seen from

the 1553 bus. MIL-STD-1553 requires a minimum input imped-

ance of 2000 ohms for direct coupled ter minals and 1000 ohms

for transformer (stub) coupled terminals. If there are ground

planes under the analog bus signal tr aces, it is likely that the ter-

minal will not meet this requirement.

POWER AND GROUND DISTRIBUTION

Another important consideration is power and ground distribu-

tion.Refer to FIGURE 16.For the SSR T hybrid/transformer com-

bination, the high current path when the SSR T is transmitting will

be from the +5 volt power supply, through the transmitter output

stage, through one leg of the isolation transformer to the trans-

former center tap. It is impor tant to realize that the high current

return path is through the transformer center tap and not through

the SSRT GROUND pins.

Another impor tant layout consideration is to minimize the power

supply distribution impedance along this path.Any resistance will

result in voltage drops for the power supply input voltage, and

can ultimately lower the transmitter output voltage, possibly

below the minimum level required by MIL-STD-1553 or

MIL-STD-1760.

However, it is very important that there be NO ground

and/or power supply planes underneath the analog bus

signal traces. This applies to the TX/RX signals running

between the SSRT and the isolation transformers as well

as the traces between the transformers to any connectors

or cables leaving the board.

FIGURE 16. POWER - GROUND DISTRIBUTION

LOGIC RX TRANSCEIVER

HIGH LEVEL

CURRENTS

LOW LEVEL

CURRENTS

LOW / MEDIUM

LEVEL

CURRENTS

LOGIC

GND GND A/B

LOGIC

+5 V A/B

+5 V

+3.3 V

SSRT

1553 BUS CONNECTIONS

The isolation transformers should be placed as physically close

as possible to the respective TX/RX pins on the SSRT. In addi-

tion, the distance from the isolation transformers to any connec-

tors or cables leaving the board should be as shor t as possible.

In addition to limiting the voltage drops in the analog signal

traces when transmitting, reducing the hybrid-to-transformer and

transformer-to-connector spacing serves to minimize crosstalk

from other signals on the board.

The general practice in connecting the stub side of a tr ansf ormer

(or direct) coupled terminal to an external system connector is to

make use of 78 ohm twisted-pair shielded cable.This minimizes

impedance discontinuities.The decision of whether to isolate or

make connections between the center tap of the isolation trans-

for mer's secondar y, the stub shield, the bus shield, and/or chas-

sis ground must be made on a system basis, as determined by

an analysis of EMI/RFI and lightning considerations.

In most systems, it is specified that the 1553 terminal's input

impedance must be measured at the system connector. This is

despite the fact that the MIL-STD-1553B requirement is for it to

be measured looking directly in from the bus side of the isolation

transformer.

The effect of a relatively long stub cable will be to reduce the

measured impedance (looking in from the bus). In order to keep

the impedance above the required level of 1000 ohms (for trans-

f ormer-coupled stubs), the length of any cable betw een the 1553

RT and the system connector should be minimized.

"SIMULATED BUS" (LAB BENCH) INTERCON-

NECTIONS

For purposes of software development and system integration, it

is generally not necessary to integrate the required couplers, ter-

minators, etc., that comprise a complete MIL-STD-1553B bus. In

most instances, a simplified electrical configuration will suffice.

The three connection methods illustrated in FIGURE 17 allow

the SSRT to be interfaced over a "simulated bus" to simulation

and test equipment. It is important to note that the termination

resistors indicated are necessary in order to ensure reliab le com-

munications between the SSRT and the simulation/test

equipment.

FIGURE 17. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS

SSRT

HYBRID TEST/

SIMULATION

EQUIPMENT

STUB

COUPLING

STUB

COUPLING

ISOLATION

TRANSFORMER

78Ω

1.5W

(A)

SSRT

HYBRID TEST/

SIMULATION

EQUIPMENT

DIRECT

COUPLING

DIRECT

COUPLING

ISOLATION

TRANSFORMER

39Ω

0.5W

(B)

55Ω

SSRT

HYBRID TEST/

SIMULATION

EQUIPMENT

STUB

COUPLING

DIRECT

COUPLING

ISOLATION

TRANSFORMER

39Ω

0.5W

(C)

55Ω

20Ω

0.5W

20S

0.5W

(A) TRANSFORMER COUPLED TO TRANSFORMER COUPLED

(B) DIRECT COUPLED TO DIRECT COUPLED

SIMPLE SYSTEM INTERFACE

FIGURE 15 illustrates the capability of the SSRT to interface to

a system with no host processor in burst mode. In this example,

only one set of external latches is needed to buffer the data

words written by the SSR T to the e xternal system.In burst mode ,

all received data words are stored in the internal FIFO until the

last word is received. At this point, the SSRT will transfer the

entire contents of the FIFO to the system if the message is vali-

dated. In this case, will be dr iven low for two clock cycles

following the burst transfer cycle.

If the received message is not valid, the FIFO data will not be

transferred to the external system and will remain high.

GBR

FIGURE 15. SSRT-TO-SIMPLE SYSTEM INTERFACE (Shown for BURST MODE)

D15-D0

Write

Address

Decoder

Read

Address

Decoder

LATCH

TRI-STATE

BUFFER

TRI-STATE

BUFFER

TRI-STATE

BUFFER

L-BRO , T/R, SA4-0,

WC/CWC4-0

MEMWR

DISCRETE

DIGITAL

INPUTS

DISCRETE

DIGITAL

OUTPUTS

AUTO-

CONFIGURATION

(OPTIONAL)

RTACTIVE

DTACK

AUTO_CFG

MEMOE

BU-61703/5

SSRT

Clock

Oscillator CLK-IN

RTAD4-0, RTADP

MSTCLR

+5V

ADDRESS

BUS A

BUS B

DTGRT

+5V

BIT WORD

The BU-61703/5 provides an internally formulated Built-In-Test

word (BIT word).This word is transmitted to the BC in response to a Transmit BIT Word Mode Code Command.The BIT word bit

functions and descriptions are provided in Table 5.

If set, indicates that, for the previous message, the SSRT was the receiving RT for an RT-to-RT trans-

fer and that the transmitting RT either did not respond or responded later than the SSRT RT-to-RT

timeout time.The SSRT's RT-to-RT response timeout time is defined as the time from the mid-bit

crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the transmitting

RT status word.The value of the SSRT's RT-to-RT response timeout time is in the range from 17.5 to

19.5 µs.

Indicates that a received command word is not defined in accordance with MIL-STD-1553B.This

includes the following undefined Command Words: (1) The Command Word is a non-mode code,

broadcast, transmit command; (2) a message with a T/R bit of "0", a subaddress/mode field of 00000

or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command

that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111.

Indicates that the SSRT received one or more words containing one or more of the following error

types: sync field error, Manchester encoding error, parity error, and/or bit count error.

This bit is set if the SSRT is the receiving RT for an RT-to-RT transfer and one or more of the following

errors occurs: (1) If the transmitting RT responds with a response time of less than 4 µs, per MIL-

STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 µs dead time; and/or (2) There is an incorrect

sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT Status Word;

and/or (3) The RT address field of the transmitting RT Status Word does not match the RT address in

the transmit Command Word.

If the SSRT is the receiving RT for an RT-to-RT transfer, if this bit is set, it indicates one or more of the

following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) subaddress =

00000 or 11111; (3) same RT Address field as the receive Command Word.

If set, indicates that the SSRT detected a Command sync in a received Data Word.

Set to logic "1" if the previous message had a low word count error.

RT-RT TRANSFER

NO RESPONSE

TIMEOUT

COMMAND WORD

CONTENTS ERROR

INVALID WORD

MANCHESTER/PARITY ERROR

RECEIVED

RT-RT TRANSFER RESPONSE

ERROR (no gap, data, sync,

address mismatch)

RT-RT TRANSFER -

T/R ERROR ON

SECOND COMMAND

INVALID ADDRESS

INCORRECT SYNC TYPE

RECEIVED

LOW WORD COUNT

0 (LSB)

6Set to logic "1" if the previous message had a high word count error.HIGH WORD COUNT7

Set to logic "1" to denote that the SSRT has failed its off-line protocol self-test.This bit will be logic "0"

if the self-test passed or had not been performed.

BIT TEST FAIL8

Set to logic "1" if the SSRT's Terminal flag RT status bit has been disabled by an Inhibit terminal flag

mode code command.Will rever t to logic "0" if an Override inhibit ter minal flag mode code command

is received.

TERMINAL FLAG INHIBITED9

If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input

DTGRT* asserted within 10 µs after the SSRT has asserted DTREQ*.

HANDSHAKE FAILURE12

A loopback test is performed on the transmitted por tion of ever y non-broadcast message. A validity

check is performed on the received version of every word transmitted by the SSRT. In addition, a bit-

by-bit comparison is performed on the last word transmitted by the RT for each message. If either the

received version of the last word does not match the transmitted version and/or the received version

of any transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe

timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective bus chan-

nel will be set.

CH. B LOOP TEST FAILURE

CH. A LOOP TEST FAILURE

Set if the SSRT's failsafe timer detected a fault condition.The transmitter timeout circuit will automati-

cally shut down the CH. A or CH. B transmitter if it transmits for longer than 660.5 µs.

TRANSMITTER TIMEOUT15 (MSB)

TABLE 5. INTERNAL BUILT-IN-TEST (BIT) WORD DEFINITION

DESCRIPTIONFUNCTIONBIT

If either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut

down by means of a Transmitter shutdown mode command.

TRANSMITTER SHUTDOWN B

TRANSMITTER SHUTDOWN A

Note:

Bits 15 through 9 are cleared only following a RESET input or receipt of a Reset Remote Terminal mode command. Bits 8 through 0 are updated

as a result of every message processed.

MODE CODES

The BU-61703/5 fully implements all 13 of the dual redundant

MIL-STD-1553B mode codes.Four mode codes, Transmit vector

word, Synchronize (with data), Selected transmitter shutdown,

and Override transmitter shutdown, involve data transfers with

the subsystem. For the Transmit last command mode command,

the data word transmitted is from the SSRT's last command

internal register. For the Transmit BIT word mode command, the

SSRT's internally formulated BIT Word is transmitted. Table 6

provides a summary of the 1553B mode codes supported by the

BU-61703/5.

SUMMARY OF RESPONSES TO MODE CODE

MESSAGES

The SSRT's responses to mode codes, including responses to

various error conditions, are summarized in Table 6.

Yes

Transmit BIT Word

Inhibit Terminal Flag

From Internal Register

10011

00110

Yes

Transmit Last Command

Override Transmitter Shutdown

From Internal Register

10010

00101

TBD

Yes

RESERVED

Tr ansmit Vector Word

Initiate Self Test

From Subsystem

10110-11111

10000

00011

Yes

TBD

Override Selected Transmitter Shutdown

(see Note)

RESERVED

Transmit Status Word

To Subsystem

10101

01001-01111

00010

Yes

Selected Transmitter Shutdown (see Note)

Reset Remote Ter minal

Synchronize

To Subsystem

10100

01000

00001

Yes

Override Inhibit Ter minal Flag

Dynamic Bus Control

00111

00000

NoUndefined No00000-011110

TABLE 6. MODE CODE SUMMARY

BROADCAST

ALLOWED

FUNCTION D A TA W ORDMODE CODET/R BIT

TBD

Yes

RESERVED

Synchronize with Data

Transmitter Shutdown

To Subsystem

10110-11111

10001

00100

Note:

For the Selected transmitter shutdown and Override transmitter shutdown mode commands, the SSRT responds with Clear Status but no action

is taken.

DETAILED MODE CODES FUNCTIONAL

DESCRIPTION

The applicable Mode Codes for the SSRT are described below:

DYNAMIC BUS CONTROL ( = 1; 00000)

MESSAGE SEQUENCE = DBC + STATUS

The SSRT responds with Status showing non-acceptance of the mode code command.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Command Word Contents Error (BIT Word).

5. Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Command Word Contents Error (BIT Word).

RT/

SYNCHRONIZE WITHOUT DATA WORD ( = 1; 00001)

MESSAGE SEQUENCE = SYNC + STATUS

The SSRT responds with Status.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Command Word Contents Error (BIT Word).

RT/

TRANSMIT STATUS WORD ( = 1; 00010)

MESSAGE SEQUENCE = TRANSMIT STATUS + STATUS

The Status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was not

a Transmit status or Transmit last command mode command).

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word)

3. bit Set to Zero .No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Command Word Contents Error (BIT Word).

5. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word),

Command Contents Error (BIT Word).

RT/

INITIATE SELF-TEST ( = 1; 00011)

MESSAGE SEQUENCE = SELF TEST + STATUS

If the command was non-broadcast, the SSRT responds with Status. If the command was either non-broadcast or broadcast, the SSRT will go

offline and perform its internal off-line protocol self-test. The self-test exercises the SSRT's encoder and decoders, registers, transmitter watchdog

timer, and protocol logic.This test is completed in approximately 32,000 clock cycles.That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16

MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz.

While the SSRT is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus.The bus

controller may determine the result of the self-test be means of a Transmit BIT word mode command. If the self-test passes, bit 8 of the SSRT's

BIT word (BIT Test Fail) will be logic "0"; if the self-test fails, this bit will be logic "1". In addition, if self-test fails, the terminal flag status word bit will

be set to logic “1”in response to the next non-broadcast message.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

5. Loopback T est Failure. Set Ter minal Flag bit in internal Status register (Status Word for next non-broadcast command),

Current Channel (A or B) Loop Test Failure and CH A/B Loop Test Failure (BIT Word), asser t output.

RTFAIL

RT/

OVERRIDE INHIBIT TERMINAL FLAG BIT ( = 1; 00111)

MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG + STATUS

The SSRT responds with Status and re-enables the Ter minal Flag bit in its inter nal Status register. If the command was a broadcast, the

Broadcast Command Received bit is set and status transmission is suppressed.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

INHIBIT TERMINAL FLAG BIT ( = 1; 00110)

MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG + STATUS

The SSRT responds with Status and inhibits further setting of the Terminal Flag bit in its internal Status Word register. Once the Terminal Flag

has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT mode code commands, or by Reset. If the com-

mand was broadcast, the Broadcast Received bit is set, the state of the Ter minal Flag bit in the inter nal Status Word register remains unchanged

and Status transmission is suppressed.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

OVERRIDE TRANSMITTER SHUTDOWN ( = 1; 00101)

MESSAGE SEQUENCE = OVERRIDE SHUTDOWN + STATUS

This command is only used with dual redundant bus systems. The SSRT responds with Status. At the end of the Status transmission, the

SSRT reactivates the transmitter of the alternate redundant bus. If the command was broadcast, the Broadcast Command Received Status

Word bit is set and status transmission is suppressed.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

TRANSMITTER SHUTDOWN ( = 1; 00100)

MESSAGE SEQUENCE =SHUTDOWN + STATUS

This command is only used with dual redundant bus systems. The SSRT responds with Status. Following the Status transmission, the SSRT

inhibits any further transmission from the alter nate redundant channel. Once shutdown, the transmitter can only be reactivated by an Override

Transmitter Shutdown or Reset RT mode command, or Hardware Reset (MSTRCLR input). Note that the receivers on both channels are always

active, even when the transmitters are inhibited.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

TRANSMIT VECT OR WORD ( = 1; 10000)

MESSAGE SEQUENCE = TRANSMIT VECTOR WORD + STATUS VECTOR WORD

The SSRT transmits a Status Word followed by a vector word.The vector word is read from the external subsystem.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word).

4. bit Set to Zero plus one Data Word. The SSRT will respond with Status

5. Zero bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Command Received bits

(Status Word), and Low Word Count (BIT word).

6. Zero bit and Broadcast Address, plus one Data Word. No Status response. Set Broadcast Command Received bits (Status Word)

7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word),

Command Word Contents Error (BIT word).

RT/

SYNCHRONIZE WITH DATA WORD ( = 0; 10001)

MESSAGE SEQUENCE = SYNCHRONIZE COMMAND/DATA WORD + STATUS

The SSRT will write the received 16 bit data word to the external subsystem.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Correct Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word)

3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), High Word Count (BIT word).

4. Command bit set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and

High Word Count (BIT Word).

5. Command bit set to One not followed by Data Word. he SSRT replies with Status plus one Data Word. The Data Word is read from

the subsystem (or single-word data block for subaddress 0000 or 1111).

6. Command bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received

bits (Status Word); Set Command Word Contents Error (BIT word).

RT/

RESERVED MODE CODES ( = 1; 01001 - 01111)

MESSAGE SEQUENCE = RESERVED MODE COMMAND + STATUS

The SSRT responds with status. If the command has been illegalized by means of the illegalization table, the Message Error Status Word bit will

be set.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

RESET REMOTE TERMINAL ( = 1; 01000)

MESSAGE SEQUENCE = RESET REMOTE TERMINAL + STATUS

The SSRT responds with Status and internally resets. The Message Error and Broadcast Command Received bits of the internal Status register

are reset to 0. The inter nal BIT Word Register is reset to 0. If either of the 1553 transmitters has been shut down, the shutdown condition is over-

ridden. If the Ter minal Flag bit has been inhibited, the inhibit is overridden.

If the command is received as a broadcast, the Broadcast Command Received bit is set and the Status Word is suppressed. Also, if the com-

mand is received as a broadcast and the Terminal Flag bit had been set as a result of the Loopback test of the previous message, the Ter minal

Flag bit is not reset to zero.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).

4. Zero bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),

Command Word Contents Error (BIT Word).

RT/

SELECTED TRANSMITER SHUTDOWN ( = 0; 10100)

MESSAGE SEQUENCE = TRANSMITER SHUTDOWN/DATA + STATUS

The Data Word received is transferred to the subsystem and Status is transmitted. No other action is taken by the SSRT. No transmitters are

shut down as a result of this mode command. This command is intended for use with RTs with more than one dual redundant channel. If the

command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count Bit (BIT Word).

No status response. Bits Set: message error (SW), High Word Count, Illegal Mode Code (BIT Word)

3. Command Followed by too many Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count Bit

(BIT Word).

4. Command bit Set to One followed by one Data Word. No Status response. Set Message Error bit (Status Word), and High Word

Count (BIT Word).

5. Command bit Set to One not followed by Data Word. The SSRT replies with Status plus one Data Word. The Data Word is read

from the subsystem.

6. Command bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits

(Status Word), and Command Contents Error (BIT Word).

RT/

TRANSMIT BIT WORD ( = 1; 10011)

MESSAGE SEQUENCE = TRANSMIT BIT WORD + STATUS/BIT WORD

The SSRT responds with Status followed by the Built-in Test (BIT) word.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word).

3. bit Set to Zero, no Data Word.No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word).

4. bit Set to Zero, plus one Data Word. The SSRT will respond with Status. The Data Word is transferred to internal registers.

5. Zero bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Low Word Count Error (BIT Word).

6. Zero bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word).The Data Word is

transferred to internal registers.

7. Broadcast Address. No Status response. Set Message Error and Broadcast Command received bits (Status Word), Command Word contents

Error (BIT Word).

RT/

TRANSMIT LAST COMMAND ( = 1; 10010)

MESSAGE SEQUENCE = TRANSMIT LAST COMMAND + STATUS/LAST COMMAND

The Status register is not updated before transmission. It contains the Status from the previous command. The Data Word transmitted contains

the previous valid command (providing it was not another TRANSMIT LAST COMMAND or TRANSMIT STATUS WORD mode command).

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word).

3. bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word).

4. bit Set to Zero, plus one Data Word. The SSRT will respond with Status. The Data Word is transferred to the internal register.

5. Zero bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word),

Low Word Count Error(BIT Word).

6. Zero bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word).The Data Word is

transferred to the internal register.

7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word

Contents Error (BIT Word).

RT/

RESERVED MODE CODES ( = 1; 11111)

MESSAGE SEQUENCE (when T/R = 1) = RESERVED MODE CODE STATUS/DATA

(when T/R = 0) = RESERVED MODE CODE DATA + STATUS

For a RESERVED receive Command, the SSRT stores the Data Word to the subsystem. If the command was a broadcast, the Broadcast

Command Received bit is set and Status transmission is suppressed. For a RESERVED transmit Command Word, the SSRT responds with

Status plus a single Data Word. The Data Word is read from the subsystem.

ERROR CONDITIONS (T/R = 1)

1. Invalid Command. No response, command ignored.

2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).

3. Broadcast Command. No Status response. Set Message Error bit (status word), and Command Word Contents Error (BIT Word).

ERROR CONDITIONS (T/R = 0)

1. Invalid Command. No response, command ignored.

2. Command not followed by Contiguous Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count

(BIT Word).

3. Command followed by to many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT word).

RT/

OVERRIDE SELECTED TRANSMITER SHUTDOWN ( = 0; 10101)

MESSAGE SEQUENCE = TRANSMITER SHUTDOWN/DATA + STATUS

The Data Word received is transferred to the subsystem. No transmitters that have been previously shut down are reactivated as a result of this

command. No other action is taken by the SSRT. This command is intended for use with RTs with more than one dual redundant channel. If the

command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed.

ERROR CONDITIONS

1. Invalid Command. No response, command ignored.

2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word).

3. Command Followed by too many Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count bit

(BIT Word).

4. Command bit Set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count

(BIT Word).

5. Command bit Set to One not followed by Data Word. The SSRT replies with Status plus one Data Word.The Data Word is read from

the subsystem.

6. Command bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits

(Status Word), and Command Contents Error (BIT Word).

RT/

TABLE 7. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS

MIL-STD-1553 ISOLATION TRANSFORMER INTERFACE

Analog transmit/receive signals. Connect directly to 1553 isolation transformers.

16TX/RX-B (I/O)

13TX/RX-B (I/O)

7TX/RX-A (I/O)

5TX/RX-A (I/O)

DESCRIPTIONPINSIGNAL NAME

Bi-directional data bus.When the SSRT is writing data to the external system, these signals are active outputs. At all other

times, these signals are high impedance inputs.

D10 (I/O)

D0 (I/O) (LSB)

38D1 (I/O)

43D2 (I/O)

44D3 (I/O)

D4 (I/O) 39

45D5 (I/O)

36D6 (I/O)

47D7 (I/O)

46D8 (I/O) 51

D9 (I/O)

52D11 (I/O)

49D12 (I/O)

DATA BUS (16)

48D13 (I/O)

50D14 (I/O)

53D15 (I/O) (MSB)

DESCRIPTIONPINSIGNAL NAME

+5V Vcc CH A

PINSIGNAL NAME

72 Channel A transceiver power.

+5V Vcc CH B 20 Channel B transceiver power.

+5V / +3.3V Logic 37 Logic power. For BU-61703 this pin must be connected to +3.3V.

For BU-61705 this pin must be connected to +5V.

GROUND 17 Ground.

POWER AND GROUND

DESCRIPTION

DESCRIPTIONSIGNAL

DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS

Data Transfer Acknowledge. Active low output signal used to indicate the SSRT's acceptance of the system

data bus (D15-D0), in response to a data transfer grant (DTGRT).The SSRT's data transfers over D15-D0 will

be framed by the time that DTACK is asserted low.

If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of

MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted

low to enable configuration data to be read from an external tr i-state buffer.

For transmit massages, or a receive messages in non-burst mode, or for receive messages to subaddress 30

assuming that Subaddress 30 Autowrap is disabled, DTACK will be asser ted low to indicate the transfer of

individual words between the external system and the SSRT.

For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the

DTREQ-to-DTGRT handshake following the receipt of the last received data word. It will remain low for the

duration of the DMA burst write transfer from the SSRT to the exter nal system.The total time for a burst write

transfer is three clock cycles times the number of data words.

Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT write

cycles. Used to transfer data from the SSRT to the external system. The external system may latch data on

either the falling or rising edge of MEMWR.

Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external sys-

tem to be enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the

external system.The SSRT latches the data one clock cycle prior to the rising edge of MEMOE.

Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition.That is, the system

did not respond with a DTGRT in time, following the SSRT's asser tion of DTREQ.

Data Transfer Grant. Input from the external subsystem that must be asser ted low in response to the SSRT

asser ting DTREQ low in order to enable the SSRT to read data from or write data to the external subsystem.

The maximum allowable time from DTREQ to DTGRT is 10 µs.

If the SSRT's DMA handshake isn't required, DTGRT may be hardwired to logic "0".

DTACK (O)

MEMWR (O)

MEMOE (O)

HS_FAIL (O)

DTGRT (I)

Data Transfer Request. Active low level output signal used to request use of the external system data bus

(D15-D0).

DTREQ (O) 24

3L_BRO (0) Latched Broadcast.This two-state output signal is latched following receipt of a new command word. For a

broadcast command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will out-

put logic "0".

4T / R Transmit/Receive.This two-state output signal is latched following receipt of a new command word. For a trans-

mit message, this signal will output a value of logic "1". For a receive message, this signal will output logic "0".

SA2 (0)

Subaddress.These five two-state output signals are latched following receipt of a new command word.They

provide the subaddress field of the received command word.

WC / MC / CWC2 (O)

Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state

output signals provide the contents of the command word's Word Count/Mode Code field.

For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the

value of the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in

burst mode). CWC increments from 0 to the value of the Word Count field - 1 during the message.

At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from

0 to the value of the word count field -1, as each word is transferred from the internal FIFO to the external sys-

tem over D15-D0. In burst mode, it takes three clock cycles to transfer each word to the external system.

For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word

Count - 1, as each word is read from the external system and transferred to the SSRT.

For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched

through the end of the message (until receipt of a subsequent command word).

COMMAND / ADDRESS BUS

SIGNAL

SA4 (0)

SA3 (0)

SA1 (0) 22

SA0 (0) 68

WC / MC / CWC4 (O) (MSB)

WC / MC / CWC3 (O)

WC / MC / CWC1 (O) 27

DESCRIPTION

WC / MC / CWC0 (O) (LSB) 15

DESCRIPTION

Remote Ter minal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and

RTADP input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity.

Note, if RT_AD_ERR is low, then the SSRT will not recognize any valid Command Word received to its own

RT address.

RT_AD_ERR (O) 1

RT Address inputs.

RTAD0 (i) (LSB)

RTAD1 (i)

RTAD2 (i)

RTAD3 (i)

RTAD4 (i) (MSB)

SIGNAL

RT ADDRESS

Remote Ter minal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in

order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s

from among RTAD-4-RTAD0 and RTADP.

RTADP (I) 40

RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT is configured to accept a hardwired

RT address from RTAD4-RTAD and RTADP.

If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and

RTADP will be latched inter nally by the SSRT on the rising edge of RT_AD_LAT.

RT_AD_LAT (I) 31

DESCRIPTION

Busy. If this input is asserted low, the Busy bit will be set to logic "1" in the SSRT's Status Word. If the Busy bit

in the status word is logic "1", the SSRT will not transmit any data words, except for a Transmit last command

or Transmit BIT word mode command. For a receive command, if the SSRT is Busy, it will still transfer data

words to the external system (although these transfers may be blocked by means of exter nal logic).

Subsystem Flag. If this input is asserted low, the Subsystem Flag bit will be set in the SSRT's Status Word.

BUSY (I)

SSFLAG (I)

SIGNAL

RT STATUS WORD INPUTS

Illegal. Input to the SSRT that is sampled after the Command Word transfer. A logic "0" will cause the Message

Error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the

Message Error bit.

ILLEGAL (I) 62

Service Request. When this input is logic "0", the Ser vice request bit in the SSRT's status word will be logic

"1".When this input is logic "1", the Ser vice request bit in the SSRT's status word will be logic "0".

SRV_RQST (I) 61

DESCRIPTION

Remote Ter minal Fail.This two-state output signal will be asserted low following a failure of the built-in self-test

performed following power tur n-on or as the result of the receipt of an Initiate self-test mode command.The

built-in off-line self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and

RT protocol logic.

In addition, RTFAIL will be asser ted low following a failure of the on-line loop test for any non-broadcast mes-

sage.The on-line loop test verifies the validity of the received version of all transmitted words (sync,

Manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last trans-

mitted word.

If asser ted to logic "0", RTFAIL will clear to logic "1" when the SSRT begins transmission of its status word in

response to a subsequent valid non-broadcast message.

Message Error. Active low level two-state output signal used to flag to the external system that there was a

message error on the 1553 bus communication (word, gap, or word count error) for a par ticular message.This

output goes low upon detecting the error and is reset following the receipt of the next valid command word (to

the RT) from the 1553 bus, or if MSTCLR is asserted low. If this output goes low, all further ser vicing of the

current message is abor ted.

Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the

external system that a valid, legal, non-mode receive command with the correct number of valid data words

has been received and transferred to the external system.

For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT

time of 0, this will be approximately 4 µs following the mid-parity bit crossing of the last received data word.

For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst

write transfer.

RTFAIL (O)

MSG_ERR (O)

GBR (O)

SIGNAL

RT ACTIVITY AND MESSAGE STATUS INDICATORS

RT Active.This signal will be low (logic "0") following power turn-on, and when the SSRT is reading its Auto-

configure word or is performing its inter nal self-test. After the self-test passes, or if the Auto-configure option is

not used, or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to

always go online), RTACTIVE will then transition to logic "1".When this occurs, the SSRT will begin processing

messages over the 1553 bus.

If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTAC-

TIVE will remain at logic "0". In this case, the SSRT will remain offline and not process any 1553 messages.

A failed self test will cause RTFAIL_L to be asserted low (logic “0").

If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when

RTACTIVE and DTACK are both outputting logic "0".

RTACTIVE 56

In-command.This two-state output is asser ted low whenever a message is being processed by the SSRT.INCMD 25

DESCRIPTION

Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connect-

ed to logic "0".To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should

be applied to this input.

TX_INH (I) 59

Broadcast Enable. If this input is logic "1", the SSRT will recognize RT address 31 as the broadcast address. If

this input is logic "0", the SSRT will not recognize RT ad dress 31 as the broadcast address; however, in this

configuration, RT address 31 may be used as a standard RT address.

BRO_ENA (I) 63

Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configura-

tion parameters revert to their default values as listed in Table 2. Note that the default condition for each config-

uration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default).

If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a

DMA read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic

"0" to logic "1". Each of the configuration parameters is enabled if the SSRT reads a value of logic "1" for the

respective data bit.

AUTO_CFG (I) 70

Master Clear. Negative true Reset input, asser ted low following power turn-on. When coming out of a “reset”

condition, note that the risetime of MSTCLR must be less than 10 µs.

MSTCLR (I) 2

SIGNAL

CONTROL INPUTS

DESCRIPTIONSIGNAL

CLOCK INPUT

Clock Input.The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs.CLK_IN (I) 30

These two inputs are used to designate the SSRT's clock frequency, as follows:

CLK_SEL_1 CLK_SEL_0 Clock Frequency

0 0 10 MHz

0 1 20 MHz

1 0 12 MHz

1 1 16 MHz

CLK_SEL_1 (I)

CLK_SEL_0 (I)

DESCRIPTION

XCVR_TP

(RESET*)

XCVR_TP

(READOUTA)

P5(*)

P3(*)

SIGNAL

F A CTOR Y TEST

XCVR_TP

(ZAP V OLTA) P1(*)

XCVR_TP

(READOUTB) P2(*)

For factory test only. Do not connect for normal operation.

XCVR_TP

(ZAP V OLTB)

XCVR_TP

(CLOCK)

P6(*)

P4(*)

(*) Note that the Test Output pins are pads located on the bottom of the package.

+5V Vcc-CH. A

GROUND

70 AUTO_CFG

69 SA4

SA0

GROUND

66 CLK_SEL_1

65 GROUND

DTGRT

BRO_ENA

62 ILLEGAL

61 SRV_RQST

GBR

TX_INH

RT_FAIL

57 HS_FAIL

56 RTACTIVE

55 BUSY

D10

D15

D11

51 D9

50 D14

49 D12

48 D13

47 D7

43 D2

42 D0

41 RTAD1

BU-61703 (3.3V / 5V)

BU-61705 (5V)

RTADP

37 +5V/3.3V-LOGIC

GNDN/A

XCVR TP

(ZAP V OLTB)

P6 **

XCVR TP

(RESET_L)

P5 **

GND

XCVR TP

(CLOCK)

P4 **

XCVR TP

(READOUTA)

P3 **

N/A

XCVR TP

(READOUTB)

P2 **

XCVR TP

(ZAP V OLTA)

P1 **

GND

PIN BU-61703 (3.3V / 5V)

BU-61705 (5V)

N/A

** Note that the Test Output pins

on the flat pack are pads

which are located on the

bottom of the package.

TABLE 8. NUMERICAL PIN LISTING

RT_AD_ERR

MSTCLR

L_BRO

T/R

BU-61703 (3.3V / 5V)

BU-61705 (5V)

TX/RX_A5

SA36

TX/RX_A7

CLK_SEL_0

WC4

WC3

SA211

WC212

TX/RX_B13

MEMOE14

WC015

TX/RX-B

GROUND

GROUND19

+5V Vcc-CH. B20

RTAD221

SA1

MEMWR

DTREQ

INCMD25

GROUND26

WC1

MSG_ERR

DTACK29

CLOCK_IN30

RT_AD_LAT

SSFLAG

RTAD033

RTAD334

RTAD4

FIGURE 16. MECHANICAL OUTLINE DRAWING

1.000 SQ ±0.010

(25.400 ±0.254)

VIEW "B"

0.018 ±0.002

(0.457 ±0.051) 0.050 ±0.005

(1.270 ±0.127)

Notes:

1) Dimensions are in inches (mm).

2) Package Material: Alumina (AL2O3)

3) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.

4) There are 6 test pads located on the bottom of the package. These pads are recessed

so as not to interfere when mounting the hybrid There are no user connections to these pads.

VIEW "B"

2.000 ±0.015

(50.800 ±0.381)

0.500 ±0.005

(12.70 ±0.127)

0.200 ±0.005

(5.080 ±0.127)

0.850 ±0.008

(21.590 ±0.203)

0.010 ±0.002

(0.254 ±0.051)

0.035 ±0.005

(0.889 ±0.127) 0.040 ±0.004

(1.016 ±0.102)

0.050 ±0.005

(1.270 ±0.127)

0.090 ±0.010

(2.286 ±0.254)

0.155 MAX

(3.94)

BOTTOM VIEW

SIDE VIEW

VIEW "A"

INDEX DENOTES

PIN NO. 1

P2 P1

P6 P5 P4 P3

0.100 DIA.

(2.540) (see note 4)

1.024 ±0.014 NOM.

(26.010 ±0.356)

FIGURE 17. MECHANICAL OUTLINE DRAWING

1.00 SQ ±0.01

(25.40 ±0.25)

VIEW "B"

Notes:

1) Dimensions are in inches (mm).

2) Package Material: Alumina (AL2O3)

3) Lead Material: Kovar, Plated by 50µ in.

minimum nickel under 60µ in. minimum gold.

4) There are 6 test pads located on the bottom of

the package. These pads are recessed so as

not to interfere when mounting the hybrid.

There are no user connections to these pads.

VIEW "B"

1.38 ±0.02

(35.05 ±0.51)

0.19 ±0.01

(4.83 ±0.25)

0.850 ±0.008

(21.590 ±0.203)

0.08 MIN FLAT

(2.03)

0.155 MAX

(3.94)

0.018 ±0.002

(0.457 ±0.051) 0.050 ±0.005

(1.270 ±0.127)

BOTTOM VIEW

SIDE VIEW

VIEW "A"

INDEX DENOTES

PIN NO. 1

P2 P1

P6 P5 P4 P3

0.100 DIA.

(2.540) (see note 4)

0.010 ±0.002

(0.254 ±0.051)

0.012 R. MAX

(0.305 R.)

0.05 MIN FLAT

(1.27)

0.006 -0.004,+0.010

(0.152 -0.100,+ 0.254)

1.024 ±0.014 NOM.

(26.010 ±0.356)

0.050 ±0.005

(1.27 ±0.127)

ORDERING INFORMATION

BU-61705F3-120X

Supplemental Process Requirements:

S = Pre-Cap Source Inspection

L = Pull Test

Q = Pull Test and Pre-Cap Inspection

K = One Lot Date Code

W = One Lot Date Code and PreCap Source

Y = One Lot Date Code and 100% Pull Test

Z = One Lot Date Code, PreCap Source and 100% Pull Test

Blank = None of the Above

Test Criteria:

0 = Standard Testing

2 = MIL-STD-1760 Amplitude Compliant

Process Requirements:

0 = Standard DDC practices, no Burn-In (See table below.)

1 = MIL-PRF-38534 Compliant

2 = B*

3 = MIL-PRF-38534 Compliant with PIND Testing

4 = MIL-PRF-38534 Compliant with Solder Dip

5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip

6 = B* with PIND Testing

7 = B* with Solder Dip

8 = B* with PIND Testing and Solder Dip

9 = Standard DDC Processing with Solder Dip, no Burn-In

Temperature Rang e/Data Requirements:

1 = -55°C to +125°C

2 = -40°C to +85°C

3 = 0°C to +70°C

4 = -55°C to +125°C with Variables Test Data

5 = -40°C to +85°C with Variables Test Data

6 = Custom Par t (Reser ved)

7 = Custom Par t (Reser ved)

8 = 0°C to +70°C with Variables Test Data

Voltage/Transceiver Option:

3 = +5 Volts r ise/fall times = 100 to 300 ns

4 = +5 Volts r ise/fall times = 200 to 300 ns ( McAir compatible)

Package T ype:

F = Flat Pack

G = “Gull Wing”(Formed Lead)

Logic Voltage

3 = 3.3 Volt

5 = 5 Volt

Product T ype:

BU-6170 = RT only with simple (non-processor) interface

—1015, Table 1BURN-IN A2001CONSTANT ACCELERATION C1010TEMPERATURE CYCLE A and C1014SEAL —2009, 2010, 2017, and 2032INSPECTION CONDITION(S)METHOD(S)

MIL-STD-883

TEST

STANDARD DDC PROCESSING

B-08/00-500 PRINTED IN THE U.S.A.

DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Corporation for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, New York 11716-2482

For Technical Support - 1-800-DDC-5757 ext. 7382 or 7234

Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358

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