Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-60
Block Diagram
Pentium/ProTM System Clock Chip
9148-60 Rev D 10/19/99
Pin Configuration
28 pin SOIC and SSOP
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, PCI, IOAPIC ,
14.314 MHz, 48 and 24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU, IOAPIC
3.3V outputs: PCI, REF
No power supply sequence requirements
28 pin SOIC and SSOP
Spread Spectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
The ICS9148-60 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz,
and one selectable 48_24MHz.
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz
GNDL = CPUCLK (0:1)
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = 48MHz
VDDL = CPUCLK (0:1)
VDDL1=IOAPIC
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9148-60
Pin Descriptions
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9,62DDVRWPV3.3yllanimon,stuptuoKLCICProfrewoP
213DDVRWPzHM84rofreoP
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513DNGRWPzHM84rofdnuorG
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3
ICS9148-60
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS ( S lave/Rece iver)
Start Bit
Address
D2(H) AC
K
Du mmy Co mmand Co de AC
K
Dummy Byte Count AC
K
By te 0 ACK
By te 1 AC
K
By te 2 AC
K
By te 3 ACK
By te 4 AC
K
By te 5 AC
K
By te 6 ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H) AC
K
Byte Coun
t
ACK Byte
0
ACK Byte 1
ACK Byte
2
ACK Byte
3
ACK Byte
4
ACK Byte
5
ACK Byte
6
ACK
Stop Bit
How to Read:
4
ICS9148-60
Note: PWD = Power-Up Default
Byte 3: Functionality & Frequency Select
& Spread Slect Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4:
Notes: 1 = Enabled; 0 = Disabled, outputs held low
tiB#niPemaNniPDWP noitpircseD 0=eulaVtiB1=eulaVtiB
7- - - )devreseR()devreseR(
6- - - )devreseR()devreseR(
5- - - )devreseR()devreseR(
4- - - )devreseR()devreseR(
3- - - )devreseR()devreseR(
2121KLCUPC1delbasiD )wol( delbanE
1- - 0 )devreseR()devreseR(
0220KLCUPC1 )delbasiD( )wol( delbanE
Byte 5:
Notes: 1 = Enabled; 0 = Disabled, outputs held low
tiB#niPemaNniPDWP noitpircseD 0=eulaVtiB1=eulaVtiB
74 F_KLCICP1
delbasiD )wol( delbanE
6115KLCICP1delbasiD )wol( delbanE
5014KLCICP1delbasiD )wol( delbanE
4- - 0 )devreseR()devreseR(
38 3KLCICP1delbasiD )wol( delbanE
27 2KLCICP1delbasiD )wol( delbanE
16 1KLCICP1delbasiD )wol( delbanE
05 0KLCICP1delbasiD )wol( delbanE
Serial Bitmap
Byte 6:
tiB#niPemaNniPDWP noitpircseD 0=eulaVtiB1=eulaVtiB
7- - 0 )devreseR()devreseR(
6- - 0 )devreseR()devreseR(
542CIPAOI1 delbasiD )wol( delbanE
4- - 0 )devreseR()devreseR(
3- - 0 )devreseR()devreseR(
2- - 0 )devreseR()devreseR(
1720FER1 )delbasiD( )wol( delbanE
0720FER1 )delbasiD( )wol( delbanE
Notes:
1 = Enabled; 0 = Disabled, outputs held low
For pin 27, there are 2 output stages together for 1 pin. These 2
latches must be both 0 or 1 simultaneously or there will be a short to
ground if one is disabled and the other is running.
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000 100 010 110 001 101 011 111
5.86 0.57 3.38 6.66 301 211 3.331 001
52.43 5.73 6.14 3.33 3.43 3.73 34.44 33.33
0
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00
5
ICS9148-60
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electr ical Charac teristics - Input/Supply/Com m on Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD+0.3 V
Input Low Volt age VIL VSS-0.3 0.8 V
Input High Current IIH VIN = VDD 0.1 5 µA
Input Low Current IIL1 VIN = 0 V; Input s wi th no pul l-up resi st ors -5 2.0 µA
Input Low Current IIL2 VIN = 0 V; Inputs w i th pull-up resistors -200 -100 µA
Operating IDD3.3OP66 CL = 0 pF ; Sel e c t @ 66MHz 60 170 m A
Supply Current IDD3.3OP100 CL = 0 pF ; Sele c t @ 100MHz 66 170 m A
Power D own Supply
Current IDD3.3PD CL = 0 pF; With input a ddress to Vdd or GND 3 650 µA
Input freque nc y F iVDD = 3.3 V; 14.318 MHz
CIN Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pF
Transition Time1Ttrans To 1st cros sing of target Freq. 3 ms
Settling Time1TsF rom 1st crossing to 1% ta rget Freq. 5 m s
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms
Skew1TAGP-PCI1 VT = 1.5 V; 1 3.5 4 ns
1Guarant e ed by design, not 100% teste d in product i on.
Input Ca pacitanc e1
Elect r i cal Charact eri st i cs - I nput/ Suppl y/Comm on O utput Param et ers
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2. 5 V + /-5% (unless other wise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 16 72 mA
Supply Current IDD2.5OP100 CL = 0 pF; Select @ 100 MHz 23 100 mA
Power Down
Su
pp
l
y
Current IDD2.5PD CL = 0 pF; With inp ut address t o Vdd or GND 10 100 µA
tCPU-AGP 00.51ns
tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1 2.6 4 ns
1Guarante ed by de sign, not 100% t e ste d in produc t ion.
Skew1
6
ICS9148-60
Elect ri cal Charact eri st i cs - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5% , VDDL = 2.5 V +/-5%; CL = 20 pF (unle ss ot he rwise stat e d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Outp ut High Volta ge VOH2B IOH = -12.0 mA 2 2. 3 V
Output Low Voltage VOL2B IOL = 12 mA 0.2 0. 4 V
Outpu t High C urre nt IOH2B VOH = 1. 7 V -41 -19 mA
Output Low Current IOL2B VOL = 0. 7 V 19 37 m A
Rise T im e tr2B1VOL = 0. 4 V, VOH = 2.0 V 1.25 1.6 ns
F all T ime tf2B1VOH = 2.0 V, VOL = 0.4 V 1 1. 6 ns
Duty Cycle dt2B1VT = 1.25 V 454855%
Skew tsk2B1VT = 1.25 V 30 175 ps
J itte r, Cycle-to-cycle t
j
c
y
c-c
y
c2B1VT = 1.25 V 150 250 ps
Jitte r, One S igma t
j
1s2B1VT = 1. 25 V 40 150 ps
J itte r, Absolute tjabs2B1VT = 1. 25 V -250 140 +250 ps
1Gua ra nt e e d by de sign, not 100% t e ste d in producti on.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH1 IOH = -11 mA 2. 4 3. 1 V
Output Low Voltage VOL1 IOL = 9. 4 mA 0. 1 0. 4 V
Output H igh C ur r ent I OH1 VOH = 2. 0 V -62 - 22 mA
Output Lo w Current IOL1 VOL = 0. 8 V 16 57 m A
Rise Time1tr1 VOL = 0. 4 V, VOH = 2.4 V 1.5 2 ns
Fa ll T ime1tf1 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns
Duty Cycle1dt1 VT = 1.5 V 455055%
Skew1tsk1 VT = 1. 5 V 140 500 ps
J itte r , One Sigma1t
j
1s1 VT = 1. 5 V 17 150 ps
J itter, Abs olute 1tjabs1 VT = 1.5 V - 5 00 70 500 ps
1Guar a nte ed by d es ign, not 100% te s ted in produc tion.
7
ICS9148-60
Elect ri cal Charact eri sti cs - I O A PIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH4B IOH = -1 8 mA 2 2 .2 V
Output Low Voltage VOL4B IOL = 18 mA 0.33 0.4 V
Output High Cur rent I OH4B VOH = 1.7 V -41 -28 mA
Output Low Curr ent IOL4B VOL = 0.7 V 29 37 mA
Rise Tim e1Tr4B VOL = 0.4 V, VOH = 2.0 V 1.3 1.6 ns
Fall Time1Tf4B VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns
Duty Cycle1Dt4B VT = 1.25 V 45 54 55 %
Skew1tsk4B1VT = 1. 25 V 60 250 ps
J itter, One Sigma1Tj1s4B VT = 1.25 V 1 3 %
J itter, Absolute1Tjabs4B VT = 1.25 V -5 5 %
1Gua rantee d by de sign, not 100% te ste d in production.
Elect ri cal Charact eri st i cs - REF
TA = 0 - 70C; V DD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise state d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltag e VOH5 IOH = -1 2 mA 2 .6 3 .1 V
Output L ow Voltage VOL5 IOL = 9 m A 0.17 0.4 V
Output High Cur rent IOH5 VOH = 2.0 V -44 -22 mA
Output L ow C urrent IOL5 VOL = 0.8 V 29 42 mA
Rise Tim e1tr5 VOL = 0.4 V , VOH = 2.4 V 1 .4 2 ns
Fal l Ti me1tf5 VOH = 2.4 V, VOL = 0 .4 V 1 .1 2 ns
Duty Cycle1dt5 VT = 1.5 V 47 54 57 %
J itter , One S igma1tj1s5 VT = 1.5 V 1 3 %
J itter, Absolute1tjabs5 VT = 1.5 V 35%
1Guarante e d by de sign, not 100% t e sted in production.
8
ICS9148-60
Electr i cal Characteri sti cs - 48, 24 M Hz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise state d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output H igh Voltage VOH5 IOH = -1 2 mA 2.6 3 V
Output L ow Voltage VOL5 IOL = 9 m A 0.14 0.4 V
Output High Current IOH5 VOH = 2.0 V -44 -22 mA
Output L ow C urrent IOL5 VOL = 0.8 V 16 42 mA
Rise Time1tr5 VOL = 0.4 V, VOH = 2 .4 V 1 .2 4 ns
Fall Time1tf5 VOH = 2.4 V, VOL = 0 .4 V 1 .2 4 ns
Duty Cycle1dt5 VT = 1.5 V 45 52 55 %
J itter , One S igma1tj1s5 VT = 1.5 V 1 3 %
J itter, Absolute1tjabs5 VT = 1.5 V 3 5 %
1Guarante ed by design, not 100% tested in production.
9
ICS9148-60
SOIC Package
TNUOCDAELL82
LNOISNEMID407.0
Ordering Information
ICS9148yM-60
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y M - PPP
10
ICS9148-60
SSOP Package
Dimensions in inches
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
LOBMYS NOMMOC SNOISNEMID SNOITAIRAV D
.NIM.MON.XAMN .NIM.MON.XAM
A860.0370.0870.041932.0442.0942.0
1A200.0500.0800.061932.0442.0942.0
2A660.0860.0070.002872.0482.0982.0
b010.0210.0510.042813.0323.0823.0
c400.0600.0800.082793.0204.0704.0
DsnoitairaVeeS03793.0204.0704.0
E502.0902.0212.0
eCSB6520.0
H103.0703.0113.0
L520.0030.0730.0
NsnoitairaVeeS
µ
°0°4°8
Ordering Information
ICS9148yF-60
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP
