MC74HC4051DR2 - ON Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 7

 Motorola, Inc. 1995

10/95

  

 

High–Performance Silicon–Gate CMOS

The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili-

con–gate CMOS technology to achieve fast propagation delays, low ON

resistances, and low OFF leakage currents. These analog multiplexers/

demultiplexers control analog voltages that may vary across the complete

power supply range (from VCC to VEE).

The HC4051, HC4052 and HC4053 are identical in pinout to the

metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select

inputs determine which one of the Analog Inputs/Outputs is to be connected,

by means of an analog switch, to the Common Output/Input. When the

Enable pin is HIGH, all analog switches are turned off.

The Channel–Select and Enable inputs are compatible with standard

CMOS outputs; with pullup resistors they are compatible with LSTTL

outputs.

These devices have been designed so that the ON resistance (Ron) is

more linear over input voltage than Ron of metal–gate CMOS analog

switches.

For multiplexers/demultiplexers with channel–select latches, see

HC4351, HC4352 and HC4353.

•Fast Switching and Propagation Speeds

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V

•Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V

•Improved Linearity and Lower ON Resistance Than Metal–Gate

Counterparts

•Low Noise

•In Compliance With the Requirements of JEDEC Standard No. 7A

•Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates

HC4052 — 168 FETs or 42 Equivalent Gates

HC4053 — 156 FETs or 39 Equivalent Gates

LOGIC DIAGRAM

MC54/74HC4051

Single–Pole, 8–Position Plus Common Off

X0 13

X1 14

X2 15

X3 12

X4 1

X5 5

X6 2

X7 4

A11

B10

C9

ENABLE 6

MULTIPLEXER/

DEMULTIPLEXER X

3

ANALOG

INPUTS/

CHANNEL

INPUTS

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

COMMON

OUTPUT/

INPUT

1516 14 13 12 11 10

21 34567

VCC 9

8

X2 X1 X0 X3 A B C

X4 X6 X X7 X5 Enable VEE GND

Pinout: MC54/74HC4051 (Top View)

OUTPUTS

SELECT

L

H

X

L

H

L

H

X

L

H

L

H

L

H

L

H

X







FUNCTION TABLE – MC54/74HC4051

Control Inputs

ON Channels

Enable Select

C B A

X0

X1

X2

X3

X4

X5

X6

X7

NONE

L

HX = Don’t Care

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

ORDERING INFORMATION

MC54HCXXXXJ

MC74HCXXXXN

MC74HCXXXXD

MC74HCXXXXDW

MC74HCXXXXDT

Ceramic

Plastic

SOIC

SOIC Wide

TSSOP

1

16 DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

DW SUFFIX

SOIC PACKAGE

CASE 751G–02

1

16

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

LOGIC DIAGRAM

MC74HC4052

Double–Pole, 4–Position Plus Common Off

X0 12

X1 14

X2 15

X3 11

Y0 1

Y1 5

Y2 2

Y3 4

A10

B9

ENABLE 6

X SWITCH

Y SWITCH

X

13

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

COMMON

OUTPUTS/INPUTS

L

H

X

L

H

L

H

X

FUNCTION TABLE – MC74HC4052

Control Inputs

ON ChannelsEnable Select

B A

X0

X1

X2

X3

L

H

X = Don’t Care

Pinout: MC74HC4052 (Top View)

1516 14 13 12 11 10

21 34567

VCC 9

8

X2 X1 X X0 X3 A B

Y0 Y2 Y Y3 Y1 Enable VEE GND

Y

3

Y0

Y1

Y2

Y3 NONE

LOGIC DIAGRAM

MC54/74HC4053

Triple Single–Pole, Double–Position Plus Common Off

X0 12

X1 13

A11

B10

C9

ENABLE 6

X SWITCH

Y SWITCH

X

14

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

COMMON

OUTPUTS/INPUTS

L

H

X

L

H

L

H

X

L

H

L

H

L

H

L

H

X

FUNCTION TABLE – MC54/74HC4053

Control Inputs

ON Channels

Enable Select

CBA

L

H

X = Don’t Care

Pinout: MC54/74HC4053 (Top View)

1516 14 13 12 11 10

21 3 4 5 6 7

VCC 9

8

Y X X1 X0 A B C

Y1 Y0 Z1 Z Z0 Enable VEE GND

Z0

Z1

Y0

Y1

Y0

Y1

X0

X1

X0

X1

X0

X1

X0

X1

NONE

Y0 2

Y1 1Y

15

Z0 5

Z1 3Z

4

Z SWITCH

NOTE: This device allows independent control of each switch.

Channel–Select Input A controls the X–Switch, Input B controls

the Y–Switch and Input C controls the Z–Switch

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

– 0.5 to + 14.0

ÎÎÎ

V

ÎÎÎ

VEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 7.0 to + 5.0

ÎÎÎ

V

ÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage

ÎÎÎÎÎÎ

VEE – 0.5 to

VCC + 0.5

ÎÎÎ

V

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎ

I

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current, Into or Out of Any Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

mA

ÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_

C

ÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

Ceramic DIP

ÎÎÎÎÎÎ

260

300

ÎÎÎ

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

_

C from 65

_

to 125

_

C

Ceramic DIP: – 10 mW/

_

C from 100

_

to 125

_

C

SOIC Package: – 7 mW/

_

C from 65

_

to 125

_

C

TSSOP Package: – 6.1 mW/

_

C from 65

_

to 125

_

C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

ÎÎÎ

2.0

ÎÎÎ

6.0

12.0

ÎÎÎ

V

ÎÎÎÎ

VEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage, Output (Referenced to

GND)

ÎÎÎ

– 6.0

ÎÎÎ

GND

ÎÎÎ

V

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage

ÎÎÎ

VEE

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

VIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across Switch

ÎÎÎ

1.2

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

_

C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time VCC = 2.0 V

(Channel Select or Enable Inputs) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

0

ÎÎÎ

1000

500

400

ÎÎÎ

ns

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The

reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

v

(Vin or V out)

v

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

Symbol

Parameter

Condition

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

Condition

VCC

V

–55 to 25°C≤85°C≤125°C

Unit

VIH Minimum High–Level Input Voltage,

Channel–Select or Enable Inputs Ron = Per Spec 2.0

4.5

6.0

1.50

3.15

4.20

1.50

3.15

4.20

1.50

3.15

4.20

V

VIL Maximum Low–Level Input Voltage,

Channel–Select or Enable Inputs Ron = Per Spec 2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

Iin Maximum Input Leakage Current,

Channel–Select or Enable Inputs Vin = VCC or GND,

VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ICC Maximum Quiescent Supply

Current (per Package) Channel Select, Enable and

VIS = VCC or GND; VEE = GND

VIO = 0 V VEE = – 6.0 6.0

6.0 2

820

80 40

160

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

DC CHARACTERISTICS — Analog Section

Symbol

Parameter

Condition

VCC

VEE

Guaranteed Limit

Unit

Symbol

Parameter

Condition

VCC

VEE

–55 to 25°C≤85°C≤125°C

Unit

Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to

VEE; IS ≤ 2.0 mA

(Figures 1, 2)

4.5

6.0

0.0

– 4.5

– 6.0

190

120

100

240

150

125

280

170

140

Ω

Vin = VIL or VIH; VIS = VCC or

VEE (Endpoints); IS ≤ 2.0 mA

(Figures 1, 2)

4.5

6.0

0.0

– 4.5

– 6.0

150

100

80

190

125

100

230

140

115

∆Ron Maximum Difference in “ON”

Resistance Between Any Two

Channels in the Same Package

Vin = VIL or VIH;

VIS = 1/2 (VCC – VEE);

IS ≤ 2.0 mA

4.5

6.0

0.0

– 4.5

– 6.0

30

12

10

35

15

12

40

18

14

Ω

Ioff Maximum Off–Channel Leakage

Current, Any One Channel Vin = VIL or VIH;

VIO = VCC – VEE;

Switch Off (Figure 3) 6.0 – 6.0 0.1 0.5 1.0 µA

Maximum Off–Channel HC4051

Leakage Current, HC4052

Common Channel HC4053

Vin = VIL or VIH;

VIO = VCC – VEE;

Switch Off (Figure 4)

6.0

– 6.0

0.2

0.1

2.0

1.0

4.0

2.0

Ion Maximum On–Channel HC4051

Leakage Current, HC4052

Channel–to–Channel HC4053

Vin = VIL or VIH;

Switch–to–Switch =

VCC – VEE; (Figure 5)

6.0

– 6.0

0.2

0.1

2.0

1.0

4.0

2.0

µA

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

–55 to 25°C≤85°C≤125°C

Unit

tPLH,

tPHL Maximum Propagation Delay, Channel–Select to Analog Output

(Figure 9) 2.0

4.5

6.0

370

74

63

465

93

79

550

110

94

ns

tPLH,

tPHL Maximum Propagation Delay, Analog Input to Analog Output

(Figure 10) 2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

tPLZ,

tPHZ Maximum Propagation Delay, Enable to Analog Output

(Figure 11) 2.0

4.5

6.0

290

58

49

364

73

62

430

86

73

ns

tPZL,

tPZH Maximum Propagation Delay, Enable to Analog Output

(Figure 11) 2.0

4.5

6.0

345

69

59

435

87

74

515

103

87

ns

Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF

CI/O Maximum Capacitance Analog I/O 35 35 35 pF

(All Switches Off) Common O/I: HC4051

HC4052

HC4053

130

80

50

130

80

50

130

80

50

Feedthrough 1.0 1.0 1.0

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Figure 13)* HC4051

HC4052

HC4053

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

pF

CPD Power Dissipation Capacitance (Figure 13)* HC4051

HC4052

HC4053

45

80

45

pF

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbol

Parameter

Condition

VCC

V

VEE

V

Limit*

Unit

Symbol

Parameter

Condition

VCC

V

VEE

V

25°C

Unit

BW Maximum On–Channel Bandwidth

or Minimum Frequency Response

(Figure 6)

fin = 1MHz Sine Wave; Adjust fin Voltage to

Obtain 0dBm at VOS; Increase fin Frequency

Until dB Meter Reads –3dB;

RL = 50Ω, CL = 10pF

2.25

4.50

6.00

‘51 ‘52 ‘53

MHz

or Minimum Frequency Response

(Figure 6)

Obtain 0dBm at VOS; Increase fin Frequency

Until dB Meter Reads –3dB;

RL = 50Ω, CL = 10pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

80

95

120

— Off–Channel Feedthrough Isolation

(Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain

0dBm at VIS

fin = 10kHz, RL = 600Ω, CL = 50pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

–50

dB

fin = 1.0MHz, RL = 50Ω, CL = 10pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

–40

— Feedthrough Noise.

Channel–Select Input to Common

I/O (Figure 8)

Vin ≤ 1MHz Square Wave (tr = tf = 6ns);

Adjust RL at Setup so that IS = 0A;

Enable = GND RL = 600Ω, CL = 50pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

25

105

135

mVPP

RL = 10kΩ, CL = 10pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

35

145

190

— Crosstalk Between Any Two

Switches (Figure 12)

(Test does not apply to HC4051)

fin = Sine Wave; Adjust fin Voltage to Obtain

0dBm at VIS

fin = 10kHz, RL = 600Ω, CL = 50pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

–50

dB

fin = 1.0MHz, RL = 50Ω, CL = 10pF

2.25

4.50

6.00

–2.25

–4.50

–6.00

–60

THD Total Harmonic Distortion

(Figure 14) fin = 1kHz, RL = 10kΩ, CL = 50pF

THD = THDmeasured – THDsource

VIS = 4.0VPP sine wave

VIS = 8.0VPP sine wave

VIS = 11.0VPP sine wave

2.25

4.50

6.00

–2.25

–4.50

–6.00

0.10

0.08

0.05

%

*Limits not tested. Determined by design and verified by qualification.

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V

Figure 1c. Typical On Resistance, VCC – VEE = 6.0 V Figure 1d. Typical On Resistance, VCC – VEE = 9.0 V

Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V Figure 2. On Resistance Test Set–Up

1.0 2.0

300

250

200

150

100

50

00 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron, ON RESISTANCE (OHMS)

120

100

80

60

40

20

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron, ON RESISTANCE (OHMS)

120

105

90

75

60

45

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron, ON RESISTANCE (OHMS)

90

75

60

45

30

15

00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron, ON RESISTANCE (OHMS)

80

70

60

50

40

30

00

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron, ON RESISTANCE (OHMS)

25

°

C

–55

°

C

125

°

C25

°

C

–55

°

C

125

°

C

30

15

5.0 5.5 6.0

25

°

C

–55

°

C

125

°

C

25

°

C

–55

°

C

125

°

C

20

10

3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0

25

°

C

–55

°

C

125

°

C

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY DC ANALYZER

VCC

DEVICE

UNDER TEST

+–

ANALOG IN COMMON OUT

GND VEE

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up Figure 4. Maximum Off Channel Leakage Current,

Common Channel, Test Set–Up

Figure 5. Maximum On Channel Leakage Current,

Channel to Channel, Test Set–Up Figure 6. Maximum On Channel Bandwidth,

Test Set–Up

Figure 7. Off Channel Feedthrough Isolation,

Test Set–Up Figure 8. Feedthrough Noise, Channel Select to

Common Out, Test Set–Up

OFF

6

7

8

16

COMMON O/I

VCC

VEE

VIH

NC

A

VCC

VEE

VCC

OFF

6

7

8

16

COMMON O/I

VCC

VEE

VIH

ANALOG I/O

VCC

VEE

VCC

ON

OFF

6

7

8

16

COMMON O/I

VCC

VEE

VIL

VCC

VEE

VCC

N/C

A

ANALOG I/O

ON

6

7

8

16

VCC

VEE

0.1

µ

F

CL*

fin RL

dB

METER

*Includes all probe and jig capacitance

OFF

6

7

8

16

VCC

VEE

0.1

µ

F

CL*

fin RL

dB

METER

*Includes all probe and jig capacitance

VOS

RL

VIS

VIL or VIH CHANNEL SELECT

ON/OFF

6

7

8

16

VCC

VEE

CL*

RL

*Includes all probe and jig capacitance

CHANNEL SELECT

TEST

POINT

COMMON O/I

11 VCC

OFF/ON

ANALOG I/O

RL

VCC

GND

Vin

≤

1 MHz

tr = tf = 6 ns

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 9 MOTOROLA

Figure 9a. Propagation Delays, Channel Select

to Analog Out Figure 9b. Propagation Delay, Test Set–Up Channel

Select to Analog Out

Figure 10a. Propagation Delays, Analog In

to Analog Out Figure 10b. Propagation Delay, Test Set–Up

Analog In to Analog Out

Figure 11a. Propagation Delays, Enable to

Analog Out Figure 11b. Propagation Delay, Test Set–Up

Enable to Analog Out

VCC

GND

CHANNEL

SELECT

ANALOG

OUT 50%

tPLH tPHL

50% ON/OFF

6

7

8

16

VCC

CL*

*Includes all probe and jig capacitance

CHANNEL SELECT

TEST

POINT

COMMON O/I

OFF/ON

ANALOG I/O

VCC

GND

ANALOG

IN

ANALOG

OUT 50%

tPLH tPHL

50% ON

6

7

8

16

VCC

CL*

*Includes all probe and jig capacitance

TEST

POINT

COMMON O/I

ANALOG I/O

ON/OFF

6

7

8

ENABLE

VCC

ENABLE 90%

50%

10%

tftrVCC

GND

ANALOG

OUT

tPZL

ANALOG

OUT

tPZH

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

10%

90%

tPLZ

tPHZ

50%

ANALOG I/O

CL*

TEST

POINT

16

VCC 1k

Ω

1

2

1

2

POSITION 1 WHEN TESTING tPHZ AND tPZH

POSITION 2 WHEN TESTING tPLZ AND tPZL

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

10

RL

Figure 12. Crosstalk Between Any Two

Switches, Test Set–Up Figure 13. Power Dissipation Capacitance,

Test Set–Up

Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

0

–10

–20

–30

–40

–50

–100 1.0 2.0 3.125

FREQUENCY (kHz)

dB

–60

–70

–80

–90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

ON

6

7

8

16

VEE CL*

*Includes all probe and jig capacitance

OFF

RL

VIS

RLCL*

VOS

fin 0.1

µ

F

ON/OFF

6

7

8

16

VCC

CHANNEL SELECT

NC

COMMON O/I

OFF/ON

ANALOG I/O

VCC A

11

VCC

VEE

ON

6

7

8

16

VCC

VEE

0.1

µ

F

CL*

fin RL

TO

DISTORTION

METER

*Includes all probe and jig capacitance

VOS

VIS

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at

VCC or GND logic levels. VCC being recognized as a logic

high and GND being recognized as a logic low. In this exam-

ple: VCC = +5V = logic high

GND = 0V = logic low

The maximum analog voltage swings are determined by

the supply voltages VCC and VEE. The positive peak analog

voltage should not exceed VCC. Similarly, the negative peak

analog voltage should not go below VEE. In this example, the

difference between VCC and VEE is ten volts. Therefore,

using the configuration of Figure 15, a maximum analog sig-

nal of ten volts peak–to–peak can be controlled. Unused

analog inputs/outputs may be left floating (i.e., not con-

nected). However, tying unused analog inputs and outputs to

VCC or GND through a low value resistor helps minimize

crosstalk and feedthrough noise that may be picked up by an

unused switch.

Although used here, balanced supplies are not a require-

ment. The only constraints on the power supplies are that:

VCC – GND = 2 to 6 volts

VEE – GND = 0 to –6 volts

VCC – VEE = 2 to 12 volts

and VEE ≤ GND

When voltage transients above VCC and/or below VEE are

anticipated on the analog channels, external Germanium or

Schottky diodes (Dx) are recommended as shown in Figure

16. These diodes should be able to absorb the maximum

anticipated current surges during clipping.

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 11 MOTOROLA

ANALOG

SIGNAL

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

a. Using Pull–Up Resistors b. Using HCT Interface

Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

ON

6

7

8

16

+5V

–5V

ANALOG

SIGNAL

+5V

–5V

+5V

–5V

11

10

9

TO EXTERNAL CMOS

CIRCUITRY 0 to 5V

DIGITAL SIGNALS

ON/OFF

7

8

16

VCC

VEE

Dx

VCC

Dx

VEE

Dx

VCC

Dx

ANALOG

SIGNAL

ON/OFF

6

7

8

16

+5V

VEE

ANALOG

SIGNAL

+5V

VEE

+5V

VEE

11

10

9

R

*R R

LSTTL/NMOS

CIRCUITRY

+5V

* 2K

≤

R

≤

10K

ANALOG

SIGNAL

ON/OFF

6

7

8

16

+5V

VEE

ANALOG

SIGNAL

+5V

VEE

+5V

VEE

11

10

9LSTTL/NMOS

CIRCUITRY

+5V

HCT

BUFFER

Figure 18. Function Diagram, HC4051

13 X0

14 X1

15 X2

12 X3

1X4

5X5

2X6

4X7

3X

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

11

A

10

B

9

C

6

ENABLE

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

12

Figure 20. Function Diagram, HC4053

Figure 19. Function Diagram, HC4052

13 X1

12 X0

1Y1

2Y0

3Z1

5Z0

14 X

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

11

A

10

B

9

C

6

ENABLE

12 X0

14 X1

15 X2

11 X3

1Y0

5Y1

2Y2

4Y3

3Y

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

10

A

9

B

6

ENABLE

13 X

15 Y

4Z

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 13 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10

—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51 15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM 0.750

0.240

—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A

B

C

D

E

F

G

J

K

L

M

N0

°

0.020 15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE

THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

C

K

N

G

E

F

D 16 PL

–T

–

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

MS0.25 (0.010) T B

MS

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A

B

C

D

F

G

H

J

K

L

M

S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

HGD 16 PL

S

C

–T

–

SEATING

PLANE

KJM

L

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A

B

C

D

F

G

J

K

M

P

R

9.80

3.80

1.35

0.35

0.40

0.19

0.10

0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

18

916

–A

–

–B

–

D16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

MJ

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC4051 MC74HC4052 MC54/74HC4053

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

14

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR

GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE –W–.

_ _ _ _

SECTION N–N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉ

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A10.15 10.45 0.400 0.411

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.50 0.90 0.020 0.035

G1.27 BSC 0.050 BSC

J0.25 0.32 0.010 0.012

K0.10 0.25 0.004 0.009

M0 7 0 7

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

M

B

M

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

–A–

–B– P8X

G14X

D16X

SEATING

PLANE

–T–

S

A

M

0.010 (0.25) B S

T

16 9

81

F

J

RX 45

_

_ _ _ _

M

C

K

MC54/74HC4051 MC74HC4052 MC54/74HC4053

High–Speed CMOS Logic Data

DL129 — Rev 6 15 MOTOROLA

How to reach us:

USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

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MC54/74HC4051/D

*MC54/74HC4051/D*

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