FDG6317NZ - APTINA IMAGING

July, 2019 − Rev.2

1Publication Order Number:

FDG6317NZ/D

FDG6317NZ

MOSFET – Dual, N-Channel,

POWERTRENCH)

20 V, 2.1 A, 550 mW

General Description

This dual N−Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using either

synchronous or conventional switching PWM controllers. It has been

optimized use in small switching regulators, providing an extremely

Iow RDS(ON) and gate charge (QG) in a small package.

Features

•0.7 A, 20 V

♦RDS(ON) = 400 mW @ VGS = 4.5 V

♦RDS(ON) = 550 mW @ VGS = 2.5 V

•Gate−Source Zener for ESD ruggedness

•Low Gate Charge

•High Performance Trench Technology for Extremely Low RDS(ON)

•Compact Industry Standard SC70−6 Surface Mount Package

•These Devices are Pb−Free and are RoHS Compliant

Applications

•DC/DC Converter

•Power Management

•Load Switch

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Symbol Parameter Ratings Units

VDSS Drain−Source Voltage 20 V

VGSS Gate−Source Voltage ±12 V

IDDrain Current:

Continuous (Note1)

Pulsed

0.7

2.1

PDPower Dissipation for Single

Operation

0.3 W

TJ, TSTG Operating and Storage Junction

Temperature Range

−55 to +150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS

Symbol Parameter FDG6317NZ Unit

RqJA Thermal Resistance, Junction to Ambient, (Note 1) 415 _C/W

1. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder

mounting surface of the drain pins. RqJC is guaranteed by design while RqJA is determined by the user’s board design. RqJA = 415_C/W when

mounted on a minimum pad.

SC70−6

CASE 419B

www.onsemi.com

See detailed ordering and shipping information on page 2 of

this data sheet.

ORDERING INFORMATION

&Y = Data Code

&.67&G = Specific Device Code

&E&E&E&

&.67&G

MARKING DIAGRAM

VDSS RDS(ON) MAX ID MAX

20 V 550 mW2.1 A

Pin 1

FDG6317NZ

www.onsemi.com

PACKAGE MARKING AND ORDERING INFORMATION

Device Marking Device Reel Size Tape Width Quantity

.67 FDG6317NZ 7” 8 mm 3000 units

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

OFF CHARACTERISTICS

BVDSS Drain to Source Breakdown Voltage VGS =0V, I

D= 250 mA20 − − V

DBVDSS/DTJBreakdown Voltage Temperature

Coefficient

ID= 250 mA, Referenced to 25_C−13 −mV/_C

IDSS Zero Gate Voltage Drain Current VDS =16V, V

GS =0V − − 1mA

IGSS Gate−Body Leakage VGS =±12 V, VDS =0V − − ±10 mA

IGSS Gate−Body Leakage VGS =±4.5 V, VDS =0V ±1mA

ON CHARACTERISTICS

VGS(th) Gate Threshold Voltage VDS =V

GS, ID= 250 mA0.6 1.2 1.5 V

DVGS(th)/DTJGate Threshold Voltage

Temperature Coefficient

ID=−250 mA, Referenced to 25_C− −2mV/_C

RDS(on) Static Drain−Source

On−Resistance

VGS = 4.5 V, ID= 0.7 A

VGS = 2.5 V, ID= 0.6 A

VGS = 4.5 V, ID= 0.7 A, TJ = 125_C

300

450

390

400

550

560

ID(on) On−State Drain Current VGS =10V, V

DS =0V 1 A

gFS Forward Transconductance VDS =20V, I

D=5A −1.8 −S

DYNAMIC CHARACTERISTICS

Ciss Input Capacitance VDS =10V, V

GS = 0 V, f = 1.0 MHz −66.5 −pF

Coss Output Capacitance −19 −pF

Crss(eff.) Reverse Transfer Capacitance −10 −pF

RGGate Resistance VGS = 15 mV, f = 1.0 MHz −5.8 −W

SWITCHING CHARACTERISTICS

td(on) Turn-On Delay Time VDD =10V, I

D=1A,

VGS = 4.5 V, RGEN =6W

−5.5 11 ns

trTurn-On Rise Time −7 15 ns

td(off) Turn-Off Delay Time −7.5 15 ns

tfTurn-Off Fall Time −2.5 5 ns

QgTotal Gate Charge VDS =10V, I

D= 0.7 A,

VGS = 4.5 V,

0.76 1.1 nC

Qgs Gate−Source Charge 0.18 nC

Qgd Gate−Drain Charge 0.20 nC

DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

ISMaximum Continuous Source to Drain Diode Forward Current − − 0.25 A

VSD Source to Drain Diode Forward

Voltage

VGS =0V, I

S= 0.25 A (Note 2) −0.8 1.2 V

trr Diode Reverse Recovery Time IF = 0.7 A, dIF/dt = 100 A/ms−8.3 −nS

Qrr Diode Reverse Recovery Charge −1.2 −nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%

3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.

FDG6317NZ

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 1. On−Region Characteristics Figure 2. On−Resistance Variation with

Drain Current and Gate Voltage

Figure 3. On−Resistance Variation with

Temperature

Figure 4. On−Resistance Variation with

Gate−to−Source Voltage

Figure 5. Transfer Characteristics Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature

0.5

1.5

0 0.5 1 1.5 2 2.5

VDS, DRAIN−SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

3.0V

2.0V

2.5V

VGS = 10V

4.5V 2.0V

0.9

1.1

1.3

1.5

1.7

00.511.52

ID, DRAIN CURRENT (A)

RDS(ON) , NORMALIZED

DRAIN−SOURCE ON−RESISTANCE

VGS = 2.5V

4.5V

3.0V

10V

6.0V

3.5V

4.0V

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE ( oC)

RDS(ON) , NORMALIZED

DRAIN−SOURCE ON−RESISTANCE

ID = 0.7A

VGS =10V

0.2

0.4

0.6

0.8

0246810

VGS, GATE TO SOURCE VOLTAGE (V)

RDS(ON) , ON−RESISTANCE (OHM)

ID = 0.35A

TA = 125oC

TA = 25oC

0.5

1.5

01234

VGS, GATE TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

TA = 125oC−55

VDS = 5V

25oC

0.0001

0.001

0.01

0.1

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSD, BODY DIODE FORWARD VOLTAGE (V)

IS, REVERSE DRAIN CURRENT (A)

TA= 125oC

25oC

−55

VGS = 0V

FDG6317NZ

www.onsemi.com

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics

Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum Power

Dissipation

Figure 11. Transient Thermal Response Curve

0 0.2 0.4 0.6 0. 8 1

Qg, GATE CHARGE (nC)

VGS, GATE−SOURCE VOLTAGE (V)

ID = 0.7A VDS = 5V 15V

10V

100

0 5 10 15 20

VDS, DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

Ciss

Crss

Coss

f = 1MHz

VGS = 0 V

0.001

0.01

0.1

0.1 1 10 100

VDS, DRAIN−SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

100m

100ms

RDS(ON) LIMIT

VGS = 10V

SINGLE PULSE

RqJA = 415

oC/W

TA = 25oC

10ms

1ms

0.0001 0.001 0.01 0.1 1 10 100 1000

t1, TIME (sec)

P(pk), PEAK TRANSIENT POWER (W)

SINGLE PULSE

RqJA = 415°C/W

TA = 25°C

0.01

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

t1, TIME (sec)

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

RqJA(t) = r(t)*R

qJA

RθJA = 415°C/W

TJ − T

A = P * RθJA(t)

Duty Cycle, D = t 1/ t2

P(pk)

SINGLE PULSE

0.01

0.02

0.05

0.1

0.2

D = 0.5

POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United

States and/or other countries.

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-

SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.

4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY AND DATUM H.

5. DATUMS A AND B ARE DETERMINED AT DATUM H.

6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE

LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.

7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN

EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-

TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OF THE FOOT.

Cddd M

123

654

XXXMG

XXX = Specific Device Code

M = Date Code*

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

STYLES ON PAGE 2

DIM MIN NOM MAX

MILLIMETERS

A−−− −−− 1.10

A1 0.00 −−− 0.10

ddd

b0.15 0.20 0.25

C0.08 0.15 0.22

D1.80 2.00 2.20

−−− −−− 0.043

0.000 −−− 0.004

0.006 0.008 0.010

0.003 0.006 0.009

0.070 0.078 0.086

MIN NOM MAX

INCHES

0.10 0.004

E1 1.15 1.25 1.35

e0.65 BSC

L0.26 0.36 0.46

2.00 2.10 2.20

0.045 0.049 0.053

0.026 BSC

0.010 0.014 0.018

0.078 0.082 0.086

(Note: Microdot may be in either location)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65

0.66

DIMENSIONS: MILLIMETERS

0.30

PITCH

2.50

RECOMMENDED

TOP VIEW

SIDE VIEW END VIEW

bbb H

SEATING

PLANE

DETAIL A E

A2 0.70 0.90 1.00 0.027 0.035 0.039

L2 0.15 BSC 0.006 BSC

aaa 0.15 0.006

bbb 0.30 0.012

ccc 0.10 0.004

A-B D

aaa C

2X 3 TIPS

aaa H D

PLANE

DETAIL A

GAGE

ccc C

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42985B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SC−88/SC70−6/SOT−363

STYLE 1:

PIN 1. EMITTER 2

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

6. COLLECTOR 2

STYLE 3:

CANCELLED

STYLE 2:

CANCELLED

STYLE 4:

PIN 1. CATHODE

2. CATHODE

3. COLLECTOR

4. EMITTER

5. BASE

6. ANODE

STYLE 5:

PIN 1. ANODE

2. ANODE

3. COLLECTOR

4. EMITTER

5. BASE

6. CATHODE

STYLE 6:

PIN 1. ANODE 2

2. N/C

3. CATHODE 1

4. ANODE 1

5. N/C

6. CATHODE 2

STYLE 7:

PIN 1. SOURCE 2

2. DRAIN 2

3. GATE 1

4. SOURCE 1

5. DRAIN 1

6. GATE 2

STYLE 8:

CANCELLED

STYLE 11:

PIN 1. CATHODE 2

2. CATHODE 2

3. ANODE 1

4. CATHODE 1

5. CATHODE 1

6. ANODE 2

STYLE 9:

PIN 1. EMITTER 2

2. EMITTER 1

3. COLLECTOR 1

4. BASE 1

5. BASE 2

6. COLLECTOR 2

STYLE 10:

PIN 1. SOURCE 2

2. SOURCE 1

3. GATE 1

4. DRAIN 1

5. DRAIN 2

6. GATE 2

STYLE 12:

PIN 1. ANODE 2

2. ANODE 2

3. CATHODE 1

4. ANODE 1

5. ANODE 1

6. CATHODE 2

STYLE 13:

PIN 1. ANODE

2. N/C

3. COLLECTOR

4. EMITTER

5. BASE

6. CATHODE

STYLE 14:

PIN 1. VREF

2. GND

3. GND

4. IOUT

5. VEN

6. VCC

STYLE 15:

PIN 1. ANODE 1

2. ANODE 2

3. ANODE 3

4. CATHODE 3

5. CATHODE 2

6. CATHODE 1

STYLE 17:

PIN 1. BASE 1

2. EMITTER 1

3. COLLECTOR 2

4. BASE 2

5. EMITTER 2

6. COLLECTOR 1

STYLE 16:

PIN 1. BASE 1

2. EMITTER 2

3. COLLECTOR 2

4. BASE 2

5. EMITTER 1

6. COLLECTOR 1

STYLE 18:

PIN 1. VIN1

2. VCC

3. VOUT2

4. VIN2

5. GND

6. VOUT1

STYLE 19:

PIN 1. I OUT

2. GND

3. GND

4. V CC

5. V EN

6. V REF

STYLE 20:

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

4. EMITTER

5. COLLECTOR

6. COLLECTOR

STYLE 22:

PIN 1. D1 (i)

2. GND

3. D2 (i)

4. D2 (c)

5. VBUS

6. D1 (c)

STYLE 21:

PIN 1. ANODE 1

2. N/C

3. ANODE 2

4. CATHODE 2

5. N/C

6. CATHODE 1

STYLE 23:

PIN 1. Vn

2. CH1

3. Vp

4. N/C

5. CH2

6. N/C

STYLE 24:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

STYLE 25:

PIN 1. BASE 1

2. CATHODE

3. COLLECTOR 2

4. BASE 2

5. EMITTER

6. COLLECTOR 1

STYLE 26:

PIN 1. SOURCE 1

2. GATE 1

3. DRAIN 2

4. SOURCE 2

5. GATE 2

6. DRAIN 1

STYLE 27:

PIN 1. BASE 2

2. BASE 1

3. COLLECTOR 1

4. EMITTER 1

5. EMITTER 2

6. COLLECTOR 2

STYLE 28:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

STYLE 29:

PIN 1. ANODE

2. ANODE

3. COLLECTOR

4. EMITTER

5. BASE/ANODE

6. CATHODE

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

STYLE 30:

PIN 1. SOURCE 1

2. DRAIN 2

3. DRAIN 2

4. SOURCE 2

5. GATE 1

6. DRAIN 1

Note: Please refer to datasheet for

style callout. If style type is not called

out in the datasheet refer to the device

datasheet pinout or pin assignment.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42985B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SC−88/SC70−6/SOT−363

www.onsemi.com

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