1
1999 Integrated Device Technology, Inc. DSC-4266/2
JULY 1999
Common Bus CPU Card (C3)
Family for 64-bit MIPS
Processors
PRELIMINARY
IDT7M9516 IDT7M9521
IDT7M9518 IDT7M9522
IDT7M9519 IDT7M9523
IDT7M9520
4266 dwg 01
FEATURES:
• Supports IDT Common Bus CPU Card (C3) electrical and
mechanical specifications.
• C3 Card family supports IDT 64bit MIPS family including R4650,
R4700, R64475, R5000, R64575 for easy scaling of performance.
• Low profile, mezzanine form-factor. Ideal daughtercard for:
– Compact PCI
–VME
– Ethernet / ATM switches
• Utilizes SAMTEC CLP connectors
– 100 pin Conn. A: part number: CLP-150-02-L-D-PA
– 96 pin Conn. B: part number: CLP-148-02-L-D-PA
• Onboard clock generation circuitry for processor/system
clocks
• Onboard processor reset and configuration circuitry.
• 5V Tolerance
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The C3 family are CPU mezzanine daughtercards based on IDT's MIPS
processors. The C3 Card family is designed to replace the CPU and specific
support circuitry around the CPU in a system design. The goal of the C3 is
to provide the system designer a seamless hardware migration path
through IDT's family of 64-bit MIPS processors(R4650, R4700, R64475,
R5000, R64575), and to simplify the overall system implementation require-
ments of those processors.
Each of the above processors has a unique pin configuration/package;
therefore, a system designer would normally be required to implement a
unique board design for each of the processors. The goal of the C3 is to
eliminate the differences between these processors at the system interface
level, and to allow the system designer to implement a single baseboard
design which will support C3 cards featuring the R4650, R4700, R64475,
R5000, R64575 or future processors.
Reset
Generation
Configuration
Logic
MIPS CPU
SyncO ut SyncIn
SysAD, etc.
CLOCK
GENERATION
System
Clocks
C3/System
Boundary
S y nc Ou t mu st be tie d to
SyncIn for proper operation
Configuration
Inputs
2
1999 Integrated Device Technology, Inc. DSC-4266/2
IDTIDT7M9516/18/19/20/21/22/23
CLOCK GENERATION
The C3 provides nine clock outputs that are associated with system bus clock
generation, as well as a 20MHz clock output and a 24MHz clock output. The
ten bus clock outputs consist of nine identical buffered system clocks and one
dedicated output for processor to system clock synchronization. The system
clocks - SysCLK(0:8) - are provided to drive devices on the system bus, as well
as other devices that need to operate at the system clock frequency. The
processor synchronization clock output (SyncOut) must be connected to the
processor synchronization clock input (SyncIn) through a delay path that
matches the delay path of the system clocks to ensure proper operation of the
C3 in the system. The 20MHz and 24MHz clocks are provided for system
peripherals that have fixed frequency requirements.
WATCHDOG TIMER
The watchdog timer input (WDStrb pin B-172) of the C3 must be strobed
periodically to prevent the watchdog timer output (WDO* pin B-173) from being
asserted. If the input is not strobed within 1 second of the previous strobe, the
output will be asserted. Note that if the watchdog timer functionality is not required,
these pins can be left unconnected.
5V TOLERANCE CIRCUITRY
5V tolerance is provided by running the signals through bus switches.
All inputs and I/O's are 5V tolerant except for SYNCIN. The input voltage
on SYNCIN must not exceed VCC3 + 0.3V. (Not available on 7M9521 and
7M9522).
BOARD OVERVIEW
The C3 processor cards consist of the following functional blocks: 64bit
MIPS CPU, clock generation circuitry for the processor/system clocks,
processor reset and configuration circuitry, and an optional L2 cache
subsystem.
RESET CONFIGURATION
The C3 contains on board reset generation logic that provides all of the
reset requirements of the processor. This reset logic handles all Power On
Reset requirements, as well as handling two system hard reset sources
(S_HardRST*, A_HardRST*) and a system soft reset source (SoftRST*).
In addition, the reset logic of the C3 also provides a reset output (RSTOut*)
to the system that is asserted whenever there is a processor hard reset.
C3 CONFIGURATION
The C3 is configured through a set of static configuration inputs. The
configuration inputs are used for both C3 clock configuration and proces-
sor configuration. The clock configuration inputs are used to set the
system bus clock frequency and the CPU core to system bus clock
multiplier. The processor configuration inputs are used to configure the
following: endianess (big/little), drive strength (83%/100%), internal timer
(enabled/disabled), write type (R4X00/pipelined) and block write data rate
(D/Dx/Dxx/Dxxx).
NOTES:
1. All dimensions in inches.
2. Actual component placement may differ from those shown in the diagram.
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4266 dwg 05
TOP VIEW BOTTOM VIEW
PACKAGE DIMENSIONS
MIPS
CPU
FST
FST FST
FST
FST FST FST
FST FST FST
XTAL
CLKGEN
PAL
CLK D RV
2.45
2.60
0.50
Pin 1
Pin 1
.050
.050
2.450
(+/- 0.010)
.169 REF
.075 R EF
2.013
.050 TYP
2.600
(+/- 0.01 0)
Pin 50
Pin 149
Pin 196
3
1999 Integrated Device Technology, Inc. DSC-4266/2
IDT
IDT7M9516/18/19/20/21/22/23
PINOUT(1)
4266 dwg 03
NOTE:
1. The pinout of the C3 card is from a top view.
2. This pin is not connected (NC) on the 7M9516.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Connector A
VCC5
S
y
sAD(10)
S
y
sAD(41)
S
y
sCMD(6)
GND
S
y
sAD(8)
ClkMult(0)
ClkMult(1)
GND
S
y
sADP(4)
RSVD
S
y
sCMD(4)
GND
S
y
sAD(7)
S
y
sAD(38)
WrRd
y
*
GND
S
y
sAD(5)
S
y
sAD(36)
GND
S
y
sCMD(1)
S
y
sAD(3)
GND
S
y
sAD(34)
INT5*
S
y
sAD(33)
GND
S
y
sAD(0)
INT2*
GND
S
y
sAD(48)
S
y
sAD(17)
GND
INT0*
S
y
sAD(50)
GND
S
y
sAD(19)
S
y
sAD(20)
GND
S
y
sAD(21)
RELEASE*
GND
RdRd
y
*
S
y
sAD(54)
GND
S
y
sAD(23)
NMI*
GND
S
y
sAD(24)
VCC5
VCC5
S
y
sCMD(7)
GND
S
y
sAD(9)
S
y
sAD(40)
S
y
sCMD(5)
ScTCE*
A_HardRst*
ClkMult(2)
S
y
sADC(0)
S
y
sAD(39)
GND
RSVD
S
y
sCMD(3)
S
y
sAD(6)
VCC3
S
y
sAD(37)
S
y
sCMD(2)
S
y
sAD(4)
GND
S
y
sAD(35)
S
y
sCMD(0)
S
y
sAD(2)
VCC3
INT4*
S
y
sAD(1)
S
y
sAD(32)
VCC3
INT3*
S
y
sAD(16)
INT1*
VCC3
S
y
sAD(49)
S
y
sAD(18)
ValidIn*
GND
RSVD
S
y
sAD(51)
S
y
sAD(52)
VCC3
ValidOut*
RSVD
GND
S
y
sAD(53)
S
y
sAD(22)
S
y
sAD(55)
VCC3
S
y
sADP(2)
S
y
sADP(6)
VCC5
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
(2)
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
VCC5
S_HardRst*
OutDrv
SoftRst*
GND
20MHzOut
GND
24MhzOut
GND
S
y
sAD
(
42
)
S
y
sAD
(
11
)
S
y
sAD
(
12
)
VCC3
S
y
sAD
(
13
)
BlkWr
(
0
)
BlkWr
(
1
)
VCC3
S
y
sAD
(
14
)
S
y
sAD
(
15
)
S
y
sADP
(
1
)
GND
S
y
sClk
(
8
)
Endian
VCC3
S
y
ncIn
VCC3
S
y
sClk
(
1
)
VCC3
S
y
ncOut
VCC3
S
y
sCLK
(
3
)
VCC3
S
y
sCLK
(
5
)
VCC3
S
y
sCLK
(
7
)
VCC3
S
y
sADP
(
7
)
GND
S
y
sAD
(
63
)
S
y
sAD
(
62
)
S
y
sAD
(
29
)
VCC3
S
y
sAD
(
28
)
S
y
sAD
(
27
)
S
y
sAD
(
26
)
GND
S
y
sAD
(
56
)
VCC5
VCC5
CLKFre
q
(
0
)
CLKFre
q
(
1
)
CLKFre
q
(
2
)
ScDOE*
GND
ScWord
(
0
)
ScWord
(
1
)
L2_Hit
S
y
sCMD
(
8
)
GND
S
y
sAD
(
43
)
S
y
sAD
(
44
)
S
y
sAD
(
45
)
GND
TimerEn*
WrT
y
pe
RSVD
GND
S
y
sAD
(
46
)
S
y
sAD
(
47
)
S
y
sADP
(
5
)
GND
WD_Strb
WDO*
RstOut*
GND
S
y
sCLK
(
0
)
GND
S
y
sCLK
(
2
)
GND
S
y
sCLK
(
4
)
GND
S
y
sCLK
(
6
)
GND
ExtRe
q
*
S
y
sADC
(
3
)
S
y
sAD
(
31
)
S
y
sAD
(
30
)
GND
S
y
sAD
(
61
)
S
y
sAD
(
60
)
S
y
sAD
(
59
)
GND
S
y
sAD
(
58
)
S
y
sAD
(
57
)
S
y
sAD
(
25
)
VCC5
Connector B
4
1999 Integrated Device Technology, Inc. DSC-4266/2
IDTIDT7M9516/18/19/20/21/22/23
PIN DEFINITIONS
Signal Name Signal Definition Type Description
SysAD(63:0) System (CPU) I/O 64-bit multiplexed address/data bus. This bus is driven by the C3 during the address
Address/Data Bus phase (SysCMD(8)=0) of a bus transaction. Valid data is driven by the C3 during the
data phase (SysCMD(8)=1) for writes when ValidOut* is asserted. The C3 receives
data on this bus during the data phase for reads when ValidIn* is sampled low.
SysADP(7:0) SysAD Parity I/O Even parity is generated during the data phase for writes. Even parity is checked during
the data phase for reads if SysCMD(4) is low. Timing and valid sample windows match
SysAD(63:0). SysADP(0) is assosciated with SysAD(7:0), SysADP(1) is associated
withSysAD(15:8).
SysCMD(8:0) System (CPU) I/O This is the 9-bit processor command bus.
command/data
SysCLK(8:0) System (CPU) Output Nine identical clocks for devices residing on the C3 processor bus. All processor
Clocks transitions/transactions are referenced with respect to these clocks.
SyncOut Synchronization Output The C3 system clock generator synchronization output must be connected to SyncIn
Clock Output through an interconnect scheme that matches that used on SysCLK(8:0).
SyncIn Synchronization Input C3 system clock generator synchronization input. This pin must be connected to
Clock Input SyncOut for the C3 to operate.
RdRdy* Read Ready Input This pin is driven low by the system to indicate that the system is ready to accept a C3 read
request.
WrRdy* Write Ready Input This pin is driven low by the system to indicate that the system is ready to accept a C3
write request.
ValidOut* Valid Output Output This pin is driven low by the C3 to indicate that it is driving a valid address/data on the SysAD,
SysADP and SysCMD busses.
ValidIn* Valid Input Input This pin in driven low by the system to indicate that it is presenting valid address/data on
the SysAD, SysADP and SysCMD busses.
Endian Endian Config Endian configuration input.
Input 0=big, 1=little
OutDrv Output Drive Config Output drive strength configuration input.
Input 0=100%, 1=83%
TimerEn* Timer Enable Config CPU internal timer interrupt enable configuration input.
Input 0=enable timer, 1=disable timer
WrType Write Type Config Write Type configuration input.
Input 0=R4X00 compatible, 1=Pipelined
ClockMult(2:0) Clock Multiplier Config 000=x2
Input 001=x3
010=x4
011=x5
100-101=reserved
110=SmartClock mode 0 (max CPU core frequency)
111=SmartClock mode 1(max CPU bus frequency)
BlkWr(1:0) Block Write Config Block Write data rate
Input 00=DDDD
01=DxDxDxD
10=DxxDxxDxxD
11=DxxxDxxxDxxxD
RELEASE* Release Interface Output This pin is driven low to signal to the requesting device that the system interface is available.
ExtReq* External Request Intput This pin is driven low to request the use of the system interface.
4266 tbl 01
5
1999 Integrated Device Technology, Inc. DSC-4266/2
IDT
IDT7M9516/18/19/20/21/22/23
PIN DEFINITIONS (CONTINUED)
Signal Name Signal Definition Type Description
ClkFreq(2:0) SysCLK Config In normal mode these inputs specify the system bus clock frequency. In SmartClock
Frequency Input mode, these inputs specify the maximum system clock frequency.
000=45MHz (includes 43.75/44) 100=75MHz
001=50MHz 101=83MHz
010=60MHz (includes 58.33) 110=90MHz
011=66MHz 111=100MHz
INT*(5:0) Interrupts Input General processor interrupts.
NMI* Non-Maskable Input Non-maskable interrupt
Interrupt
SoftRST* Soft Reset Input Asserting this input causes a processor soft (or warm) reset.
S_HardRST* Synchronous Input Asserting this input causes a processor hard (or cold) reset.
Hard Reset
A_HardRST* Asynchronous Input Asserting this input causes a processor hard (or cold) reset.
Hard Reset
RSTOut* Reset Output Output This pin is asserted by the C3 to reset system logic. This output is asserted during
power-on reset, and whenever HardRST* is asserted.
WDO* Watch Dog Output This pin asserted by the C3 whenever there is a timeout of the watchdog
Output timer.
WD_Strb Watch Dog Input This pin must be strobed periodically by the system to prevent the Strobe watchdog timer
from timing out.
L2_HIT L2 Cache Hit Output This pin indicates to the system that a hit has occurred in the on board
(ScMatch) L2 cache. This pin is a no connect on the 7M9516/18/19/20/23.
ScDOE* Secondary Input Only used when a secondary cache is implemented with the R5K internal
Cache Data cache controller. This pin is a no connect on the 7M9516/18/19/20/23.
OE*
ScWord(1:0) Secondary I/O Only used when a secondary cache is implemented with the R5K internal
Cache Word cache controller
ScTCE* Secondary Cache Output This pin indicates to the system when the L2 cache controller of the R5K is accessing the
Tag Chip Enable Tag RAM. This pin is driven high by the 7M9516/18/19/20/23.
20MHz Out 20MHz Clock Output 20MHz Clock
24MHz Out 24MHz Clock Output 24MHz Clock
GND Ground Supply System Ground
VCC3 +3.3V Supply System 3.3V Supply
VCC5 +5V Supply System 5V Supply
4266 tbl 03
ENVIRONMENTAL
Temp. (°C) Humidity (1) Condition
Min Max Min Max
Operating 0 55 20% 80%
Non-Op. -10 60 10% 90%
Storage -25 60 10% 90%
NOTE:
1. Non-Condensing
4266 tbl 02
6
CORPORATE HEADQUATERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 408-988-5647
Santa Clara, CA 95054 fax: 408-492-8674 ssdhelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
4266 dwg 04
X
Power
X
Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
M 196-pin Mezzanine Connector
333
300
250
200
180
175
150
100
S Standard Power
XXXXX
Device
Type
7M9516
7M9518
7M9519
7M9520
7M9521
7M9522
7M9523
Comm on Bus CPU (C 3) C ard for R4700
Comm on Bus CPU (C 3) C ard for R4650
Comm on Bus CPU (C 3) C ard for R64475
Comm on Bus CPU (C 3) C ard for R5000
Comm on Bus CPU (C 3) C ard for R5000 w/512K L2 Cache
Comm on Bus CPU (C 3) C ard for R5000 w/1MB L2 Cache
Comm on Bus CPU (C 3) C ard for R64575
IDT
Processor Core Frequency (M Hz)
7M9523 Only
7M9523 Only
Excluding 7M 9516 and 7M9518
Excluding 7M 9516 and 7M9523
7M9516 Only
Excluding 7M 9519 and 7M9523
7M9516/18 Only
