[AK5388]
MS1096-E-02 2012/03
- 1 -
GENERAL DESCRIPTION
The AK5388 is a 24bit, 216kHz sampling 4-channel A/D converter for high-end audio systems. The
modulator in the AK5388 uses AKM’s Enhanced Dual Bit architecture, enabling the AK5388 to realize
high accuracy and low cost. The AK5388 achieves 120dB dynamic range and 110dB S/(N+D), and an
optional mono mode extends dynamic range to 123dB. The AK5388’s digital filter features a modified FIR
architecture that minimizes group delay while maintaining excellent linear phase response. So the device
is suitable for professional audio applications including recording, sound reinforcement, effects
processing, sound cards, and high-end A/V receivers. The AK5388 is available in 44pin LQFP package.
FEATURES
Sampling Rate: 8kHz ~ 216kHz
Full Differential Inputs
S/(N+D): 110dB
DR, S/N: 120dB(Mono Mode: 123dB)
Short Delay Digital Filter (GD=12.6/fs)
• Passband: 0~21.648kHz (@fs=48kHz)
• Ripple: 0.01dB
• Stopband: 80dB
Digital HPF
Power Supply: 4.75 ~ 5.25V(Analog), 3.0 ~ 3.6V(Digital)
Output format: 24bit MSB justified, I2S or TDM
Cascade TDM I/F: 8ch/48kHz, 4ch/96kHz, 4ch/192kHz
Master & Slave Mode
Overflow Flag
Power Dissipation: 575 mW (@fs=48kHz)
Package: 44pin LQFP
ΔΣ
Modulator LIN1- LRCK
BICK
SDTO1
VCOM1
Clock Divider
AVDD2AVDD1
Decimation
Filter
Aud io
Interface
Voltage R efere nce
DVDD1VSS6
PDN
LIN1+
ΔΣ
Modulator RIN1- Decimation
Filter
RIN1+
ΔΣ
Modulator
LIN2- Decimation
Filter
LIN2+
ΔΣ
Modulator
RIN2- Decimation
Filter
RIN2+
SDTO2
DIF
TDM0
MSN
MCLK
TDMIN
TDM1
DVDD2
OVF
VCOM2
VSS1 VSS3 VSS4 VSS5
HPF
MONO
CKS0 CKS2
VREFL1 VREFP2 VREFL2
VREFP1 CKS2
AK5388
120dB 24-bit 192kHz 4-Channel ADC
[AK5388]
MS1096-E-02 2012/03
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■ Ordering Guide
AK5388EQ –10 ~ +70°C 44pin LQFP (0.8mm pitch)
AKD5388 Evaluation Board for AK5388
■ Pin Layout
VREFP2
RIN2+
34
VREFL2
3
3
35
VCOM2 36
LIN2+ 37
LIN2- 38
TEST3 39
RIN 1- 40
RIN1+ 41
VCOM1 42
VREFL1 43
VREFP1 44
RIN2- 32
VSS6 31
A
VDD2 30
TE ST2 29
VSS5 28
VSS4 2
7
DVDD2
2
6
HPFE 25
MONO 24
DIF 23
LIN1+ 1
LIN1- 2
VSS1 3
AVDD1 4
TE ST1 5
VSS2 6
CKS
0
7
CKS1 8
CKS
2
9
PDN 10
M/SN 11
22
21
20
19
18
17
16
15
14
13
12
TDM1
TDM0
TDMI N
OVF
SDTO2
SDTO1
VSS3
DV DD1
LRCK
BICK
MCLK
AK5388EQ
Top View
[AK5388]
MS1096-E-02 2012/03
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PIN / FUNCTION
No. Pin Name I/O Function
1 LIN1+ I ADC1 Lch Positive Analog Input Pin
2 LIN1− I ADC1 Lch Negative Analog Input Pin
3 VSS1 - Ground Pin
4 AVDD1 - Analog Power Supply Pin, 4.75 ∼ 5.25V
5 TEST1 I Test Pin (Connected to VSS1-6)
6 VSS2 Ground pin
7 CKS0 I Clock Mode Select #0 Pin
8 CKS1 I Clock Mode Select #1 Pin
9 CKS2 I Clock Mode Select #2 Pin
10 PDN I
Power-Down Mode Pin
When “L”, the circuit is in power-down mode.
The AK5388should always be reset upon power-up.
11 MSN I Master/Slave mode Select Pin
“L”: Slave mode, “H”: Master mode
12 MCLK I Master Clock Input Pin
13 BICK I/O Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
14 LRCK I/O Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
15 DVDD1 - Digital Power Supply Pin, 3.0 ∼ 3.6V
16 VSS3 - Ground Pin
17 SDTO1 O ADC1 Audio Serial Data Output Pin
“L” Output at Power-down mode.
18 SDTO2 O ADC2 Audio Serial Data Output Pin
“L” Output at Power-down mode.
19 OVF O
Analog Input Overflow Detect Pin
This pin goes to “H” if any analog inputs overflows.
“L” Output at Power-down mode.
20 TDMIN I TDM Data Input Pin
21 TDM0 I TDM I/F Format Enable Pin
“L” : Normal Mode, “H” : TDM Mode
22 TDM1 I TDM I/F BICK Frequency Select Pin
“L” : Normal Mode, “H” : TDM Mode
23 DIF I Audio Interface Format Pin
“L”: 24BitMSB justified, “H”: 24BitI2S Compatible
24 MONO I Stereo/Mono mode Select Pin
“L”: Stereo mode, “H”: Mono mode
25 HPFE I HPF Enable Pin
“L”: Disable, “H” Enable
26 DVDD2 - Digital Power Supply Pin, 3.0 ∼ 3.6V
27 VSS4 - Ground Pin
28 VSS5 Ground pin
[AK5388]
MS1096-E-02 2012/03
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No. Pin Name I/O Function
29 TEST2 I Test Pin (Connected to VSS1-6)
30 AVDD2 - Analog Power Supply Pin, 4.75 ∼ 5.25V
31 VSS6 - Ground Pin
32 RIN2− I ADC2 Rch Negative Analog Input Pin
33 RIN2+ I ADC2 Rch Positive Analog Input Pin
34 VREFP2 I ADC2 High Level Voltage Reference Input Pin
35 VREFL2 I ADC2 Low Level Voltage Reference Input Pin
36 VCOM2 O
Common Voltage Output Pin, (AVDD2)/2
Normally connected to AVSS2 with a 0.1μF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2μF.
37 LIN2+ I ADC2 Lch Positive Analog Input Pin
38 LIN2− I ADC2 Lch Negative Analog Input Pin
39 TEST3 I Test Pin (Connected to VSS1-6)
40 RIN1− I ADC1 Rch Negative Analog Input Pin
41 RIN1+ I ADC1 Rch Positive Analog Input Pin
42 VCOM1 O
Common Voltage Output Pin, (AVDD1)/2
Normally connected to AVSS1 with a 0.1μF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2μF.
43 VREFL1 I ADC1 Low Level Voltage Reference Input Pin
44 VREFP1 I ADC1 High Level Voltage Reference Input Pin
Note: All digital input pins should not be left floating.
[AK5388]
MS1096-E-02 2012/03
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■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification Pin Name Setting
LIN1+/−, RIN1+/− These pins should be connected to VSS1-6
Analog LIN2+/−, RIN+/− These pins should be connected to VSS1-6
OVF This pin should be open.
TEST1 This pin should be connected to VSS1-6
TEST2 This pin should be connected to VSS1-6
Digital
TEST3 This pin should be connected to VSS1-6
ABSOLUTE MAXIMUM RATINGS
(VSS1-6=0V; Note 1)
Parameter Symbol min max Units
Power
Supplies:
Analog
Analog
Digital
Digital Output Buffer
AVDD1
AVDD2
DVDD1
DVDD2
−0.3
−0.3
−0.3
−0.3
6.0
6.0
6.0
6.0
V
V
V
V
Input Current, Any Pin Except Supplies IIN − ±10 mA
Analog Input Voltage (Note 2)
VINA
VINA
−0.3
−0.3
AVDD1+0.3
AVDD2+0.3 V
Digital Input Voltage (Note 3)
VIND
VIND
−0.3
−0.3
DVDD1+0.3
DVDD2+0.3 V
Ambient Temperature (power applied) Ta −10 70 °C
Storage Temperature Tstg −65 150 °C
Note 1. All voltages with respect to VSS1-6 pins.
Note 2. VREFP1, VREFP2, VREFL1, VREFL2, AINL1/2+, AINL1/2-, AINR1/2+ and AINR1/2- pins
Note 3. PDN, CKS0, CKS1, CKS2, TDMIN, MCLK, BICK, LRCK, DIF, TDM0, TDM1, HPFE, MONO and TST1/2/3
pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
[AK5388]
MS1096-E-02 2012/03
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RECOMMENDED OPERATING CONDITIONS
(VSS1-6=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies:
Analog
Analog
AVDD1
AVDD2
4.75
4.75
5.0
5.0
5.25
5.25
V
V
(Note 4) Digital DVDD1/2 3.0 3.3 3.6 V
Voltage Reference
(Note 5)
“H” voltage Reference
“L” voltage reference
VREFP1 – VREFL1
VREFP2 – VREFL2
VREFP1
VREFP2
VREFL1
VREFL2
ΔVREF
ΔVREF
AVDD1-0.5
AVDD2-0.5
VSS1-6
VSS1-6
AVDD1-0.5
AVDD2-0.5
-
-
-
-
-
-
AVDD1
AVDD2
-
-
AVDD1
AVDD2
V
V
V
V
V
V
Note 1. All voltages with respect to VSS1-6 pins.
Note 4. The power up sequence between AVDD1/2 and DVDD1/2 is not critical.
Note 5. VREFL– and VREFR– pins should be connected to VSS1-6 pins.
Analog input voltage scales with voltage of {(VREFP) – (VREFL)}.
Vin (typ, @ 0dB) = ±2.8 x {(VREF+) – (VREF–)} / 5 [V].
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK5388]
MS1096-E-02 2012/03
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ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD1/2=5.0V; DVDD1/2=3.3V; VSS1-6=0V; VREFP1=VREFP2=AVDD, VREFL1 = VREFL2 =
VSS1-6; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz ∼
20kHz at fs = 48kHz, 40Hz ∼ 40kHz at fs = 96kHz, 40Hz ∼ 40kHz at fs = 192kHz; unless otherwise specified)
Parameter min typ max Units
Analog Input Characteristics:
Resolution - - 24 Bits
Input Voltage (Note 6)±2.7 ±2.8 ±2.9 Vpp
fs=48kHz
BW=20kHz
−1dBFS
−20dBFS
−60dBFS
100
-
-
110
97
57
-
-
-
dB
dB
dB
fs=96kHz
BW=40kHz
−1dBFS
−20dBFS
−60dBFS
97
-
-
107
90
50
-
-
-
dB
dB
dB
S/(N+D)
fs=192kHz
BW=40kHz
−1dBFS
−20dBFS
−60dBFS
-
-
-
107
90
50
-
-
-
dB
dB
dB
Dynamic Range
(−60dBFS with A-weighted)
Stereo Mode
Mono Mode
114
-
120
123
-
- dB
S/N
(A-weighted)
Stereo Mode
Mono Mode
114
-
120
123
-
- dB
Input Resistance 3.3 3.7 4.1 kΩ
Interchannel Isolation 110 120 dB
Interchannel Gain Mismatch 0.1 0.5 dB
Power Supply Rejection (Note 7) 60 - dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD1/2
DVDD (fs=48kHz)
DVDD (fs=96kHz)
DVDD (fs=192kHz)
Power down mode (PDN pin = “L”) (Note 8)
AVDD+DVDD
105
15
27
20
10
130
22
39
29
100
mA
mA
mA
mA
μA
Note 6. This value is (LIN+)−(LIN−) and (RIN+)−(RIN−). Input voltage is proportional to VREF voltage.
Vin = 0.56 x VREF1/2 (Vpp).
Note 7. PSR is applied to AVDD1/2 and DVDD1/2 with 1kHz, 20mVpp. The VREFP1 and VREFP2 pins held a constant
voltage.
Note 8. All digital input pins are held DVDD1/2 or VSS3/4.
[AK5388]
MS1096-E-02 2012/03
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FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “L”, DFS0 = “L”)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 9)
−0.01dB
−0.1dB
−3.0dB
−6.0dB
PB
0
-
-
-
22.0
23.8
24.4
21.6
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 27.9 kHz
Passband Ripple PR ±0.01 dB
Stopband Attenuation SA 80 dB
Group Delay (Note 10) GD 12.6 1/fs
Group Delay Distortion ΔGD ±0.01 μs
ADC Digital Filter (HPF):
Frequency Response (Note 9)
−3dB
−0.1dB
FR
1.0
6.5
Hz
Hz
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “L”, DFS0 = “H”)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 9)
−0.01dB
−0.1dB
−3.0dB
−6.0dB
PB
0
-
-
-
44.2
47.6
48.9
43.3
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 55.9 kHz
Passband Ripple PR ±0.01 dB
Stopband Attenuation SA 80 dB
Group Delay (Note 10) GD 12.6 1/fs
Group Delay Distortion ΔGD ±0.013 μs
ADC Digital Filter (HPF):
Frequency Response (Note 9)
−3dB
−0.1dB
FR
1.0
6.5
Hz
Hz
Note 9. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
[AK5388]
MS1096-E-02 2012/03
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FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “H”, DFS0 = “L”)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 11)
−0.08dB
−0.1dB
−3.0dB
−6.0dB
PB
-
-
-
-
-
83.4
99.9
106.5
83.0
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 141.1 kHz
Passband Ripple PR ±0.08 dB
Stopband Attenuation SA 80 dB
Group Delay (Note 12) GD 9.8 1/fs
Group Delay Distortion ΔGD 0 μs
ADC Digital Filter (HPF):
Frequency Response (Note 11)
−3dB
−0.1dB
FR
1.0
6.5
Hz
Hz
Note 11. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 12. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V)
Parameter Symbol min typ Max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%DVDD1
70%DVDD2
-
-
-
-
-
-
30%DVDD1
30%DVDD2
V
V
V
V
High-Level Output Voltage (Iout=−400μA)
Low-Level Output Voltage (Iout=400μA)
VOH
VOL
DVDD1−0.4
DVDD2−0.4
-
-
-
-
-
0.4
V
V
V
Input Leakage Current Iin - - ±10 μA
[AK5388]
MS1096-E-02 2012/03
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Master Clock 128fs:
Pulse Width Low
Pulse Width High
192fs:
Pulse Width Low
Pulse Width High
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
768fs:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
1.024
0.4fCLK
0.4fCLK
1.536
0.4fCLK
0.4fCLK
2.048
0.4fCLK
0.4fCLK
3.072
0.4fCLK
0.4fCLK
4.096
0.4fCLK
0.4fCLK
6.144
0.4fCLK
0.4fCLK
24.576
36.864
12.288
18.432
24.576
36.864
27.648
41.472
27.648
41.472
27.648
41.472
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK Timing (Slave Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
fs
Duty
8
45
216
55
kHz
%
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/256fs
1/256fs
54
kHz
ns
ns
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/128fs
1/128fs
216
kHz
ns
ns
LRCK Timing (Master Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
fs
Duty
8
50
216
kHz
%
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time (Note 13)
fs
tLRH
8
1/8fs
54
kHz
ns
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time (Note 13)
fs
tLRH
8
1/4fs
216
kHz
ns
Note 13. “L” time at I2S format
[AK5388]
MS1096-E-02 2012/03
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Parameter Symbol min typ max Units
Audio Interface Timing (Slave mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Period
Normal Speed Mode
Double , Quad Speed Mode
Duty Cycle
LRCK Edge to BICK “↑” (Note 14)
BICK “↑” to LRCK Edge (Note 14)
LRCK to SDTO1/2 (MSB) (Except I2S mode)
BICK “↓” to SDTO1/2
TBCK
TBCK
Duty
tLRB
tBLR
tLRS
tBSD
1/128fs
1/64fs
40
20
20
60
20
ns
ns
%
ns
ns
ns
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑” (Note 14)
BICK “↑” to LRCK Edge (Note 14)
BICK “↓” to SDTO1/2 (Note 15)
TDMIN Setup time
tBCK
Duty
tLRB
tBLR
tBSD
tTDMS
1/256fs
40
20
20
16
60
20
ns
%
ns
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8KHz ≤ fs < 108KHz)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑” (Note 14)
BICK “↑” to LRCK Edge (Note 14)
BICK “↓” to SDTO1 (Note 15)
tBCK
Duty
tLRB
tBLR
tBSD
1/128fs
40
20
20
60
20
ns
%
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(108KHz < fs ≤ 216KHz)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑” (Note 14)
BICK “↑” to LRCK Edge (Note 14)
SDTO1 Setup time BICK “↑ “ (Note 15)
SDTO1 Hold time BICK “↑ “ (Note 15)
tBCK
Duty
tLRB
tBLR
tBSS
tBSH
1/128fs
40
10
10
10
5
60
ns
%
ns
ns
ns
ns
[AK5388]
MS1096-E-02 2012/03
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Parameter Symbol min typ max Units
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
20
Hz
%
ns
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
BICK Duty (Note 16)
BICK “↓” to LRCK
BICK “↓” to SDTO1 (Note 15)
fBCK
dBCK
tMBLR
tBSD
−12
−20
256fs
50
12
20
Hz
%
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8KHz ≤ fs < 108KHz)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1 (Note 15)
fBCK
dBCK
tMBLR
tBSD
−12
−20
128fs
50
12
20
Hz
%
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(108KHz < fs ≤ 216KHz)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
fBCK
dBCK
tMBLR
tBSD
−6
−10
128fs
50
6
10
Hz
%
ns
ns
Power-Down & Reset Timing
PDN Pulse Width (Note 17)
PDN “↑” to SDTO1/2 valid (Note 18)
tPD
tPDV
150
516
ns
1/fs
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. SDTO2 output is fixed to “L”.
Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 17. The AK5388 can be reset by bringing the PDN pin = “L”.
Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”. The value is when the AK5388 is in
master mode. In case of in slave mode, the value will be 1LRCK clock cycle (1/fs) longer.
[AK5388]
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■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
Figure 1. MCLK Timing (TDM0 pin = “L” or “H”)
1/fs
LRCK VIH
VIL
tLRLtLRH
Figure 2. LRCK Timing (TDM0 pin = “L” or “H”)
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Duty = tBCKH/tBCK, tBCKL/tBCK
Figure 3.BICK Timing (TDM0 pin = “L” or “H”)
[AK5388]
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LRCK VIH
VIL
tBLR
BICK VIH
VIL
tLRS
SDTO 50%DVDD
tLRB
tBSD
Figure 4. Audio Interface Timing (Slave mode, TDM0 pin = “L”)
Note: SDTO shows SDTO1 and SDTO2.
TDMIN VIH
VIL
LRCK VIH
VIL
tBLR
BICK VIH
VIL
SDTO1 50%DVDD
tLRB
tBSD
tTDMS
Figure 5. Audio Interface Timing (Slave mode, TDM0 pin = “H”)
[AK5388]
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LRCK VIH
VIL
tBLR
BICK VIH
VIL
SDTO1 50%DVDD
tLRB
tBSD
Figure 6. Audio Interface Timing (Slave mode, TDM0 pin = “H”, TDM1 pin = “H”, 8KHz ≤ fs < 108KHz)
LRCK VIH
VIL
tBLR
BICK VIH
VIL
tBSS
SDTO1 50%DVDD
tLRB
tBSH
DATA
Figure 7. Audio Interface Timing (Slave mode, TDM0 pin = “H”, TDM1 pin = “H”, 108KHz < fs ≤ 216KHz)
[AK5388]
MS1096-E-02 2012/03
- 16 -
LRCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tMBLR dBCK
50%DVDD
Figure 8. Audio Interface Timing (Master mode)
PDN VIH
VIL
tPDV
SDTO 50%DVDD
tPD
Figure 9. Power Down & Reset Timing
Note: SDTO shows SDTO1 and SDTO2.
[AK5388]
MS1096-E-02 2012/03
- 17 -
OPERATION OVERVIEW
■ System Clock
MCLK (128fs/192fs/256fs/384fs/512fs/768fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The
LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1, Table 2 and Table 3
show the relationship of typical sampling frequency and the system clock frequency. MCLK frequency is selected by
CKS1-0 pins as shown in Table 4.
Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the
synchronization is out of phase after changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”. In case of using two or more devices, the AK5388 should be reset
by the PDN pin when changing clocks, changing clock modes and switching digital interfaces for a synchronization.
Clock or mode changes should be made during the reset, and a stable clock is needed after the reset.
MCLK
fs 128fs 192fs 256fs 384fs 512fs 768fs
32kHz N/A N/A 8.192MHz 12.288MHz 16.384MHz 24.576MHz
48kHz N/A N/A 12.288MHz 18.432MHz 24.576MHz 36.864MHz
96kHz N/A N/A 24.576MHz N/A N/A N/A
192kHz 24.576MHz 36.864MHz N/A N/A N/A N/A
(N/A: Not available)
Table 1. System Clock Example (Slave Mode)
MCLK
fs 128fs 192fs 256fs 384fs 512fs 768fs
32kHz N/A N/A 8.192MHz 12.288MHz 16.384MHz 24.576MHz
48kHz N/A N/A 12.288MHz 18.432MHz 24.576MHz 36.864MHz
96kHz N/A N/A 24.576MHz 36.864MHz N/A N/A
192kHz 24.576MHz 36.864MHz N/A N/A N/A N/A
(N/A: Not available)
Table 2. System Clock Example (Master Mode)
MCLK
fs 128fs 192fs 256fs 384fs 512fs 768fs
32kHz N/A N/A N/A N/A 16.384MHz 24.576MHz
48kHz N/A N/A N/A N/A 24.576MHz 36.864MHz
96kHz N/A N/A 24.576MHz 36.864MHz N/A N/A
192kHz 24.576MHz 36.864MHz N/A N/A N/A N/A
(N/A: Not available)
Table 3. System Clock Example (Auto Mode)
[AK5388]
MS1096-E-02 2012/03
- 18 -
CKS2 pin CKS1 pin CKS0 pin M/S Pin MCLK Frequency
L
L L L
H
Quad Speed Mode
128fs (108KHz < fs ≤ 216KHz)
L
L L H
H
Quad Speed Mode
192fs (108KHz < fs ≤ 216KHz)
L
L H L
H
Normal Speed Mode
256fs (8KHz ≤ fs ≤ 54KHz)
L
L H H
H
Double Speed Mode
256fs (54KHz < fs ≤ 108KHz)
L Auto (8KHz ≤ fs ≤ 216KHz)
H L L
H Double Speed Mode
384fs (54KHz < fs ≤ 108KHz)
L
H L H
H
Normal Speed Mode
384fs (8KHz ≤ fs ≤ 54KHz)
L
H H L
H
Normal Speed Mode
512fs (8KHz < fs ≤ 54KHz)
H H H L Normal Speed Mode
768fs (8KHz ≤ fs ≤ 54KHz)
Table 4. MCLK Frequency
When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = “L”.
■ Audio Interface Format
12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in Table 5. The
audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The
SDTO1/2 is clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock
in Mode 2-3.
In TDM256 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pins. The SDTO2 output is
fixed to “L”. BICK should be fixed to 256fs. In slave mode, “H” time and “L” time of LRCK should be at least 1/256fs. In
master mode, “H” time (“L” time at I2S mode) of LRCK is 1/8fs (typ). TDM256 mode only supports 48kHz sampling.
In TDM128 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed
to “L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be at least 1/128fs. In
master mode, “H” time (“L” time at I2S mode) of LRCK is 1/4fs (typ). TDM128 mode supports up to 192kHz sampling.
[AK5388]
MS1096-E-02 2012/03
- 19 -
LRCK BICK
Mode TDM1 TDM0 M/S DIF SDTO I/O I/O
0 L 24bit, MSB justified H/L I 48-128fs I
1 L H 24bit, I2S Compatible L/H I 48-128fs I
2 L 24bit, MSB justified H/L O 64fs O
3
Normal L L
H H 24bit, I2S Compatible L/H O 64fs O
4 L 24bit, MSB justified ↑ I 256fs I
5 L H 24bit, I2S Compatible ↓ I 256fs I
6 L 24bit, MSB justified ↑ O 256fs O
7
TDM256 L H
H H 24bit, I2S Compatible ↓ O 256fs O
8 L 24bit, MSB justified ↑ I 128fs I
9 L H 24bit, I2S Compatible ↓ I 128fs I
10 L 24bit, MSB justified ↑ O 128fs O
11
TDM128 H H
H H 24bit, I2S Compatible ↓ O 128fs O
12 N/A H L N/A N/A N/A N/A N/A N/A N/A
Table 5. Audio Interface Formats (N/A: Not available)
LRCK
BICK(64fs)
SDTO1/2(o)
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0
23
1
22 023 22 12 11 10 0 23
Lch Data Rch Data
12 11 10
23:MSB, 0:LSB
Figure 10. Mode 0/2 Timing (Normal mode, MSB justified)
LRCK
BICK(64fs)
SDTO1/2(o)
0 1 2 3 23 24 25 26 0 0 13129 30
23 22 1
23:MSB, 0:LSB Lch Data Rch Data
2 0
2 3 23 24 25 26 03129 30
23 22 12 0
1
Figure 11. Mode 1/3 Timing (Normal mode, I2S Compatible)
23
LRCK (Mode 4)
BICK (256fs)
SDTO1 22 0
L1
32 BICK
256 BICK
22 0
R1
32 BICK
2223 2322 0
L2
32 BICK
22 0
R2
32 BICK
23 23
LRCK (Mode 6)
Figure 12. Mode 4/6 Timing (TDM256 mode, MSB justified)
[AK5388]
MS1096-E-02 2012/03
- 20 -
LRCK (Mode5)
BICK (256fs)
SDTO1 23 0
L1
32 BICK
256 BICK
23 0
R1
32 BICK
2323 0
L2
32 BICK
23 0
R2
32 BICK
LRCK (Mode 7)
Figure 13. Mode 5/7 Timing (TDM256 mode, I2S Compatible)
LRCK (Mode 8)
BICK (128fs)
128 BICK
L1
32 BICK R1
32 BICK L2
32 BICK R2
32 BICK
SDTO1 22 022 022 022 023 23 23 23 2223
LRCK (Mode 10)
Figure 14. Mode 8/10 Timing (TDM128 mode, MSB justified)
LRCK (Mode 9)
BICK (128fs)
128 BICK
L1
32 BICK R1
32 BICK L2
32 BICK R2
32 BICK
SDTO1 22 022 022 022 023 23 23 23 23
LRCK (Mode 11)
Figure 15. Mode 9/11 Timing (TDM128 mode, I2S Compatible)
[AK5388]
MS1096-E-02 2012/03
- 21 -
■ Digital High Pass Filter (HPF)
The ADC has a digital high pass filter for DC offset cancellation. The HPF is controlled by the HPFE pin. If the HPF
setting (ON/OFF) is changed during operation, a click noise occurs due to the change in DC offset. The HPF setting
should only be changed when the PDN pin = “L”.
■ Overflow Detection
The AK5388 has an overflow detect function for the analog input. The OVF pin goes to “H” if either channel overflows
(more than −0.3dBFS). OVF output for overflowed analog input has the same group delay as the ADC
(GD=13/fs=0.27ms@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after the PDN pin = “↑”, and then
overflow detection is enabled.
■ Power Down and Reset
The AK5388 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog
initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK
clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are
forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of initialization (Settling
takes approximately the group delay time).
The AK5388 should be reset once by bringing the PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
Normal Operation
Internal
State
PDN
Power-d own Initia lize N orm al O per ation
(1)
Idle Noise
GD GD
“0”data
A
/D In
(Analog)
A
/D Ou
t
(Digital)
Clock In
MCLK,LRCK,SCLK
(2)
(3)
(4)
“0”data Idle Noise
Notes:
(1) 517/fs in slave mode and 516/fs in master mode.
(2) Digital output corresponding to analog input has group delay (GD).
(3) A/D output is “0” data in power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5388 should be in the power-down state.
Figure 16. Power-down/up sequence example
[AK5388]
MS1096-E-02 2012/03
- 22 -
■ Cascade TDM Mode
The AK5388 supports cascading of up to two devices in a daisy chain configuration in TDM256 mode. In this mode,
SDTO1 pin of device #1 is connected to TDMIN pin of device #2. The SDTO1 pin of device #2 can output 8-chnnels of
TDM data multiplexed with 4-chnnel of TDM data from device #1 and 4-channel of TDM data from device #2. Figure 17
shows a connection example of a daisy chain.
When using two AK5388’s in slave mode by cascade connection, the internal timing between device #1 and #2 may differ
for 1MCLK clock cycle. BICK falling edge must me more than ±10ns from a MICK rising edge to prevent this phase
difference between two devices. (Table 6)
BICK must be divided by two on a MCLK falling edge (Figure 19) when MCLK=2 x BICK (Normal speed 512fs mode or
Double speed 256fs mode), and BICK must be in-phase signal to MCLK (Figure 20) when MCLK = BICK (Normal
speed 256fs mode or Quad speed 128fs mode) to achieve this internal timing synchronization.
48kHz
256fs
8ch TDM
LRC
K
A
K5388 #1
BIC
K
TDMIN
SDTO1
SDTO2
MCL
K
256fs or 512fs
GND
LRC
K
A
K5388 #
2
BIC
K
TDMIN
SDTO1
SDTO2
MCL
K
Figure 17. Cascade TDM Connection Diagram
LRCK
BICK(256fs)
#1 SD TO1(o) 22 0
L1
32 BICK
256 BICK
22 0
R1
32 BICK
2223 23 2322 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#1 SD TO2(o) 22 0
L1
32 BICK
22 0
R1
32 BICK
23 23 22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#2 TDMIN(i) 22 0
L1
32 BICK
22 0
R1
32 BICK
23 23 22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#2 SD TO1(o) 22 0
L1
32 BICK
22 0
R1
32 BICK
2223 23 2322 0
L2
32 BICK
22 0
R2
32 BICK
23 23 22 0
L1-#1
32 BICK
22 0
R1-#1
32 BICK
23 23 22 0
L2-#1
32 BICK
22 0
R2-#1
32 BICK
23 23
Figure 18. Cascade TDM Timing
[AK5388]
MS1096-E-02 2012/03
- 23 -
Parameter Symbol min typ max Units
MCLK “↑” to BICK “↓”
BICK “↓” to MCLK“↑”
tMCB
tBIM
10
10
ns
ns
Table 6 TDM Mode Clock Timing
tBIM
VIH
tMCB
MCLK VIL
VIH
BICK VIL
Figure 19. Audio Interface timing (Slave mode, TDM0 Mode MCLK=2 x BICK)
tBIM
VIH
tMCB
MCLK VIL
VIH
BICK VIL
Figure 20. Audio Interface Timing (Slave mode, TDM0 Mode MCLK=BICK)
■ Mono mode
When the MONO pin is set to “H”, the AK5388 is in Mono mode. In this mode, dynamic range and S/N can be improved
by approximately 3dB when the same analog signal is inputted to LIN1 and RIN1, LIN2 and RIN2. The LIN1 and RIN1
data are summed and the amplitude is attenuated into half to be output from the SDTO1 pin. The LIN2 and RIN2 data are
summed and the amplitude is attenuated into half to be output from the SDTO2 pin.
MONO pin SDTO1/2 Output Data
L Stereo Mode
H Mono Mode
Table 7. Setup of MONO mode
[AK5388]
MS1096-E-02 2012/03
- 24 -
SYSTEM DESIGN
Figure 21 and Figure 22 show the system connection diagram. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
LIN1+
VREFP1
1
LIN1-
2
VSS1 3
A
VDD14
TEST1
5
VSS2 6
CKS0 7
CKS1 8
CKS2
9
PDN 10
M_SN 11
VREFL1
VCOM1 42
RIN1+ 41
RIN1
-
TEST3
LIN2
-
38
LIN2+ 37
VCOM2 36
VREFL2 35
VREFP2 34
MCLK
12
BICK
LRCK
14
DVDD1
15
VSS3
SDTO1
SDTO2
18
OVF
19
TDMIN
20
TDM0
21
TDM1
22
33
32
31
30
29
28
27
26
25
24
23
RIN 2+
RIN2-
VSS6
AVDD2
TE ST2
VSS5
VSS4
DVDD2
HP FE
MONO
DIF
AK5388
To p Vi ew +Digital3.3
v
0.1u 10u
+
Analog5.0V
10u0.1u
0.1u
10u +
0.1u
2.2u
+
10u 0.1u
0.1u
+
0.1u
+ +
Analog5.0V
+
0.1u
+
Digital3.3v
10u 2.2u
10u
Ceram ic Capacitor
+ Electrolyti c Capacitor
LIN1+
LIN1-
RIN2+
RIN2-
LIN2+
LIN2-
RIN1+
RIN1-
Micro-
Controller
fs
64fs
Micro-
Controller
A
nalog
Digital
Digital
Note:
- VSS1-6 should be distributed separately from the ground of external digital devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 21. Typical Connection Diagram
[AK5388]
MS1096-E-02 2012/03
- 25 -
Analog Ground Digit al Ground
System
Controller
LIN1+
VREFP1
1
LIN1-
44
2
VSS13
A
VDD14
TEST1
5
VSS2 6
CKS0 7
CKS18
CKS2
9
PDN10
M/SN11
MCLK 12
33
RIN2+
AK5388EQ
13
14
15
16
17
18
19
20
21
22
BICK
LRCK
DVDD1
VSS3
SDTO1
SDTO2
OVF
TD MIN
TDM0
TDM1
32 RIN2-
31 VSS6
30
A
VDD2
29 TEST2
28 VSS5
27 VSS4
26 DVDD2
25 HPFE
24 MONO
23
DIF
VREFL1 43
VCOM1 42
RIN1+ 41
RIN1- 40
TEST3 39
LIN2- 38
LIN2+ 37
VCOM
2
36
VREFL2 35
VREFP
2
34
Figure 22. Ground Layout
Note: VSS1-6 must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK5388 requires careful attention to power supply and grounding arrangements. AVDD1/2 and DVDD1/2 are
usually supplied from the system’s analog supply. Alternatively if AVDD1/2 and DVDD1/2 are supplied separately, the
power up sequence is not critical. VSS1-6 of the AK5388 must be connected to the analog ground plane. System
analog ground and digital ground should be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors should be as near to the AK5388 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference Inputs
The reference voltage for A/D converter is supplied from VREFP1/2 pins at VREFL1/2 reference. VREFL1/2 pins are
connected to analog ground and an electrolytic capacitor over 10μF parallel with a 0.1μF ceramic capacitor between the
VREFP1/2 pins and the VREFL1/2 pins eliminate the effects of high frequency noise. It is important that a ceramic
capacitor should be as near to the pins as possible. All digital signals, especially clocks, should be kept away from the
VREFP1/2 pins in order to avoid unwanted coupling into the AK5388.
VCOM1/2 is a signal ground for this device. An electrolytic capacitor (2.2µF typical) attached to the VCOM1/2 pins
eliminates the effects of high frequency noise. It is important that a ceramic capacitor should be as near to the pins as
possible. No load current may be drawn from the VCOM1/2 pins. All signals, especially clocks, should be kept away
from the VCOM1/2 pins in order to avoid unwanted coupling into the AK5388.
3. Analog Inputs
The Analog input signal is differentially supplied into the modulator via the LIN+ (RIN+) and the LIN− (RIN−) pins. The
input voltage is the difference between the LIN+ (RIN+) and LIN− (RIN−) pins. The full scale signal on each pin is
nominally ±2.8Vpp(typ). The AK5388 can accept input voltages from VSS1-6 to AVDD1/2. The ADC output data
format is two’s complement. The internal HPF removes DC offset.
The AK5388 samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects
noise above the stop band except for multiples of 128fs. The AK5388 includes an anti-aliasing filter (RC filter) to
attenuate a noise around 128fs.
The AK5388 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of AVDD1/2+0.3V and
lower limit of VSS1-6 − 0.3V and any current beyond 10mA for the analog input pins (LIN+/−, RIN+/−) should be
avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at
or beyond these limits. Use caution especially when using ±15V for other analog circuits in the system.
[AK5388]
MS1096-E-02 2012/03
- 26 -
4. External Analog Circuit Examples
Figure 23 shows an input buffer circuit example 1. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351kHz, gain=-14.5dB).
The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2
for XLR input). The input level of this circuit is +/-15.0Vpp (AK5388: +/-2.8Vpp Typ.). When using this circuit, analog
characteristics at fs=48kHz is DR=120dB, S/(N+D)=110dB.
4.7k
-
+ -
+
91
3.3k
620
-
+
91
620
Analog In
15.4Vpp
68µ
NJM5534
VA=+5
VP=±15
4.7k
10
µ
+
10k
10k
0.1
µ
Bias
VA+
2.9Vpp
2.9Vpp
VP+
VP- Bias
1n
3.3k
1n
Bias
2.2n
68µ
XLR
Vin+
Vin-
JP1
JP2
NJM5534
NJM5534
A
K5388 AIN+
A
K5388 AIN-
Figure 23.Input Buffer example1
fin 1Hz 10Hz
Frequency Response −1.77dB −0.02dB
Table 8. Frequency Response of HPF
fin 20kHz 40kHz 80kHz 6.144MHz
Frequency Response 0.00dB 0.00dB 0.00dB −49.68dB
Table 9. Frequency Response of LPF
[AK5388]
MS1096-E-02 2012/03
- 27 -
Figure 24 shows an input buffer circuit example in Mono mode. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351kHz,
gain=-14.5dB).
4.7k -
+ -
+
11
3.3k
620
-
+
11
620
Analog In
15.0Vpp
68µ
NJM5534
VA=+5V
VP=
±
15V
4.7k
10µ
+
11k
10k
0.1µ
Bias
VA+
2.8Vpp
2.8Vpp
VP+
VP- Bias
1n
3.3k
1n
Bias
15n
68µ
XLR
Vin+
Vin -
JP 1
JP2
NJM5534
NJM5534
A
K5388 LIN+
A
K5388 LIN -
15n
A
K5388 RIN+
A
K5388 RIN-
Figure 24 External Analog Circuit Examples
fin 1Hz 10Hz
Frequency Response −1.77dB −0.02dB
Table 10. Frequency Response of HPF
fin 20kHz 40kHz 80kHz 6.144MHz
Frequency Response 0.00dB 0.00dB 0.00dB −49.68dB
Table 11. Frequency Response of LPF
[AK5388]
MS1096-E-02 2012/03
- 28 -
5. Performance Plot
Figure 25 shows a FFT measurement result.
[Conditions]
Ta=25ºC; AVDD1/2=5.0V; VREFP1/2=5.0V, VREFL1/2=0V, DVDD=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
fs=48kHz; Signal Frequency =1kHz, -1dBFS, Measured by Audio Precision, System Two.
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 25. FFT (Blue: Left Channel, Red: Right Channel)
[AK5388]
MS1096-E-02 2012/03
- 29 -
PACKAGE
0.10
0.17±0.05
0.37±0.08
10.0
1.70ma
x
111
23
33
44
p
in LQFP
(
Uni t: mm
)
10.0
12.8±0.3
34
44
0.8
22
12
12.8±0.3
0.10±0.10
0°
∼
10°
0.6
±
0.20
1.40
0.20 M
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
[AK5388]
MS1096-E-02 2012/03
- 30 -
MARKING
A
K5388EQ
XXXXXXX
A
KM
1
1) Pin #1 indication
2) Audio 4 pro Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK5388
5) AKM Logo
Date (YY/MM/DD) Revision Reason Page Contents
09/07/09 00 First Edition
09/08/20 01 Error Correct 1 Pin names of block diagram were changed.
VRP1 →VREFP1, VRL1 →VREFL1
VRP2 →VREFP2, VRL2 →VREFL2
22 ■ Cascade TDM Mode
Figure 17 and description were corrected.
SDTO2 is connected to TDMIN
→
SDTO1 is connected to TDMIN
26 Figure 23
A resistor value was corrected. 3.3 → 3.3k
28 [Conditions]
VREFL1/2=5.0V → =0V
12/03/05 02 Error Correct 18 Table 4 was changed.
128fs (108KHz < fs ≤ 216KHz)
Double Speed Mode → Quad Speed Mode
REVISION HISTORY
[AK5388]
MS1096-E-02 2012/03
- 31 -
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.