LH28F640BFE-PBTL90 - Sharp Electronics Corp.

®

Integrated Circuits Group

LH28F640BFE-PBTL90

Flash Memory

64M (4M × 16)

(Model No.: LHF64F11)

Issue Date: August 29, 2001

PRELIMINARY PRODUCT SPECIFICATIONS

LHF64F11

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,

full or in part, of this material is prohibited without the express written permission of the company.

• When using the products covered herein, please observe the conditions written herein and the precautions outlined in

the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly

adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application areas. When using the

products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure

to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph

(3).

• Office electronics

• Instrumentation and measuring equipment

• Machine tools

• Audiovisual equipment

• Home appliance

• Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which demands high

reliability, should first contact a sales representative of the company and then accept responsibility for

incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring

reliability and safety of the equipment and the overall system.

• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment

• Mainframe computers

• Traffic control systems

• Gas leak detectors and automatic cutoff devices

• Rescue and security equipment

• Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands extremely high performance

in terms of functionality, reliability, or accuracy.

• Aerospace equipment

• Communications equipment for trunk lines

• Control equipment for the nuclear power industry

• Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales

representative of the company.

• Please direct all queries regarding the products covered herein to a sales representative of the company.

Rev. 2.41

sharp

LHF64F11 1

PAGE

48-Lead TSOP Pinout................................................. 3

Pin Descriptions.......................................................... 4

Simultaneous Operation Modes

Allowed with Four Planes .................................. 5

Memory Map.............................................................. 6

Identifier Codes and OTP Address

for Read Operation ............................................. 7

Identifier Codes and OTP Address for

Read Operation on Partition Configuration........ 7

OTP Block Address Map for OTP Program............... 8

Bus Operation............................................................. 9

Command Definitions .............................................. 10

Functions of Block Lock and Block Lock-Down..... 12

Block Locking State Transitions upon

Command Write................................................ 12

Block Locking State Transitions upon

WP# Transition................................................. 13

Status Register Definition......................................... 14

PAG E

Extended Status Register Definition......................... 15

Partition Configuration Register Definition.............. 16

Partition Configuration ............................................. 16

1 Electrical Specifications......................................... 17

1.1 Absolute Maximum Ratings ........................... 17

1.2 Operating Conditions ...................................... 17

1.2.1 Capacitance .............................................. 18

1.2.2 AC Input/Output Test Conditions ............ 18

1.2.3 DC Characteristics ................................... 19

1.2.4 AC Characteristics

- Read-Only Operations ......................... 21

1.2.5 AC Characteristics

- Write Operations ................................. 24

1.2.6 Reset Operations ...................................... 26

1.2.7 Block Erase, Full Chip Erase,

(Page Buffer) Program and

OTP Program Performance.................... 27

2 Related Document Information.............................. 28

CONTENTS

Rev. 2.41

sharp

LHF64F11 2

LH28F640BFE-PBTL90

64Mbit (4Mbit×16)

Page Mode Dual Work Flash MEMORY

64M density with 16Bit I/O Interface

High Performance Reads

• 90/35ns 8-Word Page Mode

Configurative 4-Plane Dual Work

• Flexible Partitioning

• Read operations during Block Erase or (Page Buffer)

Program

• Status Register for Each Partition

Low Power Operation

• 2.7V Read and Write Operations

• VCCQ for Input/Output Power Supply Isolation

• Automatic Power Savings Mode Reduces ICCR

in Static Mode

Enhanced Code + Data Storage

• 5µs Typical Erase/Program Suspends

OTP (One Time Program) Block

• 4-Word Factory-Programmed Area

• 4-Word User-Programmable Area

High Performance Program with Page Buffer

• 16-Word Page Buffer

• 5µs/Word (Typ.) at 12V VPP

Operating Temperature 0°C to +70°C

CMOS Process (P-type silicon substrate)

Flexible Blocking Architecture

• Eight 4K-word Parameter Blocks

• One-hundred and twenty-seven 32K-word Main

Blocks

• Bottom Parameter Location

Enhanced Data Protection Features

• Individual Block Lock and Block Lock-Down with

Zero-Latency

• All blocks are locked at power-up or device reset.

• Absolute Protection with VPP≤VPPLK

• Block Erase, Full Chip Erase, (Page Buffer) Word

Program Lockout during Power Transitions

Automated Erase/Program Algorithms

• 3.0V Low-Power 11µs/Word (Typ.)

Programming

• 12V No Glue Logic 9µs/Word (Typ.)

Production Programming and 0.5s Erase (Typ.)

Cross-Compatible Command Support

• Basic Command Set

• Common Flash Interface (CFI)

Extended Cycling Capability

• Minimum 100,000 Block Erase Cycles

48-Lead TSOP

ETOXTM* Flash Technology

Not designed or rated as radiation hardened

The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low

power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can

operate at VCC=2.7V-3.6V and VPP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends

battery life for portable applications.

The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus

eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual

work operation.

The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main

Blocks that provide maximum flexibility for safe nonvolatile code and data storage.

Fast program capability is provided through the use of high speed Page Buffer Program.

Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.

* ETOX is a trademark of Intel Corporation.

Rev. 2.41

sharp

LHF64F11 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

48-LEAD TSOP

STANDARD PINOUT

12mm x 20mm

TOP VIEW

A

15

A

14

A

13

A

12

A

11

A

10

A

9

A

8

A

21

A

20

WE#

RST#

V

PP

WP#

A

19

A

18

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

16

V

CCQ

GND

DQ

15

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

DQ

11

DQ

3

DQ

10

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

OE#

GND

CE#

A

0

Figure 1. 48-Lead TSOP (Normal Bend) Pinout

Rev. 2.41

sharp

LHF64F11 4

Table 1. Pin Descriptions

Symbol Type Name and Function

A0-A21 INPUT ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21

DQ0-DQ15 INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code and partition configuration register code reads. Data pins float to high-

impedance (High Z) when the chip or outputs are deselected. Data is internally latched

during an erase or program cycle.

CE# INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to

standby levels.

RST# INPUT

RESET: When low (VIL), RST# resets internal automation and inhibits write operations

which provides data protection. RST#-high (VIH) enables normal operation. After

power-up or reset mode, the device is automatically set to read array mode. RST# must

be low during power-up/down.

OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of CE# or WE# (whichever goes high first).

WP# INPUT

WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase

or program operation can be executed to the blocks which are not locked and locked-

down. When WP# is VIH, lock-down is disabled.

VPP INPUT

MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.

With VPP≤VPPLK, block erase, full chip erase, (page buffer) program or OTP program

cannot be executed and should not be attempted.

Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this

mode, VPP is power supply pin. Applying 12V±0.3V to VPP during erase/program can

only be done for a maximum of 1,000 cycles on each block. VPP may be connected to

12V±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits

may reduce block cycling capability or cause permanent damage.

VCC SUPPLY

DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the

flash memory are inhibited. Device operations at invalid VCC voltage (see DC

Characteristics) produce spurious results and should not be attempted.

VCCQ SUPPLY INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output

pins.

GND SUPPLY GROUND: Do not float any ground pins.

Rev. 2.41

sharp

LHF64F11 5

NOTES:

1. "X" denotes the operation available.

2. Configurative Partition Dual Work Restrictions:

Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each

partition. Only one partition can be erased or programmed at a time - no command queuing.

Commands must be written to an address within the block targeted by that command.

Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2)

IF ONE

PARTITION IS:

THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:

Read

Array

Read

ID/OTP

Read

Status

Read

Query

Word

Program

Page

Buffer

Program

OTP

Program

Block

Erase

Full Chip

Erase

Program

Suspend

Block

Erase

Suspend

Read Array X X X X X X X X X

Read ID/OTP X X X X X X X X X

Read StatusXXXXXXXXXXX

Read Query X X X X X X X X X

Word Program X X X X X

Page Buffer

Program XXXX X

OTP Program X

Block EraseXXXX

Full Chip Erase X

Program

Suspend XXXX X

Block Erase

Suspend XXXX X X X

Rev. 2.41

sharp

LHF64F11 6

6

5

4

3

2

1

0

74K-WORD 007000H - 007FFFH

4K-WORD 006000H - 006FFFH

4K-WORD 005000H - 005FFFH

4K-WORD 004000H - 004FFFH

4K-WORD

003000H - 003FFFH

4K-WORD

002000H - 002FFFH

4K-WORD

001000H - 001FFFH

4K-WORD

000000H - 000FFFH

PLANE2 (UNIFORM PLANE)

92

93

94

95

64

65

72

73

74

75

32K-WORD

278000H - 27FFFFH

32K-WORD

270000H - 277FFFH

32K-WORD

268000H - 26FFFFH

32K-WORD

260000H - 267FFFH

32K-WORD

258000H - 25FFFFH

32K-WORD

250000H - 257FFFH

32K-WORD

248000H - 24FFFFH

32K-WORD

240000H - 247FFFH

32K-WORD

238000H - 23FFFFH

32K-WORD

230000H - 237FFFH

32K-WORD

228000H - 22FFFFH

32K-WORD

220000H - 227FFFH

32K-WORD

218000H - 21FFFFH

32K-WORD 210000H - 217FFFH

32K-WORD 208000H - 20FFFFH

32K-WORD 200000H - 207FFFH

2F8000H - 2FFFFFH

2F0000H - 2F7FFFH

2E8000H - 2EFFFFH

2E0000H - 2E7FFFH

2D8000H - 2DFFFFH

2D0000H - 2D7FFFH

2C8000H - 2CFFFFH

2C0000H - 2C7FFFH

2B8000H - 2BFFFFH

2B0000H - 2B7FFFH

2A8000H - 2AFFFFH

2A0000H - 2A7FFFH

298000H - 29FFFFH

290000H - 297FFFH

288000H - 28FFFFH

280000H - 287FFFH

32K-WORD

76

78

79

80

81

82

83

77

84

85

66

68

69

70

71

67

86

88

89

90

91

87

PLANE1 (UNIFORM PLANE)

BLOCK NUMBER ADDRESS RANGE

62

63

32

33

34

35

42

43

44

45

32K-WORD

178000H - 17FFFFH

32K-WORD

170000H - 177FFFH

32K-WORD

168000H - 16FFFFH

32K-WORD

160000H - 167FFFH

32K-WORD

158000H - 15FFFFH

32K-WORD

150000H - 157FFFH

32K-WORD

148000H - 14FFFFH

32K-WORD

140000H - 147FFFH

32K-WORD

138000H - 13FFFFH

32K-WORD

130000H - 137FFFH

32K-WORD

128000H - 12FFFFH

32K-WORD

120000H - 127FFFH

32K-WORD

118000H - 11FFFFH

32K-WORD 110000H - 117FFFH

32K-WORD 108000H - 10FFFFH

32K-WORD 100000H - 107FFFH

1F8000H - 1FFFFFH

1F0000H - 1F7FFFH

1E8000H - 1EFFFFH

1E0000H - 1E7FFFH

1D8000H - 1DFFFFH

1D0000H - 1D7FFFH

1C8000H - 1CFFFFH

1C0000H - 1C7FFFH

1B8000H - 1BFFFFH

1B0000H - 1B7FFFH

1A8000H - 1AFFFFH

1A0000H - 1A7FFFH

198000H - 19FFFFH

190000H - 197FFFH

188000H - 18FFFFH

180000H - 187FFFH

32K-WORD

46

48

49

50

51

52

53

47

54

55

36

38

39

40

41

37

56

58

59

60

61

57

12

13

14

15

32K-WORD

078000H - 07FFFFH

32K-WORD

070000H - 077FFFH

32K-WORD

068000H - 06FFFFH

32K-WORD

060000H - 067FFFH

32K-WORD

058000H - 05FFFFH

32K-WORD

050000H - 057FFFH

32K-WORD

PLANE0 (PARAMETER PLANE)

048000H - 04FFFFH

32K-WORD

040000H - 047FFFH

32K-WORD

038000H - 03FFFFH

32K-WORD

030000H - 037FFFH

32K-WORD

028000H - 02FFFFH

32K-WORD

020000H - 027FFFH

32K-WORD

018000H - 01FFFFH

32K-WORD 010000H - 017FFFH

32K-WORD 008000H - 00FFFFH

0F8000H - 0FFFFFH

0F0000H - 0F7FFFH

0E8000H - 0EFFFFH

0E0000H - 0E7FFFH

0D8000H - 0DFFFFH

0D0000H - 0D7FFFH

0C8000H - 0CFFFFH

0C0000H - 0C7FFFH

0B8000H - 0BFFFFH

0B0000H - 0B7FFFH

0A8000H - 0AFFFFH

0A0000H - 0A7FFFH

098000H - 09FFFFH

090000H - 097FFFH

088000H - 08FFFFH

080000H - 087FFFH

32K-WORD

16

18

19

20

21

22

23

17

24

25

8

9

10

11

26

28

29

30

31

27

127

128

129

130

131

132

133

32K-WORD

PLANE3 (UNIFORM PLANE)

3F8000H - 3FFFFFH

122

123

124

102

103

104

105

32K-WORD

378000H - 37FFFFH

32K-WORD

370000H - 377FFFH

32K-WORD

368000H - 36FFFFH

32K-WORD

360000H - 367FFFH

32K-WORD

358000H - 35FFFFH

32K-WORD

350000H - 357FFFH

32K-WORD

348000H - 34FFFFH

32K-WORD

340000H - 347FFFH

32K-WORD

338000H - 33FFFFH

32K-WORD

330000H - 337FFFH

32K-WORD

328000H - 32FFFFH

32K-WORD

320000H - 327FFFH

32K-WORD

318000H - 31FFFFH

32K-WORD 310000H - 317FFFH

32K-WORD 308000H - 30FFFFH

32K-WORD 300000H - 307FFFH

3F0000H - 3F7FFFH

3E8000H - 3EFFFFH

3E0000H - 3E7FFFH

3D8000H - 3DFFFFH

3D0000H - 3D7FFFH

3C8000H - 3CFFFFH

3C0000H - 3C7FFFH

3B8000H - 3BFFFFH

3B0000H - 3B7FFFH

3A8000H - 3AFFFFH

3A0000H - 3A7FFFH

398000H - 39FFFFH

390000H - 397FFFH

388000H - 38FFFFH

380000H - 387FFFH

32K-WORD

106

108

109

110

111

112

113

107

114

115

96

98

99

100

101

97

116

118

119

120

121

117

125

126

134

BLOCK NUMBER ADDRESS RANGE

Rev. 2.41

Figure 2. Memory Map (Bottom Parameter)

sharp

LHF64F11 7

NOTES:

1. The address A21-A16 are shown in below table for reading the manufacturer, device, lock configuration,

device configuration code and OTP data.

2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).

3. DQ15-DQ2 are reserved for future implementation.

4. PCRC=Partition Configuration Register Code.

5. OTP-LK=OTP Block Lock configuration.

6. OTP=OTP Block data.

NOTES:

1. The address to read the identifier codes or OTP data is dependent on the partition which is selected

when writing the Read Identifier Codes/OTP command (90H).

2. Refer to Table 12 for the partition configuration register.

Table 3. Identifier Codes and OTP Address for Read Operation

Code Address

[A15-A0](1)

Data

[DQ15-DQ0]Notes

Manufacturer Code Manufacturer Code 0000H 00B0H

Device Code Bottom Parameter Device Code 0001H 00B1H 2

Block Lock Configuration

Code

Block is Unlocked

Block

Address

+ 2

DQ0 = 0 3

Block is Locked DQ0 = 1 3

Block is not Locked-Down DQ1 = 0 3

Block is Locked-Down DQ1 = 1 3

Device Configuration Code Partition Configuration Register 0006H PCRC 4

OTP OTP Lock 0080H OTP-LK 5

OTP 0081-0088H OTP 6

Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) (64M-bit device)

Partition Configuration Register (2) Address (64M-bit device)

PCR.10 PCR.9 PCR.8 [A21-A16]

0 0 0 00H

0 0 1 00H or 10H

0 1 0 00H or 20H

1 0 0 00H or 30H

0 1 1 00H or 10H or 20H

1 1 0 00H or 20H or 30H

1 0 1 00H or 10H or 30H

1 1 1 00H or 10H or 20H or 30H

Rev. 2.41

sharp

LHF64F11 8

Rev. 2.41

Customer Programmable Area Lock Bit (DQ

1

)

Factory Programmed Area Lock Bit (DQ

0

)

Customer Programmable Area

Factory Programmed Area

Reserved for Future Implementation

000080H

000081H

000084H

000085H

000088H

[A

21

-A

0

]

(DQ

15

-DQ

2)

Figure 3. OTP Block Address Map for OTP Program

(The area outside 80H~88H cannot be used.)

sharp

LHF64F11 9

Rev. 2.41

NOTES:

1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but cannot be altered.

2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP

. See DC Characteristics for VPPLK

and VPPH1/2 voltages.

3. RST# at GND±0.2V ensures the lowest power consumption.

4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when

VPP=VPPH1/2 and VCC=2.7V-3.6V.

Command writes involving full chip erase are reliably executed when VPP=VPPH1 and VCC=2.7V-3.6V.

5. Refer to Table 6 for valid DIN during a write operation.

6. Never hold OE# low and WE# low at the same timing.

7. Refer to Appendix of LH28F640BF series for more information about query code.

Table 5. Bus Operation(1, 2)

Mode Notes RST# CE# OE# WE# Address VPP DQ0-15

Read Array 6 VIH VIL VIL VIH XXD

OUT

Output Disable VIH VIL VIH VIH X X High Z

Standby VIH VIH X X X X High Z

Reset 3 VIL X X X X X High Z

Read Identifier

Codes/OTP 6VIH VIL VIL VIH

See

Table 3 and

Table 4

X

See

Table 3 and

Table 4

Read Query 6,7 VIH VIL VIL VIH See

Appendix XSee

Appendix

Write 4,5,6 VIH VIL VIH VIL XXD

IN

sharp

LHF64F11 10

NOTES:

1. Bus operations are defined in Table 5.

2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus

cycle.

X=Any valid address within the device.

PA=Address within the selected partition.

IA=Identifier codes address (See Table 3 and Table 4).

QA=Query codes address. Refer to Appendix of LH28F640BF series for details.

BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.

WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.

OA=Address of OTP block to be read or programmed (See Figure 3).

PCRC=Partition configuration register code presented on the address A0-A15.

3. ID=Data read from identifier codes. (See Table 3 and Table 4).

QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.

SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.

WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes

high first).

OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes

high first).

N-1=N is the number of the words to be loaded into a page buffer.

4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock

configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).

The Read Query command is available for reading CFI (Common Flash Interface) information.

5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked

block can be erased or programmed when RST# is VIH.

6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.

7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any

valid address within the target partition to be programmed and the confirm command (D0H). Refer to Appendix of

Table 6. Command Definitions(11)

Command

Bus

Cycles

Req’d

Notes

First Bus Cycle Second Bus Cycle

Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)

Read Array 1 2 Write PA FFH

Read Identifier Codes/OTP ≥ 2 2,3,4 Write PA 90H Read IA or OA ID or OD

Read Query ≥ 2 2,3,4 Write PA 98H Read QA QD

Read Status Register 2 2,3 Write PA 70H Read PA SRD

Clear Status Register 1 2 Write PA 50H

Block Erase 2 2,3,5 Write BA 20H Write BA D0H

Full Chip Erase 2 2,5,9 Write X 30H Write X D0H

Program 2 2,3,5,6 Write WA 40H or

10H Write WA WD

Page Buffer Program ≥ 4 2,3,5,7 Write WA E8H Write WA N-1

Block Erase and (Page Buffer)

Program Suspend 1 2,8,9 Write PA B0H

Block Erase and (Page Buffer)

Program Resume 1 2,8,9 Write PA D0H

Set Block Lock Bit 2 2 Write BA 60H Write BA 01H

Clear Block Lock Bit 2 2,10 Write BA 60H Write BA D0H

Set Block Lock-down Bit 2 2 Write BA 60H Write BA 2FH

OTP Program 2 2,3,9 Write OA C0H Write OA OD

Set Partition Configuration Register

2 2,3 Write PCRC 60H Write PCRC 04H

Rev. 2.41

sharp

LHF64F11 11

LH28F640BF series for details.

8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the

suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.

9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while

the block erase operation is being suspended.

10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is VIL. When

WP# is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.

11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

Rev. 2.41

sharp

LHF64F11 12

NOTES:

1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.

DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.

2. Erase and program are general terms, respectively, to express: block erase, full chip erase and

(page buffer) program operations.

3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,

[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.

4. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are

automatically locked.

5. OTP (One Time Program) block has the lock function which is different from those described

above.

NOTES:

1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit

command and "Set Lock-down" means Set Block Lock-Down Bit command.

2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the

corresponding block is locked-down and automatically locked at the same time.

3. "No Change" means that the state remains unchanged after the command written.

4. In this state transitions table, assumes that WP# is not changed and fixed VIL or VIH.

Table 7. Functions of Block Lock(5) and Block Lock-Down

Current State

Erase/Program Allowed (2)

State WP# DQ1(1) DQ0(1) State Name

[000] 0 0 0 Unlocked Yes

[001](3) 00 1Locked No

[011] 0 1 1 Locked-down No

[100] 1 0 0 Unlocked Yes

[101](3) 10 1Locked No

[110](4) 1 1 0 Lock-down Disable Yes

[111] 1 1 1 Lock-down Disable No

Table 8. Block Locking State Transitions upon Command Write(4)

Current State Result after Lock Command Written (Next State)

State WP# DQ1DQ0Set Lock(1) Clear Lock(1) Set Lock-down(1)

[000] 0 0 0 [001] No Change [011](2)

[001] 0 0 1 No Change(3) [000] [011]

[011] 0 1 1 No Change No Change No Change

[100] 1 0 0 [101] No Change [111](2)

[101] 1 0 1 No Change [100] [111]

[110] 1 1 0 [111] No Change [111](2)

[111] 1 1 1 No Change [110] No Change

Rev. 2.41

sharp

LHF64F11 13

Rev. 2.41

NOTES:

1. "WP#=0→1" means that WP# is driven to VIH and "WP#=1→0" means that WP# is driven to

VIL.

2. State transition from the current state [011] to the next state depends on the previous state.

3. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are

automatically locked.

4. In this state transitions table, assumes that lock configuration commands are not written in

previous, current and next state.

Table 9. Block Locking State Transitions upon WP# Transition(4)

Previous State

Current State Result after WP# Transition (Next State)

State WP# DQ1DQ0WP#=0→1(1) WP#=1→0(1)

- [000] 0 0 0 [100] -

- [001] 0 0 1 [101] -

[110](2)

[011] 0 1 1

[110] -

Other than [110](2) [111] -

- [100] 1 0 0 - [000]

- [101] 1 0 1 - [001]

-[110]110- [011](3)

- [111] 1 1 1 - [011]

sharp

LHF64F11 14

Table 10. Status Register Definition

RRRRRRRR

15 14 13 12 11 10 9 8

WSMS BESS BEFCES PBPOPS VPPS PBPSS DPS R

76543210

SR.15 - SR.8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = BLOCK ERASE AND FULL CHIP ERASE

STATUS (BEFCES)

1 = Error in Block Erase or Full Chip Erase

0 = Successful Block Erase or Full Chip Erase

SR.4 = (PAGE BUFFER) PROGRAM AND

OTP PROGRAM STATUS (PBPOPS)

1 = Error in (Page Buffer) Program or OTP Program

0 = Successful (Page Buffer) Program or OTP Program

SR.3 = VPP STATUS (VPPS)

1 = VPP LOW Detect, Operation Abort

0 = VPP OK

SR.2 = (PAGE BUFFER) PROGRAM SUSPEND

STATUS (PBPSS)

1 = (Page Buffer) Program Suspended

0 = (Page Buffer) Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a

Locked Block, Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Status Register indicates the status of the partition, not WSM

(Write State Machine). Even if the SR.7 is "1", the WSM may

be occupied by the other partition when the device is set to 2,

3 or 4 partitions configuration.

Check SR.7 to determine block erase, full chip erase, (page

buffer) program or OTP program completion. SR.6 - SR.1 are

invalid while SR.7="0".

If both SR.5 and SR.4 are "1"s after a block erase, full chip

erase, page buffer program, set/clear block lock bit, set block

lock-down bit, set partition configuration register attempt, an

improper command sequence was entered.

SR.3 does not provide a continuous indication of VPP level.

The WSM interrogates and indicates the VPP level only after

Block Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. SR.3 is not guaranteed to

report accurate feedback when VPP≠VPPH1, VPPH2 or VPPLK.

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates the block lock bit only after Block

Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. It informs the system,

depending on the attempted operation, if the block lock bit is

set. Reading the block lock configuration codes after writing

the Read Identifier Codes/OTP command indicates block

lock bit status.

SR.15 - SR.8 and SR.0 are reserved for future use and should

be masked out when polling the status register.

Rev. 2.41

sharp

LHF64F11 15

Rev. 2.41

Table 11. Extended Status Register Definition

RRRRRRRR

15 14 13 12 11 10 9 8

SMSRRRRRRR

76543210

XSR.15-8 =

RESERVED FOR FUTURE

ENHANCEMENTS (R)

XSR.7 = STATE MACHINE STATUS (SMS)

1 = Page Buffer Program available

0 = Page Buffer Program not available

XSR.6-0 =

RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

After issue a Page Buffer Program command (E8H),

XSR.7="1" indicates that the entered command is accepted.

If XSR.7 is "0", the command is not accepted and a next Page

Buffer Program command (E8H) should be issued again to

check if page buffer is available or not.

XSR.15-8 and XSR.6-0 are reserved for future use and

should be masked out when polling the extended status

register.

sharp

LHF64F11 16

Rev. 2.41

Table 12. Partition Configuration Register Definition

RRRRRPC2PC1PC0

15 14 13 12 11 10 9 8

RRRRRRRR

76543210

PCR.15-11 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

PCR.10-8 = PARTITION CONFIGURATION (PC2-0)

000 = No partitioning. Dual Work is not allowed.

001 = Plane1-3 are merged into one partition.

(default in a bottom parameter device)

010 = Plane 0-1 and Plane2-3 are merged into one

partition respectively.

100 = Plane 0-2 are merged into one partition.

(default in a top parameter device)

011 = Plane 2-3 are merged into one partition. There are

three partitions in this configuration. Dual work

operation is available between any two partitions.

110 = Plane 0-1 are merged into one partition. There are

three partitions in this configuration. Dual work

operation is available between any two partitions.

101 = Plane 1-2 are merged into one partition. There are

three partitions in this configuration. Dual work

operation is available between any two partitions.

111 = There are four partitions in this configuration.

Each plane corresponds to each partition respec-

tively. Dual work operation is available between any

two partitions.

PCR.7-0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

NOTES:

After power-up or device reset, PCR10-8 (PC2-0) is set to

"001" in a bottom parameter device and "100" in a top

parameter device.

See Figure 4 for the detail on partition configuration.

PCR.15-11 and PCR.7-0 are reserved for future use and

should be masked out when polling the partition

configuration register.

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION1

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PARTITION1

PARTITION0

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION1

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PLANE1

PLANE0

PLANE2

PLANE3

PARTITION0

PARTITION1

PARTITION0

PARTITION2PARTITION3

PARTITION2

PARTITION1

PARTITION2

000

001

010

100

011

110

101

111

PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITIONING FOR DUAL WORK

PC2 PC1PC0

Figure 4. Partition Configuration

sharp

LHF64F11 17

1 Electrical Specifications

1.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Erase and Program ......0°C to +70°C(1)

Storage Temperature

During under Bias............................... -10°C to +80°C

During non Bias................................ -65°C to +125°C

Voltage On Any Pin

(except VCC and VPP).............. -0.5V to VCC+0.5V (2)

VCC and VCCQ Supply Voltage .......... -0.2V to +3.9V (2)

VPP Supply Voltage ...................... -0.2V to 12.6V (2, 3, 4)

Output Short Circuit Current...........................100mA (5)

*WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent

damage. These are stress ratings only. Operation

beyond the "Operating Conditions" is not

recommended and extended exposure beyond

the "Operating Conditions" may affect device

reliability.

NOTES:

1. Operating temperature is for commercial temperature

product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins

and -0.2V on VCC and VPP pins. During transitions,

this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input/output pins and VCC is

VCC+0.5V which, during transitions, may overshoot to

VCC +2.0V for periods <20ns.

3. Maximum DC voltage on VPP may overshoot to

+13.0V for periods <20ns.

4. VPP erase/program voltage is normally 2.7V-3.6V.

Applying 11.7V-12.3V to Vpp during erase/program

can be done for a maximum of 1,000 cycles on the

main blocks and 1,000 cycles on the parameter blocks.

VPP may be connected to 11.7V-12.3V for a total of 80

hours maximum.

5. Output shorted for no more than one second. No more

than one output shorted at a time.

Rev. 2.41

1.2 Operating Conditions

NOTES:

1. See DC Characteristics tables for voltage range-specific specification.

2. Applying VPP=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks

and 1,000 cycles on the parameter blocks. A permanent connection to VPP=11.7V-12.3V is not allowed and can cause

damage to the device.

Parameter Symbol Min. Typ. Max. Unit Notes

Operating Temperature TA0+25+70°C

VCC Supply Voltage VCC 2.7 3.0 3.6 V 1

I/O Supply Voltage VCCQ 2.7 3.0 3.6 V 1

VPP Voltage when Used as a Logic Control VPPH1 1.65 3.0 3.6 V 1

VPP Supply Voltage VPPH2 11.7 12 12.3 V 1, 2

Main Block Erase Cycling: VPP=3.0V 100,000 Cycles

Parameter Block Erase Cycling: VPP=3.0V 100,000 Cycles

Main Block Erase Cycling: VPP=12V, 80 hrs. 1,000 Cycles

Parameter Block Erase Cycling: VPP=12V, 80 hrs. 1,000 Cycles

Maximum VPP hours at 12V 80 Hours

sharp

LHF64F11 18

TEST POINTSVCCQ/2 VCCQ/2INPUT

VCCQ

0.0

OUTPUT

AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".

Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.

Worst case speed conditions are when VCC=VCC(min).

DEVICE

UNDER

TEST

RL=3.3k

CL

VCCQ(min)/2

OUT

CL Includes Jig

Capacitances.

1N914

Figure 6. Transient Equivalent Testing Load Circuit

Rev. 2.41

Table 13. Configuration Capacitance Loading Value

Test Configuration CL (pF)

VCC=2.7V-3.6V 50

1.2.2 AC Input/Output Test Conditions

1.2.1 Capacitance(1) (TA=+25°C, f=1MHz)

NOTE:

1. Sampled, not 100% tested.

Parameter Symbol Condition Min. Typ. Max. Unit

Input Capacitance CIN VIN=0.0V 68pF

Output Capacitance COUT VOUT=0.0V 10 12 pF

Figure 5. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V

sharp

LHF64F11 19

Rev. 2.41

1.2.3 DC Characteristics

VCC=2.7V-3.6V

Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions

ILI Input Load Current 1 -1.0 +1.0 µAVCC=VCCMax.,

VCCQ=VCCQMax.,

VIN/VOUT=VCCQ or

GND

ILO Output Leakage Current 1 -1.0 +1.0 µA

ICCS VCC Standby Current 1420µA

VCC=VCCMax.,

CE#=RST#=

VCCQ±0.2V,

WP#=VCCQ or GND

ICCAS VCC Automatic Power Savings Current 1,4 4 20 µA

VCC=VCCMax.,

CE#=

GND±0.2V,

WP#=VCCQ or GND

ICCD VCC Reset Power-Down Current 1420µA RST#=GND±0.2V

ICCR

Average VCC Read

Current

Normal Mode

1,7 15 25 mA VCC=VCCMax.,

CE#=VIL,

OE#=VIH,

f=5MHz

Average VCC Read

Current

Page Mode

8 Word Read 1,7 5 10 mA

ICCW VCC (Page Buffer) Program Current 1,5,7 20 60 mA VPP=VPPH1

1,5,7 10 20 mA VPP=VPPH2

ICCE

VCC Block Erase, Full Chip

Erase Current

1,5,7 10 30 mA VPP=VPPH1

1,5,7 10 30 mA VPP=VPPH2

ICCWS

ICCES

VCC (Page Buffer) Program or

Block Erase Suspend Current 1,2,7 10 200 µACE#=VIH

IPPS

IPPR

VPP Standby or Read Current 1,6,7 2 5 µAVPP≤VCC

IPPW VPP (Page Buffer) Program Current 1,5,6,7 2 5 µAVPP=VPPH1

1,5,6,7 10 30 mA VPP=VPPH2

IPPE

VPP Block Erase, Full Chip

Erase Current

1,5,6,7 2 5 µAVPP=VPPH1

1,5,6,7 5 15 mA VPP=VPPH2

IPPWS

VPP (Page Buffer) Program

Suspend Current

1,6,7 2 5 µAVPP=VPPH1

1,6,7 10 200 µAVPP=VPPH2

sharp

LHF64F11 20

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25°C

unless VCC is specified.

2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend

mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.

3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VPP≤VPPLK, and not guaranteed

in the range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above VPPH2(max.).

4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle

completion. Standard address access timings (tAVQV) provide new data when addresses are changed.

5. Sampled, not 100% tested.

6. VPP is not used for power supply pin. With VPP≤VPPLK, block erase, full chip erase, (page buffer) program and OTP

program cannot be executed and should not be attempted.

Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and

supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths

and layout considerations given to the VCC power bus.

Applying 12V±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP

may be connected to 12V±0.3V for a total of 80 hours maximum.

7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.

IPPES VPP Block Erase Suspend Current 1,6,7 2 5 µAVPP=VPPH1

1,6,7 10 200 µAVPP=VPPH2

VIL Input Low Voltage 5 -0.4 0.4 V

VIH Input High Voltage 5 VCCQ

-0.4

VCCQ

+ 0.4 V

VOL Output Low Voltage 5 0.2 V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOL=100µA

VOH Output High Voltage 5 VCCQ

-0.2 V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOH=-100µA

VPPLK

VPP Lockout during Normal

Operations 3,5,6 0.4 V

VPPH1

VPP during Block Erase, Full Chip

Erase, (Page Buffer) Program or OTP

Program Operations

6 1.65 3.0 3.6 V

VPPH2

VPP during Block Erase, (Page Buffer)

Program or OTP Program Operations 6 11.7 12 12.3 V

VLKO VCC Lockout Voltage 1.5 V

VCC=2.7V-3.6V

Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions

Rev. 2.41

DC Characteristics (Continued)

sharp

LHF64F11 21

1.2.4 AC Characteristics - Read-Only Operations(1)

NOTES:

1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. OE# may be delayed up to tELQV  tGLQV after the falling edge of CE# without impact to tELQV

.

VCC=2.7V-3.6V, TA=0°C to +70°C

Symbol Parameter

Notes

Min. Max. Unit

tAVAV Read Cycle Time 90 ns

tAVQV Address to Output Delay 90 ns

tELQV CE# to Output Delay 3 90 ns

tAPA Page Address Access Time 35 ns

tGLQV OE# to Output Delay 3 20 ns

tPHQV RST# High to Output Delay 150 ns

tEHQZ, tGHQZ CE# or OE# to Output in High Z, Whichever Occurs First 2 20 ns

tELQX CE# to Output in Low Z 2 0 ns

tGLQX OE# to Output in Low Z 2 0 ns

tOH Output Hold from First Occurring Address, CE# or OE# change 2 0 ns

Rev. 2.41

sharp

LHF64F11 22

tAVQV

tEHQZ

tGHQZ

tELQV

tPHQV

tGLQV

tOH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

(P)

(D/Q)

(W)

(G)

(E)

(A)A20-0

DQ15-0

CE#

OE#

WE#

RST#

High Z

tELQX

VALID

OUTPUT

VALID

ADDRESS

tGLQX

A21-0 (A)

Figure 7. AC Waveform for Single Asynchronous Read Operations

from Status Register, Identifier Codes, OTP Block or Query Code

Rev. 2.41

sharp

LHF64F11 23

tAVQV

tELQV tEHQZ

tGHQZ

tOH

tAPA

tGLQV

tPHQV

High Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

(P)

(W)

(G)

(E)

(A)A20-3

VIH

VIL

(A)A2-0

VOH

VOL

(D/Q)

DQ15-0

CE#

OE#

WE#

RST#

tGLQX

tELQX

VALID

ADDRESS

VALID

ADDRESS VALID

ADDRESS

VALID

OUTPUT VALID

OUTPUT

VALID

ADDRESS

A21-3 (A)

Figure 8. AC Waveform for Asynchronous Page Mode Read Operations

from Main Blocks or Parameter Blocks

Rev. 2.41

sharp

LHF64F11 24

Rev. 2.41

1.2.5 AC Characteristics - Write Operations(1), (2)

NOTES:

1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and

OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only

operations.

2. A write operation can be initiated and terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of

CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.

5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling

edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.

6. VPP should be held at VPP=VPPH1/2 until determination of block erase, (page buffer) program or OTP program success

(SR.1/3/4/5=0) and held at VPP=VPPH1 until determination of full chip erase success (SR.1/3/5=0).

7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.

8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit

configuration.

VCC=2.7V-3.6V, TA=0°C to +70°C

Symbol Parameter Notes Min. Max. Unit

tAVAV Write Cycle Time 90 ns

tPHWL (tPHEL)

RST# High Recovery to WE# (

CE#

) Going Low

3150 ns

tELWL (tWLEL)CE# (WE#) Setup to WE# (CE#) Going Low 4 0 ns

tWLWH (tELEH)WE# (CE#) Pulse Width 4 60 ns

tDVWH (tDVEH)Data Setup to WE# (CE#) Going High 8 40 ns

tAV W H (tAV E H )Address Setup to WE# (CE#) Going High 8 50 ns

tWHEH (tEHWH)CE# (WE#) Hold from WE# (CE#) High 0 ns

tWHDX (tEHDX)Data Hold from WE# (CE#) High 0 ns

tWHAX (tEHAX)Address Hold from WE# (CE#) High 0 ns

tWHWL (tEHEL)WE# (CE#) Pulse Width High 5 30 ns

tSHWH (tSHEH)WP# High Setup to WE# (CE#) Going High 3 0 ns

tVVWH (tVVEH)V

PP Setup to WE# (CE#) Going High 3200 ns

tWHGL (tEHGL)Write Recovery before Read 30 ns

tQVSL WP# High Hold from Valid SRD 3, 6 0 ns

tQVVL VPP Hold from Valid SRD 3, 6 0 ns

tWHR0 (tEHR0)WE# (CE#) High to SR.7 Going "0" 3, 7 tAV Q V +

50 ns

sharp

LHF64F11 25

tAVAV tAVWH (tAVEH)

tWHAX

(tEHAX)

tELWL (tWLEL)

tPHWL (tPHEL)

tWLWH

tWHWL (tEHEL)

tWHDX (tEHDX)tDVWH (tDVEH)

tSHWH (tSHEH)

tVVWH (tVVEH)

tWHQV1,2,3 (tEHQV1,2,3)

tQVSL

tQVVL

tWHEH (tEHWH)t

WHGL (tEHGL)

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

(D/Q)

(W)

(G)

(E)

(A)

NOTES 5, 6

A20-0

DQ15-0

(V)

VPP

VIH

VPPH1,2

VPPLK

VIL

(P)

RST#

CE#

OE#

WE#

VIH

VIL

(S)WP#

(tELEH )

NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5

VALID

ADDRESS VALID

ADDRESS

DATA IN DATA IN VALID

SRD

NOTES:

1. VCC power-up and standby.

2. Write each first cycle command.

3. Write each second cycle command or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.

"1"

"0"

(R)SR.7

tWHR0 (tEHR0)

NOTES 5, 6

A21-0 (A)

Figure 9. AC Waveform for Write Operations

Rev. 2.41

sharp

LHF64F11 26

ABORT

COMPLETE

tPLPH

t2VPH

tPLRH tPHQV

tPHQV

(A) Reset during Read Array Mode

(B) Reset during Erase or Program Mode

(C) RST# rising timing

RST#

VIL

VIH

VIL

VIH

VCC GND

VCC(min)

RST# VIL

VIH

SR.7="1"

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

(P)

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

tPHQV

tVHQV

NOTES:

1. A reset time, tPHQV

, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC

Characteristics - Read-Only Operations for tPHQV

.

2. tPLPH is <100ns the device may still reset but this is not guaranteed.

3. Sampled, not 100% tested.

4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,

the reset will complete within 100ns.

5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and

also has been in stable there.

Reset AC Specifications (VCC=2.7V-3.6V, TA=0°C to +70°C)

Symbol Parameter Notes Min. Max. Unit

tPLPH RST# Low to Reset during Read

(RST# should be low during power-up.) 1, 2, 3 100 ns

tPLRH RST# Low to Reset during Erase or Program 1, 3, 4 22 µs

t2VPH VCC 2.7V to RST# High 1, 3, 5 100 ns

tVHQV VCC 2.7V to Output Delay 31ms

Figure 10. AC Waveform for Reset Operations

Rev. 2.41

1.2.6 Reset Operations

sharp

LHF64F11 27

Rev. 2.41

1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)

NOTES:

1. Typical values measured at VCC=3.0V, VPP=3.0V or 12V, and TA=+25°C. Assumes corresponding lock bits

are not set. Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter

than tERES and its sequence is repeated, the block erase operation may not be finished.

VCC=2.7V-3.6V, TA=0°C to +70°C

Symbol Parameter Notes

Page Buffer

Command is

Used or not

Used

VPP=VPPH1

(In System)

VPP=VPPH2

(In Manufacturing)

Unit

Min. Typ.(1)

Max.

(2)

Min. Typ.(1)

Max.

(2)

tWPB 4K-Word Parameter Block

Program Time

2 Not Used 0.05 0.3 0.04 0.12 s

2 Used 0.03 0.12 0.02 0.06 s

tWMB

32K-Word Main Block

Program Time

2 Not Used 0.38 2.4 0.31 1.0 s

2 Used 0.24 1.0 0.17 0.5 s

tWHQV1/

tEHQV1

Word Program Time 2 Not Used 11 200 9 185 µs

2 Used 7 100 5 90 µs

tWHOV1/

tEHOV1

OTP Program Time 2 Not Used 36 400 27 185 µs

tWHQV2/

tEHQV2

4K-Word Parameter Block

Erase Time 2 - 0.3 4 0.2 4 s

tWHQV3/

tEHQV3

32K-Word Main Block

Erase Time 2 - 0.6 5 0.5 5 s

Full Chip Erase Time 2 80 700 66 700 s

tWHRH1/

tEHRH1

(Page Buffer) Program Suspend

Latency Time to Read 4- 510 510µs

tWHRH2/

tEHRH2

Block Erase Suspend

Latency Time to Read 4- 520 520µs

tERES

Latency Time from Block Erase

Resume Command to Block

Erase Suspend Command

5-500 500 µs

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LHF64F11 28

Rev. 2.41

2 Related Document Information(1)

NOTE:

1. International customers should contact their local SHARP or distribution sales offices.

Document No. Document Name

FUM00701 LH28F640BF series Appendix

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Rev. 1. 10

i

A-1 RECOMMENDED OPERATING COND ITIONS

A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

Figure A-1. AC Timing at Device Power-Up

For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“

described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in

the next page.

t2VPH

VCC

GND

VCC(min)

RP#

VIL

VIH

(P)

tPHQV

VCCW *1

GND

VCCWH1/2

(V)

CE#

VIL

VIH

(E)

WE#

VIL

VIH

(W)

OE#

VIL

VIH

(G)

WP#

VIL

VIH

(S)

VOH

VOL

(D/Q)

DATA High Z Valid

Output

tVR

tFtELQV

tFtGLQV

(A)ADDRESS Valid

(RST#)

(VPP)

tRor tF

Address

VIL

VIH

tAVQV tRor tF

tR

*1 To prevent the unwanted writes, system designers should consider the design, which applies VCCW (VPP)

to 0V during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.

(VPPH1/2)

See the application note AP-007-SW-E for details.

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Rev. 1. 10

ii

A-1.1.1 Rise a nd Fall Ti me

NOTES:

1. Sampled, not 100% test ed.

2. This specifi cation is applied for not only the device power-up but also the normal operations.

Symbol Parameter Notes Min. Max. Unit

tVR VCC Ris e Time 1 0.5 30000 µs/V

tRInput Signal R ise Time 1, 2 1 µs/V

tFInput Si gnal Fall Time 1, 2 1 µs/V

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Rev. 1. 10

iii

A-1.2 Glitch Noises

Do n ot in put the glitch noises whic h a re bel ow VIH (Min .) or above VIL ( Max.) on address, data, res et , a nd control s ign al s,

as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).

Figure A-2. Waveform for Glitch Noises

See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).

(a) Acceptable Glitch Noises

Input Signal

VIH (Min.)

Input Signal

VIH (Min.)

Input Signal

VIL (Max.)

Input Signal

VIL (Max.)

(b)

NOT

Acceptable Glitch Noises

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Rev. 1. 10

iv

A-2 RELATED DOCUMENT INFORMATION(1)

NOTE:

1. International customers should contact their local SHARP or distribution sales office.

Document No. Document Name

AP-001-SD-E Flash Memory Family Software Drivers

AP-006-PT-E Data Protection Method of SHARP Flash Memory

AP-007-SW-E RP#, VPP Elec tric Pot ential Switc hin g Circu it

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SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited 

Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. 

ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND 

FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,

for any incidental or consequential economic or property damage.

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