Features
nTotal dose capability to 100 kRads(Si)
nFloating channel designed for bootstrap operation
nFully operational to +400V
nTolerant to negative transient voltage
ndV/dt immune
nGate drive supply range from 10 to 20V
nUndervoltage lockout for both channels
nSeparate logic supply range from 5 to 20V
Logic and power ground ±5V offset
nCMOS Schmitt-triggered inputs with pull-down
nCycle by cycle edge-triggered shutdown logic
nMatched propagation delay for both channels
nOutputs in phase with inputs
nHermetically Sealed
nLightweight
nESD Rating: Class 1C per MIL-STD-883, Method 3015
RADIATION HARDENED HIGH AND LOW SIDE GATE DRIVER
Product Summary
VOFFSET 400V max.
IO+/- 2A / 2A
VOUT 10 - 20V
ton/off (typ.) 120 & 100 ns
Delay Matching(typ.) 5 ns
Symbol Parameter Min. Max. Units
VBHigh Side Floating Supply Voltage -0.5 VS + 20
VSHigh Side Floating Supply Offset Voltage 400
VHO High Side Floating Output Voltage VS - 0.5 VB + 0.5
VCC Low Side Fixed Supply Voltage -0.5 20
VLO Low Side Output Voltage -0.5 VCC + 0.5 V
VDD Logic Supply Voltage -0.5 VSS + 20
VSS Logic Supply Offset Voltage VCC - 20 VCC + 0.5
VIN Logic Input Voltage (HIN, LIN & SD) VSS - 0.5 VDD + 0.5
dVs/dt Allowable Offset Supply Voltage Transient (Figure 2) 50 V/ns
PDPackage Power Dissipation @ TLEAD ≤ +25°C 0.8 W
RthJC Thermal Resistance, Junction to Case 12 (Typ) 15.9
RthJ-LEAD Thermal Resistance, Junction to Lead *150 (Typ) °C/W
RthJ-LID Thermal Resistance, Junction to Lid * 27 (Typ)
TJJunction Temperature -55 125
TSStorage Temperature -55 150 °C
TLLead Temperature (Soldering, 10 seconds) 300
Weight 0.6(typical) g
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are
absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board
mounted and still air conditions.
Description
The RIC7113A4 is a high voltage, high speed power
MOSFET and IGBT driver with independent high and low
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. Logic inputs are compatible with
standard CMOS or LSTTL outputs. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use in high frequency applications.
The floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration
which operates up to 400 volts.
RIC7113A4
* Guaranteed by design, not tested
10/27/15
www.irf.com 1
PD-94703D
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RIC7113A4
Tj = 25°C Tj =
-55 to 125°C
Symbol Parameter Min. Typ. Max. Min. Max. Units Test Conditions
ton Turn-On Propagation Delay 120 150 260 VS = 0V
toff Turn-Off Propagation Delay 100 125 220 VS = 400V
tsd Shutdown Propagation Delay 110 140 235 VS = 400V
trTurn-On Rise Time 25 35 50 CL = 1000pf
tfTurn-Off Fall Time 17 25 40 CL = 1000pf
MT Delay Matching, HS & LS Turn-On/Off 5 20 |Hton-Lton| or|Htoff-Ltoff|
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. The VS and VSS offset ratings are tested
with all supplies biased at 15V differential.
Symbol Parameter Min. Max. Units
VBHigh Side Floating Supply Absolute Voltage VS + 10 VS + 20
VSHigh Side Floating Supply Offset Voltage -4 400
VHO High Side Floating Output Voltage VSVB
VCC Low Side Fixed Supply Voltage 10 20 V
VLO Low Side Output Voltage 0 VCC
VDD Logic Supply Voltage VSS + 5 VSS + 20
VSS Logic Supply Offset Voltage -5 5
VIN Logic Input Voltage (HIN, LIN & SD) VSS VDD
ns
Dynamic Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, and VSS = COM unless otherwise specified. The dynamic electrical
characteristics are measured using the test circuit shown in Figure 3.
Typical Connection
Pre-Irradiation
HIN
up to 500V
TO
LOA D
V
DD
V
B
V
S
HO
LO
COM
HIN
LIN
V
SS
SD
V
CC
LIN
V
DD
SD
V
SS
V
CC
400
RIC7113A4
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Tj = 25°C Tj =
-55 to 125°C
Symbol Parameter Min. Max. Min. Max. Units Test Conditions
VIH Logic 1 Input Voltage 3.1 3.3 VDD = 5V
6.4 6.8 VDD = 10V
9.5 10 VVDD = 15V
12.5 13.3 VDD = 20V
VIL Logic 0 Input Voltage 1.6 1.6 VDD = 5V
3.8 3.6 VDD = 10V
6.0 5.7 VVDD = 15V
8.3 7.9 VDD = 20V
VOH High Level Output Voltage, VBIAS - VO 1.2 1.5 VIN =VIH, IO = 0A
VOL Low Level Output Voltage, VO 0.1 0.1 VIN =VIH, IO = 0A
ILK Offset Supply Leakage Current 50 250 VB = VS = 400V
IQBS Quiescent VBS Supply Current 230 500 µA VIN =0V or VDD
IQCC Quiescent VCC Supply Current 340 600 VIN =0V, or VDD
IQDD Quiescent VDD Supply Current 30 60 VIN =0V, or VDD
IIN+ Logic 1 Input Bias Current 40 70 VIN = V
DD
IIN- Logic 0 Input Bias Current 1.0 10 VIN = 0V
VBSUV+ VBS Supply Undervoltage Positive 7.5 9.7
Going Threshold
VBSUV- VBS Supply Undervoltage Negative 7.0 9.4
Going Threshold
VCCUV+ VCC Supply Undervoltage Positive 7.4 9.6 V
Going Threshold
VCCUV- VCC Supply Undervoltage Negative 7.0 9.4
Going Threshold
IO+ Output High Short Circuit Pulsed 2.0 VO = 0V, VIN = VDD
Current *APW < 10 µs
IO- Output Low Short Circuit Pulsed 2.0 VO = 15V, VIN = 0V
Current * PW < 10 µs
Static Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, unless otherwise specified. The VIN, VTH and IIN parameters are refer-
enced to VSS and are applicable to all three logic input pins: HIN, LIN and SD. The VO and IO parameters
are referenced to COM or VS and are applicable to the respective output pins: HO or LO.
Pre-Irradiation
* Guaranteed by design, not tested
4www.irf.com
RIC7113A4 Radiation characteristics
Radiation Performance
International Rectifier Radiation Hardened gate drivers are tested to verify their hardness capability. The
hardness assurance program at International rectifier uses a Cobalt-60 (60 Co) source and heavy ion
irradiation.
Every wafer shall be tested per MIL-STD-883, Method 1019, test condition A “Ionizing Radiation
(Total Dose) Test Procedure”.
Both pre- and post- irradiation performances are tested and specified using the same drive circuitry and test
conditions to provide a direct comparison.
For Static Irradiation Test Conditions refer to figure 7.
Static Electrical Characteristics Tj = 25°C
Symbol Parameter 100K Rads (Si) Units Test Conditions
Min Max
VIH Logic “1” Input Voltage 3.1 — VDD = 5V
6.4 — VDD = 10V
9.5 — VDD = 15V
12.5 — VDD = 20V
VIL Logic “0” Input Voltage — 1.6 VDD = 5V
— 1.6 VDD = 10V
6.0 VDD = 15V
— 8.3 VDD = 20V
VOH High Level Output Voltage, VBIAS - VO — 1.2 VIN =VIH, IO = 0A
VOL Low Level Output Voltage, VO 0.1 VIN =VIH, IO = 0A
ILK Offset Supply Leakage Current 50 VB =VS = 400V
IQBS Quiescent VBS Supply Current 230 VIN =0V or VDD
IQCC Quiescent VCC Supply Current 340 VIN =0V or VDD
IQDD Quiescent VDD Supply Current 30 VIN =0V or VDD
IIN+ Logic 1 Input Bias Current 40 VIN =VDD
IIN- Logic 0 Input Bias Current 1.0 VIN =0V
VBSUV+ VBS Supply Undervoltage Positive 7.5 9.7
Going Threshold
VBSUV- VBS Supply Undervoltage Negative 7.0 9.4
Going Threshold
VCCUV+ VCC Supply Undervoltage Positive 7.4 9.9
Going Threshold
VCCUV- VCC Supply Undervoltage Negative 7.0 9.6
Going Threshold
IO+ Output High Short Circuit Pulsed 2.0 VO =0V, VIN =VDD
Current * PW < 10 µs
IO- Output Low Short Circuit Pulsed 2.0 VO =15V, VIN =0V
Current * PW < 10 µs
µA
V
V
A
V
* Guaranteed by design, not tested
RIC7113A4
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International Rectifier radiation hardened Gate Drivers have been characterized in heavy ion environment
for Single Event Effects (SEE). Single Event Effects characterization data is illustrated below. For Static Bias
Test Conditions refer to figure 8.
Single Event Effect Safe Operating Area
Ion LET Energy Angle VS (V)
MeV/(mg/cm2)) (MeV) (degrees) @VBS= 10V @VBS= 15V @VBS= 17.5V
Br 37 284 0 400 400 400
I 60 344 0 325 250 200
Au 82 346 0 250 200 175
I 85 344 45 400 400 350
Au 100 346 35 400 400 350
Note: VCC/VDD = 20V, except for LET=100, then VCC/VDD = 17.5V
Single Event Effect, Safe Operating Area
Radiation characteristics
STATIC BIAS
0
50
100
150
200
250
300
350
400
450
-10 -15 -17.5
VB (V)
VS (V)
Br, 0° angle
I, 0° angle
Au, 0° angle
I, 45° angle
Au, 35° angle
10 15 17.5
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RIC7113A4
Figure 1. Input/Output Logic
Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition
Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions
HV = 10 to 400V
(0 to 400V)
IRF820A
RIC7113
RIC7113
HIN
LIN
t
r
t
on
t
f
t
off
HO
LO
50%
50%
90%
90%
10%
10%
SD
t
sd
HO
LO
50%
90%
HIN
LI N
HO
50%
50%
10%
LO
90%
MT
HO
LO
MT
RIC7113A4
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RIC7113L4
SCHEMATIC 2
Logic
20V
20V
400V
4K
4K
4K
50
2.4K
VDD
HIN
LIN
SD
VSS
VB
HO
VS
VCC
LO
COM
RIC7113
1 nF
1 nF
Figure 7. Static Bias Conditions for Total Ionizing DoseTest
Figure 8. Static Bias Conditions for Single Event Effect Test
8www.irf.com
RIC7113A4
V
B
SD
LIN
V
DD
PULSE
GEN
R
S
Q
V
SS
UV
DETECT
DELAY
HV
LEVEL
SHIFT
V
CC
PULSE
FILTER
UV
DETECT
V
DD
/V
CC
LEVE L
SHIFT
V
DD
/V
CC
LEVE L
SHIFT
LO
V
S
COM
R
S
Q
R
S
R
Q
HIN
HO
Symbol Description
VDD Logic supply
HIN Logic input for high side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low side gate driver output (LO), in phase
VSS Logic ground
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return
Lead Definitions
Functional Block Diagram
RIC7113A4
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Case Outline and Dimensions — 14 Lead FlatPack
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 10/2015
