1
TM
FN4029.5
HIP5010, HIP5011
7V, 17A SynchroFET™ Complementary
Drive Synchronous Half-Bridge
Designed with the P6 and Pentium® in mind, the Int ersil
SynchroFET™ family provides a new approach for
implementing a synchronous rect ified buck switching regulat or.
The SynchroFET replaces two power DMOSs, a Schottky
diode, two gate drivers and synchronous control circuitry. The
complementary drive circuit tur ns the upper FET on and the
lower FET off when the input from the PWM is high. When the
input from the PWM goes low the upper FET turns of f and the
lower FET turns on. The HIP5011 has a PWM pin that inverts
the relationship from the input to PHASE. This architecture
allows the designer t o uti liz e a low cost single-ended PWM
controller in either a current or voltage mode confi guration. The
SynchroFET oper ates in continuous conduction mode reducing
EMI constraints and enabling high bandwidth operation.
Several features ensure easy start-up. First, the supply currents
stay below speci fication as t he supply voltages ramp up; no
unexpected surges occur that might pertur b a soft-start or
deplete a charge-pump. Second, any power-up sequence of
the VCC, VIN, or PWM pins can be used without causing large
currents. Third, the chip operates when VCC is greater than 2V
so VCC can be created from a charge pump powered from VIN.
Features
• Complementary Drive, Hal f- Bri dge Power NMOS
• Use With Low-Cos t Si ngle-Output PWM Controllers
• Improve Efficiency Over Con ventional Buc k Converter wit h
Schottky Clamp
• Minimum Deadtime Provid ed by Adaptive Shoot-Through
Protect ion Elimi nates External Schottky
• Grounded Case for Low EMI and Simple Heatsinking
• Low Operati ng Current
• Frequency Exceeding 1MHz
• Dual Polarity Input Options
• All Pins Surge Protected
Applications
•5V to ≤3.3V Synchronous Buck Converters
• Pentium and P6 Power Supplies
• PowerPC™ Power Suppl ies
• Bus Terminations (BTL and GTL)
• Drive 5V Motor s Directl y from Microprocessor
Typical Application Block Diagram
Pentium® i s a registered trademark of Intel Corporation.
PowerPC™ is a trademark of International Business Machines.
SynchroFET™ is a trademark of Intersi l Corporation.
Pinouts
HIP5 010IS1, HIP5011IS1 (SIP - VERTICAL)
TOP VIEW
HIP5010IS, HIP5011IS (SI P - GULLWING)
TOP VIEW
1 PHASE
2V
IN
3V
CC
4
5 PWM ( HIP 5010), PWM (HI P501 1)
6V
IN
7 PHASE
GND (TAB) FRONT ROWS = PINS 1, 3, 5, 7
BACK ROWS = PINS 2, 4, 6
1 PHASE
2V
IN
3V
CC
4
5 PWM (HIP5010), PWM (HIP5011)
6V
IN
7 PHASE
GND
(TAB)
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HIP5010IS -40 to 85 7 Ld Gullwing S IP Z7.05B
HIP5010IS1 -40 to 85 7 Ld Staggered Vertical SIP Z7.05C
HIP5011IS -40 to 85 7 Ld Gullwing S IP Z7.05B
HIP5011IS1 -40 to 85 7 Ld Staggered Vertical SIP Z7.05C
+12V
+3.3V
PHASE
PWM
VIN
VCC
CONTROL
+5V
HIP5010
PWM
CONTROLLER
SYNCHRONOUS RECTIFIED BUCK CONVERT ER
GND
Data S heet Mar ch 199 6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-8 88-INTERSI L or 321-72 4-7143 |Intersil (and design) is a trademar k of Intersil Am ericas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
Non-Invert ing SynchroFET Block Diagram
HIP5010
DRIVER
DRIVER
VIN
PHASE
GND
VCC
BUFFER
PWM VCC
ADAPTIVE
SHOOT-THROUGH
PROTECTION
Inverting SynchroFET Block Diagram HIP5011
DRIVER
DRIVER
VIN
PHASE
GND
VCC
BUFFER
PWM VCC
ADAPTIVE
SHOOT-THROUGH
PROTECTION
HIP5010, HIP5011
3
Absolute Maximum Ratings Thermal Information (Typical)
Suppl y Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16V
Input Voltage VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
IPHASE, IVIN, IGND (TJ = 25oC) . . . . . . . . . . . 17A (Repetitive Peak)
IPHASE, IVIN, IGND (TJ = 15 0oC) . . . . . . . . . . 15A (Repetitive Peak)
PWM Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to +16V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3 (4kV)
Lead Temperature (Soldering 10s) (Lead Tips Only) . . . . . . 300oC
Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to 150oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC
Ope rat i ng Conditio ns
Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . +12V, ±20%
Input Voltage VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.5V
Supply Voltage, VCC, mini mum for char ge-pumped st art-up .+4.0V
Package θJC†† θJA (oC/W)†
(oC/W)01233†††
SOIC (IB) . . . 26 63 45 42 41 35
SIP (IS). . . . . 2 55 30 25 24 18
SIP (IS1). . . . 2 - ----
†Versus additional square inches of 1 ounce copper on the
printed circuit board.
†† θJC is measured to pin 12 for the SOIC. Printed circuit board
had 1 square inch of copper. For SIP Packages valu e shown is
typical with an infinite heat sink.
††† 200 linear feet per minute of air flow.
IPHASE.SIPs:11.5A(RMS), 11.2A(DC); SOIC:7.4A(RMS), 7.4A(DC)
IVIN . . . SIPs:10.0A(RMS), 8.5A(DC); SOIC:6.4A(RMS), 6.4A(DC)
IGND. . . . .SIPs:8.5A(RMS), 6.0A(DC); SOIC:5.4A(RMS), 5.4A(DC)
CAUTIO N: S tresses abov e those l isted i n “ A bsolute Max imum Ra ting s” ma y cause per manen t dam age to th e de vice. This is a s tress on l y rating and ope ration of th e
device at these or any other conditions above those indicated in the recommended operating conditions of thi s specification is not implied.
Electrical Speci fications
PARAMETERS SYMBOL TEST CONDITIONS
TJ = 25oCTJ = - 40oC
TJ = 150oC
UNITSMIN TYP MAX MIN MAX
rDS(ON) Upper MOSFET RDSU VCC = 12 V , VIN = 5V - 34 39 - 65 mΩ
rDS(ON) Low er MOSFET RDSL VCC = 12V , VIN = 5V - 36 42 - 68 mΩ
VIN Op erating Current IVINO VIN = 5V, No Load, 500kHz - 5 8 - 10 mA
VIN Qu ie sc ent C urr ent IVIN PWM or PWM = VCC or GND - 0.1 10 - 100 µA
VCC O p erat i ng C u rr en t ICCO VCC = 12 V, 500kHz - 8 1 2 - 1 5 mA
VCC Q u iesce nt Cur ren t (HIP 50 10 ) ICCIH PWM = VCC -80- -400µA
VCC Q u iesce nt Cur ren t (HIP 50 10 ) ICCIL PWM = GND - 0.1 10 - 100 µA
VCC Q u iesce nt Cur ren t (HIP 50 11 ) ICCNIH PWM = VCC - 0.1 10 - 100 µA
VCC Q u iesce nt Cur ren t (HIP 50 11 ) ICCNIL PWM = GND - 140 - - 400 µA
Low Level PWM Input Voltage VIL -1.8- 1 - V
High Level PWM Input Voltag e VIH -2.1- - 3 V
PWM Input Voltage Hysteresis VIHYS -0.3---V
Input Pulldown Resistance (HIP5010) RPWM -220-100400kΩ
Input Pullup Resistance (HIP5011) RPWM -220-100400kΩ
Switching Spec ifications
PARAMETERS SYMBOL TEST CONDITIONS
TJ = 25oCTJ = - 40oC
TJ = 150oC
UNITSMIN TYP MAX MIN MAX
Upper Device Turn -Off Dela y tPHL VCC = 12V , IPHASE = -1A - 30 50 - 80 n s
Lower Device Turn-Off Delay tPLH VCC = 12V , IPHASE = +1A - 30 50 - 80 ns
Dead Time tDT VCC = +12V, IPHASE = -1A -10---ns
Phase Rise-Time trVCC = 12 V, IPHASE = -1A -20---ns
Phase Fall-Time tfVCC = 12V , IPHASE = +1A -20---ns
HIP5010, HIP5011
4
Timing Diagram
Pin Descr iption s
SYMBOL DESCRIPTION
VCC Positive sup ply to control logic and gate dri vers. De-couple this pin to GND .
VIN FET Switch Input Voltage. De- c ouple this pi n to GN D. Tie all VIN terminal s tog ether.
PH AS E Output. Tie all phase terminals together.
PWM (HIP5010)
PWM (HIP5011) Single Ended Control Input. Th is i nput connect s to the PW M controller output .
GND System G round.
12V
2V
12V
0V
2V
0V
5V
4.5V
2.5V
0.5V
0V
-0.5V
tPHL
tPLH
tftr
tDT
PWM (HIP5010)
PWM (HIP5011)
PHASE
NOTE: IPHASE = +1A fo r tPLH and tf, IPHASE = -1A for tPHL, tDT, and tr.
FIGURE 1.
HIP5010, HIP5011
5
Typical Performance Curves
FIGURE 2. ICCO vs FREQUENCY FIGURE 3. IVINO vs FREQUENCY
FIGURE 4. RDSU vs VCC FIGURE 5. RDSL vs VCC
FIGURE 6. RDSU OR RDSL vs TEMPERATURE
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
ICCO (mA)
20
18
16
14
12
10
8
6
4
2
00 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
IVINO (mA)
6.0
5.5
5.0
4.5
3.5
3.0
2.5
2.0
1.5
1.0
0
456789101112
VCC (V)
rDSU (mΩ)
120
110
100
90
80
70
60
50
40
30
20 13 14 15 16
VIN = 5V
VIN = 3.3V
456789101112
VCC (V)
rDSL (m Ω)
120
110
100
90
80
70
60
50
40
30
20 13 14 15 16
VIN = 5V AND 3.3 V
-40 -20 0 20 40 60 80 100 120 140
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
TEMPERATURE (oC)
RDSU OR RDSL (NORMALIZED)
HIP5010, HIP5011
6
HIP5010, HIP5011
Single-In-Line Plastic Packages (SIP)
E
C2
A
L2
D
L
b
L1
c
D1
E1
0.350
0.609
-A-
-C-
0.006
-B-
0.004
0.00 - 0.0098
BACK VIEW
0.450
LAND PATTERN
0.010 (0.25) B AM M CM
e
(0.15)
HEATSLUG
PLANE
(0.00 - 0. 25)
(0.10)
(15.46)
MIN
(11.43) MIN
(8.89)
MIN
0.129
(3.27)
TYP
0.030
(0.76)
TYP
e
PIN
#1
0o- 8o
L3
Z7.05B
7 LEAD P LAS TIC S INGLE -I N-LIN E PACKA GE SUR F ACE MOUNT
“GULLWING” LEAD FORM
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
C2 0.048 0.055 1.22 1.39 5
D 0.350 0.370 8.89 9.39 -
E 0.395 0.405 10.04 10.28 -
D1 0.310 - 7.88 - -
E1 0.310 - 7.88 - -
L 0.549 0.569 13.95 14.45 -
L1 0.068 0.088 1.72 2.24 -
L2 0.045 0.055 1.15 1.40 -
L3 0.030 BSC 0.76 BSC 4
b 0.028 0.034 0.71 0.86 5, 6, 7
c 0.018 0.024 0.46 0.60 5
e 0.050 BSC 1.27 BSC -
Rev. 2 12/95
NOTES:
1. Thes e p ack ag e d imens io ns ar e wi th in al l owa bl e di me ns io ns o f
JEDEC MO-16 9AC, Issue A.
2. C o nt r ol lin g di mensio n: Inc h.
3. Dimen s ioning and tolera nce per ANSI Y14.5M-1982.
4. G a ug e pla ne L3 is par a lle l t o he ats lu g plane.
5. Dimensions include lead finish.
6. Leads are not allowed above the datum .
7. Dimension “b” does not include dambar protrusion. Allowable
dam bar pr ot ru s io n shall not c a us e t he lead wi dth to ex c ee d the
maximu m “b” by more t han 0.003’’ (0.08mm).
-B-
7
HIP5010, HIP5011
Single-In-Line Plastic Packages (SIP)
eB
HEADER
-A-
E
A
D1
D
ØP -B-
E2
E1
0.010 (0.25) A BM M
7 PLACES
L
BOTTOM
L1
e1e2
C
0.024 (0.61) AM
ALL LEADS
F
0.006 (0.15)
LH
HHHH
LLL
e3
Z7.05C
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED
VERTICAL LEAD FORM
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
B 0.028 0.034 0.71 0.86 3, 4
C 0.018 0.024 0.46 0.60 3
D 0.395 0.405 10.04 10.28 -
D1 0.198 0.202 5.03 5.13 -
E 0.595 0.605 15.11 15.37 -
E1 0.350 0.370 8.89 9.39 -
E2 0.110 BSC 2.79 BSC
e 0.050 BSC 1.27 BSC -
e1 0.200 BSC 5.08 BSC -
e2 0.169 BSC 4.29 BSC -
e3 0.300 BSC 7.62 BSC -
F 0.048 0.055 1.22 1.39 3
L 0.150 0.176 3.81 4.47 -
L1 0.600 0.620 15.24 15.74 -
ØP 0.147 0.152 3.73 3.86 3
Rev. 1 4/98
NOTES:
1. Co ntrolling dimension: I NCH.
2. Dimen s ioning and tolera ncing per ANSI Y14.5M-1982.
3. Dimensions include lead finish.
4. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall not cause lead width to exceed maxi-
mum “B” b y more than 0.003 inches (0.08mm).
