IN OUT
S/D ADJ
BYPASS GND
LP3878-ADJ
VIN
**S/D
*0.01 µF
VOUT
*4.7 µF
(Ceramic or
Tantalum
recommended)
*10 µF
(Ceramic
recommended)
CFF
R1
R2
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LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
LP3878-ADJ Micropower 800-mA Low-Noise "Ceramic Stable" Adjustable Voltage
Regulator for 1-V to 5-V Applications
1 Features 3 Description
The LP3878-ADJ is an 800-mA, adjustable output,
1• Input Supply Voltage: 2.5 V to 16V voltage regulator designed to provide high
• Output Voltage Range: 1 V to 5.5 V performance and low noise in applications requiring
• Designed for Use With Low-ESR Ceramic output voltages as low as 1 V.
Capacitors Using an optimized VIP (Vertically Integrated PNP)
• Very Low Output Noise process, the LP3878-ADJ delivers superior
• 8-Lead SO PowerPAD™ and WSON Surface- performance:
Mount Packages • Ground Pin Current: Typically 5.5 mA at 800-mA
load, and 180 µA at 100-µA load.
• < 10-μA Quiescent Current in Shutdown • Low Power Shutdown: The LP3878-ADJ draws
• Low Ground Pin Current at all Loads less than 10-μA quiescent current when the
• Overtemperature and Overcurrent Protection SHUTDOWN pin is pulled low.
• –40°C to 125°C Operating Junction Temperature • Precision Output: Ensured output voltage
Range accuracy is 1% at room temperature.
• Low Noise: Broadband output noise is only 18 μV
2 Applications (typical) with a 10-nF bypass capacitor.
• ASIC Power Supplies In: Device Information(1)
– Desktops, Notebooks, and Graphic Cards PART NUMBER PACKAGE BODY SIZE (NOM)
– Set Top Boxes, Printers, and Copiers SO PowerPAD (8) 4.89 mm × 3.90 mm
LP3878-ADJ
• DSP and FPGA Power Supplies WSON (8) 4.00 mm × 4.00 mm
• SMPS Post-Regulator (1) For all available packages, see the orderable addendum at
• Medical Instrumentation the end of the data sheet.
Basic Application Circuit
*Capacitor values shown are minimum required to assure stability. A larger output capacitor provides improved
dynamic response. Output capacitor must meet ESR requirements (see Application Information).
**The SHUTDOWN (or S/D) pin must be actively terminated (see Device Functional Modes). Tie to IN (pin 4) if not
used.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 12
1 Features.................................................................. 18 Application and Implementation ........................ 13
2 Applications ........................................................... 18.1 Application Information............................................ 13
3 Description............................................................. 18.2 Typical Application ................................................. 13
4 Revision History..................................................... 29 Power Supply Recommendations...................... 17
5 Pin Configuration and Functions......................... 310 Layout................................................................... 17
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 17
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 17
6.2 ESD Ratings.............................................................. 410.3 Power Dissipation ................................................. 17
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 18
6.4 Thermal Information.................................................. 411.1 Documentation Support ........................................ 18
6.5 Electrical Characteristics........................................... 511.2 Trademarks........................................................... 18
6.6 Typical Characteristics.............................................. 611.3 Electrostatic Discharge Caution............................ 18
7 Detailed Description............................................ 11 11.4 Glossary................................................................ 18
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 11 Information ........................................................... 18
7.3 Feature Description................................................. 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2014) to Revision D Page
• Deleted trademark symbol from VIP - no longer trademark; add reference design icon to Top Navigators.......................... 1
• Deleted soldering info - now in POA ..................................................................................................................................... 4
• Changed wording of footnote 5 to Ab Max Ratings ............................................................................................................... 4
• Changed IOUT to IOUT throughout document............................................................................................................................ 5
• Changed wording of Reverse Input-Output Voltage ............................................................................................................ 11
• Changed outpin pin to OUT pin ........................................................................................................................................... 15
• Added new paragraph to Noise Bypass Capacitor subsection ........................................................................................... 15
Changes from Revision B (April 2013) to Revision C Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section; update
thermal values ....................................................................................................................................................................... 1
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 16
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1
2
3
45
6
7
8
BYPASS
N/C
GROUND
IN
ADJ
OUT
SHUTDOWN
Thermal Pad
N/C
1
2
3
4
8
7
6
5
Thermal
Pad
BYPASS
N/C
GROUND
IN ADJ
OUT
N/C
SHUTDOWN
LP3878-ADJ
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SNVS311D –MAY 2005–REVISED FEBRUARY 2015
5 Pin Configuration and Functions
SO PowerPAD (DDA) Package
8-Pin
Top View
WSON (NGT) Package
8-Pin
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NUMBER
ADJ 6 I Provides feedback to error amplifier from the resistive divider that sets the output voltage.
The capacitor connected between BYPASS and GROUND lowers output noise voltage level
BYPASS 1 — and is required for loop stability.
GROUND 3 — Device ground.
IN 4 I Input source voltage.
DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration of the
LP3878-ADJ VADJ accuracy. This pin must be left floating. Do not connect to any potential.
Do not connect to ground. Any attempt to do pin continuity testing on device pin 2 is
N/C 2 discouraged. Continuity test results will be variable depending on the actions of the factory
calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 2
may activate the trim circuitry forcing VADJ to move out of tolerance.
N/C 7 No internal connection.
OUT 5 O Regulated output voltage.
SHUTDOWN 8 I Output is enabled above turnon threshold voltage. Pull down to turn off regulator output.
The exposed thermal pad on the bottom of the package should be connected to a copper
thermal pad on the PCB under the package. The use of thermal vias to remove heat from
the package into the PCB is recommended. Connect the thermal pad to ground potential or
Thermal Pad — — leave floating. Do not connect the thermal pad to any potential other than the same ground
potential seen at device pin 3. For additional information on using TI's Non Pull Back WSON
package, see Application Note AN-1187,SNOA401.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
SHUTDOWN pin 1 kV
Power dissipation(3) Internally Limited
Input supply voltage (survival), VIN −0.3 16 V
ADJ pin −0.3 6 V
Output voltage (survival), VOUT(4) −0.3 6 V
IOUT (survival) Short-Circuit Protected
Input – output voltage (survival), VIN – VOUT(5) −0.3 16 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military- or Aerospace-specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: P(MAX) = (TJ(MAX) – TA) / RθJA. The value of RθJA for the WSON (NGT) and SO PowerPAD (DDA) packages are specifically
dependent on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power
dissipation for the WSON package, see Application Note AN-1187, SNOA401. Exceeding the maximum allowable power dissipation will
cause excessive die temperature, and the regulator will go into thermal shutdown.
(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3878-ADJ output must be diode-
clamped to ground.
(5) The PNP pass element contains a parasitic diode between the IN pin and the OUT pin that is normally reverse-biased. Forcing the OUT
pin voltage above the IN pin voltage will turn on this diode and may induce a latch-up mode which can damage the part (see Application
and Implementation).
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Supply input voltage 2.5 16 V
VSD SHUTDOWN input voltage VIN V
IOUT Output current 800 mA
TJOperating junction temperature −40 125 °C
6.4 Thermal Information LP3878-ADJ
THERMAL METRIC(1) DDA NGT UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 42.5 38.1
RθJC(top) Junction-to-case (top) thermal resistance 54.0 27.9
RθJB Junction-to-board thermal resistance 26.5 15.2 °C/W
ψJT Junction-to-top characterization parameter 8.0 0.2
ψJB Junction-to-board characterization parameter 26.4 15.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 4.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Limits are specified through design, testing, or correlation. The limits are used to calculate TI's Average Outgoing Quality
Level (AOQL). Unless otherwise specified: TJ= 25°C, VIN = 3 V, VOUT = 1 V, IOUT = 1 mA, COUT = 10 µF, CIN = 4.7 µF, VSD = 2
VVSD, CBYPASS = 10 nF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.99 1.00 1.01
1 mA ≤IOUT ≤800 mA, 3 V ≤VIN ≤6 V 0.98 1.00 1.02
VADJ Adjust pin voltage V
1 mA ≤IOUT ≤800 mA, 3 V ≤VIN ≤6 V 0.97 1.03
–40°C ≤TJ≤125°C
3 V ≤VIN ≤16 V 0.007 0.014
ΔVOUT/ΔVIN Output voltage line regulation %/V
3 V ≤VIN ≤16 V, –40°C ≤TJ≤125°C 0.032
IOUT = 800 mA, VOUT ≥VOUT(NOM) – 1% 2.5
IOUT = 800 mA, VOUT ≥VOUT(NOM) – 1% 3.1
–40°C ≤TJ≤125°C
IOUT = 800 mA, VOUT ≥VOUT(NOM) – 1% 2.5
Minimum input voltage 0≤TJ≤125°C
VIN(MIN) required to maintain output V
IOUT = 800 mA, VOUT ≥VOUT(NOM) – 1%
regulation 2.8
0≤TJ≤125°C, –40°C ≤TJ≤125°C
IOUT = 750 mA, VOUT ≥VOUT(NOM) – 1% 2.5
IOUT = 750 mA, VOUT ≥VOUT(NOM) – 1% 3.0
–40°C ≤TJ≤125°C
IOUT = 100 µA 1 2
IOUT = 100 µA, –40°C ≤TJ≤125°C 3
IOUT = 200 mA 150 200
Dropout voltage(1)
VDOUT mV
VOUT = 3.8 V IOUT = 200 mA, –40°C ≤TJ≤125°C 300
IOUT = 800 mA 475 600
IOUT = 800 mA, –40°C ≤TJ≤125°C 1100
IOUT = 100 µA 180 200 µA
IOUT = 100 µA, –40°C ≤TJ≤125°C 225
IOUT = 200 mA 1.5 2
IGND Ground pin current IOUT = 200 mA, –40°C ≤TJ≤125°C 3.5 mA
IOUT = 800 mA 5.5 8.5
IOUT = 800 mA, –40°C ≤TJ≤125°C 15
IOUT(PK) Peak output current VOUT ≥VOUT(NOM) −5% 1200 mA
IOUT(MAX) Short-circuit current RL= 0 Ω(steady state) 1300
Bandwidth = 100 Hz to 100 kHz, CBYPASS = 10
enOutput noise voltage (RMS) 18 µV(RMS)
nF
ΔVOUT/ΔVIN Ripple rejection f = 1 kHz 60 dB
IADJ ADJ pin bias current IOUT = 800 mA 200 nA
(sourcing)
SHUTDOWN Input
VH= Output ON 1.4
VH= Output ON, –40°C ≤TJ≤125°C 1.6
VL= Output OFF, IIN ≤10 µA 0.20
VSD SHUTDOWN input voltage V
VL= Output OFF, IIN ≤10 µA 0.04
–40°C ≤TJ≤125°C
VOUT ≤10 mV, IIN ≤50 µA 0.6
VSD = 0 V 0.02
VSD = 0 V, –40°C ≤TJ≤125°C −1
ISD SHUTDOWN input current µA
VSD = 5 V 5
VSD = 5 V, –40°C ≤TJ≤125°C 15
(1) Dropout voltage specification applies only if VIN is sufficient so that it does not limit regulator operation.
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1.0 1.5 2.0 2.5 3.0 3.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN (V)
VOUT (V)
IL = 800 mA IL = 400 mA
IL = 100 mA
TJ = 0°C
1.0 1.5 2.0 2.5 3.0 3.5
1.0
1,5
2.0
2.5
3.0
3.5
4.0
4.5
VIN (V)
VOUT (V)
800 mA
400 mA
100 mA
TJ = 125oC
-60 -40 -20 0 20 40 60 80 100 120 140
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
IGND (mA)
TEMPERATURE (°C)
IL = 800 mA
IL = 240 mA
IL = 1 mA
LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
www.ti.com
6.6 Typical Characteristics
Unless otherwise specified: VIN = 3.3 V, VOUT = 1 V, IOUT = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VSD = 2 V, CBYP = 10 nF, TJ=
25°C.
Figure 2. Minimum VIN Over Temperature
Figure 1. IGND vs Temperature
Figure 3. IGND vs ILoad Figure 4. VOUT vs Temperature
Figure 5. Minimum VIN vs VOUT Figure 6. Minimum VIN vs VOUT
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0
10
20
30
40
50
100
RIPPLE REJECTION (dB)
10 100 1k 10k 100k
FREQUENCY (Hz)
60
70
80
90
1M
IL= 800 mA
0
10
20
30
40
50
100
RIPPLE REJECTION (dB)
10 100 1k 10k 100k
FREQUENCY (Hz)
60
70
80
90
1M
1.0 1.5 2.0 2.5 3.0 3.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN (V)
VOUT (V)
IL = 400 mA
IL = 800 mA
IL = 100 mA
TJ = -40°C
LP3878-ADJ
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SNVS311D –MAY 2005–REVISED FEBRUARY 2015
Typical Characteristics (continued)
Unless otherwise specified: VIN = 3.3 V, VOUT = 1 V, IOUT = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VSD = 2 V, CBYP = 10 nF, TJ=
25°C.
Figure 7. Minimum VIN vs VOUT Figure 8. Ripple Rejection
Figure 10. Output Noise Spectral Density
Figure 9. Ripple Rejection
Figure 12. Line Transient Response
Figure 11. Output Noise Spectral Density
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Typical Characteristics (continued)
Unless otherwise specified: VIN = 3.3 V, VOUT = 1 V, IOUT = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VSD = 2 V, CBYP = 10 nF, TJ=
25°C.
Figure 14. Line Transient Response
Figure 13. Line Transient Response
Figure 15. Line Transient Response Figure 16. Line Transient Response
Figure 17. Line Transient Response Figure 18. Line Transient Response
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Typical Characteristics (continued)
Unless otherwise specified: VIN = 3.3 V, VOUT = 1 V, IOUT = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VSD = 2 V, CBYP = 10 nF, TJ=
25°C.
Figure 19. Line Transient Response Figure 20. Line Transient Response
Figure 22. Line Transient Response
Figure 21. Line Transient Response
Figure 23. Load Transient Response Figure 24. Load Transient Response
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0 0.5 1 1.5 2
VS/D
0
0.2
0.4
0.6
0.8
1
1.2
VOUT (V)
0oC
125oC
25oC
0
0.2
0.4
0.6
0.8
1
1.2
VOUT (V)
0 0.5 1 1.5 2
VS/D
0oC
125oC
25oC
LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified: VIN = 3.3 V, VOUT = 1 V, IOUT = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VSD = 2 V, CBYP = 10 nF, TJ=
25°C.
Figure 25. Turnon Characteristics Figure 26. Turnoff Characteristics
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+
-
2
7
8
5416
3
1 V
VREF
Error
Amp
LP3878-
ADJ
BYPASS
N/C
GROUND
IN
ADJ OUT
N/C
SHUTDOWN
+
LP3878-ADJ
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SNVS311D –MAY 2005–REVISED FEBRUARY 2015
7 Detailed Description
7.1 Overview
The LP3878-ADJ is an adjustable regulator; the output voltage can be set from 1 V to 5.5 V. The device can
deliver 800-mA continuous load current. Standard regulator features, such as overcurrent and overtemperature
protection, are also included.
The LP3878-ADJ contains other features:
• Low power shutdown current and low ground pin current
• Very low output noise
• 8-lead SO PowerPAD or WSON surface-mount packages to allow for increased power dissipation.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Shutdown Input Operation
The LP3878-ADJ is shut off by pulling the SHUTDOWN input low, and turned on by pulling it high. If this feature
is not to be used, the SHUTDOWN input should be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the SHUTDOWN input must be able to swing above
and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under VON/OFF.
7.3.2 Reverse Input-Output Voltage
The PNP power transistor used as the pass element in the LP3878-ADJ contains a parasitic diode between the
IN pin and the OUT pin. During normal operation (where the IN pin voltage is higher than the OUT pin voltage)
this parasitic diode is reverse-biased. However, if the OUT pin voltage is pulled above the IN pin voltage this
diode will turn ON, and current will flow into the LP3878-ADJ OUT pin.
In such cases, a parasitic SCR between the IN pin and the GND pin can latch ON which will allow a high current
to flow from the VIN supply, into the IN pin to ground, which can damage the part. In any application where the
OUT pin voltage may be higher than the IN pin voltage, even momentarily, an external Schottky diode must be
connected from the IN pin to the OUT pin (cathode to IN pin, anode to OUT pin), to limit the reverse voltage
across the LP3878-ADJ to 0.3 V (see Absolute Maximum Ratings).
7.3.3 Low Output Noise
With a 10-nF capacitor on the BYPASS pin, the output noise is only 18 µV.
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7.4 Device Functional Modes
7.4.1 Operation With VOUT(TARGET) +2V≤VIN ≤16 V
The device operates if the input voltage is equal to, or exceeds VOUT(TARGET) + 2 V. At input voltages below the
minimum VIN requirement, the device does not operate correctly and output voltage may not reach target value.
7.4.2 Operation With SHUTDOWN Pin Control
LP3878-ADJ is turned off by pulling the SHUTDOWN pin low, and turned on by pulling it high. If this feature is
not used, the SHUTDOWN pin should be tied to VIN to keep the regulator output on at all times. To assure
proper operation, the signal source used to drive the SHUTDOWN input must be able to swing above and below
the specified turnon and turnoff voltage thresholds listed in the Electrical Characteristics under VLand VH.
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IN OUT
S/D ADJ
BYPASS GND
LP3878-ADJ
VIN
**S/D
*0.01 µF
VOUT
*4.7 µF
(Ceramic or
Tantalum
recommended)
*10 µF
(Ceramic
recommended)
CFF
R1
R2
LP3878-ADJ
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SNVS311D –MAY 2005–REVISED FEBRUARY 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3878-ADJ can provide 800-mA output current with 2.5-V to 6-V output voltage. A minimum 10-µF output
capacitor is required for loop stability. An input capacitor of at least 4.7-µF is required also. The SHUTDOWN pin
must be tied to input if not used. A 10-nF bypass capacitor is required to improve loop stability, it also can reduce
noise on the regulator output significantly. A capacitor, CFF, is required to increase phase margin and assure loop
stability. Output voltage can be set by two resistors R1 and R2 (see Figure 27), and R2 must be less than 5 kΩ
to ensure loop stability.
8.2 Typical Application
*Capacitor values shown are minimum required to assure stability. Larger output capacitor provides improved
dynamic response. Output capacitor must meet ESR requirements (see Application Information).
**The SHUTDOWN (or S/D) pin must be actively terminated (see Device Functional Modes). Tie to IN (pin 4) if not
used.
Figure 27. Basic Application Circuit
8.2.1 Design Requirements
DESIGN PARAMETER VALUE
Input voltage 3.8 V ±10%
Output voltage 1.8 V ±3%
Output current 800 mA (maximum)
Input capacitor 4.7 µF (minimum)
Output capacitor 10 µF (minimum)
Bypass capacitor 10 nF
External resistor R2 1 kΩ(less than 5 kΩ)
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0.001
0.01
0.1
1
10
ESR (:)
0 200 400 600 800
LOAD CURRENT (mA)
STABLE REGION
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8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
Like any low-dropout regulator, the LP3878-ADJ requires external capacitors for regulator stability. These
capacitors must be correctly selected for good performance.
8.2.2.1.1 Input Capacitor
A capacitor whose value is at least 4.7 µF (±20%) is required between the LP3878-ADJ input and ground. A
good quality X5R or X7R ceramic capacitor should be used.
Capacitor tolerance and temperature variation must be considered when selecting a capacitor (see Capacitor
Characteristics) to assure the minimum requirement of input capacitance is met over all operating conditions.
The input capacitor must be located not more than 0.5 inches from the input pin and returned to a clean analog
ground. Any good quality ceramic or tantalum capacitor may be used, assuming the minimum input capacitance
requirement is met.
8.2.2.1.2 Output Capacitor
The LP3878-ADJ requires a ceramic output capacitor whose size is at least 10 µF (±20%). A good quality X5R or
X7R ceramic capacitor should be used. Capacitance tolerance and temperature characteristics must be
considered when selecting an output capacitor.
The LP3878-ADJ is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows
the regulator to be stable across the entire range of output current with an ultra-low equivalent series resistance
(ESR) output capacitor.
The output capacitor selected must meet the requirement for minimum amount of capacitance and also have an
ESR value which is within the stable range. A curve is provided which shows the stable ESR range as a function
of load current (see Figure 28).
Figure 28. Stable Region for Output Capacitor ESR
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NOTE
Important: The output capacitor must maintain its ESR within the stable region over the
full operating temperature range of the application to assure stability.
The output capacitor ESR forms a zero which is required to add phase lead near the loop gain crossover
frequency, typically in the range of 50 kHz to 200 kHz. The ESR at lower frequencies is of no importance. Some
capacitor manufacturers list ESR at low frequencies only, and some give a formula for Dissipation Factor (DF)
which can be used to calculate a value for a term referred to as ESR. However, because the DF formula is
usually at a much lower frequency than the range listed above, it will give an unrealistically high value. If good
quality X5R or X7R ceramic capacitors are used, the actual ESR in the 50-kHz to 200-kHz range will not exceed
25 mΩ. If these are used as output capacitors for the LP3878-ADJ, the regulator stability requirements are
satisfied.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range (see Capacitor Characteristics).
The output capacitor must be located not more than 0.5 inches from the OUT pin and returned to a clean analog
ground.
8.2.2.1.3 Noise Bypass Capacitor
The 10-nF capacitor on the BYPASS pin significantly reduces noise on the regulator output and is required for
loop stability. However, the capacitor is connected directly to a high-impedance circuit in the bandgap reference.
Because this circuit has only a few µA flowing in it, any significant loading on this node will cause a change in the
regulated output voltage. For this reason, dc leakage current through the noise bypass capacitor must never
exceed 100 nA, and should be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropylene and
polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low
leakage current.
While the capacitor value on the BYPASS will affect start-up time, this is not intended to be used as a soft-start
circuit. There is no dedicated discharge circuitry for this capacitor, and it can be pre-biased if the IN pin, or the
SHUTDOWN pin are not at 0 V at start-up.
8.2.2.2 Feedforward Capacitor
The feedforward capacitor designated CFF in Figure 27 is required to increase phase margin and assure loop
stability. Improved phase margin also gives better transient response to changes in load or input voltage, and
faster settling time on the output voltage when transients occur. CFF forms both a pole and zero in the loop gain,
the zero providing beneficial phase lead (which increases phase margin) and the pole adding undesirable phase
lag (which should be minimized). The zero frequency is determined both by the value of CFF and R1:
fZ= 1 / (2πCFF × R1) (1)
The pole frequency resulting from CFF is determined by the value of CFF and the parallel combination of R1 and
R2: fP= 1 / (2πCFF × (R1 // R2)) (2)
At higher output voltages where R1 is much greater than R2, the value of R2 primarily determines the value of
the parallel combination of R1 // R2. This puts the pole at a much higher frequency than the zero. As the
regulated output voltage is reduced (and the value of R1 decreases), the parallel effect of R2 diminishes and the
two equations become equal (at which point the pole and zero cancel out). Because the pole frequency gets
closer to the zero at lower output voltages, the beneficial effects of CFF are increased if the frequency range of
the zero is shifted slightly higher for applications with low VOUT (because then the pole adds less phase lag at the
loop crossover frequency).
CFF should be selected to place the pole-zero pair at a frequency where the net phase lead added to the loop at
the crossover frequency is maximized. The following design guidelines were obtained from bench testing to
optimize phase margin, transient response, and settling time:
• For VOUT ≤2.5 V: CFF should be selected to set the zero frequency in the range of about 50 kHz to 200 kHz.
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LP3878-ADJ
LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
www.ti.com
• For VOUT > 2.5 V: CFF should be selected to set the zero frequency in the range of about 20 kHz to 100 kHz.
8.2.2.3 Capacitor Characteristics
8.2.2.3.1 Ceramic
The LP3878-ADJ was designed to work with ceramic capacitors on the output to take advantage of the benefits
they offer: for capacitance values in the 10-µF range, ceramics are the least expensive and also have the lowest
ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10-µF ceramic
capacitor is in the range of 5 mΩto 10 mΩ, which meets the ESR limits required for stability by the LP3878-ADJ.
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value
ceramic capacitors (≥2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
Another significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with
applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated
voltage applied to it.
For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the LP3878-
ADJ.
8.2.2.4 Setting the Output Voltage
The output voltage is set using resistors R1 and R2 (see Figure 27).
The formula for output voltage is:
VOUT = VADJ × (1 + (R1 / R2)) (3)
R2 must be less than 5 kΩto ensure loop stability.
To prevent voltage errors, R1 and R2 must be located near the LP3878-ADJ and connected via traces with no
other currents flowing in them (Kelvin connect). The bottom of the R1/R2 divider must be connected directly to
the LP3878-ADJ ground pin.
8.2.3 Application Curves
Figure 29. Load Transient Response Figure 30. Load Transient Response
16 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LP3878-ADJ
Bypass
Capacitor
BYP
N/C
GND
S/D
ADJ
N/C
OUTIN
Input
Capacitor
CFF
R2
R1
Output
Capacitor
LP3878-ADJ
www.ti.com
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
9 Power Supply Recommendations
The LP3878-ADJ is designed to operate from an input voltage supply range between 2.5 V and 16 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. An input capacitor of at least 4.7 μF is required.
10 Layout
10.1 Layout Guidelines
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.
The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator
using traces which do not have other currents flowing in them (Kelvin connect).
The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and ground
pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its
capacitors have a single point ground.
It should be noted that stability problems have been seen in applications where vias to an internal ground plane
were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing through the ground plane. Using a single-point ground
technique for the regulator and its capacitors fixed the problem.
Because high current flows through the traces going into IN and coming from OUT, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series with the input and output capacitors.
10.2 Layout Example
10.3 Power Dissipation
The LP3878-ADJ is offered in the 8-lead SO PowerPAD or WSON surface-mount packages to allow for
increased power dissipation compared to the SO-8 and Mini SO-8. For details on thermal performance as well as
mounting and soldering specifications, refer to Application Note AN-1187,SNOA401.
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LP3878-ADJ
LP3878-ADJ
SNVS311D –MAY 2005–REVISED FEBRUARY 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Application Note AN-1187,SNOA401
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LP3878-ADJ
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3878MR-ADJ NRND SO PowerPAD DDA 8 95 Non-RoHS
& Green Call TI Call TI -40 to 125 3878
MRADJ
LP3878MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 3878
MRADJ
LP3878MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 3878
MRADJ
LP3878SD-ADJ/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 3878ADJ
LP3878SDX-ADJ/NOPB ACTIVE WSON NGT 8 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 3878ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3878MRX-ADJ/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP3878SD-ADJ/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LP3878SDX-ADJ/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3878MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LP3878SD-ADJ/NOPB WSON NGT 8 1000 200.0 183.0 25.0
LP3878SDX-ADJ/NOPB WSON NGT 8 4500 346.0 346.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8 0.15
0.00
2.71
2.11
3.4
2.8 0.25
GAGE PLANE
1.27
0.40
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
9
TYP
6.2
5.8
1.7 MAX
A
NOTE 3
5.0
4.8
B4.0
3.8
www.ti.com
EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.71)
(3.4)
SOLDER MASK
OPENING
(1.3)
TYP
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
9
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.71)
(3.4)
BASED ON
0.125 THICK
STENCIL
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
9
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
3 0.05
2X
2.4
2.6 0.05
6X 0.8
0.8 MAX
0.05
0.00
8X 0.5
0.3
A4.1
3.9 B
4.1
3.9
(0.2) TYP
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(3)
(3.8)
6X (0.8)
(2.6)
( 0.2) VIA
TYP (1.05)
(1.25)
8X (0.6)
(R0.05) TYP
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
SYMM
1
45
8
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
(1.31)
(0.675)
8X (0.3)
8X (0.6)
(1.15)
(3.8)
(0.755)
6X (0.8)
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
METAL
TYP
SYMM 9
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