1998
Apr
02
1869
Philips Semiconductors
PowerMOS transistors
Package outlines
P
ACKAGE OUTLINES
Package
Surface-mount
Page
SOT23
yes
....
SOT54 (TO-92)
no
....
SOT54variant (TO-92variant)
no
....
SOT78 (TO-220AB)
no
....
SOT89
yes
....
SOT96-1 (SO8)
yes
....
SOT137-1 (SO24)
yes
....
SOT186 (TO-220 exposed tabs)
no
....
SOT186A (TO-220)
no
....
SOT223
yes
....
SOT226 (low-proļ¬le TO-220)
no
....
SOT263 (5-lead TO-220)
no
....
SOT263-01 (lead option TO-220)
no
....
SOT323
yes
....
SOT338-1 (SSOP16)
yes
....
SOT340-1 (SSOP24)
yes
....
SOT363
yes
....
SOT404
yes
....
SOT426
yes
....
SOT428
yes
....
SOT429 (TO-247)
no
....
SOT457 (TSOP6)
yes
....
1998
Apr
02
1870
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
1
max.
b
p
cD
E
e
1
H
E
L
p
Qw
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
IEC
JEDEC
EIAJ
mm
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
0.95
e
1.9
2.5
2.1
0.55
0.45
0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT23
b
p
D
e
1
e
A
A
1
L
p
Q
detail X
H
E
E
w
M
v
M
A
B
A
B
0
1
2 mm
scale
A
1.1
0.9
c
X
12
3
Plastic surface mounted package; 3 leads
SOT23
1998
Apr
02
1871
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
5.2
5.0
b
0.48
0.40
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
L
14.5
12.7
e
2.54
e
1
1.27
L
1
(1)
2.5
b
1
0.66
0.56
DIMENSIONS (mm are the original dimensions)
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
SOT54
TO-92
SC-43
97-02-28
A
L
0
2.5
5 mm
scale
b
c
D
b
1
L
1
d
E
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
e
1
e
1
2
3
1998
Apr
02
1872
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
5.2
5.0
b
0.48
0.40
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
L
14.5
12.7
e
2.54
e
1
1.27
L
1
(1)
max
L
2
max
2.5
2.5
b
1
0.66
0.56
DIMENSIONS (mm are the original dimensions)
Notes
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
SOT54 variant
TO-92 variant
SC-43
A
L
0
2.5
5 mm
scale
b
c
D
b
1
L
1
d
E
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
SOT54 variant
1
2
3
L
2
e
1
e
98-03-26
1998
Apr
02
1873
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT78
TO-220AB
D
D
1
q
P
L
12
3
L
2
(1)
b
1
e
e
b
0
5
10 mm
scale
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
DIMENSIONS (mm are the original dimensions)
A
E
A
1
c
Note
1. Terminals in this zone are not tinned.
Q
L
1
UNIT
A
1
b
1
D
1
e
P
mm
2.54
qQ
A
b
D
c
L
2
(1)
max.
3.0
3.8
3.6
15.0
13.5
3.30
2.79
3.0
2.7
2.6
2.2
0.7
0.4
15.8
15.2
0.9
0.7
1.3
1.0
4.5
4.1
1.39
1.27
6.4
5.9
10.3
9.7
L
1
E
L
97-06-11
1998
Apr
02
1874
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
DIMENSIONS (mm are the original dimensions)
SOT89
97-02-28
w
M
e
1
e
E
H
E
B
0
2
4 mm
scale
b
3
b
2
b
1
c
D
L
A
Plastic surface mounted package;
collector pad for good heat transfer; 3 leads
SOT89
12
3
UNIT
A
mm
1.6
1.4
0.48
0.35
c
0.44
0.37
D
4.6
4.4
E
2.6
2.4
H
E
4.25
3.75
e
3.0
w
0.13
e
1
1.5
L
min.
0.8
b
2
b
1
0.53
0.40
b
3
1.8
1.4
drain pad for good heat transfer; 3 leads
1998
Apr
02
1875
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(2)
(1)
eH
E
LL
p
QZ
y
w
v
Īø
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
Īø
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S
MS-012AA
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.01
0.041
0.004
0.039
0.016
0
2.5
5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
95-02-04
97-05-22
1998
Apr
02
1876
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
Q
Z
y
w
v
Īø
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT137-1
X
12
24
w
M
Īø
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
c
L
v
M
A
13
(A )
3
A
y
0.25
075E05
MS-013AD
pin 1 index
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.61
0.60
0.30
0.29
0.050
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01
0.004
0.043
0.016
0.01
e
1
0
5
10 mm
scale
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
95-01-24
97-05-22
1998
Apr
02
1877
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT186
TO-220
0
5
10 mm
scale
Plastic single-ended package; isolated heatsink mounted;
1 mounting hole; 3 lead TO-220 exposed tabs
SOT186
A
A
1
Q
c
Note
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
D
D
1
L
L
2
L
1
m
q
e
1
e
b
w
M
1
23
E
1
E
P
b
1
UNIT
D
b
1
D
1
e
q
Q
P
L
c
L
2
e
1
A
5.08
mm
4.4
4.0
A
1
2.9
2.5
b
0.9
0.7
1.5
1.3
0.55
0.38
17.0
16.4
7.9
7.5
E
10.2
9.6
5.7
5.3
E
1
2.54
14.3
13.5
10
0.4
L
1
(1)
4.8
4.0
1.4
1.2
4.4
4.0
w
3.2
3.0
m
0.9
0.5
DIMENSIONS (mm are the original dimensions)
97-06-11
1998
Apr
02
1878
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT186A
TO-220
0
5
10 mm
scale
Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220
SOT186A
A
A
1
Q
c
K
j
Notes
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
2. Both recesses are
ā
2.5
Ć
0.8 max. depth
D
D
1
L
L
2
L
1
b
1
b
2
e
1
e
b
w
M
1
23
q
E
P
T
UNIT
D
b
1
D
1
e
q
Q
P
L
c
L
2
(1)
max.
e
1
A
5.08
3
mm
4.6
4.0
A
1
2.9
2.5
b
0.9
0.7
1.1
0.9
b
2
1.4
1.2
0.7
0.4
15.8
15.2
6.5
6.3
E
10.3
9.7
2.54
14.4
13.5
T
(2)
2.5
0.4
L
1
3.30
2.79
j
2.7
2.3
K
0.6
0.4
2.6
2.3
3.0
2.6
w
3.2
3.0
DIMENSIONS (mm are the original dimensions)
97-06-11
1998
Apr
02
1879
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
1
b
p
cD
E
e
1
H
E
L
p
Qy
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.10
0.01
1.8
1.5
0.80
0.60
b
1
3.1
2.9
0.32
0.22
6.7
6.3
3.7
3.3
2.3
e
4.6
7.3
6.7
1.1
0.7
0.95
0.85
0.1
0.1
0.2
DIMENSIONS (mm are the original dimensions)
SOT223
96-11-11
97-02-28
w
M
b
p
D
b
1
e
1
e
A
A
1
L
p
Q
detail X
H
E
E
v
M
A
A
B
B
c
y
0
2
4 mm
scale
A
X
13
2
4
Plastic surface mounted package;
collector pad for good heat transfer; 4 leads
SOT223
drain pad for good heat transfer; 4 leads
1998
Apr
02
1880
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT226
low-profile
TO-220
D
D
1
L
12
3
L
2
L
1
mounting
base
b
1
e
e
Q
b
0
5
10 mm
scale
Plastic single-ended package; 3 lead low-profile TO-220
SOT226
DIMENSIONS (mm are the original dimensions)
A
E
A
1
c
Note
1. Terminals in this zone are not tinned.
UNIT
A
1
b
1
D
1
eQ
mm
2.54
L
1
2.6
2.2
3.30
2.79
15.0
13.5
10.3
9.7
1.5
1.1
11.0
10.0
0.7
0.4
1.3
1.0
0.9
0.7
1.39
1.27
4.5
4.1
Ab
D
c
3.0
L
2
(1)
max
E
L
97-06-11
1998
Apr
02
1881
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT263
5-lead TO-220
D
D
1
q
P
L
15
L
1
mounting
base
L
2
L
3
m
e
Q
b
0
5
10 mm
scale
Plastic single-ended package; heatsink mounted; 1 moumting hole; 5-lead TO-220
SOT263
DIMENSIONS (mm are the original dimensions)
A
E
A
1
c
Notes
1. Terminal dimensions are uncontrolled in this zone.
2. Positional accuracy of the terminals is controlled in this zone.
3. Terminals in this zone are not tinned.
w
M
UNIT
A
1
D
1
e
P
mm
1.7
qQ
A
b
D
c
L
2
(2)
0.5
L
3
(3)
max.
3.5
3.8
3.6
m
0.8
0.6
15.0
13.5
2.4
1.6
3.0
2.7
2.6
2.2
w
0.4
0.7
0.4
15.8
15.2
0.9
0.7
4.5
4.1
1.39
1.27
6.4
5.9
10.3
9.7
L
1
(1)
E
L
97-06-11
1998
Apr
02
1882
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT263-01
5-lead (option)
TO-220
D
D
1
q
P
L
15
L
4
mounting
base
L
5
L
3
m
e
Q
b
0
5
10 mm
scale
Plastic single-ended package; heatsink mounted; 1 mounting hole;
5-lead TO-220 lead form option
SOT263-01
UNIT
A
1
D
1
eL
P
mm
1.7
L
1
L
2
q
3.0
2.7
4.5
4.1
1.39
1.27
0.90
0.75
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
9.8
9.7
5.9
5.3
5.2
5.0
2.4
1.6
0.8
0.6
3.8
3.6
Q
1
Q
2.0
4.5
Q
2
8.2
R
0.5
w
0.4
DIMENSIONS (mm are the original dimensions)
A
b
D
c
0.5
3.5
L
3
(1)
max.
L
4
(2)
L
5
(3)
max.
E
m
A
E
A
1
c
Q
1
Q
2
Notes
1. Terminals in this zone are not tinned.
2. Positional accuracy of the terminals is controlled in this zone.
3. Terminal dimensions are uncontrolled in this zone.
L
1
L
2
R
R
w
M
97-06-11
1998
Apr
02
1883
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
1
max
b
p
cD
E
e
1
H
E
L
p
Qw
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.1
1.1
0.8
0.4
0.3
0.25
0.10
2.2
1.8
1.35
1.15
0.65
e
1.3
2.2
2.0
0.23
0.13
0.2
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT323
SC-70
w
M
b
p
D
e
1
e
A
B
A
1
L
p
Q
detail X
c
H
E
E
v
M
A
A
B
y
0
1
2 mm
scale
A
X
12
3
Plastic surface mounted package; 3 leads
SOT323
97-02-28
1998
Apr
02
1884
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZ
y
w
v
Īø
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.13
0.2
0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
94-01-14
95-02-04
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
1
8
16
9
Īø
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150AC
pin 1 index
0
2.5
5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
max.
2.0
1998
Apr
02
1885
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZ
y
w
v
Īø
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
1.25
7.9
7.6
0.9
0.7
0.8
0.4
8
0
o
o
0.13
0.1
0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT340-1
MO-150AG
93-09-08
95-02-04
X
w
M
Īø
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
11
2
24
13
0.25
y
pin 1 index
0
2.5
5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
A
max.
2.0
1998
Apr
02
1886
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT363
SC-88
wB
M
b
p
D
e
1
e
pin 1
index
A
A
1
L
p
Q
detail X
H
E
E
v
M
A
A
B
y
0
1
2 mm
scale
c
X
13
2
4
5
6
Plastic surface mounted package; 6 leads
SOT363
UNIT
A
1
max
b
p
cD
E
e
1
H
E
L
p
Qy
w
v
mm
0.1
0.30
0.20
2.2
1.8
0.25
0.10
1.35
1.15
0.65
e
1.3
2.2
2.0
0.2
0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.25
0.15
A
1.1
0.8
97-02-28
1998
Apr
02
1887
Philips Semiconductors
PowerMOS transistors
Package outlines
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
A
1
D
1
D
E
eL
p
H
D
Q
c
2.54
2.60
2.20
15.4
14.8
2.9
2.1
9.65
8.65
1.6
1.2
10.3
9.7
4.5
4.1
1.40
1.27
0.85
0.60
0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
98-04-07
0
2.5
5 mm
scale
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
e
e
E
b
D
1
H
D
D
Q
L
p
c
A
1
A
13
2
mounting
base
1998
Apr
02
1888
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT426
0
2.5
5 mm
scale
Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads
(one lead cropped)
SOT426
e
e
e
e
E
b
H
E
D
L
1
c
A
1
A
A
1
L
1
bc
D
max.
e
A
UNIT
DIMENSIONS (mm are the original dimensions)
E
11
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
2.90
2.10
H
E
15.80
14.80
10.30
9.70
1.70
98-04-07
1
3
24
5
mounting
base
1998
Apr
02
1889
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT428
98-04-07
0
10
20 mm
scale
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
E
b
2
D
1
wA
M
bc
b
1
L
1
L
13
2
D
E
1
H
E
L
2
Note
1. Measured from heatsink back to lead.
e
1
e
A
A
2
A
A
1
y
seating plane
mounting
base
A
1
(1)
D
max.
b
D
1
max.
E
max.
H
E
max.
w
y
max.
A
2
b
2
b
1
max.
c
E
1
min.
ee
1
L
1
min.
L
2
L
A
max.
UNIT
DIMENSIONS (mm are the original dimensions)
0.2
0.2
mm
2.38
2.22
0.65
0.45
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
6.22
5.98
4.81
4.45
2.285
4.57
10.4
9.6
0.5
0.7
0.5
6.73
6.47
4.0
2.95
2.55
1998
Apr
02
1890
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT429
TO-247
98-04-07
0
10
20 mm
scale
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247
SOT429
E
P
A
A
1
Ī²
w
M
b
12
3
e
e
b
1
b
2
c
Q
q
L
Y
R
D
S
L
1
(1)
Ī±
UNIT
A
1
D
b
E
e
w
S
R
q
Q
P
LY
b
2
b
1
c
L
1
(1)
DIMENSIONS (mm are the original dimensions)
A
Ī²
Ī±
mm
17
Ā°
13
Ā°
6
Ā°
4
Ā°
5.3
4.7
1.9
1.7
2.2
1.8
1.2
0.9
3.2
2.8
0.9
0.6
21
20
16
15
5.45
3.7
3.3
2.6
2.4
5.3
7.5
7.1
0.4
15.7
15.3
16
15
4.0
3.6
3.5
3.3
Note
1. Tinning of terminals are uncontrolled within zone L
1
.
1998
Apr
02
1891
Philips Semiconductors
PowerMOS transistors
Package outlines
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT457
SC-74
wB
M
b
p
D
e
pin 1
index
A
A
1
L
p
Q
detail X
H
E
E
v
M
A
A
B
y
0
1
2 mm
scale
c
X
13
2
4
5
6
Plastic surface mounted package; 6 leads
SOT457
UNIT
A
1
b
p
cD
E
H
E
L
p
Qy
w
v
mm
0.1
0.013
0.40
0.25
3.1
2.7
0.26
0.10
1.7
1.3
e
0.95
3.0
2.5
0.2
0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2
0.33
0.23
A
1.1
0.9
97-02-28
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