11-S5-24A Series-072001 DATA SHEET S524A Series (I2C-Bus) Serial EEPROM Revision 1 2 S524A Series (I C-Bus) Serial EEPROM DATA SHEET Revision 1 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. 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Box #37, Suwon 449-900 TEL: (82)-(31)-209-6530 FAX: (82)-(31)-209-6547 Home-Page URL: Http://www.samsungsemi.com Printed in the Republic of Korea Serial EEPROM Selection Guide S524A40X10/40X20/40X40 S524A40X11/40X21/40X41/60X81/60X51 S524AB0X91/B0XB1 S524AD0XD1/D0XF1 S524AE0XH1 Packaging Information Application Note Marking Information Ordering Information Serial EEPROM Selection Guide Data Sheet SERIAL EEPROM SELECTION GUIDE Product Density (Organization) Page Buffer Write Time (Max) Write Protect Endurance Operating Voltage Package S524A40X11 1K-bit (128 x 8) 16 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A40X10 1K-bit (128 x 8) 16 bytes 5 ms H/W, S/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A40X21 2K-bit (256 x 8) 16 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A40X20 2K-bit (256 x 8) 16 bytes 5 ms H/W, S/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A40X41 4K-bit (512 x 8) 16 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A40X40 4K-bit (512 x 8) 16 bytes 5 ms H/W, S/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A60X81 8K-bit (1024 x 8) 16 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524A60X51 16K-bit (2048 x 8) 16 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524AB0X91 32K-bit (4096 x 8) 32 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524AB0XB1 64K-bit (8192 x 8) 32 bytes 5 ms H/W 1M 1.8V-5.5V 8DIP/SOP/TSSOP S524AD0XD1 128K-bit (16384 x 8) 64 bytes 5 ms H/W 500K 1.8V-5.5V 8DIP/TSSOP S524AD0XF1 256K-bit (32768 x 8) 64 bytes 5 ms H/W 500K 1.8V-5.5V 8DIP/TSSOP 1-1 SERIAL EEPROM SELECTION GUIDE DATA SHEET NOTES 1-2 S524A40X10/40X20/40X40 1K/2K/4K-bit Serial EEPROM for Low Power Data Sheet OVERVIEW The S524A40X10/40X20/40X40 serial EEPROM has a 1,024/2,048/4,096-bit (128/256/512-byte) capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). Important features are a hardware-based write protection circuit for the entire memory area and software-based write protection logic for the lower 128 bytes. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. The software-based method is one-time programmable and permanent. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524A40X10/40X20/40X40 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics * Two-wire serial interface * * Automatic word address increment EEPROM Operating voltage -- 1.8 V to 5.5 V * Operating current * 1K/2K/4K-bit (128/256/512-byte) storage area -- Maximum write current: < 3 mA at 5.5 V * 16-byte page buffer -- Maximum read current: < 200 A at 5.5 V * Hardware-based write protection for the entire EEPROM (using the WP pin) -- Maximum stand-by current: < 5 A at 5.5 V * Software-based write protection for the lower 128-byte EEPROM * EEPROM programming voltage generated on chip * 1,000,000 erase/write cycles -- 100 kHz at standard mode * 100 years data retention -- 400 kHz at fast mode * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * * Operating clock frequencies Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, SOP, and TSSOP 2-1 S524A40X10/40X20/40X40 SERIAL EEPROM SDA Start/Stop Logic HV Generation Timing Control Control Logic WP SCL DATA SHEET Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 128 x 8 bits 256 x 8 bits 512 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 2-1. S524A40X10/40X20/40X40 Block Diagram 2-2 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM VCC WP SCL SDA S524A40X10/ 40X20/40X40 A0 NOTE: A1 A2 VSS The S524A40X10/40X20/40X40 is available in 8-pin DIP, SOP, and TSSOP package. Figure 2-2. Pin Assignment Diagram Table 2-1. S524A40X10/40X20/40X40 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. 1 Ground pin. - VSS - SDA I/O SCL 2 Bi-directional data pin for the I C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 k (100 kHz) and 1 k (400 kHz). 3 Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. 1 VCC - Single power supply. - NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 2-3 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET A0, A1, A2, WP Noise Filter SCL Figure 2-3. Pin Circuit Type 1 Figure 2-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Figure 2-5. Pin Circuit Type 3 2-4 Data In DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524A40X10/40X20/40X40 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the "transmitter" and any device that gets data from the bus is the "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524A40X10/40X20 (four for S524A40X40) devices can be connected to the same I2C-bus as slaves (see Figure 2-6). Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active. VCC VCC SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) Slave 2 Slave 3 Slave 8 S524A40X20 Tx/Rx A0 A1 A2 S524A40X20 Tx/Rx A0 A1 A2 S524A40X20 Tx/Rx A0 A1 A2 S524A40X20 Tx/Rx A0 A1 A2 To VCC or V SS To VCC or V SS To VCC or V SS To VCC or V SS MCU NOTE: The A0 does not affect the device address of the S524A40X40. 2 Figure 2-6. Typical Configuration (16 Kbits of Memory on the I C-Bus) 2-5 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: -- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: * Bus not busy: The SDA and the SCL lines remain High level when the bus is not active. * Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. * Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 2-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 2-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. * ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 2-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. 2-6 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 2-8. Acknowledge Response From Receiver * Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier". The identifier for the S524A40X10/40X20/40X40 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight S524A40X10/40X20 or four S524A40X40 on the bus (see Table 2-2 below). The b1 for S524A40X40 is used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bit is in effect the most significant bit of the word address. * Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed. Table 2-2. Slave Device Addressing Function Device Identifier R/W Bit Device Address b7 b6 b5 b4 b3 b2 b1(note) b0 Read 1 0 1 0 A2 A1 A0 1 Write 1 0 1 0 A2 A1 A0 0 Write-protect 0 1 1 0 A2 A1 A0 0 NOTE: The b1 for S524A40X40 corresponds to the MSB of the memory array address word. 2-7 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the S524A40X10/40X20/40X40 slave device (see Figure 2-9). Start Slave Address Word Address A C K Data A C K Stop A C K Figure 2-9. Byte Write Operation Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Then the addressed S524A40X10/40X20/40X40 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the S524A40X10/40X20/40X40. When the S524A40X10/40X20/40X40 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the S524A40X10/40X20/40X40 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the S524A40X10/40X20/40X40 begins the internal write cycle. While the internal write cycle is in progress, all S524A40X10/40X20/40X40 inputs are disabled and the S524A40X10/40X20/40X40 does not respond to additional requests from the master. 2-8 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM PAGE WRITE OPERATION The S524A40X10/40X20/40X40 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The S524A40X10/40X20/40X40 responds with an ACK each time it receives a complete byte of data (see Figure 2-10). Start Slave Address Word Address (n) A C K Data (n) A C K Data ( n + 15) A C K A C K Stop A C K Figure 2-10. Page Write Operation The S524A40X10/40X20/40X40 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the S524A40X10/40X20/40X40 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the S524A40X10/40X20/40X40 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed. 2-9 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524A40X10/40X20/40X40 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524A40X10/40X20/40X40 remains busy with the write operation, no ACK is returned. When the S524A40X10/40X20/40X40 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 2-11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 2-11. Master Polling for an ACK Signal from a Slave Device 2-10 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM SOFTWARE-BASED WRITE PROTECTION You can write-protect the lower 128 bytes of the EEPROM, locations 00H-7FH, in one operation. To do this, you simply write a value to a one-time, write-only register. Once you have applied this write protection, any write attempt to access the lower 128-byte area is ignored. In other words, the write protection is permanent. The effect of such a failed attempt is processed in the same way as an invalid I2C-bus protocol. To enable write protection, you must execute a write operation to the write protection register. To access the write protection register, you use the device address "0110". The word address and data in this write operation can be any value and the timing and wave form characteristics are identical to a normal byte write operation (see Figure 2-12). Start Word Address (Ignored) Slave Address A C K Data (Ignored) A C K Stop A C K Figure 2-12. Write Protection Operation HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524A40X10/40X20/40X40. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The S524A40X10/40X20/40X40 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. 2-11 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would access data at address "n+1". When the S524A40X10/40X20/40X40 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the S524A40X10/40X20/40X40 effectively stops the transmission (see Figure 2-13). Start Slave Address Data A C K Stop N O A C K Figure 2-13. Current Address Byte Read Operation 2-12 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the S524A40X10/40X20/40X40 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The S524A40X10/40X20/40X40 then sends an ACK and the 8-bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. 5. In response, the S524A40X10/40X20/40X40 stops transmitting data and reverts to its stand-by mode (see Figure 2-14). Start Slave Address Word Address A C K Start A C K Slave Address Data (n) A C K Stop N O A C K Figure 2-14. Random Address Byte Read Operation 2-13 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The S524A40X10/40X20/40X40 continues to output data for each ACK it receives. To stop the sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address "n" followed by the data from "n+1". The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the S524A40X10/40X20/40X40 continues to transmit data for each ACK it receives from the master (see Figure 215). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 2-15. Sequential Read Operation 2-14 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM ELECTRICAL DATA Table 2-3. Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Rating Unit Supply voltage VCC - - 0.3 to + 7.0 V Input voltage VIN - - 0.3 to + 7.0 V Output voltage VO - - 0.3 to + 7.0 V Operating temperature TA - - 40 to + 85 C Storage temperature TSTG - - 65 to + 150 C Electrostatic discharge VESD HBM 5000 V MM 500 Table 2-4. D.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit - - 0.3 VCC V 0.7 VCC - - V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC - - 10 A Output leakage current ILO VO = 0 to VCC - - 10 A Output low voltage VOL IOL = 0.15 mA, VCC = 1.8 V - - 0.2 V IOL = 2.1 mA, VCC = 2.5 V - - 0.4 ICC1 VCC = 5.5 V, 400 kHz - - 3 ICC2 VCC = 1.8 V, 100 kHz - - 1 ICC3 VCC = 5.5 V, 400 kHz - - 0.2 ICC4 VCC = 1.8 V, 100 kHz - - 60 A ICC5 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V - - 5 A ICC6 VCC = SDA = SCL = 1.8 V, all other inputs = 0 V - - 1 Supply current Write Read Stand-by current SCL, SDA, A0, A1, A2 mA 2-15 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET Table 2-4. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN 25C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin - - 10 pF Input/output capacitance CI/O 25C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin - - 10 Table 2-5. A.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) VCC = 2.5 to 5.5 V (Fast Mode) Min Max Min Max Unit External clock frequency FCLK - 0 100 0 400 kHz Clock high time tHIGH - 4 - 0.6 - s Clock low time tLOW - 4.7 - 1.3 - Rising time tR SDA, SCL - 1 - 0.3 Falling time tF SDA, SCL - 0.3 - 0.3 Start condition hold time tHD:STA - 4 - 0.6 - Start condition setup time tSU:STA - 4.7 - 0.6 - Data input hold time tHD:DAT - 0 - 0 - Data input setup time tSU:DAT - 0.25 - 0.1 - Stop condition setup time tSU:STO - 4 - 0.6 - Bus free time tBUF Before new transmission 4.7 - 1.3 - Data output valid from clock low (note) tAA - 0.3 3.5 - 0.9 Noise spike width tSP - - 100 - 50 ns Write cycle time tWR - - 5 - 5 ms NOTES: 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the S524A40X10/40X20/40X40 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. 2-16 DATA SHEET S524A40X10/40X20/40X40 SERIAL EEPROM tF tHIGH tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out Figure 2-16. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ ~ SDA 8th Bit ACK ~ WORDn tWR Stop Condition Start Condition Figure 2-17. Write Cycle Timing Diagram 2-17 S524A40X10/40X20/40X40 SERIAL EEPROM DATA SHEET NOTES 2-18 S524A40X11/40X21/ 40X41/60X81/60X51 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power Data Sheet OVERVIEW The S524A40X11/40X21/40X41/60X81/60X51 serial EEPROM has a 1,024/2,048/4,096/8,192/16,384-bit capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524A40X11/40X21/40X41/60X81/60X51 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics * Two-wire serial interface * * Automatic word address increment EEPROM Operating voltage -- 1.8 V to 5.5 V * Operating current * 1K/2K/4K/8K/16K-bit (128/256/512/1,024/2,048-byte) storage area -- Maximum write current: < 3 mA at 5.5 V * 16-byte page buffer * -- Maximum stand-by current: < 5 A at 5.5 V Hardware-based write protection for the entire EEPROM (using the WP pin) * EEPROM programming voltage generated on chip * 1,000,000 erase/write cycles * 100 years data retention -- Maximum read current: < 200 A at 5.5 V * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 100 kHz at standard mode -- 400 kHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, SOP, and TSSOP 3-1 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM SDA Start/Stop Logic HV Generation Timing Control Control Logic WP SCL DATA SHEET Slave Address Comparator Word Address Pointer Row decoder A0 EEPROM Cell Array 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits 2048 x 8 bits A1 A2 Column Decoder Data Register DOUT and ACK Figure 3-1. S524A40X11/40X21/40X41/60X81/60X51 Block Diagram 3-2 DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM VCC WP SCL SDA S524A40X11/40X21/ 40X41/60X81/60X51 A0 NOTE: A1 A2 VSS The S524A40X11/40X21/40X41/60X81/60X51 is available in 8-pin DIP, SOP, and TSSOP package. Figure 3-2. Pin Assignment Diagram Table 3-1. S524A40X11/40X21/40X41/60X81/60X51 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. 1 Ground pin. - Bi-directional data pin for the I2C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 k (100 kHz) and 1 k (400 kHz). 3 VSS - SDA I/O SCL Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. 1 VCC - Single power supply. - NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 3-3 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM A0, A1, A2, WP DATA SHEET Noise Filter SCL Figure 3-3. Pin Circuit Type 1 Figure 3-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Figure 3-5. Pin Circuit Type 3 3-4 Data In DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524A40X11/40X21/40X41/60X81/60X51 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the "transmitter" and any device that gets data from the bus is the "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524A40X11/40X21 (four S524A40X41, two for S524A60X81, one for S524A60X51) devices can be connected to the same I2C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active. VCC VCC SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) Slave 2 Slave 3 Slave 8 S524A40X21 Tx/Rx A0 A1 A2 S524A40X21 Tx/Rx A0 A1 A2 S524A40X21 Tx/Rx A0 A1 A2 S524A40X21 Tx/Rx A0 A1 A2 To VCC or V SS To VCC or V SS To VCC or V SS To VCC or V SS MCU NOTES: 1. The A0 does not affect the device address of the S524A40X41. 2. The A0, A1 do not affect the device address of the S524A60X81. 3. The A0, A1, and A2 do not affect the device address of the S524A60X51. Figure 3-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus) 3-5 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: -- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: * Bus not busy: The SDA and the SCL lines remain High level when the bus is not active. * Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. * Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 3-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 3-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. * ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 3-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. 3-6 DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 3-8. Acknowledge Response From Receiver * Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier". The identifier for the S524A40X11/40X21/40X41/60X81/60X51 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight S524A40X11/40X21 or four S524A40X41 or two S524A60X81 or one S524A60X51 on the bus (see Table 3-2 below). The b1 for S524A40X41 or the b1, b2 for S524A60X81 or the b1, b2, b3 for S524A60X51 are used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in effect the most significant bits of the word address. * Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed. Table 3-2. Slave Device Addressing Device Device Identifier R/W Bit Device Address b7 b6 b5 b4 b3 b2 b1 b0 S524A40X11/40X21 1 0 1 0 A2 A1 A0 R/W S524A40X41 1 0 1 0 A2 A1 B0 R/W S524A60X81 1 0 1 0 A2 B1 B0 R/W S524A60X51 1 0 1 0 B2 B1 B0 R/W NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word. 3-7 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the S524A40X11/40X21/40X41/60X81/60X51 slave device (see Figure 3-9). Start Slave Address Word Address A C K Data A C K Stop A C K Figure 3-9. Byte Write Operation Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Then the addressed S524A40X11/40X21/40X41/60X81/60X51 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the S524A40X11/40X21/40X41/60X81/60X51. When the S524A40X11/40X21/40X41/60X81/60X51 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the S524A40X11/40X21/40X41/60X81/60X51 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the S524A40X11/40X21/40X41/60X81/60X51 begins the internal write cycle. While the internal write cycle is in progress, all S524A40X11/40X21/40X41/60X81/60X51 inputs are disabled and the S524A40X11/40X21/40X41/60X81/60X51 does not respond to additional requests from the master. 3-8 DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM PAGE WRITE OPERATION The S524A40X11/40X21/40X41/60X81/60X51 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The S524A40X11/40X21/40X41/60X81/60X51 responds with an ACK each time it receives a complete byte of data (see Figure 3-10). Start Slave Address Word Address (n) A C K Data (n) A C K Data ( n + 15) A C K A C K Stop A C K Figure 3-10. Page Write Operation The S524A40X11/40X21/40X41/60X81/60X51 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the S524A40X11/40X21/40X41/60X81/60X51 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the S524A40X11/40X21/40X41/60X81/60X51 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed. 3-9 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524A40X11/40X21/40X41/60X81/60X51 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524A40X11/40X21/40X41/60X81/60X51 remains busy with the write operation, no ACK is returned. When the S524A40X11/40X21/40X41/60X81/60X51 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 3-11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 3-11. Master Polling for an ACK Signal from a Slave Device 3-10 DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524A40X11/40X21/40X41/60X81/60X51. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The S524A40X11/40X21/40X41/60X81/60X51 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would access data at address "n+1". When the S524A40X11/40X21/40X41/60X81/60X51 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the S524A40X11/40X21/40X41/60X81/60X51 effectively stops the transmission (see Figure 3-12). Start Slave Address Data A C K Stop N O A C K Figure 3-12. Current Address Byte Read Operation 3-11 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM DATA SHEET RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the S524A40X11/40X21/40X41/60X81/60X51 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The S524A40X11/40X21/40X41/60X81/60X51 then sends an ACK and the 8-bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. 5. In response, the S524A40X11/40X21/40X41/60X81/60X51 stops transmitting data and reverts to its stand-by mode (see Figure 3-13). Start Slave Address Word Address A C K Start A C K Slave Address Data (n) A C K Stop N O A C K Figure 3-13. Random Address Byte Read Operation 3-12 DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The S524A40X11/40X21/40X41/60X81/60X51 continues to output data for each ACK it receives. To stop the sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address "n" followed by the data from "n+1". The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the S524A40X11/40X21/40X41/60X81/60X51 continues to transmit data for each ACK it receives from the master (see Figure 3-14). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 3-14. Sequential Read Operation 3-13 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 3-3. Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Rating Unit Supply voltage VCC - - 0.3 to + 7.0 V Input voltage VIN - - 0.3 to + 7.0 V Output voltage VO - - 0.3 to + 7.0 V Operating temperature TA - - 40 to + 85 C Storage temperature TSTG - - 65 to + 150 C Electrostatic discharge VESD HBM 5000 V MM 500 Table 3-4. D.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit - - 0.3 VCC V 0.7 VCC - - V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC - - 10 A Output leakage current ILO VO = 0 to VCC - - 10 A Output low voltage VOL IOL = 0.15 mA, VCC = 1.8 V - - 0.2 V IOL = 2.1 mA, VCC = 2.5 V - - 0.4 ICC1 VCC = 5.5 V, 400 kHz - - 3 ICC2 VCC = 1.8 V, 100 kHz - - 1 ICC3 VCC = 5.5 V, 400 kHz - - 0.2 ICC4 VCC = 1.8 V, 100 kHz - - 60 A ICC5 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V - - 5 A ICC6 VCC = SDA = SCL = 1.8 V, all other inputs = 0 V - - 1 Supply current Write Read Stand-by current 3-14 SCL, SDA, A0, A1, A2 mA DATA SHEET S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM Table 3-4. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit pF Input capacitance CIN 25 C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin - - 10 Input/output capacitance CI/O 25 C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin - - 10 Table 3-5. A.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) VCC = 2.5 to 5.5 V (Fast Mode) Min Max Min Max Unit External clock frequency FCLK - 0 100 0 400 kHz Clock high time tHIGH - 4 - 0.6 - s Clock low time tLOW - 4.7 - 1.3 - Rising time tR SDA, SCL - 1 - 0.3 Falling time tF SDA, SCL - 0.3 - 0.3 Start condition hold time tHD:STA - 4 - 0.6 - Start condition setup time tSU:STA - 4.7 - 0.6 - Data input hold time tHD:DAT - 0 - 0 - Data input setup time tSU:DAT - 0.25 - 0.1 - Stop condition setup time tSU:STO - 4 - 0.6 - Bus free time tBUF Before new transmission 4.7 - 1.3 - Data output valid from clock low (note) tAA - 0.3 3.5 - 0.9 Noise spike width tSP - - 100 - 50 ns Write cycle time tWR - - 5 - 5 ms NOTES: 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the S524A40X11/40X21/40X41/60X81/60X51 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. 3-15 S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM tF tHIGH DATA SHEET tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out Figure 3-15. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ ~ ~ SDA 8th Bit ACK ~ ~ WORDn tWR Stop Condition Figure 3-16. Write Cycle Timing Diagram 3-16 Start Condition S524AB0X91/B0XB1 32K/64K-bit Serial EEPROM for Low Power Data Sheet OVERVIEW The S524AB0X91/B0XB1 serial EEPROM has a 32K/64K-bit (4,096/8,192 bytes) capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 32 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524AB0X91/B0XB1 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics * Two-wire serial interface * * Automatic word address increment EEPROM Operating voltage -- 1.8 V to 5.5 V * Operating current * 32K/64K-bit (4,096/8,192 bytes) storage area -- Maximum write current: < 3 mA at 5.5 V * 32-byte page buffer -- Maximum read current: < 400 A at 5.5 V * Hardware-based write protection for the entire EEPROM (using the WP pin) -- Maximum stand-by current: < 5 A at 5.5 V * EEPROM programming voltage generated on chip * 1,000,000 erase/write cycles * 100 years data retention * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 100 kHz at standard mode -- 400 kHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, SOP, and TSSOP 4-1 S524AB0X91/B0XB1 SERIAL EEPROM SDA Start/Stop Logic HV Generation Timing Control Control Logic WP SCL DATA SHEET Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 4,096 x 8 bits 8,192 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 4-1. S524AB0X91/B0XB1 Block Diagram 4-2 DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM VCC WP SCL SDA S524AB0X91/B0XB1 A0 NOTE: A1 A2 VSS The S524AB0X91/B0XB1 is available in 8-pin DIP, SOP, and TSSOP package. Figure 4-2. Pin Assignment Diagram Table 4-1. S524AB0X91/B0XB1 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. 1 VSS - Ground pin. - SDA I/O SCL 2 Bi-directional data pin for the I C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VDD. Typical values for this pull-up resistor are 4.7 K (100 KHz) and 1 K (400 KHz). 3 Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. 1 VCC - Single power supply. - NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 4-3 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET A0, A1, A2, WP Noise Filter SCL Figure 4-3. Pin Circuit Type 1 Figure 4-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Figure 4-5. Pin Circuit Type 3 4-4 Data In DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524AB0X91/B0XB1 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a "transmitter" and any device that gets data from the bus is a "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AB0X91/B0XB1 devices can be connected to the same I2C-bus as slaves (see Figure 4-6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. VCC VCC SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) Slave 2 Slave 3 Slave 8 S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 S524AB0X91/ B0XB1 Tx/Rx A0 A1 A2 To VCC or V SS To VCC or V SS To VCC or V SS To VCC or V SS MCU Figure 4-6. Typical Configuration 4-5 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: -- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: * Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active. * Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in High level. All bus commands must be preceded by a start condition. * Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 4-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 4-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. * ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 4-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected but no stop condition, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. 4-6 DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 4-8. Acknowledge Response From Receiver * Slave Address: After the master initiates a start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier." The identifier for the S524AB0X91/B0XB1 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1, and A2 pins. Using this addressing scheme, you can cascade up to eight S524AB0X91/B0XB1s on the bus (see Figure 4-9 below). * Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed. Device Identifier Slave Address 1 0 1 Device Select 0 A2 A1 A0 R/W A9 A8 A1 A0 First (High) Address First Word Address X X X(2) A12(1) A11 A10 Second (Low) Address Second Word Address A7 A6 A5 A4 A3 A2 NOTES: 1. The A12 is "don't care" for the S524AB0X91. 2. X = Don't care. Figure 4-9. Device Address 4-7 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION A write operation requires 2-byte word addresses, the first (high) word address and the second (low) word address. In a byte write operation, the master transmits the slave address, the first word address, the second word address, and one data byte to the S524AB0X91/B0XB1 slave device (see Figure 4-10). Start Slave Address First Word Address A C K Second t Word Address A C K A C K Data Stop A C K Figure 4-10. Byte Write Operation Following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Upon the receipt of the slave address, the S524AB0X91/B0XB1 responds with an ACK. And the master transmits the first word address, the second word address, and one byte data to be written into the addressed memory location. The master terminates the transfer by generating a stop condition, at which time the S524AB0X91/B0XB1 begins the internal write cycle. While the internal write cycle is in progress, all S524AB0X91/B0XB1 inputs are disabled and the S524AB0X91/B0XB1 does not respond to any additional request from the master. 4-8 DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM PAGE WRITE OPERATION The S524AB0X91/B0XB1 can also perform 32-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 31 additional bytes. The S524AB0X91/B0XB1 responds with an ACK each time it receives a complete byte of data (see Figure 4-11). Start Slave Address First Word Address A C K Second Word Address A C K Data Byte N (N 31) Data Byte 0 A C K A C K A C K Stop A C K Figure 4-11. Page Write Operation The S524AB0X91/B0XB1 automatically increments the word address pointer each time it receives a complete data byte. When one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. If the master transmits more than 32 bytes before it generates a stop condition to end the page write operation, the S524AB0X91/B0XB1 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 32 bytes and generates a stop condition, the S524AB0X91/B0XB1 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed. 4-9 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524AB0X91/B0XB1 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle is completed. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524AB0X91/B0XB1 remains busy with the write operation, no ACK is returned. When the S524AB0X91/B0XB1 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 4-12). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 4-12. Master Polling for an ACK Signal from a Slave Device 4-10 DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524AB0X91/B0XB1. This write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to it is ignored. The S524AB0X91/B0XB1 will acknowledge slave and word addresses, but it will not generate an acknowledge after receiving the first byte of data. In this situation, the write cycle will not be started when a stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to protect data from being overwritten. Whenever the write function is disabled, a slave address and word addresses are acknowledged on the bus, but data bytes are not acknowledged. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would be to access data at address "n+1". When the S524AB0X91/B0XB1 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. In a current address byte read operation, the master does not acknowledge the data, and it generates a stop condition, forcing the S524AB0X91/B0XB1 to stop the transmission (see Figure 4-13). Start Slave Address Data A C K Stop N O A C K Figure 4-13. Current Address Byte Read Operation 4-11 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a start condition, the slave address, and the word address (the first and the second addresses) to be read. (This step sets the internal word address pointer of the S524AB0X91/B0XB1 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The S524AB0X91/B0XB1 then sends an ACK and the 8-bit data stored at the pointed address. 4. At this point, the master does not acknowledge the transmission, generating a stop condition. 5. The S524AB0X91/B0XB1 stops transmitting data and reverts to stand-by mode (see Figure 4-14). Start Slave Address First Word Address A C K Second Word Address A C K Start Slave Address A C K Data A C K Stop N O A C K Figure 4-14. Random Address Byte Read Operation 4-12 DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. The first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. If the master responds with an ACK, the S524AB0X91/B0XB1 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the slave stops transmission, ending the sequential read operation. Using this method, data is output sequentially from address "n" followed by address "n+1". The word address pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the S524AB0X91/B0XB1 continues to transmit data for each ACK it receives from the master (see Figure 4-15). Start Slave Address Data (n) Data (n + x) Stop ~ ~ A C K A C K A C K N O A C K Figure 4-15. Sequential Read Operation 4-13 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 4-2. Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Rating Unit Supply voltage VCC - - 0.3 to + 7.0 V Input voltage VIN - - 0.3 to + 7.0 V Output voltage VO - - 0.3 to + 7.0 V Operating temperature TA - - 40 to + 85 C Storage temperature TSTG - - 65 to + 150 C Electrostatic discharge VESD HBM 5000 V MM 500 Table 4-3. D.C. Electrical Characteristics (TA = - 25C to + 70C (Commercial), - 40C to + 85C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit - - 0.3 VCC V 0.7 VCC - - V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC - - 10 A Output leakage current ILO VO = 0 to VCC - - 10 A Output low voltage VOL IOL = 0.15 mA, VCC = 1.8 V - - 0.2 V IOL = 2.1 mA, VCC = 2.5 V - - 0.4 ICC1 VCC = 5.5 V, 400 kHz - - 3 ICC2 VCC = 1.8 V, 100 kHz - - 1 ICC3 VCC = 5.5 V, 400 kHz - - 0.4 ICC4 VCC = 1.8 V, 100 kHz - - 60 A ICC5 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V - - 5 A ICC6 VCC = SDA = SCL = 1.8 V, all other inputs = 0 V - - 1 Supply current Write Read Stand-by current 4-14 SCL, SDA, A0, A1, A2 mA DATA SHEET S524AB0X91/B0XB1 SERIAL EEPROM Table 4-3. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 70C (Commercial), - 40C to + 85C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN 25C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin - - 10 pF Input/Output capacitance CI/O 25C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin - - 10 Table 4-4. A.C. Electrical Characteristics (TA = - 25C to + 70C (Commercial), - 40C to + 85C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) Min Max (1) VCC = 2.5 to 5.5 V (Fast Mode) Unit Min Max 0 400 (1) kHz Fclk - 0 100 Clock High time tHIGH - 4 - 0.6 - s Clock Low time tLOW - 4.7 - 1.3 - s External clock frequency Rising time tR SDA, SCL - 1 - 0.3 s Falling time tF SDA, SCL - 0.3 - 0.3 s Start condition hold time tHD:STA - 4 - 0.6 - s Start condition setup time tSU:STA - 4.7 - 0.6 - s Data input hold time tHD:DAT - 0 - 0 - s Data input setup time tSU:DAT - 0.25 - 0.1 - s Stop condition setup time tSU:STO - 4 - 0.6 - s Bus free time tBUF Before new transmission 4.7 - 1.3 - s Data output valid from clock low (2) tAA - 0.3 3.5 - 0.9 s Noise spike width tSP - - 100 - 50 ns Write cycle time tWR - - 5 - 5 ms NOTES: 1. 2. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. When acting as a transmitter, the S524AB0X91/B0XB1 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. 4-15 S524AB0X91/B0XB1 SERIAL EEPROM DATA SHEET tF tHIGH tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out Figure 4-16. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ ~ ~ SDA 8th Bit ACK ~ ~ WORDn tWR Stop Condition Figure 4-17. Write Cycle Timing Diagram 4-16 Start Condition S524AD0XD1/D0XF1 128K/256K-bit Serial EEPROM for Low Power Data Sheet OVERVIEW The S524AD0XD1/D0XF1 serial EEPROM has a 128K/256K-bit (16,384/32,768 bytes) capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 64 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524AD0XD1/D0XF1 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics * Two-wire serial interface * * Automatic word address increment EEPROM Operating voltage -- 1.8 V to 5.5 V * Operating current * 128K/256K-bit (16,384/32,768 bytes) storage area -- Maximum write current: < 3 mA at 5.5 V * 64-byte page buffer * -- Maximum stand-by current: < 5 A at 5.5 V Hardware-based write protection for the entire EEPROM (using the WP pin) * EEPROM programming voltage generated on chip * 500,000 erase/write cycles * 50 years data retention -- Maximum read current: < 400 A at 5.5 V * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 400 kHz at standard mode -- 1 MHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, and TSSOP 5-1 S524AD0XD1/D0XF1 SERIAL EEPROM SDA Start/Stop Logic HV Generation Timing Control Control Logic WP SCL DATA SHEET Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 16,384 x 8 bits 32,768 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 5-1. S524AD0XD1/D0XF1 Block Diagram 5-2 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM VCC WP SCL SDA S524AD0XD1/D0XF1 A0 NOTE: A1 A2 VSS The S524AD0XD1/D0XF1 is available in 8-pin DIP, and TSSOP package. Figure 5-2. Pin Assignment Diagram Table 5-1. S524AD0XD1/D0XF1 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. 1 VSS - Ground pin. - SDA I/O Bi-directional data pin for the I2C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VDD. Typical values for this pull-up resistor are 4.7 K (100 KHz) and 1 K (400 KHz). 3 SCL Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. 1 VCC - Single power supply. - NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 5-3 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET A0, A1, A2, WP Noise Filter SCL Figure 5-3. Pin Circuit Type 1 Figure 5-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Figure 5-5. Pin Circuit Type 3 5-4 Data In DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524AD0XD1/D0XF1 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a "transmitter" and any device that gets data from the bus is a "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AD0XD1/D0XF1 devices can be connected to the same I2C-bus as slaves (see Figure 5-6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. VCC VCC SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) Slave 2 Slave 3 Slave 8 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 To VCC or V SS To VCC or V SS To VCC or V SS To VCC or V SS MCU Figure 5-6. Typical Configuration 5-5 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: -- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: * Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active. * Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in High level. All bus commands must be preceded by a start condition. * Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 5-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 5-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. * ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected but no stop condition, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. 5-6 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 5-8. Acknowledge Response from Receiver * Slave Address: After the master initiates a start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier." The identifier for the S524AD0XD1/D0XF1 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1, and A2 pins. Using this addressing scheme, you can cascade up to eight S524AD0XD1/D0XF1s on the bus (see Figure 5-9 below). * Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed. Device Identifier Slave Address 1 0 1 Device Select 0 A2 A1 A0 R/W A10 A9 A8 A1 A0 First (High) Address First Word Address X(2) A14(1) A13 A12 A11 Second (Low) Address Second Word Address A7 A6 A5 A4 A3 A2 NOTES: 1. The A14 is "don't care" for the S524AD0XD1. 2. X = Don't care Figure 5-9. Device Address 5-7 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION A write operation requires 2-byte word addresses, the first (high) word address and the second (low) word address. In a byte write operation, the master transmits the slave address, the first word address, the second word address, and one data byte to the S524AD0XD1/D0XF1 slave device (see Figure 5-10). Start Slave Address First Word Address A C K Second Word Address A C K Data A C K Stop A C K Figure 5-10. Byte Write Operation Following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Upon the receipt of the slave address, the S524AD0XD1/D0XF1 responds with an ACK. And the master transmits the first word address, the second word address, and one byte data to be written into the addressed memory location. The master terminates the transfer by generating a stop condition, at which time the S524AD0XD1/D0XF1 begins the internal write cycle. While the internal write cycle is in progress, all S524AD0XD1/D0XF1 inputs are disabled and the S524AD0XD1/D0XF1 does not respond to any additional request from the master. 5-8 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM PAGE WRITE OPERATION The S524AD0XD1/D0XF1 can also perform 64-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 63 additional bytes. The S524AD0XD1/D0XF1 responds with an ACK each time it receives a complete byte of data (see Figure 5-11). Start Slave Address First Word Address A C K Second Word Address A C K Data Byte N (N 63) Data Byte 0 A C K A C K A C K Stop A C K Figure 5-11. Page Write Operation The S524AD0XD1/D0XF1 automatically increments the word address pointer each time it receives a complete data byte. When one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. If the master transmits more than 64 bytes before it generates a stop condition to end the page write operation, the S524AD0XD1/D0XF1 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 64 bytes and generates a stop condition, the S524AD0XD1/D0XF1 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed. 5-9 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524AD0XD1/D0XF1 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle is completed. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524AD0XD1/D0XF1 remains busy with the write operation, no ACK is returned. When the S524AD0XD1/D0XF1 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 5-12). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 5-12. Master Polling for an ACK Signal from a Slave Device 5-10 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524AD0XD1/D0XF1. This write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to it is ignored. The S524AD0XD1/D0XF1 will acknowledge slave address, word address, and data bytes. But the write cycle will not be started when a stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to protect data from being overwritten. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would be to access data at address "n+1". When the S524AD0XD1/D0XF1 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. In a current address byte read operation, the master does not acknowledge the data, and it generates a stop condition, forcing the S524AD0XD1/D0XF1 to stop the transmission (see Figure 5-13). Start Slave Address Data A C K Stop N O A C K Figure 5-13. Current Address Byte Read Operation 5-11 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a start condition, the slave address, and the word address (the first and the second addresses) to be read. (This step sets the internal word address pointer of the S524AD0XD1/D0XF1 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The S524AD0XD1/D0XF1 then sends an ACK and the 8-bit data stored at the pointed address. 4. At this point, the master does not acknowledge the transmission, generating a stop condition. 5. The S524AD0XD1/D0XF1 stops transmitting data and reverts to stand-by mode (see Figure 5-14). Start Slave Address First Word Address A C K Second Word Address Start A C K Slave Address A C K Data A C K Stop N O A C K Figure 5-14. Random Address Byte Read Operation 5-12 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. The first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. If the master responds with an ACK, the S524AD0XD1/D0XF1 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the slave stops transmission, ending the sequential read operation. Using this method, data is output sequentially from address "n" followed by address "n+1". The word address pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the S524AD0XD1/D0XF1 continues to transmit data for each ACK it receives from the master (see Figure 5-15). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 5-15. Sequential Read Operation 5-13 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 5-2. Absolute Maximum Ratings (TA = 25 C) Parameter Symbol Conditions Rating Unit Supply voltage VCC - - 0.3 to + 7.0 V Input voltage VIN - - 0.3 to + 7.0 V Output voltage VO - - 0.3 to + 7.0 V Operating temperature TA - - 40 to + 85 C Storage temperature TSTG - - 65 to + 150 C Electrostatic discharge VESD HBM 5000 V MM 500 Table 5-3. D.C. Electrical Characteristics (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit - - 0.3 VCC V 0.7 VCC - - V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC - - 10 A Output leakage current ILO VO = 0 to VCC - - 10 A Output Low voltage VOL IOL = 0.15 mA, VCC = 1.8 V - - 0.2 V SCL, SDA, A0, A1, A2 0.4 IOL = 2.1 mA, VCC = 2.5 V Supply current Write Read Stand-by current 5-14 ICC1 VCC = 5.5 V, 400 kHz - - 3 ICC2 VCC = 1.8 V, 100 kHz - - 1 ICC3 VCC = 5.5 V, 400 kHz - - 0.4 ICC4 VCC = 1.8 V, 100 kHz - - 60 A ICC5 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V - - 5 A ICC6 VCC = SDA = SCL = 1.8 V, all other inputs = 0 V - - 1 mA DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM Table 5-3. D.C. Electrical Characteristics (Continued) (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit pF Input capacitance CIN 25 C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin - - 10 Input/Output capacitance CI/O 25 C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin - - 10 Table 5-4. A.C. Electrical Characteristics (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) VCC = 2.5 to 5.5 V (Fast Mode) Min Max Min Max Unit Fclk - 0 400 0 1000 kHz Clock High time tHIGH - 0.6 - 0.5 - s Clock Low time tLOW - 1.3 - 0.5 - s External clock frequency Rising time tR SDA, SCL - 0.3 - 0.3 s Falling time tF SDA, SCL - 0.3 - 0.1 s Start condition hold time tHD:STA - 0.6 - 0.25 - s Start condition setup time tSU:STA - 0.6 - 0.25 - s Data input hold time tHD:DAT - 0 - 0 - s Data input setup time tSU:DAT - 0.1 - 0.1 - s WP hold time tHD:WP - 1.3 - 1.3 - s WP setup time tSU:WP - 0.6 - 0.6 - s Stop condition setup time tSU:STO - 0.6 - 0.25 - s Bus free time tBUF Before new transmission 1.3 - 0.5 - s Data output valid from clock low tAA - 0.1 0.9 0.05 0.55 s Noise spike width tSP - - 50 - 50 ns Write cycle time tWR - - 5 - 5 ms NOTES: 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the S524AD0XD1/D0XF1 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. 5-15 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET tF tHIGH tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out tSU:WP (Protected) WP (Unprotected) Figure 5-16. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ SDA 8th Bit ACK ~ ~ WORDn tWR Stop Condition Figure 5-17. Write Cycle Timing Diagram 5-16 Start Condition tHD:WP S524AE0XH1 512K-bit Serial EEPROM for Low Power Preliminary Data Sheet OVERVIEW The S524E0XH1 serial EEPROM has a 512K-bit (65,536 bytes) capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 128 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524E0XH1 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics * Two-wire serial interface * * Automatic word address increment EEPROM Operating voltage -- 1.8 V to 5.5 V * Operating current * 512K-bit (65,536 bytes) storage area -- Maximum write current: < 3 mA at 5.5 V * 128-byte page buffer -- Maximum read current: < 400 A at 5.5 V * Hardware-based write protection for the entire EEPROM (using the WP pin) -- Maximum stand-by current: < 5 A at 5.5 V * EEPROM programming voltage generated on chip * 500,000 erase/write cycles * 50 years data retention * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 400 kHz at standard mode -- 1 MHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, and SOP 6-1 S524AE0XH1 SERIAL EEPROM (Preliminary Spec) DATA SHEET NOTES 6-2 Packaging Information Data Sheet #5 0.2 5 8-DIP-300 +0 - 0 .10 .05 0-15 7.62 6.40 0.20 #8 2.54 (0.79) 0.46 0.10 5.08 MAX 9.20 0.20 3.30 0.30 9.60 MAX 3.40 0.20 #4 0.33 MIN #1 1.52 0.10 NOTE: Dimensions are in millimeters. Figure 7-1. 8-DIP-300 Package Dimensions 7-1 PACKAGING INFORMATION DATA SHEET 0-8 #4 0.15 5.13 MAX 4.92 0.20 + 0.10 - 0.05 1.80 MAX #1 1.27 (0.56) 0.41 0.10 NOTE: 0.1-0.25 MIN 0.10 MAX Dimensions are in millimeters. Figure 7-2. 8-SOP-225 Package Dimensions 7-2 0.50 0.20 8-SOP-225 5.72 3.95 0.20 #5 1.55 0.20 6.00 0.30 #8 DATA SHEET PACKAGING INFORMATION 0-8 #1 0.125 - 0.05 0.60 + 0.15 - 0.10 8-TSSOP-SG 4.40 0.10 #5 + 0.10 1.20 MAX #4 3.10 MAX 0.15 6.40 0.15 #8 0.10 MAX 0.65 0.25 + 0.05 - 0.06 NOTES: 1. Dimensions are in millimeters. 2. Package dimensions conform to JEDEC MO-153-AA. Figure 7-3. 8-TSSOP Package Dimensions 7-3 PACKAGING INFORMATION DATA SHEET NOTES 7-4 Interfacing S524A Series Serial EEPROM to the S3C8095/S3C72F5 Microcontroller Application Note OVERVIEW This application note describes an interface between the S524A40X21 serial EEPROM and Samsung S3C8095/S3C72F5 microcontroller. The S524A series support the standard I2CTM-bus serial data transmission protocol. S3C8095 is a 8-bit general purpose microcontroller, and S3C72F5 is a 4-bit general purpose microcontroller. A typical circuit configuration between S3C8095/S3C72F5 and S524A40X21 is shown in Figure 8-1 and 8-2. As shown below, using the address inputs (A0, A1, A2), up to eight S524A40X21s can be connected to the same bus. The limited number of S524A series products (1 to 16 K-bit) which can be connected is shown in Table 8-1. The interface to the S3C8095/S3C72F5 uses there 2 I/O port lines. One of the lines is used to generate the serial clock (SCL), and the other is used as a bidirectional data line (SDA). It is recommended that an external pull-up resistor is configured to the SCL, SDL line. The S3C8095/S3C72F5 operate as a master which initiates a data transfer by generating the start condition on the bus, and a slave device S524A40X21 responds to the command issued by a master. The demonstration program which follows shows how the S524A40X21 serial EEPROM can be interfaced to the S3C8095/S3C72F5 microcontroller. Table 8-1. S524A Series (1 to 16K-bit) Device EEPROM Size Max Device Per Bus Device Address Used S524A40X10/40X11 1K-bit 8 A0, A1, A2 S524A40X20/40X21 2K-bit 8 A0, A1, A2 S524A40X40/40X41 4K-bit 4 A1, A2 S524A60X81 8K-bit 2 A2 S524A60X51 16K-bit 1 - 8-1 SERIAL EEPROM APPLICATION NOTE VCC 10 K 32 P1.7 P1.6 1 10 K 24 23 47 K Slave 1 RESET 0.1 20P 3 8 MHz 2 XOUT Slave 8 A0 SCL A0 SCL A1 SDL A1 SDL A2 A2 XIN 20P S3C8095 (8-bit MCU) S524A40X21 S524A40X21 Figure 8-1. Typical Circuit Configuration 1 VCC 10 K 15 P0.0 P0.1 16 10 K 11 12 47 K 22 0.1 20P 5 MHz 17 18 RESET XOUT Slave 1 Slave 8 A0 SCL A0 SCL A1 SDL A1 SDL A2 A2 XIN 20P S3C72F5 (4-bit MCU) S524A40X21 Figure 8-2. Typical Circuit Configuration 2 8-2 S524A40X21 APPLICATION NOTE SERIAL EEPROM ;****************************************************************************************************************************** ;This program demonstrates how the S524A40X21 serial EEPROM can be interfaced to the S3C8095 ;microcontroller. This software includes random address byte read and byte write operation. ;If you use the 8 MHz crystal in Figure 8-1, SCL frequency will be approximately 50 kHz. ;****************************************************************************************************************************** ; ; ; R14 = Word-address R15 = Write-data to the EEPROM ReadData = Read-data from the EEPROM ;*************************************************************************** ; Equation Table ;*************************************************************************** SDA SCL ReadData EQU EQU EQU 7H 6H 40H ; SDA port (P1.7) ; SCL port (P1.6) ;*************************************************************************** ;**************** Random Address Byte Read ****************** ; Start Slave Addr.(A0) Word Addr. Start #A1h Data ;*************************************************************************** Read1Byte: PUSH PUSH PUSH CALL R0 R1 R2 IICbus_Start ; IIC bus protocol start LD R0,#0A0h ; Slave address (A0) ; CLR LD RLC JP RD_Data_0 AND CALL RD_Count8bit DJNZ AND OR NOP NOP NOP TM JP AND OR RD_TxStart RD_DataShift ; R2 R1,#8 R0 C, RD_Data_1 P1,#0FFh-(01<<SDA) IIC_Clock_1Bit R1,RD_DataShift P1CONH,#00111111B P1,#01<<SCL P1,#01<<SDA NZ,CommuniFail P1,#0FFh-(01<<SCL) P1CONH,#01000000B ; ; ; ; 1byte (8bit) count Rotate left Data ( = R0) Bit value check(0 or 1) Data "0" transfer ; SDA (P1.7) = Input Mode ; Acknowledge clock ; Ack in? ; SDA (P1.7) = Output Mode (next page continued) 8-3 SERIAL EEPROM APPLICATION NOTE CP JR CP JR R2,#02 UGE,RxData R2,#01 UGE,ReStart ; TxCount = R2 LD INC JR R0,R14 R2 RD_TxStart ; TxCount++ ; TxCount++ OR NOP NOP NOP AND NOP NOP NOP NOP AND P1,#11000000B ; P1.7/P1.6 High (SDA,SCL) P1,#0FFh-(01<<SDA) ; IIC Start Condition LD INC JR R0,#0A1h R2 RD_TxStart ; Slave Address for reading ; TxCount++ AND NOP LD OR TM JR RCF JR P1CONH,#00111111B ; SDA (P1.7) = Input Mode R1,#8 P1,#01<<SCL P1,#01<<SDA NZ,SetCF ; SCL High ; Data value check ; ; ReStart P1,#0FFh-(01<<SCL) ; ; RxData RotateLoop ; SetCF DataRotate SCF RLC AND DJNZ LD R0 P1,#0FFh-(01<<SCL) R1,RotateLoop ReadData,R0 OR OR P1CONH,#01000000B P1,#01<<SDA ; SDA (P1.7) = Output ; SDA High (ACK=High): communication ; finished NOP NOP OR NOP NOP P1,#01<<SCL ; SCL High (9th clock) P1,#0FFh-(01<<SCL) ; SCL Low AND NOP ; 8-4 DataRotate (next page continued) ; SCL Low ; End of 1byte(8bit) ? APPLICATION NOTE GenIicStop ; RD_Data_1 SERIAL EEPROM CALL POP POP POP RET IICbus_Stop R2 R1 R0 OR CALL JP P1,#01<<SDA IIC_Clock_1Bit RD_Count8bit ; Data "1" trasfer ; ; *************************************************************************** ;****************** Byte Write Operation ******************* ; Start Slave Addr.(A0) Word addr. Data ; *************************************************************************** Write1Byte: PUSH PUSH PUSH CALL R0 R1 R2 IICbus_Start ; IIC bus protocol start ; LD CLR WR_TxStart LD WR_DataShift RLC JR WR_Data_0 AND CALL R0,#0A0h R2 R1,#8 R0 C,WR_Data_1 P1,#0FFh-(01<<SDA) IIC_Clock_1Bit ; Slave address WR_Count8bit DJNZ ; AND OR NOP NOP NOP TM JR ; AND OR ; CP JR CP JR LD INC JR R1,WR_DataShift ; 1byte check P1CONH,#00111111B P1,#01<<SCL ; SDA (P1.7) = Input Mode ; Acknowledge clock P1,#01<<SDA NZ,CommuniFail ; Ack in ? ; P1,#0FFh-(01<<SCL) P1CONH,#01000000B R2,#2 UGE,TxStop R2,#1 UGE,WriteData R0,R14 R2 WR_TxStart ; 1 Byte (8bit) count ; Data "0" transfer ; SDA(P1.7) = Output Mode ; Word Address ; TxCount++ (next page continued) 8-5 SERIAL EEPROM WriteData APPLICATION NOTE LD INC JR R0,R15 R2 WR_TxStart ; Data to be written to the EEPROM ; TxCount++ OR CALL JR P1,#01<<SDA IIC_Clock_1Bit WR_Count8bit ; Data "1" transfer AND NOP NOP OR JP P1,#0FFh-(01<<SCL) TxStop JP GenIicStop IICbus_Start OR NOP NOP NOP AND NOP NOP NOP NOP NOP AND RET P1,#11000000B ; WR_Data_1 ; CommuniFail P1CONH,#01000000B GenIicStop P1,#0FFh-(01<<SCL) P1,#01<<SCL; IICbus_Stop P1,#0FFh-(01<<SDA) 8-6 ; P1.7/P1.6 High (SDA, SCL) ; P1,#0FFh-(01<<SDA) IIC_Clock_1Bit OR NOP NOP NOP AND NOP RET AND NOP NOP NOP OR NOP NOP NOP NOP NOP OR RET ; SDA(P1.7) = Output Mode ; Clock Generation. P1,#0FFh-(01<<SCL) P1,#01<<SCL P1,#01<<SDA ; SDA High (Stop condition) APPLICATION NOTE SERIAL EEPROM ;********************************************************************************************************************************** ; This program demonstrates how the S524A40X21 serial EEPROM can be interfaced to the SAMSUNG S3C72F5 microcontroller. This software includes random address byte read and byte write operation. ; If you use the 5 MHz crystal oscillator, SCL frequency will be approximately 50 kHz ;********************************************************************************************************************************** ;*************************************************************************** ; Equation Table ;*************************************************************************** SDA_PORT SCL_PORT ReadAddr ReadData WriteAddr WriteData PMG1_BUF EQU EQU EQU EQU EQU EQU EQU P0.0 P0.1 20H 22H 30H 32H 40H ;*************************************************************************** ;**************** Random Address Byte Read ****************** ; Start Slave Addr.(A0) Word Addr. Start #A1h Data ;*************************************************************************** Read1Byte: CALL LD LD IICbus_Start Y,#0H EA,#0A0h ; IIC Interface start RD_TxStart RD_DataShift LD ADC BTST JP Z,#7 EA,EA C RD_Data_0 ; 1Byte (8bit) RD_Data_1 BITS CALL JP SDA_PORT IIC_Clock_1Bit RD_Count8bit ; Data "1" transfer RD_Data_0 BITR CALL SDA_PORT IIC_Clock_1Bit ; Data "0" transfer RD_Count8bi DECS JP CALL BITS NOP NOP NOP Z RD_DataShift SdaInMode SCL_PORT ; ; Slave Address (A0) ; SDA Port Input Mode (next page continued) 8-7 SERIAL EEPROM BTSF JP BITR CALL CPSE JP JP APPLICATION NOTE SDA_PORT CommuniFail SCL_PORT SdaOutMode Y,#2H NextR1 RxData ; ACK Check ; TxCount = Y NextR1 CPSE Y,#1H JP NextR2 JP ReStart NextR2 LD INCS JP EA,ReadAddr Y RD_TxStart ; Pointed Address to Read ; TxCount++ BITS BITS NOP NOP NOP NOP NOP BITR NOP NOP NOP NOP NOP BITR NOP LD INCS JP SDA_PORT SCL_PORT ; SDA HIGH ; SCL HIGH SDA_PORT ; Start Condition CALL NOP LD LD SdaInMode BITS NOP NOP NOP BTSF JP RCF JP SCL_PORT ReStart RxData RotateLoop SCL_PORT EA,#0A1h Y RD_TxStart EA,#00H Z,#7 ; Clear ; 1Byte Count(8bit) SDA_PORT SetCF ; Data "0" DataRotate SetCF SCF ; (next page continued) 8-8 ; Slave Address for Reading (A1) ; Tx Count ++ ; Data "1" APPLICATION NOTE DataRotate GenlicStop SERIAL EEPROM ADC BITR NOP NOP NOP DECS JP LD CALL BITS NOP NOP BITS NOP NOP BITR NOP EA,EA SCL_PORT CALL RET IICbus_Stop Z RotateLoop ReadData,EA SdaOutMode SDA_PORT ; Save Read Data SCL_PORT SCL_PORT ; *************************************************************************** ;****************** Byte Write Operation ******************* ; Start Slave Addr.(A0) Word addr. Data ; *************************************************************************** Write1Byte: WR_TxStart CALL LD LD IICbus_Start Y,#0H EA,#Slave_WR ; Slave Address (A0) LD Z,#7 ; 1Byte (8bit) count WR_DataShift ADC BTST JP EA,EA C WR_Data_0 WR_Data_1 BITS CALL BITR JP SDA_PORT IIC_Clock_1Bit SDA_PORT WR_Count8bit ; Data "1" transfer WR_Data_0 BITR CALL SDA_PORT IIC_Clock_1Bit ; Data "0" transfer WR_Count8bit DECS JP CALL BITS Z WR_DataShift SdaInMode SCL_PORT ; 1byte check ; (next page continued) 8-9 SERIAL EEPROM APPLICATION NOTE NOP NOP NOP BTSF JP SDA_PORT CommuniFail BITR CALL CPSE JP JP SCL_PORT SdaOutMode Y,#2H NextW1 TxStop ; ACK Check NextW1 CPSE Y,#1H JP NextW2 JP WriteData NextW2 LD INCS JP EA,WriteAddr Y WR_TxStart ; Address to be written WriteData LD INCS JP EA,WriteData Y WR_TxStart ; Data to be written TxStop JP GenlicStop IICbus_Start CALL NOP NOP NOP NOP NOP BITR NOP NOP NOP NOP NOP BITR RET BITR NOP NOP BITS NOP NOP NOP NOP NOP BITS RET SDASCL_OutMode IICbus_Stop ; 8-10 SDA_PORT ; Start Condition SCL_PORT SDA_PORT SCL_PORT SDA_PORT (next page continued) ; Stop Condition APPLICATION NOTE SERIAL EEPROM IIC_Clock_1Bit BITS NOP NOP NOP BITR RET SCL_PORT SdaInMode PUSH LD AND LD SMB LD SMB POP RET EA EA,PMG1_BUF A,#1110B PMG1_BUF,EA 15 PMG1,EA 0 EA PUSH SMB LD OR LD SMB LD SMB POP RET EA 0 EA,PMG1_BUF A,#0001B PMG1_BUF,EA 15 PMG1,EA 0 EA BITR NOP NOP CALL JP SCL_PORT SdaOutMode CommuniFail SDASCL_OutMode BITS SMB LD LD LD LD LD SMB LD BITS NOP BITS RET SCL_PORT ; SDA INPUT ; SDA OUTPUT SdaOutMode GenlicStop EMB 15 EA,#00000001B PNE1,EA EA,#00000011B PMG1,EA PUMOD1,EA 0 PMG1_BUF,EA SDA_PORT ; N-ch open drain (P0.0) ; SCL,SDA OUTPUT ; Pull-up enable SCL_PORT 8-11 SERIAL EEPROM APPLICATION NOTE NOTES 8-12 Marking Information Data Sheet DIP/SOP #8 #5 A F 1 D C (1) (2) (3) (4) (5) S 1 1 4 (6) (7) #1 #4 (1) Operating Voltage A = 1.8 V to 5.5 V L = 2.0 V to 5.5 V C = 2.5 V to 5.5 V (2) EEPROM Density 1 = 1K-bit 2 = 2K-bit 4 = 4K-bit 8 = 8K-bit 5 = 16K-bit 9 = 32K-bit B = 64K-bit D = 128K-bit F = 256K-bit H = 512K-bit (3) Write Protection 0 = Hardware and software 1 = Hardware Only (4) Package Type D = DIP type S = SOP type R = TSSOP type (5) Temperature Range C = -25 C to 70 C I = -40 C to 85 C (6) Work Week Code (7) Assembly Site Code TSSOP #1 #4 S 1 1 4 A F 1 R C #8 #5 9-1 MARKING INFORMATION DATA SHEET NOTES 9-2 Ordering Information Data Sheet S524AD0XF1-DCT0 (1) (2) (3) (1) Series Name 24: I2C interface (2) Operation Voltage C: 2.5 V - 5.5 V L: 2.0 V - 5.5 V A: 1.8 V - 5.5 V (4) (5) (6) (7) (8) (9) (5) Write Protection 0 = Hardware and software 1 = Hardware only (6) Package Type D = DIP R = TSSOP S = SOP (3) Samsung's Internal Management Data (4) ROM Size 1 = 1K-bit 2 = 2K-bit 4 = 4K-bit 8 = 8K-bit 5 = 16K-bit 9 = 32K-bit B = 64K-bit D = 128K-bit F = 256K-bit H = 512K-bit (7) Temperature Range C = -25 C to 70 C I = -40 C to 85 C (8) Package Type B = Tube T = Tape & Reel (9) Customer Type 0 = None 10-1 ORDERING INFORMATION DATA SHEET NOTES 10-2 S524A SERIES EEPROM ORDER FORM Device Name: S524A______-______ Delivery Dates and Quantities: Deliverable Required Delivery Date Quantity Comments Customer sample Please answer the following questions: + What is the purpose of this order? New product development Upgrade of an existing product Replacement of an existing EEPROM Other If you are replacing an existing EEPROM, please indicate the former product name ( + + ) What are the main reasons you decided to use a Samsung EEPROM in your product? Please check all that apply. Price Product quality Features and functions Development system Technical support Delivery on time Used same product before Quality of documentation Samsung reputation Application (Product Model ID: ________________________) Audio/Video Communications Home Appliance LCD Consumer Office Automation Industrials Remocon Identification Other Please describe in detail its application __________________________________________________________________________________________ Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _________________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) Serial EEPROM Selection Guide S524A40X10/40X20/40X40 S524A40X11/40X21/40X41/60X81/60X51 S524AB0X91/B0XB1 S524AD0XD1/D0XF1 S524AE0XH1 Packaging Information Application Note Marking Information Ordering Information