A6280 3-Channel Constant-Current LED Driver with Programmable PWM Control Features and Benefits Description The A6280 is a 3-channel constant current LED driver that has a wide range of output currents. The A6280 controls LED brightness with a Pulse Width Modulation (PWM) scheme that gives the application the capability of displaying a billion colors in an RGB cluster. The maximum current is set by an external resistor. 3 x 10-bit PWM brightness settings 3 x 7-bit dot correction current settings 5 to 17 V operation Wide output current range, 10 to 150 mA per channel Serial port/PWM clock operates at up to 5 MHz Data and clock logic architecture allows single microcontroller control of large quantities of seriallyconnected A6280s at fast data transfer rate Buffered logic outputs to drive cables Thermal shutdown and UVLO protection Power-On Reset Packages: 16 pin DIP (suffix A), and 16 pin QFN (suffix ES) The LED brightness is controlled by performing PWM control on the outputs. The brightness data of the PWM signal for each LED is stored in three 10-bit registers. The peak value for each LED can be adjusted (dot-corrected) to compensate for mismatch, aging, and temperature effects. All the internal latched registers are loaded by a 31-bit shift register. One address bit controls whether dot correction/clock divider ratio or brightness data is loaded into the registers. The remaining bits are used for the data. This helps reduce the pin count of the A6280. To further lower the A6280 pin count, the PWM clock and the serial bus clock share the same pin and work concurrently to control LED brightness and to load data. The A6280 is designed to minimize the number of components needed to drive LEDs with large pixel spacing. A large number of A6280s can be daisy chained together and controlled by just four control signals (clock, serial data, latch, and output enable). Each of these inputs has buffered outputs to drive the next chip in the chain. Also, VIN can be tied to the LED ES, approximate scale 1:1 Continued on the next page... Application Diagram Power Supply Bus VLED Clock Data Latch Enable Output Enable Microprocessor Control Board Cat5 UTP VIN OutR OutG OutB Clock In Clock Out Data In Data Out Latch In Latch Out OE In OE Out VREG A6280 REXT Pixel Board #1 VLED Cat5 UTP VIN OutR OutG OutB Clock Out Clock In Data Out Data In Latch In Latch Out OE Out OE In VREG A6280 REXT Cat5 UTP Pixel Board #2 Figure 1. Functional drawing of daisy chained display application. Additional pixel boards with A6280 ICs can be applied. A6280-DS, Rev. 5 Pixel Board #N 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Description (continued) voltage supply bus, thus eliminating the need for a separate chip supply bus or an external regulator. The A6280 is supplied in a 16-pin dual in-line (DIP) package (suffix `A') and in a 16-lead QFN (suffix `ES') package. The packages are lead (Pb) free with 100% matte-tin leadframe plating. Applications include: Colored, large-character LED signs Scrolling, colored marquees Architectural lighting High intensity monochrome displays Large video and graphic displays Selection Guide Part Number Packing* Mounting A6280EA-T 25 pieces/tube 16 pin DIP A6280EESTR-T 1500 pieces/reel 16 pin QFN *Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage Notes VIN Units 17 V Output Voltage VOUT -0.5 to 17 V Output Current IOUT 170 mA Ground Current IGND 600 mA VREG Pin VREG 6 V 7 V Logic Outputs OUT0, OUT1, OUT2 Rating VO CO, LO, OEO, SDO Logic Input Voltage Range VI CI, LI, OEI, SDI -0.3 to 7 V Operating Ambient Temperature TA Range E -40 to 85 C Maximum Junction Temperature TJ(max) 150 C Tstg -55 to 150 C Storage Temperature Thermal Characteristics Characteristic Symbol Test Conditions* RJA Package Thermal Resistance Rating Units Package A, 4 layer PCB 38 C/W 4-layer PCB based on JEDEC standard (estimated performance) 42 C/W *For additional information, refer to the Allegro website. Power Dissipation versus Ambient Temperature 3500 3250 3000 Pa (R cka Power Dissipation, PD (mW) 2750 QJ 2500 2250 2000 4l (R aye QJ A = 1750 1500 A g = eA 38 , 4 C lay /W er ) P rP C 42 B ( C esti /W ma ) te CB d) 1250 1000 750 500 250 0 25 50 75 100 125 150 Temperature (C) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Functional Block Diagram SDI SDO Shift Register CI CO 100 ns One-Shot LI LO Latched Registers OEI OEO REXT Current Regulator 0 REXT VIN Current Regulator 1 Current Regulator 2 Regulator VREG OUT0 OUT1 OUT2 PGND LGND 10 VIN VREG 8 9 LGND Package A LGND 3 VIN 4 13 SDO 14 LO 15 OEO 12 OUT0 11 OUT1 PAD 10 PGND 9 8 REXT 7 2 SDI 11 CI CO 6 1 7 12 OEI OEO 5 REXT VREG LI 13 LI 6 14 SDI LO 4 5 15 OUT2 SDO 3 CI 16 PGND OUT0 2 OEI OUT1 1 16 CO Pin-out Drawings OUT2 Package ES Terminal List Table Name OUT1 OUT0 SDO LO OEO CO REXT VREG LGND VIN CI Number A Package ES Package 1 11 2 12 3 13 4 14 5 15 6 16 7 1 8 2 9 3 10 4 11 5 OEI 12 6 LI SDI OUT2 PGND PAD 13 14 15 16 n.a. 7 8 9 10 - Description Sinking output terminal Sinking output terminal Buffered serial data output after shift register Buffered latch output Buffered output enable output Buffered clock output An external resistor at this terminal establishes overall output current Regulator decoupling Logic ground Chip power supply voltage Serial and PWM clock input Output enable input; when low (active), the output drivers are enabled; when high (inactive), all output drivers are turned off (blanked) Latch input terminal; serial data is latched with high-level input Serial data input to shift register Sinking output terminal Power ground Exposed thermal pad, not internally connected; connect externally to LGND and PGND. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 OPERATING CHARACTERISTICS, valid at TA = 25C, VIN = 4.75 to 17.0 V, unless otherwise noted Characteristic ELECTRICAL CHARACTERISTICS Quiescent Supply Current Operating Supply Current Symbol Min. Typ. Max. Units - - - - 5.0 15.0 mA mA 4.75 - 17 V 3.5 3.0 4.6 135 45 -7 1.0 - - 2.0 - - - 3.8 150 100 -20 - - - - - - 150.0 51 - - 1 - - - 150 - - 300 200 - 1 165 15 4.5 4.0 5.4 165 57 7 3.0 3 1.0 - 0.8 - 0.4 - 600 400 20 - - - V V V mA mA % V %/V A V V mV V V k k A bit C C tH(CLK) tSU(D) tH(D) tSU(LI) tH(LI) tSU(OE) 20 20 20 20 20 40 - - - - - - - - - - - - ns ns ns ns ns ns tP(OE)2 - 200 - ns - - - - - - - 200 50 30 10 10 50 100 - 100 60 - - - - ns ns ns ns ns ns ns 100 ns 100 ns 100 100 130 6 ns ns ns MHz IDD IDD Load Supply Voltage VIN Undervoltage Lockout VIN(UV) VREG Voltage Range1 VREG Output Current (any single output) IOUT Output to Output Matching Error2 Output Voltage Range Load Regulation (I%Diff / VDS) Output Leakage Current Err VDS(min) Logic Input Voltage IDSX VIH VIL Logic Input Voltage Hysteresis Logic Output Voltage VOL VOH Input Resistance RI CI and SDI Pins Logic Input Current Output Dot Correction Error Thermal Shutdown Temperature Thermal Shutdown Hysteresis SWITCHING CHARACTERISTICS Clock Hold Time Data Setup Time Data Hold Time Latch Setup Time3 Latch Hold Time Output Enable Set Up Time Output Enable Falling to Outputs Turning ON Propagation Delay Time Clock to Output Propagation Delay Time Logic Output Fall Time Logic Output Rise Time IIN TJTSD TJhys tP(OUT) tBF tBR Output Fall Time (Turn Off) tf Output Rise Time (Turn On) tr Test Conditions fCLKIN = 0.0 Hz fCLKIN = 5 Mhz VIN rising VIN falling IO =15 mA, VIN = 17 V REXT = 5 k, scalar = 100% REXT = 15 k, scalar = 100% Output to output variation--all outputs on, REXT = 5 k REXT = 5 k, VDS = 1 to 3 V VOH = 17 V All digital inputs VIN 5.0 V, IO = 2 mA OEI pin, pull-up LI pin, pull-down VIN = 0 to 5 V REXT = 5 k; LSB Temperature increasing VDS = 1.0 V, IOUT = 150 mA COB = 50 pF, 4.5 to 0.5 V COB = 50 pF, 0.5 to 4.5 V CO = 10 pF, 90% to 10% of IOUT = 10 mA CO = 10 pF, 90% to 10% of IOUT = 150 mA CO = 10 pF, 10% to 90% of IOUT = 10 mA CO = 10 pF, 10% to 90% of IOUT = 150 mA Clock Falling Edge to Serial Data Out tP(SDO) - 50 Propagation Delay Time Output Enable In to Output Enable Out tP(OE) - 50 Propagation Delay Latch In to Latch Out Propagation Delay tP(LE) - 50 Clock In to Clock Out Propagation Delay tP(CLK) - 50 Clock Out Pulse Duration tw(CLK) 70 100 Maximum CLKIN Frequency fCLKIN - - 1If V is a 4.75 to 5.5 V supply, connect VIN to VREG externally IN 2Err = [I O UT(min or max) - IOUT(av)] / IOUT(av), where IOUT(av) is the average of 3 output current values. 3In daisy-chained applications, t SU(LI) must be increased for the quantity of pixels in the chain (see Application Information section). Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Timing Diagrams CI (Clock In) tSU (D ) SDI (Serial Data In) 0 1 2 3 4 5 6 7 15 16 31 D15 D14 D0 8 tw(C L K) tH( D) D30 D29 D28 D27 D26 D24 D23 D22 D21 tP(SD O) SDO (Serial Data Out) Don't Care D30 tSU (L I ) LI (Latch In) tP(IO) LO (Latch Out) CI (Clock In) tSU (O E ) tH (L I ) Figure 2. Shift Register Timing T0 T1 T2 0 1 2 PWM Counter TN 1023 0 1 2 X 0 IOUT0 Brightness Data= 0 IOUT1 Brightness Data= 1 tP(OE)2 tP(OUT) tP(OUT) tP(OUT) IOUT2 Brightness Data = 1022 Outputs Off OEI (Output Enable Input) Outputs On tP(OE) t w (OE) OEO (Output Enable Output) Figure 3. PWM Counter and Output Timing NOTE: At least one rising edge on the CI pin is needed while OE is high in order to reset the PWM counter and start a new PWM cycle. Otherwise, when OE is brought low, the outputs will operate according to the current PWM data and PWM count, and will finish the current cycle before resetting the count to 0. Therefore, if the counter is not reset (as explained above) after new PWM data has been latched, the outputs will complete the current PWM cycle (up to 1024 clock pulses if no clock divider is selected, 2048 clock pulses if a divide-by count of 2 is selected, and so forth) before starting a new PWM cycle with the new data. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Functional Description Shift Register The A6280 has a 31 bit shift register that loads data through the SDI (Serial Data In) pin. The shift register operates by a first-in first-out (FIFO) method. The most significant bit (MSB, bit 30) is the first bit shifted in and the least significant bit (LSB, bit 0) is shifted in last. The serial data is clocked by a rising edge of the CI (Clock In) pin. The SDO (Serial Data Out) pin is updated to the state of bit 30 on the falling edge of the CI pin. This will prevent any race conditions and erroneous data that might occur while propagating information through multiple A6280 that are daisy chained together. The contents of the shift register will continue to propagate on every rising edge of the CI pin. The information in the shift register is latched on a rising edge of the LI (Latch In) pin. The LI pin must be brought low before the rising edge of the next clock pulse, to avoid latching erroneous data. The latched data remains latched on a rising OEI (Output Enable In) signal. Output Buffers The A6280 is designed to allow daisy chaining many A6280s together. It can pass the clock, data, latch, and output enable SDI signals from one A6820 to the next without any loss of data due to duty cycle skewing or signal degradation. The A6820 is equipped with output buffers that allow the data signals to travel over long distances through strings of A6280s without the need for extra driving hardware. The A6280 drives these signals to TTL levels. Each of the A6280 inputs have a corresponding buffered output: * CI (Clock In) pin to CO (Clock Out) pin * LI (Latch In) pin to LO (Latch Out) pin * OEI (Output Enable In) pin to OEO (Output Enable Out) pin * SDI (Serial Data In) pin to SDO (Serial Data Out) pin The CO (Clock Out) pin is driven by an internal one-shot circuit. When the CI pin detects an edge rising through the input threshold, the one-shot circuitry drives the CO pin high for 100 ns. The CI pin input threshold has hysteresis to prevent false triggering of the CO signal. The implementation on the one-shot solution allows many A6280s to be daisy chained together with a consistent clock signal throughout the entire chain without degradation or loss of synchronicity to the data line. Shift Register 0 to 6 7 to 8 9 10 to 16 17 to 19 20 to 26 27 28 to 29 CI SDO 30 CO 100 ns One-Shot LI LO Latched Registers Current Clock Scalar 0 Divider Unused 7 Bits 2 Bits 1 Bit PWM Counter 0 10 Bits Current Scalar 1 7 Bits Unused 3 Bits PWM Counter 1 10 Bits Current Scalar 2 Unused 7 Bits 1 Bit Test Bits 2 Bits PWM Counter 2 10 Bits Bit 30 "1" Bit 30 "0" OEI OEO REXT Current Regulator 0 REXT VIN Current Regulator 1 Current Regulator 2 +5 V Regulator VREG OUT0 OUT1 OUT2 PGND LGND Figure 4. Functional Diagram Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 3-Channel Constant-Current LED Driver with Programmable PWM Control PWM Brightness Control The A6280 controls the intensity of each LED by pulse width modulating the current of each output. The A6280 has three 10-bit brightness registers, one for each output. These brightness registers set the PWM count value at which the outputs switch off during each PWM cycle. Each 10-bit brightness register gives 1023 levels of light intensity. The duty cycle, DC (%), can be determined by the following equation: DC = [(PWMn + 1) / 1024] x100 (%), where PWMn is the PWM value greater than zero that is stored in the brightness register. The relationship of the PWMn value to the output duty cycle is given in the following table: PWMn 0 1 2 ... 1023 Duty Cycle 0/1024 (0 %) 2/1024 3/1024 ... 1024/1024 (100 %) When the brightness register is set to zero, the outputs remain off for the duration of the PWM cycle for a 0% DC. When a brightness register is set to 1023, the LED for that output remains on (100% DC) when OEI is active and begins the PWM cycle. The output remains on when the PWM counter rolls over and begins a new count. The PWM counter begins counting at zero and increments only when the OEI pin is held low. When the PWM counter reaches the count of 1024, the counter resets to zero and continues incrementing. The counter resets to zero on a rising edge of CI when OEI is high, upon recovery from UVLO, and when powering-up. Latching new data into the brightness registers will not reset the PWM counter. Table 1. Clock Divider Configurations Bits 7 0 1 0 1 8 0 0 1 1 Divide By Count / 1 (no division) /2 /4 /8 mented on every rising edge of the CI pin divided by the clock divider count value when the OEI pin is low. For example, if the clock divider is programmed to divide the CI by 2, then the PWM counter will increment once every 2 CI cycles. Given a 5 MHz CI frequency, the clock period would be 200 ns. The clock divider data in the shift register is latched on a rising edge of the LI (Latch In) pin. The latched clock divider data remains latched on a rising OEI signal. The total number of possible colors of an RGB pixel is over 1 billion. Refer to figure 6 for the mapping of shift register bits to latches. Output Current Selection The overall maximum current is set by the external resistor, REXT , connected between the REXT and LGND pins. Once set, the maximum current remains constant regardless of the LED voltage variation, supply voltage variation, temperature, or other circuit parameters that could otherwise affect LED current. The maximum output current can be calculated using the following equation: IOUT(max) = 753.12 / REXT. The relationship of the value selected for REXT and IOUT is shown in figure 5. Internal Linear Regulator The A6280 has a built-in linear regulator. The regulator operates from a supply voltage of 5.5 to 17 V. It allows the VIN pin of the A6280 to connect to the same supply as the LEDs. This simplifies board design by eliminating the need for a chip supply bus IOUT (mA) A6280 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 5 There is a programmable clock divider that can slow the PWM counter relative to the CI pin. See table 1 for bit assignments of the programmable clock divider. The PWM counter is incre- 15 25 35 45 REXT (k) 55 65 75 Figure 5. Output Current versus External Resistor, REXT Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 and external voltage regulators. For 5 V supplies, connect VIN to VREG externally. Note: When using 5 V supplies, ensure that VIN does not exceed the absolute maximum rating of the VREG pin (6 V). Refer to figure 6 for the bit configurations for the scalar registers. The dot correction data in the shift register is latched on a rising edge of the LI (Latch In) pin. The dot correction data remains latched on a rising OEI signal. The default output current when the A6280 is powered-up or recovers from a UVLO is 36.5% of the current set by the REXT resistor. The VREG pin is used by the internal linear regulator to connect to a bypass capacitor. This pin is for internal use only and is not intended as an external power source. There should be a 1.0 F, 10 V ceramic capacitor connected between the VREG pin and LGND. The capacitor should be located as close to the VREG pin as possible. Package Power Dissipation The maximum allowable package power dissipation is determined as: Dot Correction Control PD(max) = (150 - TA) / RJA . The A6280 can further control the maximum output current for each output by setting the three 7-bit dot correction registers with scale data that ranges from 36.5% to 100% of the overall maximum output current that is set by the REXT resistor. This feature is useful because not every type of LED (red, green, or blue, for example) has the same level of brightness for a given current, and the brightness could be different even from LED to LED of the same type. By scaling the output currents so that all the LEDs have matched intensities, the application will have full color depth when using the PWM counters. The dot correction current can be calculated by the following equation: The actual package power dissipation is: PD(act) = DC0 x VDS0 x IOUT0 + DC1 x VDS1 x IOUT1 + DC2 x VDS2 x IOUT2 + VIN x IIN . where DCi is the PWM duty cycle for channel i, and IOUTi is the output current for channel i, determined by the dot correction current for that channel and REXT. When calculating power dissipation, the total number of available device outputs is usually used for the worst-case situation (i.e., displaying all 3 LEDs at 100% DC). IOUTn = IOUTn(max) x (Scalen / 2 + 36.5) / 100 Where Scalen is in the range 0 to 127, as shown in the following table: Scale IOUT/IOUT(max) (%) 0 1 36.5 37.0 2 ... 37.5 ... 127 100 Thermal Shutdown (TSD) When the junction temperature of the A6280 reaches the thermal shutdown temperature threshold, TJTSD (165C typical), the outputs will shut off until the junction temperature cools down below the recovery threshold, TJTSD -TJ ( 15C typical). The shift register and output latches will remain active during the TSD event. Therefore there is no need to reset the data in the output latches. Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PWM Counter 0 Dot Correction Register 0 aSelects bAllegro Clock Mode PWM Counter 1 0 Dot Correction Register 1 0 0 0 28 PWM Counter 2 Dot Correction Register 2 29 30a Address "0" 0 ATBb ATBb Address "1" which word is written to: Dot Correction/Clock Mode selection or PWM counter. Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application. Figure 6. Register Configuration Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A6280 3-Channel Constant-Current LED Driver with Programmable PWM Control Undervoltage Lockout The A6280 includes an internal undervoltage lockout (UVLO) circuit that disables the driver outputs in the event of the logic supply voltage dropping below a minimum acceptable level. This prevents the display of erroneous information, a necessary function for some critical applications. The shift register will not shift any data in a UVLO condition. Upon recovery of the logic supply voltage and on power up, the internal shift register and all latches will be set to zero. Ballast Resistors The voltage on the outputs should be kept in the range 1 to 3 V. If the voltage goes below 1V, the current will begin to rolloff as the driver runs out of headroom. At VOUT above 3 V, the power dissipation may become a problem, as each output contributes VOUT x ILED of power loss in the output sink driver. Typically the power supply nominal voltage is chosen to keep the output voltage in this range. Alternatively, series resistors can be added to dissipate the extra power and keep the output voltage within the recommended range. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Application Information Timing Considerations A6280s can be used in large numbers to drive many LEDs with the control signals connected serially together, with short cables between each pixel (see figure 8). Because the clock negative edge drives the data to the SDO (Serial Data Out) pin, and the CO pin is driven by a 100 ns one-shot function, the clock and data signals remain synchronized with each other as you move from the first pixel in the chain to the last. After all of the data is written to each A6280 in the chain, the data is latched into each A6280 via a low-to-high transition on the LI pin. The LO pin of pixel #1 drives the LI pin of pixel #2, and so on down the chain. These signals are buffered and are driven asynchronously relative to the CI and SDI pins. Therefore the mismatch in delays between CO and LO must be taken into consideration. Although the mismatches in delays are quite small, they must be considered when creating the timing pattern for driving the chain. The key parameter is the setup time from the last CI clock rising edge to the rising edge of LI. The minimum A6280 setup time from CI to LI is 20 ns. There may be a 5 ns per pixel mismatch in the propagation delays of the CI and LI signals (the delay from CI to CO compared to the delay from LI to LO). As a rule of thumb, use a setup time, tsu , at the first A6280 in the chain as calculated below: tsu = 20 ns + n x 5 ns , where n is the number of pixels in the chain. This will ensure that the setup time at the last pixel in the chain is at least 20 ns. tsu CI(1) to CI(n) LI(1) to LI(n) CI(1) CO(1) = CI(2) CO(2) = CI(3) CO(n-1) = CI(n) LI (1) LO(1) = LI (2) LO(2) = LI (3) LO(n-1) = LI (n) Figure 7. Signal Delay Mismatch Timing Diagram. tsu is the setup time for signals (CI to LI) applied to the first pixel in the chain. Note the difference in delay for CI(1) to CI(n) compared to the delay for LI(1) to LI(n). This must be compensated by increasing tsu. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 Applications Drawings + CI OEI LI SDI VIN Output Enable PAD LGND Latch Tie LGND and PGND to PAD externally CO OEO LO SDO A6280 A6280 REXT Clock Data VREG System Logic VOn 1 to 3 V OUT0 OUT2 - Red LEDs Green LEDs OUT1 Blue LEDs 10 F PGND 8.5 V 1 F X5R 10 k Maximum of 250 pixels Figure 8. Application Driving 3 RGB LEDs at 75 mA Peak 10 V + 2 0.5 W 10 F VOn 1 to 3 V SDI Tie LGND and PGND to PAD externally OUT0 OUT1 PAD CO OEO LO SDO A6280 REXT Output Enable A6280 VREG Latch CI OEI LI LGND Clock Data VIN System Logic PGND OUT2 - 1 F 10 V 5 k Maximum of 250 pixels Figure 9. Application Driving High Power LED at 450 mA Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 3-Channel Constant-Current LED Driver with Programmable PWM Control A6280 A Package, 16 Pin DIP 0.750 16 0.010 0.250 0.430 0.300 A 1 2 0.210 0.130 0.005 0.100 0.060 All dimensions nominal, not for tooling use (reference JEDEC MS-001 BB) Dimensions in inches Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.018 ES Package, 16 Pin QFN 0.30 3 0.90 16 1 2 A 0.50 16 1 3 1.70 3.10 1.70 17X D 3.10 0.75 0.08 C C 0.25 PCB Layout Reference View 0.50 1.70 0.40 All dimensions nominal, not for tooling use (reference JEDEC MO-220WEED-4) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B 1.70 2 1 16 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P300X300X80-17W4M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A6280 3-Channel Constant-Current LED Driver with Programmable PWM Control Copyright (c)2006-2007, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13