IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: DESCRIPTION: * 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V W typ. static) * CMOS power levels (0.4 * Rail-to-Rail output swing for increased noise margin * Available in SSOP and TSSOP packages This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be enetered while the outputs are in the high-impedance state. The ALVCH162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCH162373 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. DRIVE FEATURES: * Balanced Output Drivers: 12mA * Low switching noise APPLICATIONS: * 3.3V high speed systems * 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1OE 1LE 1 48 2OE 24 2LE 25 C1 C1 2 1D1 47 13 1Q1 1D 2D1 36 2Q1 1D TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JULY 2009 1 (c) 2009 Integrated Device Technology, Inc. DSC-4575/6 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit VTERM(3) Terminal Voltage with Respect to GND -0.5 to +4.6 V Terminal Voltage with Respect to GND -0.5 to VCC+0.5 V TSTG Storage Temperature -65 to +150 C IOUT DC Output Current -50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC 50 mA IOK Continuous Clamp Current, VO < 0 -50 mA ICC ISS Continuous Current through each VCC or GND 100 mA 1OE 1 48 1LE 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25C, F = 1.0MHz) Parameter(1) NOTE: 1. As applicable to the device type. 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 Pin Names Description 2Q6 20 29 2D6 xDx Data Inputs(1) GND 21 28 GND xLE Latch Enable Inputs 2Q7 22 27 2D7 xQx 3-State Outputs xOE 3-State Output Enable Input (Active LOW) 2Q8 23 26 2D8 2OE 24 25 2LE PIN DESCRIPTION NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH 8-BIT SECTION)(1) SSOP/ TSSOP TOP VIEW Inputs Outputs xOE xLE xDx xQx L H H H L H L L H X X Z L L X Qo(2) NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2. Output level before the indicated steady-state input conditions were established. 2 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 -- -- V VCC = 2.7V to 3.6V 2 -- -- VCC = 2.3V to 2.7V -- -- 0.7 VCC = 2.7V to 3.6V -- -- 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC -- -- 5 A IIL Input LOW Current VCC = 3.6V VI = GND -- -- 5 A IOZH High Impedance Output Current VCC = 3.6V VO = VCC -- -- 10 A IOZL (3-State Output pins) VO = GND -- -- 10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = -18mA -- -0.7 -1.2 V VH ICCL ICCH ICCZ ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- 100 0.1 -- 40 mV A Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND -- -- 750 A Min. Typ.(2) Max. Unit - 75 -- -- A VI = 0.8V 75 -- -- NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current Test Conditions VCC = 3V VI = 2V IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient. 3 VI = 1.7V - 45 -- -- VI = 0.7V 45 -- -- VI = 0 to 3.6V -- -- 500 A A IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Unit V VCC = 2.3V to 3.6V IOH = - 0.1mA VCC - 0.2 -- IOH = - 4mA 1.9 -- IOH = - 6mA 1.7 -- IOH = - 4mA 2.2 -- IOH = - 8mA 2 -- IOH = - 6mA 2.4 -- IOH = - 12mA 2 -- VCC = 2.3V to 3.6V IOL = 0.1mA -- 0.2 VCC = 2.3V IOL = 4mA -- 0.4 IOL = 6mA -- 0.55 IOL = 4mA -- 0.4 IOL = 8mA -- 0.6 IOL = 6mA -- 0.55 IOL = 12mA -- 0.8 VCC = 3V Output LOW Voltage Max. VCC = 2.3V VCC = 2.7V VOL Min. VCC = 2.7V VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C. OPERATING CHARACTERISTICS, TA = 25C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V 0.2V VCC = 3.3V 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 19 22 pF 4 5 SWITCHING CHARACTERISTICS(1) VCC = 2.5V 0.2V Symbol Parameter tPLH Propagation Delay tPHL xDx to xQx tPLH Propagation Delay tPHL xLE to xQx tPZH Output Enable Time VCC = 2.7V VCC = 3.3V 0.3V Min. Max. Min. Max. Min. Max. Unit 1.5 5.3 1.5 4.5 1.5 4 ns 2 5.6 2 5 2 4 ns 1.5 6.5 1.5 6 1.5 5 ns 1.5 5.6 1.5 5.5 1.5 4.5 ns 2 -- 2 -- 2 -- ns tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Setup Time, data before LE tH Hold Time, data after LE 1.5 -- 1.5 -- 1.5 -- ns tW Pulse Duration, LE HIGH or LOW 3.3 -- 3.3 -- 3.3 -- ns Output Skew(2) -- -- -- -- -- 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF 500 (1, 2) Pulse Generator GND All Other Tests Open INPUT OUTPUT 1 tPLH1 DATA INPUT SYNCHRONOUS CONTROL tSU tH ALVC Link Set-up, Hold, and Release Times VIH VT 0V VOH VT VOL tSK (x) OUTPUT 2 LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE Pulse Width tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tH tREM ASYNCHRONOUS CONTROL VOH VT VOL tPLH2 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V TIMING INPUT tPHL1 tSK (x) VOH VHZ 0V Enable and Disable Times SWITCH POSITION GND VLOAD/2 VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns. Disable High Enable High tPLZ VIH VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. VLOAD DISABLE VLOAD/2 OUTPUT SWITCH VT NORMALLY CLOSED LOW tPHZ tPZH OUTPUT SWITCH NORMALLY V OPEN T HIGH 0V ALVC Link Open Drain Disable Low Enable Low ALVC Link tPZL 500 Switch VIH VT 0V ENABLE CL Test tPHL CONTROL INPUT D.U.T. Test Circuit for All Outputs tPLH Propagation Delay VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open VIN tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 VT ALVC Link IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX ALVC X Bus-Hold Temp. Range XX Family XX XXX Device Type Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 PVG PAG Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green 373 16-Bit Transparent D-Type Latch with 3-State Outputs 162 Double-Density with Resistors, 12mA H Bus-Hold 74 - 40C to +85C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 6 for Tech Support: logichelp@idt.com