INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
1
JULY 2009INDUSTRIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-4575/6
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μμ
μμ
μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This 16-bit transparent D-type latch is built using advanced dual metal CMOS
technology. The ALVCH162373 is particularly suitable for imple-menting buffer
registers, I/O ports, bidirectional bus drivers, and working registers. This device
can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) can be used to place the eight outputs in either
a normal logic state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus lines signifi-
cantly. The high-impedance state and the increased drive provide the capability
to drive bus lines without need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained or new data can
be enetered while the outputs are in the high-impedance state.
The ALVCH162373 has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
The ALVCH162373 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANS-
PARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
1
OE
C1
1D
1
D
147
1
LE
1
Q
1
TO 7 OTHER CHANNELS
2
OE
2
D
136
2
LE
2
Q
1
TO 7 OTHER CHANNELS
1
48
2
24
25
13
C1
1D
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
1
Q
2
GND
VCC
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
481
1
Q
1
1
OE
1
Q
4
1
Q
3
1
Q
6
1
Q
5
1
Q
8
1
Q
7
2
Q
1
2
Q
3
2
Q
2
2
Q
4
VCC
2
Q
5
2
Q
6
GND
2
Q
7
2
Q
8
2
OE
1
D
2
GND
VCC
GND
GND
1
D
1
1
LE
1
D
4
1
D
3
1
D
6
1
D
5
1
D
8
1
D
7
2
D
1
2
D
3
2
D
2
2
D
4
VCC
2
D
5
2
D
6
GND
2
D
7
2
D
8
2
LE
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output Capacitance VOUT = 0V 7 9 pF
CI/O I/O Port Capacitance VIN = 0V 7 9 pF
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, ±50 mA
VI < 0 or VI > VCC
IOK Continuous Clamp Current, VO < 0 –50 mA
ICC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Pin Names Description
xDx Data Inputs(1)
xLE Latch Enable Inputs
xQx 3-State Outputs
xOE 3-State Output Enable Input (Active LOW)
PIN DESCRIPTION
Inputs Outputs
xOE xLE xDx xQx
LHH H
LHL L
HXX Z
LLX Q
o(2)
NOTES:
1 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before the indicated steady-state input conditions were established.
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
3
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC ——±5µA
IIL Input LOW Current VCC = 3.6V VI = GND — — ±5µA
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µA
IOZL (3-State Output pins) VO = GND — — ±10
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V — 0.1 40 µA
ICCH VIN = GND or VCC
ICCZ
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1) Test Conditions Min. Typ.(2) Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — µA
IBHL VI = 0.7V 45 — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 4mA 1.9 —
IOH = – 6mA 1.7 —
VCC = 2.7V IOH = – 4mA 2.2 —
IOH = – 8mA 2 —
VCC = 3V IOH = – 6mA 2.4 —
IOH = – 12mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 4mA — 0.4
IOL = 6mA — 0.55
VCC = 2.7V IOL = 4mA — 0.4
IOL = 8mA — 0.6
VCC = 3V IOL = 6mA — 0.55
IOL = 12mA — 0. 8
SWITCHING CHARACTERISTICS(1)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 19 22 pF
CPD Power Dissipation Capacitance Outputs disabled 4 5
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tPLH Propagation Delay 1.5 5.3 1.5 4.5 1.5 4 ns
tPHL xDx to xQx
tPLH Propagation Delay 2 5.6 2 5 2 4 ns
tPHL xLE to xQx
tPZH Output Enable Time 1.5 6.5 1.5 6 1.5 5 ns
tPZL xOE to xQx
tPHZ Output Disable Time 1.5 5.6 1.5 5.5 1.5 4.5 ns
tPLZ xOE to xQx
tSU Setup Time, data before LE↓2—2—2—ns
tHHold Time, data after LE↓1.5 — 1.5 — 1.5 — ns
tWPulse Duration, LE HIGH or LOW 3 . 3 — 3 .3 — 3.3 — ns
tSK(O) Output Skew(2) — ————500 ps
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
5
Open
V
LOAD
GND
V
CC
Pulse
Generator D.U.T.
500Ω
500Ω
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK (x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK (x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK(x)
= t
PLH2 -
t
PLH1 or
t
PHL2 -
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT 0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DIS-
ABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
ORDERING INFORMATION
XX ALVC XXX XX
Package
Device Type
Temp. Range
PVG
PAG
162
74
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
16-Bit Transparent D-Type Latch with 3-State Outputs
– 40°C to +85°C
XXX
Family
Bus-Hold
373
Bus-Hold
Double-Density with Resistors, ±12mA
H
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San Jose, CA 95138 fax: 408-284-2775
www.idt.com
