AN32183A
Page 1 of 56
Product Standards
FEATURES DESCRIPTION
9 x 9 Dots Matrix LED Driver IC
AN32183A is a 81 Dots Matrix LED Driver.
It can drive up to 27 RGB LEDs.
9 9 LED Matrix Driver
(Total LED that can be driven = 81)
LED Selectable Maximum Current
LED Music Synchronizing Function
I2C interface (Standard Mode, Fast Mode and
Fast Mode Plus)
(4 Slave address selectable)
24 pin Shrink Small Outline Package (SSOP Type)
TYPICAL APPLICATION
APPLICATIONS
http://www.semicon.panasonic.co.jp/en/
Mobile Phone
Smart Phone
PCs
Game Consoles
Home Appliances etc.
Note:
The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and
verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the
above illustrated application circuit in the design of the equipment.
VCC1
VCC2
Battery
AGND
PGND1
PGND2
SDA
NRST
39 k
SCL
SLAVSEL
IREF
CLKIO
LDO
1.0 F
CPU I/F
VDD
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 2 of 56
Product Standards
CONTENTS
FEATURES ……………………………………………………………………… 1
DESCRIPTION ……………………………………………………………………… 1
APPLICATIONS ……………………………………………………………………… 1
TYPICAL APPLICATION ………………………………………………………………… 1
CONTENTS ………………………………………………………………………………… 2
ORDERING INFORMATION ……………………………………………………………... 3
ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3
POWER DISSIPATION RATING ………………………………………………………… 3
RECOMMENDED OPERATING CONDITIONS ………………………………………… 4
ELECTRICAL CHARACTERISTICS .…………………………………………………… 5
PIN CONFIGURATION …………………………………………………………………… 11
PIN FUNCTIONS …………………………………………………………………………12
FUNCTIONAL BLOCK DIAGRAM ……………………………………………………… 13
OPERATION ……………………………………………………………………………… 15
PACKAGE INFORMATION ………………………………………………………………55
IMPORTANT NOTICE………………………………………………………………………56
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 3 of 56
Product Standards
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION RATING
Note: For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does
not exceed the allowable value.
Parameter Symbol Rating Unit Note
Supply voltage VCCMAX 6.0 V *1
VDDMAX 6.0 V *1
Operating ambience temperature Topr – 30 to + 85 C*2
Operating junction temperature Tj– 30 to + 125 C*2
Storage temperature Tstg –55to+125 C*2
Input Voltage Range VSLAVSEL, VSCL, VSDA,
VCLKIO, VNRST
– 0.3 to 6.0 V —
Output Voltage Range
VLDO, VCLKIO,
VZ1, VZ2, VZ3, VZ4, VZ5,
VZ6, VZ7, VZ8, VZ9, VZ10
– 0.3 to 6.0 V —
ESD HBM 2.0 kV —
Note: This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum
rating. This rating is the maximum rating and device operating at this range is not guaranteed as it is higher than our
stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability
of the product may be affected.
*1: VCCMAX = VCC, VDDMAX = VDD.
The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for
Ta = 25C.
PACKAGE JA PD(Ta=25 C) PD(Ta=85 C)
24 pin Shrink Small Outline Package (SSOP Type) 135.1 C /W 0.740 W 0.296 W
ORDERING INFORMATION
Order Number Feature Package Output Supply
AN32183A-VF LED Driver for Illumination 24 pin SSOP Emboss Taping
CAUTION
Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS
gates.
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 4 of 56
Product Standards
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min. Typ. Max. Unit Note
Supply voltage range VCC 3.1 3.6 5.5 V *1
VDD 1.7 1.85 5.5 V *1
Input Voltage Range
VSLAVSEL, VSCL, VSDA,
VCLKIO
–0.3 — V
DD + 0.3 V *2
VNRST –0.3 — V
CC + 0.3 V *2
Output Voltage Range
VLDO, VCLKIO,
VZ1, VZ2, VZ3, VZ4, VZ5
VZ6, VZ7, VZ8, VZ9, VZ10
–0.3 — V
CC + 0.3 V *2
Note: *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
Do not apply external currents and voltages to any pin not specifically mentioned.
Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, PGND1 and GND2.
VCC is voltage for VCC1 and VCC2. VDD is voltage for VDD.
*2 : (VCC + 0.3 ) V must not exceed 6 V. (VDD + 0.3) V must not exceed 6 V.
Doc No.
TA4-EA-06028
Revision.
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Established
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2011-10-07
Revised
:
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AN32183A
Page 5 of 56
Product Standards
Parameter Symbol Condition Limits Unit Note
Min Typ Max
Circuit Current
Circuit Current (1)
OFF Mode ICC1 NRST = 0V — 0 1 A—
Circuit Current (2)
OFF Mode ICC2 NRST = 3.6V — 250 500 A—
Internal Oscillator
Oscillation Frequency FDC1 VCC = 3.6 V 1.92 2.40 2.88 MHz —
SCAN Switch
Switch On Resistance RSCAN VCC = 3.6 V
IZ1~Z9 = – 20 mA —1.5 3 —
Constant Voltage Source (LDO)
Output voltage (1) VL1 ILDO = – 10 μA 2.75 2.85 2.95 V
Output voltage (2) VL2 ILDO = – 15 mA 2.75 2.85 2.95 V
CLKIO
High Level Input
Voltage Range VIH1
High Level Acknowledged Voltage
(At External CLK Input Mode)
0.7
VDD
—VDD
+ 0.3 V—
Low Level Input
Voltage Range VIL1
Low Level Acknowledged Voltage
(At External CLK Input Mode) –0.3 — 0.3
VDD
V—
High Level Output Voltage VOH1
ICLKIO = – 1 mA
(At Internal CLK Output Mode)
0.8
VDD
—VDD
+ 0.3 V—
Low Level Output Voltage VOL1
ICLKIO = 1 mA
(At Internal CLK Output Mode) –0.3 — 0.2
VDD
V—
High Level input Current IIH1
VCC = 5.5 V
VCLKIO = 5.5 V –1 0 1 A—
Low Level input Current IIL1
VCC = 5.5 V
VCLKIO = 0 V –1 0 1 A—
ELECTRICAL CHARACTERISTICS
VCC = 3.6 V, VDD = 1.85 V
Notes: Ta= 25C2C unless otherwise noted.
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Revision.
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Established
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Revised
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AN32183A
Page 6 of 56
Product Standards
Parameter Symbol Condition Limits Unit Note
Min Typ Max
Constant Current Source (Matrix LED)
Output Current (1) IMX1
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
VZ1~Z10 = 1 V
19 20 21 mA *1
DAC Current Step DACSTEP
DAC Constant Current Mode
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
VZ1~Z10 = 1V, IDAC1 = IZ1~Z10
LED Current Setting = 22 mA
IMAX = [011], BRTXX = [1011]
VZ1~Z10 = 1 V, IDAC2 = IZ1~Z10
DACSTEP = IDAC2 – IDAC1
024mA*2
OFF Mode Leak Current1 IMXOFF1
VCC = 5.5 V, VDD = 5.5 V
MTXON = 0
VZ1~Z10 = 5.5V
–1 — 1 A*3
OFF Mode Leak Current2 IMXOFF2
VCC = 5.5 V, VDD = 5.5 V
MTXON = 0
VZ1~Z10 = 0 V
–1 — 1 A*3
Channel Difference IMXCH
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
Difference of Z1 to 10 current from
the average current value
–5 — 5 % —
Voltage at which LED driver can keep constant current value
LED Driver Voltage VLD2
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
Voltage at which LED Current
change within 5 % compared with
LED Current of pin voltage = 0.5 V.
0.4——V—
Note: * 1: This is allowable value when recommended parts (ERJ2RHD393X) are used for the terminal IREF.
* 2: Current step for individual channels (Z1~Z10).
* 3: Please refer to page 23 for more information on the setting.
ELECTRICAL CHARACTERISTICS (Continued)
VCC = 3.6 V, VDD = 1.85 V
Notes: Ta= 25C2C unless otherwise noted.
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 7 of 56
Product Standards
Parameter Symbol Condition Limits Unit Note
Min Typ Max
SLAVSEL
High Level Input Voltage
Range VIH2 High Level Acknowledged Voltage 0.7
VDD
—VDD
+ 0.3 V—
Low Level Input Voltage
Range VIL2 Low Level Acknowledged Voltage – 0.3 — 0.3
VDD
V—
High Level Input Current IIH2
VCC = 5.5 V
VSLAVSEL = 3.6 V –1 0 1 A—
Low Level Input Current IIL2
VCC = 5.5 V
VSLAVSEL = 0 V –1 0 1 A—
NRST
High Level Input Voltage
Range VIH3 High Level Acknowledged Voltage 1.5 — VCC
+ 0.3 V—
Low Level Input Voltage
Range VIL3 Low Level Acknowledged Voltage – 0.3 — 0.6 V —
High Level Input Current IIH3
VCC = 5.5 V
VNRST = 3.6 V –1 0 1 A—
Low Level Input Current IIL3
VCC = 5.5 V
VNRST = 0 V –1 0 1 A—
I2C bus (Internal I/O stage characteristics)
Low-level input voltage VIL
Voltage which recognized that
SDA and SCL are Low-level –0.5 — 0.3
VDD
V*4
High-level input voltage VIH
Voltage which recognized that
SDA and SCL are High-level
0.7
VDD
—
VDD
MAX+
0.5
V*4
Low-level output voltage 1 VOL1
VDD > 2 V
ISDA = 3 mA 0—0.4V—
Low-level output voltage 2 VOL2
VDD <2 V
ISDA = 3 mA 0—
0.2
VDD
V—
Low-level output current IOL VSDA = 0.4 V 20 — — mA —
Input current each I/O pin Ii
VCC = 5.5 V, VDD = 5.5 V
VSCL, VSDA =
0.1 VDDMAX to 0.9 VDDMAX
–10 0 10 A—
SCL clock frequency fSCL — 0 — 1 000 kHz —
Note: VDDMAX refers to the maximum operating supply voltage of VDD .
*4 : The input threshold voltage of I2C bus (Vth) is linked to VDD (I2C bus I/O stage supply voltage).
In case the pull-up voltage is not VDD, the threshold voltage (Vth) is fixed to ((VDD / 2) (Schmitt width) / 2 ) and
High-level, Low-level of input voltage are not specified. In this case, pay attention to Low-level (max.) value (VILMAX).
It is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (VDD).
ELECTRICAL CHARACTERISTICS (Continued)
VCC = 3.6 V, VDD = 1.85 V
Notes: Ta= 25C2C unless otherwise noted.
Doc No.
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Revised
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AN32183A
Page 8 of 56
Product Standards
Parameter Symbol Condition Limits Unit Note
Min Typ Max
TSD (Thermal shutdown protection circuit)
Detection temperature Tdet
Temperature which Constant
current circuit, and Matrix SW
turn off.
— 150 — C*5
*6
Constant Voltage Source (LDO)
Ripple rejection ratio (1) PSL11
VCC = 3.6 V + 0.3 V[p-p]
f = 1 kHz
ILDO = –15 mA
PSL11 = 20log(acVLDO / 0.3)
—–50— dB *6
Ripple rejection ratio (2) PSL12
VCC = 3.6 V + 0.3 V[p-p]
f = 10 kHz
ILDO = –15 mA
PSL12 = 20log(acVLDO / 0.3)
—–40— dB *6
Short-circuit protection
current IPT1 VLDO = 0 V — 40 — mA *6
I2C bus (Internal I/O stage characteristics) (Continued)
Hysteresis of Schmitt
trigger input 1 Vhys1
VDD > 2 V,
Hysteresis of SDA, SCL
0.05
VDD
—V*7
*8
Hysteresis of Schmitt
trigger input 2 Vhys2
VDD < 2 V,
Hysteresis of SDA, SCL
0.1
VDD
——V*7
*8
Output fall time from
VIHMIN to VILMAX
tof
Bus capacitance :
10pF to 550pF
IP20 mA (VOLMAX = 0.4 V)
IP: Max. sink current
— — 120 ns *7
*8
Pulse width of spikes which
must be suppressed by the
input filter
tSP —0—50ns
*7
*8
Capacitance for each
I/O pin Ci———10pF
*7
*8
Note: *5 : Constant current circuit, and Matrix SW turn off and IC reset when TSD operates.
*6 : Typical Design Value
*7 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.10. All values referred to VIHMIN and VILMAX level.
*8 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (Continued)
VCC = 3.6 V, VDD = 1.85 V
Notes: Ta= 25C2C unless otherwise noted.
Doc No.
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Revision.
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2011-10-07
Revised
:
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AN32183A
Page 9 of 56
Product Standards
Parameter Symbol Condition Limits Unit Note
Min Typ Max
I2C bus (Bus line specifications) (Continue)
Hold time
(repeated) START
condition
tHD:STA
The first clock pulse is generated
after tHD:STA.
0.26 — — s*7
*8
Low period of the SCL
clock tLOW —0.5——
s*7
*8
High period of the SCL
clock tHIGH —0.26——
s*7
*8
Set-up time for a repeat
START condition tSU:STA —0.26—
s*7
*8
Data hold time tHD:DAT —0——
s*7
*8
Data set-up time tSU:DAT —50——ns
*7
*8
Rise time of both SDA and
SCL signals tr— — — 120 ns *7
*8
Fall time of both SDA and
SCL signals tf— — — 120 ns *7
*8
Set-up time of STOP
condition tSU:STO —0.26——
s*7
*8
Bus free time between
STOP and START
condition
tBUF —0.5——
s*7
*8
Capacitive load for each
bus line Cb—— 550 pF *7
*8
Data valid time tVD:DAT ———0.45
s*7
*8
Data valid acknowledge tVD:ACK ———0.45
s*7
*8
Noise margin at the Low-
level for each connected
device
VnL —0.1
VDD
——V*7
*8
Noise margin at the High-
level for each connected
device
VnH —0.2
VDD
——V*7
*8
Note: *7 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page 10. All values referred to VIHMIN and VILMAX level.
*8 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (Continued)
VCC = 3.6 V, VDD = 1.85 V
Notes: Ta= 25C2C unless otherwise noted.
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:
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Revised
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Product Standards
ELECTRICAL CHARACTERISTICS (Continued)
S : START condition
Sr : Repetitive START condition
P : STOP condition
tftr
tf
70 %
30 %
SDA
SCL
tHD;STA
70 %
30 %
70 %
30 %
S1 / fSCL
1st clock cycle
tHD;DAT
tSU;DAT
70 %
30 %
70 %
30 %
tr
tLOW
70 %
30 %
tHIGH
tVD;DAT
●●●
cont.
9th clock
●●●
cont.
tHD;STA
Sr
tSP
70 %
30 %
tSU;STO
VILMAX = 0.3 VDD
VIHMIN = 0.7 VDD
tSU;STA
9th clock
tVD;ACK
tBUF
P S
SDA
SCL
●●●
●●●
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Product Standards
PIN CONFIGURATION
TOP VIEW
VDD
SCL
SDA
SLAVSEL
Z10
Z9
VCC2
Z8
PGND2
Z7
Z6
Z5
IREF
AGND
NRST
N.C.
CLKIO
Z1
Z2
VCC1
Z3
PGND1
Z4
LDO
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
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:
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Revised
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Page 12 of 56
Product Standards
PIN FUNCTIONS
Pin No. Pin name Type Description Pin processing
at unused
1 VDD Power supply Power supply for I2C interface (Required pin)
2 SCL Input Clock input pin for I2C interface (Required pin)
3 SDA Input/Output Data input / output pin for I2C interface (Required pin)
4 SLAVSEL Input Slave address selection pin for I2C interface GND or VCC or
SCL or SDA
5 Z10 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
6 Z9 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
7
17
VCC2
VCC1 Power supply Power supply for matrix driver,
Internal reference circuit
Battery or External
power supply
8 Z8 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
9
15
PGND2
PGND1 Ground Power Ground pin (Required pin)
10 Z7 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
11 Z6 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
12 Z5 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
13 LDO Output LDO output pin (Required pin)
14 Z4 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
16 Z3 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
18 Z2 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
19 Z1 Output Constant current circuit, PWM control output pin,
Control switch pin for matrix driver Open
20 CLKIO Input/Output Reference clock input output / Music Input pin Open
21 — — N.C —
22 NRST Input Reset input pin (Required pin)
23 AGND Ground Ground pin (Required pin)
24 IREF Output Resistor connection pin for constant current setup (Required pin)
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Revised
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Product Standards
FUNCTIONAL BLOCK DIAGRAM
Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
(2)
(1)
(3)
SCL
SDA
VDD
(4)SLAVSEL
I2C
serial
interface
Frame and brightness
controller
Moving pattern
generator
Logic
PWM Step control
(24) IREF
Reference
Generator (23) AGND
(22) NRST
Clock Output
Music
Synchronize
Function
CLKIO(20)
No Connection(21)
(13) LDO
Voltage
regulators
Z10 (5)
Z9 (6)
Z8 (8)
Z7 (10)
Z6 (11)
Z5 (12)
Z1(19)
Z2(18)
Z3(16)
Z4(14)
VCC2 (7)
PGND2 (9)
VCC1(17)
PGND1(15)
Periodical Scanning Selectors
&
LED drivers
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Product Standards
1.1 Power ON
1.2 Power OFF
1. Power Supply Sequence
Serial Input is possible
NRST
>1 ms
VCC
VDD
>3 ms
Note: For the Startup Timing of VCC and VDD, it is possible to be changed.
NRST
Serial Input is possible
VDD
VCC
1 ms or more
Note: For the Shut down Timing of VCC and VDD, it is possible to be changed.
OPERATION
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Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
01hRST00hW------------RAMRSTSRST
02h POWERCNT 00h R/W -- -- -- -- -- -- OSCEN
03h reserved -- -- -- -- -- -- -- -- -- --
04h OPTION 00h R/W -- -- -- -- ZPDEN MLDACT CLKOUT EXTCLK
05h MTXON 1Eh R/W -- -- -- IMAX
Reserved IMAX[2:0] MTXON
06h PWMEN1 00h R/W PWMA8 PWMA7 PWMA6 PWMA5 PWMA4 PWMA3 PWMA2 PWMA1
07h PWMEN2 00h R/W PWMB7 PWMB6 PWMB5 PWMB4 PWMB3 PWMB2 PWMB1 PWMA9
08h PWMEN3 00h R/W PWMC6 PWMC5 PWMC4 PWMC3 PWMC2 PWMC1 PWMB9 PWMB8
09h PWMEN4 00h R/W PWMD5 PWMD4 PWMD3 PWMD2 PWMD1 PWMC9 PWMC8 PWMC7
0Ah PWMEN5 00h R/W PWME4 PWME3 PWME2 PWME1 PWMD9 PWMD8 PWMD7 PWMD6
0Bh PWMEN6 00h R/W PWMF3 PWMF2 PWMF1 PWME9 PWME8 PWME7 PWME6 PWME5
0Ch PWMEN7 00h R/W PWMG2 PWMG1 PWMF9 PWMF8 PWMF7 PWMF6 PWMF5 PWMF4
0Dh PWMEN8 00h R/W PWMH1 PWMG9 PWMG8 PWMG7 PWMG6 PWMG5 PWMG4 PWMG3
0Eh PWMEN9 00h R/W PWMH9 PWMH8 PWMH7 PWMH6 PWMH5 PWMH4 PWMH3 PWMH2
0Fh PWMEN10 00h R/W PWMI8 PWMI7 PWMI6 PWMI5 PWMI4 PWMI3 PWMI2 PWMI1
10h PWMEN11 00h R/W -- -- -- -- -- -- -- PWMI9
11h MLDEN1 00h R/W MLDA8 MLDA7 MLDA6 MLDA5 MLDA4 MLDA3 MLDA2 MLDA1
12h MLDEN2 00h R/W MLDB7 MLDB6 MLDB5 MLDB4 MLDB3 MLDB2 MLDB1 MLDA9
13h MLDEN3 00h R/W MLDC6 MLDC5 MLDC4 MLDC3 MLDC2 MLDC1 MLDB9 MLDB8
14h MLDEN4 00h R/W MLDD5 MLDD4 MLDD3 MLDD2 MLDD1 MLDC9 MLDC8 MLDC7
15h MLDEN5 00h R/W MLDE4 MLDE3 MLDE2 MLDE1 MLDD9 MLDD8 MLDD7 MLDD6
16h MLDEN6 00h R/W MLDF3 MLDF2 MLDF1 MLDE9 MLDE8 MLDE7 MLDE6 MLDE5
17h MLDEN7 00h R/W MLDG2 MLDG1 MLDF9 MLDF8 MLDF7 MLDF6 MLDF5 MLDF4
18h MLDEN8 00h R/W MLDH1 MLDG9 MLDG8 MLDG7 MLDG6 MLDG5 MLDG4 MLDG3
19h MLDEN9 00h R/W MLDH9 MLDH8 MLDH7 MLDH6 MLDH5 MLDH4 MLDH3 MLDH2
1Ah MLDEN10 00h R/W MLDI8 MLDI7 MLDI6 MLDI5 MLDI4 MLDI3 MLDI2 MLDI1
1Bh MLDEN11 00h R/W -- -- -- -- -- -- -- MLDI9
2Ah MLDMODE1 00h R/W -- -- -- -- GRP9_9 GRP9_8 GRP9_2 GRP9_1
2Bh THOLD 00h R/W THOLD[7:0]
Note: "Reserved" registers and data bits indicated by "--" cannot be accessed. "Reserved" registers are not used.
For data bits indicated by "--" in other registers except from "reversed" registers, will return "zero" value if these bits are read.
Writing to these bits will be ignored. IMAX Reserved will give default value [1].
OPERATION (Continued)
2. Register Map
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Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
2Ch CONSTX6_1 00h R/W -- -- X6 X5 X4 X3 X2 X1
2Dh CONSTX10_7 00h R/W -- -- -- -- X10 X9 X8 X7
2Eh CONSTY6_1 00h R/W -- -- Y6 Y5 Y4 Y3 Y2 Y1
2Fh CONSTY9_7 00h R/W -- -- -- -- -- Y9 Y8 Y7
30h MASKY6_1 00h R/W -- -- Y6MSK Y5MSK Y4MSK Y3MSK Y2MSK Y1MSK
31h MASKY9_7 00h R/W -- -- -- -- -- Y9MSK Y8MSK Y7MSK
32h SLPTIME 00h R/W -- -- -- FADTIM SLOPEEXTL[1:0] SLOPEEXTH[1:0]
33h MLDCOM 03h R/W -- -- -- -- -- MLDCOM[2:0]
34h reserved -- -- -- -- -- -- -- -- -- --
35h reserved -- -- -- -- -- -- -- -- -- --
36h SCANSET 08h R/W -- -- -- -- SCANSET[3:0]
40h DTA1 00h R/W DTA1[7:0]
41h DTA2 00h R/W DTA2[7:0]
42h DTA3 00h R/W DTA3[7:0]
43h DTA4 00h R/W DTA4[7:0]
44h DTA5 00h R/W DTA5[7:0]
45h DTA6 00h R/W DTA6[7:0]
46h DTA7 00h R/W DTA7[7:0]
47h DTA8 00h R/W DTA8[7:0]
48h DTA9 00h R/W DTA9[7:0]
49h DTB1 00h R/W DTB1[7:0]
4Ah DTB2 00h R/W DTB2[7:0]
4Bh DTB3 00h R/W DTB3[7:0]
4Ch DTB4 00h R/W DTB4[7:0]
4Dh DTB5 00h R/W DTB5[7:0]
4Eh DTB6 00h R/W DTB6[7:0]
4Fh DTB7 00h R/W DTB7[7:0]
50h DTB8 00h R/W DTB8[7:0]
51h DTB9 00h R/W DTB9[7:0]
Note: "Reserved" registers and data bits indicated by "--" cannot be accessed. "Reserved" registers are not used.
For data bits indicated by "--" in other registers except from "Reserved" registers, will return "zero" value if these bits are read.
Writing to these bits will be ignored.
2. Register Map (Continued)
OPERATION (Continued)
Doc No.
TA4-EA-06028
Revision.
4
Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 17 of 56
Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
52h DTC1 00h R/W DTC1[7:0]
53h DTC2 00h R/W DTC2[7:0]
54h DTC3 00h R/W DTC3[7:0]
55h DTC4 00h R/W DTC4[7:0]
56h DTC5 00h R/W DTC5[7:0]
57h DTC6 00h R/W DTC6[7:0]
58h DTC7 00h R/W DTC7[7:0]
59h DTC8 00h R/W DTC8[7:0]
5Ah DTC9 00h R/W DTC9[7:0]
5Bh DTD1 00h R/W DTD1[7:0]
5Ch DTD2 00h R/W DTD2[7:0]
5Dh DTD3 00h R/W DTD3[7:0]
5Eh DTD4 00h R/W DTD4[7:0]
5Fh DTD5 00h R/W DTD5[7:0]
60h DTD6 00h R/W DTD6[7:0]
61h DTD7 00h R/W DTD7[7:0]
62h DTD8 00h R/W DTD8[7:0]
63h DTD9 00h R/W DTD9[7:0]
64h DTE1 00h R/W DTE1[7:0]
65h DTE2 00h R/W DTE2[7:0]
66h DTE3 00h R/W DTE3[7:0]
67h DTE4 00h R/W DTE4[7:0]
68h DTE5 00h R/W DTE5[7:0]
69h DTE6 00h R/W DTE6[7:0]
6Ah DTE7 00h R/W DTE7[7:0]
6Bh DTE8 00h R/W DTE8[7:0]
6Ch DTE9 00h R/W DTE9[7:0]
6Dh DTF1 00h R/W DTF1[7:0]
6Eh DTF2 00h R/W DTF2[7:0]
2. Register Map (Continued)
OPERATION (Continued)
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 18 of 56
Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
6Fh DTF3 00h R/W DTF3[7:0]
70h DTF4 00h R/W DTF4[7:0]
71h DTF5 00h R/W DTF5[7:0]
72h DTF6 00h R/W DTF6[7:0]
73h DTF7 00h R/W DTF7[7:0]
74h DTF8 00h R/W DTF8[7:0]
75h DTF9 00h R/W DTF9[7:0]
76h DTG1 00h R/W DTG1[7:0]
77h DTG2 00h R/W DTG2[7:0]
78h DTG3 00h R/W DTG3[7:0]
79h DTG4 00h R/W DTG4[7:0]
7Ah DTG5 00h R/W DTG5[7:0]
7Bh DTG6 00h R/W DTG6[7:0]
7Ch DTG7 00h R/W DTG7[7:0]
7Dh DTG8 00h R/W DTG8[7:0]
7Eh DTG9 00h R/W DTG9[7:0]
7Fh DTH1 00h R/W DTH1[7:0]
80h DTH2 00h R/W DTH2[7:0]
81h DTH3 00h R/W DTH3[7:0]
82h DTH4 00h R/W DTH4[7:0]
83h DTH5 00h R/W DTH5[7:0]
84h DTH6 00h R/W DTH6[7:0]
85h DTH7 00h R/W DTH7[7:0]
86h DTH8 00h R/W DTH8[7:0]
87h DTH9 00h R/W DTH9[7:0]
88h DTI1 00h R/W DTI1[7:0]
89h DTI2 00h R/W DTI2[7:0]
8Ah DTI3 00h R/W DTI3[7:0]
8Bh DTI4 00h R/W DTI4[7:0]
2. Register Map (Continued)
OPERATION (Continued)
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 19 of 56
Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
8Ch DTI5 00h R/W DTI5[7:0]
8Dh DTI6 00h R/W DTI6[7:0]
8Eh DTI7 00h R/W DTI7[7:0]
8Fh DTI8 00h R/W DTI8[7:0]
90h DTI9 00h R/W DTI9[7:0]
91h A1 00h R/W BRTA1[3:0] -- SDTA1[2:0]
92h A2 00h R/W BRTA2[3:0] -- SDTA2[2:0]
93h A3 00h R/W BRTA3[3:0] -- SDTA3[2:0]
94h A4 00h R/W BRTA4[3:0] -- SDTA4[2:0]
95h A5 00h R/W BRTA5[3:0] -- SDTA5[2:0]
96h A6 00h R/W BRTA6[3:0] -- SDTA6[2:0]
97h A7 00h R/W BRTA7[3:0] -- SDTA7[2:0]
98h A8 00h R/W BRTA8[3:0] -- SDTA8[2:0]
99h A9 00h R/W BRTA9[3:0] -- SDTA9[2:0]
9Ah B1 00h R/W BRTB1[3:0] -- SDTB1[2:0]
9Bh B2 00h R/W BRTB2[3:0] -- SDTB2[2:0]
9Ch B3 00h R/W BRTB3[3:0] -- SDTB3[2:0]
9Dh B4 00h R/W BRTB4[3:0] -- SDTB4[2:0]
9Eh B5 00h R/W BRTB5[3:0] -- SDTB5[2:0]
9Fh B6 00h R/W BRTB6[3:0] -- SDTB6[2:0]
A0h B7 00h R/W BRTB7[3:0] -- SDTB7[2:0]
A1h B8 00h R/W BRTB8[3:0] -- SDTB8[2:0]
A2h B9 00h R/W BRTB9[3:0] -- SDTB9[2:0]
A3h C1 00h R/W BRTC1[3:0] -- SDTC1[2:0]
A4h C2 00h R/W BRTC2[3:0] -- SDTC2[2:0]
A5h C3 00h R/W BRTC3[3:0] -- SDTC3[2:0]
A6h C4 00h R/W BRTC4[3:0] -- SDTC4[2:0]
A7h C5 00h R/W BRTC5[3:0] -- SDTC5[2:0]
A8h C6 00h R/W BRTC6[3:0] -- SDTC6[2:0]
Note: Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
2. Register Map (Continued)
OPERATION (Continued)
Doc No.
TA4-EA-06028
Revision.
4
Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 20 of 56
Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
A9h C7 00h R/W BRTC7[3:0] -- SDTC7[2:0]
AAh C8 00h R/W BRTC8[3:0] -- SDTC8[2:0]
ABh C9 00h R/W BRTC9[3:0] -- SDTC9[2:0]
ACh D1 00h R/W BRTD1[3:0] -- SDTD1[2:0]
ADh D2 00h R/W BRTD2[3:0] -- SDTD2[2:0]
AEh D3 00h R/W BRTD3[3:0] -- SDTD3[2:0]
AFh D4 00h R/W BRTD4[3:0] -- SDTD4[2:0]
B0h D5 00h R/W BRTD5[3:0] -- SDTD5[2:0]
B1h D6 00h R/W BRTD6[3:0] -- SDTD6[2:0]
B2h D7 00h R/W BRTD7[3:0] -- SDTD7[2:0]
B3h D8 00h R/W BRTD8[3:0] -- SDTD8[2:0]
B4h D9 00h R/W BRTD9[3:0] -- SDTD9[2:0]
B5h E1 00h R/W BRTE1[3:0] -- SDTE1[2:0]
B6h E2 00h R/W BRTE2[3:0] -- SDTE2[2:0]
B7h E3 00h R/W BRTE3[3:0] -- SDTE3[2:0]
B8h E4 00h R/W BRTE4[3:0] -- SDTE4[2:0]
B9h E5 00h R/W BRTE5[3:0] -- SDTE5[2:0]
BAh E6 00h R/W BRTE6[3:0] -- SDTE6[2:0]
BBh E7 00h R/W BRTE7[3:0] -- SDTE7[2:0]
BCh E8 00h R/W BRTE8[3:0] -- SDTE8[2:0]
BDh E9 00h R/W BRTE9[3:0] -- SDTE9[2:0]
BEh F1 00h R/W BRTF1[3:0] -- SDTF1[2:0]
BFh F2 00h R/W BRTF2[3:0] -- SDTF2[2:0]
C0h F3 00h R/W BRTF3[3:0] -- SDTF3[2:0]
C1h F4 00h R/W BRTF4[3:0] -- SDTF4[2:0]
C2h F5 00h R/W BRTF5[3:0] -- SDTF5[2:0]
C3h F6 00h R/W BRTF6[3:0] -- SDTF6[2:0]
C4h F7 00h R/W BRTF7[3:0] -- SDTF7[2:0]
C5h F8 00h R/W BRTF8[3:0] -- SDTF8[2:0]
2. Register Map (Continued)
Note: Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
OPERATION (Continued)
Doc No.
TA4-EA-06028
Revision.
4
Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 21 of 56
Product Standards
ADDR Register
Name Default R/W DATA
D7 D6 D5 D4 D3 D2 D1 D0
C6h F9 00h R/W BRTF9[3:0] -- SDTF9[2:0]
C7h G1 00h R/W BRTG1[3:0] -- SDTG1[2:0]
C8h G2 00h R/W BRTG2[3:0] -- SDTG2[2:0]
C9h G3 00h R/W BRTG3[3:0] -- SDTG3[2:0]
CAh G4 00h R/W BRTG4[3:0] -- SDTG4[2:0]
CBh G5 00h R/W BRTG5[3:0] -- SDTG5[2:0]
CCh G6 00h R/W BRTG6[3:0] -- SDTG6[2:0]
CDh G7 00h R/W BRTG7[3:0] -- SDTG7[2:0]
CEh G8 00h R/W BRTG8[3:0] -- SDTG8[2:0]
CFh G9 00h R/W BRTG9[3:0] -- SDTG9[2:0]
D0h H1 00h R/W BRTH1[3:0] -- SDTH1[2:0]
D1h H2 00h R/W BRTH2[3:0] -- SDTH2[2:0]
D2h H3 00h R/W BRTH3[3:0] -- SDTH3[2:0]
D3h H4 00h R/W BRTH4[3:0] -- SDTH4[2:0]
D4h H5 00h R/W BRTH5[3:0] -- SDTH5[2:0]
D5h H6 00h R/W BRTH6[3:0] -- SDTH6[2:0]
D6h H7 00h R/W BRTH7[3:0] -- SDTH7[2:0]
D7h H8 00h R/W BRTH8[3:0] -- SDTH8[2:0]
D8h H9 00h R/W BRTH9[3:0] -- SDTH9[2:0]
D9h I1 00h R/W BRTI1[3:0] -- SDTI1[2:0]
DAh I2 00h R/W BRTI2[3:0] -- SDTI2[2:0]
DBh I3 00h R/W BRTI3[3:0] -- SDTI3[2:0]
DCh I4 00h R/W BRTI4[3:0] -- SDTI4[2:0]
DDh I5 00h R/W BRTI5[3:0] -- SDTI5[2:0]
DEh I6 00h R/W BRTI6[3:0] -- SDTI6[2:0]
DFh I7 00h R/W BRTI7[3:0] -- SDTI7[2:0]
E0h I8 00h R/W BRTI8[3:0] -- SDTI8[2:0]
E1h I9 00h R/W BRTI9[3:0] -- SDTI9[2:0]
Note: Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
OPERATION (Continued)
2. Register Map (Continued)
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 22 of 56
Product Standards
Register Name RST
AddressR/WD7D6D5D4D3D2D1D0
01hW------------RAMRSTSRST
Default 00h00000000
Register Name POWERCNT
AddressR/WD7D6D5D4D3D2D1D0
02hR/W--------------OSCEN
Default 00h00000000
D1 : RAMRST RAM reset
[0] : RAM can be overwrite (default)
[1] : Clear all PWM duty setting and intensity setting
D0 : SRST Soft reset control
[0] : Reset release state (default)
[1] : Reset reset
D0 : OSCEN Internal oscillator ON/OFF bit
[0] : Internal oscillator OFF (default)
[1] : Internal oscillator ON
This register will auto-return to zero when written with "High" logic value.
Oscillator will auto turn ON if any of the LED drivers are enabled (MTXON = 1) even if this bit is Low.
OPERATION (Continued)
3. Register map Detailed Explanation
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 23 of 56
Product Standards
Register Name OPTION
AddressR/WD7D6D5D4D3D2D1D0
04h R/W -- -- -- -- ZPDEN MLDACT CLKOUT EXTCLK
Default 00h00000000
Register Name MTXON
AddressR/WD7D6D5D4D3D2D1D0
05h R/W -- -- -- IMAX
Reserved IMAX[2:0] MTXON
Default 1Eh00011110
D3 : ZPDEN Ghost Image Prevention Enable
[0] : Turn off ghost image prevention (default)
[1] : Turn on ghost image prevention
D2 : MLDACT External Melody Input Selection
[0] : Turn off melody mode (default)
[1] : Turn on melody mode
D1 : CLKOUT Internal clock output enable
[0] : Internal clock is not output from CLKOUT (default)
[1] : Internal clock is output from CLKOUT
D0 : EXTCLK Internal/external synchronous clock selection
[0] : Internal clock operation (default)
[1] : External clock operation
• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color combination
and LED connection method. Please refer to page 53 for details.
Please refer to page 54 for details especially when this IC is used for RGB driver.
• For D2, D1 and D0 cannot be set to High at the same time. In such case, the priority of operation will be
EXTCLK then CLKOUT and then Melody Mode will have the least priority.
D3-1 : IMAX Maximum current setup selection
[000] : 7.5 mA [100] : 37.5 mA
[001] : 15 mA [101] : 45 mA
[010] : 22.5 mA [110] : 52.5 mA
[011] : 30 mA [111] : 60 mA (default)
D0 : MTXON LED Matrix Set up ON/OFF control
[0] : OFF (default)
[1] : ON
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
Doc No.
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Revision.
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:
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Revised
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AN32183A
Page 24 of 56
Product Standards
Register Name PWMEN1
AddressR/WD7D6D5D4D3D2D1D0
06h R/W PWMA8 PWMA7 PWMA6 PWMA5 PWMA4 PWMA3 PWMA2 PWMA1
Default 00h00000000
D7 : PWMA8 A8 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D6 : PWMA7 A7 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D5 : PWMA6 A6 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D4 : PWMA5 A5 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D3 : PWMA4 A4 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D2 : PWMA3 A3 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D1 : PWMA2 A2 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D0 : PWMA1 A1 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
The definition for register addresses #07h to #10h is the same as address #06h.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
Doc No.
TA4-EA-06028
Revision.
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:
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Revised
:
2014-01-29
AN32183A
Page 25 of 56
Product Standards
Register Name MLDEN1
AddressR/WD7D6D5D4D3D2D1D0
11h R/W MLDA8 MLDA7 MLDA6 MLDA5 MLDA4 MLDA3 MLDA2 MLDA1
Default 00h00000000
D7 : MLDA8 A8 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D6 : MLDA7 A7 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D5 : MLDA6 A6 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D4 : MLDA5 A5 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D3 : MLDA4 A4 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D2 : MLDA3 A3 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D1 : MLDA2 A2 Melody mode enable
[0] : Not PWM mode (default)
[1] : Melody mode
D0 : MLDA1 A1 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
The definition for register addresses #12h to #1Bh is the same as address #11h.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
Doc No.
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Revision.
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:
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Revised
:
2014-01-29
AN32183A
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Product Standards
D3 : GRP9_9 Column 9 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I9 H9 G9 F9 E9 D9 C9 B9 A9)
D2 : GRP9_8 Column 8 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I8 H8 G8 F8 E8 D8 C8 B8 A8)
D1 : GRP9_2 Column 2 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I2 H2 G2 F2 E2 D2 C2 B2 A2)
D0 : GRP9_1 Column 1 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I1 H1 G1 F1 E1 D1 C1 B1 A1)
Register Name MLDMODE1
AddressR/WD7D6D5D4D3D2D1D0
2Ah R/W -- -- -- -- GRP9_9 GRP9_8 GRP9_2 GRP9_1
Default 00h00000000
Threshold 4
Threshold 5
Threshold 6
Threshold 7
Threshold 8
Threshold 8
GRP9_1
GRP9_2
GRP9_8
GRP9_9
Threshold 1
Threshold 2
Threshold 3
A
B
C
D
E
F
G
H
I
12 3 4 56 7 89
During Bar Meter Mode, auto threshold detection should be used. This IC does not support Bar Meter
Mode with fixed threshold setting.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 27 of 56
Product Standards
Register Name THOLD
AddressR/WD7D6D5D4D3D2D1D0
2Bh R/W THOLD[7:0]
Default 00h00000000
D7 : THOLD[7] Threshold 8 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 8 is used. (Threshold 8 is about 1.93 V)
D6 : THOLD[6] Threshold 7 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 7 is used. (Threshold 7 is about 1.80 V)
D5 : THOLD[5] Threshold 6 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 6 is used. (Threshold 6 is about 1.67 V)
D4 : THOLD[4] Threshold 5 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 5 is used. (Threshold 5 is about 1.55 V)
D3 : THOLD[3] Threshold 4 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 4 is used. (Threshold 4 is about 1.42 V)
D2 : THOLD[2] Threshold 3 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 3 is used. (Threshold 3 is about 1.30 V)
D1 : THOLD[1] Threshold 2 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 2 is used. (Threshold 2 is about 1.17 V)
D0 : THOLD[0] Threshold 1 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 1 is used. (Threshold 1 is about 1.04 V)
When all bits are set zero, threshold is in auto-detection mode (default)
Do not set more than 1 register bit to logic "High" value at the same time.
If 2 bits are set to "High" at the same time, system will only recognize the first "High" bit threshold that is set.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2014-01-29
AN32183A
Page 28 of 56
Product Standards
D5 : X6 X6 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X6 is fixed as constant current mode. The LED A6’s current setting is used.
D4 : X5 X5 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X5 is fixed as constant current mode. The LED A5’s current setting is used.
D3 : X4 X4 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X4 is fixed as constant current mode. The LED A4’s current setting is used.
D2 : X3 X3 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X3 is fixed as constant current mode. The LED A3’s current setting is used.
D1 : X2 X2 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X2 is fixed as constant current mode. The LED A2’s current setting is used.
D0 : X1 X1 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X1 is fixed as constant current mode. The LED A1’s current setting is used.
Register Name CONSTX6_1
AddressR/WD7D6D5D4D3D2D1D0
2Ch R/W -- -- X6 X5 X4 X3 X2 X1
Default 00h00000000
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
D3 : X10 X10 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X10 is fixed as constant current mode. The LED I1’s current setting is used.
D2 : X9 X9 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X9 is fixed as constant current mode. The LED A9’s current setting is used.
D1 : X8 X8 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X8 is fixed as constant current mode. The LED A8’s current setting is used.
D0 : X7 X7 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X7 is fixed as constant current mode. The LED A7’s current setting is used.
Register Name CONSTX10_7
AddressR/WD7D6D5D4D3D2D1D0
2Dh R/W -- -- -- -- X10 X9 X8 X7
Default 00h00000000
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
D5 : Y6 Z6 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z6 turns on (VCC level).
D4 : Y5 Z5 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z5 turns on (VCC level).
D3 : Y4 Z4 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z4 turns on (VCC level).
D2 : Y3 Z3 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z3 turns on (VCC level).
D1 : Y2 Z2 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z2 turns on (VCC level).
D0 : Y1 Z1 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z1 turns on (VCC level).
Register Name CONSTY6_1
AddressR/WD7D6D5D4D3D2D1D0
2Eh R/W -- -- Y6 Y5 Y4 Y3 Y2 Y1
Default 00h00000000
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
D2 : Y9 Z9 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z9 turns on (VCC level).
D1 : Y8 Z8 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z8 turns on (VCC level).
D0 : Y7 Z7 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z7 turns on (VCC level).
Register Name CONSTY9_7
AddressR/WD7D6D5D4D3D2D1D0
2Fh R/W -- -- -- -- -- Y9 Y8 Y7
Default 00h00000000
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
Register Name MASKY6_1
AddressR/WD7D6D5D4D3D2D1D0
30h R/W -- -- Y6MSK Y5MSK Y4MSK Y3MSK Y2MSK Y1MSK
Default 00h00000000
D5 : Y6MSK Z6 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z6 turns off.
D4 : Y5MSK Z5 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z5 turns off.
D3 : Y4MSK Z4 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z4 turns off.
D2 : Y3MSK Z3 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z3 turns off.
D1 : Y2MSK Z2 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z2 turns off.
D0 : Y1MSK Z1 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z1 turns off.
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
Register Name MASKY9_7
AddressR/WD7D6D5D4D3D2D1D0
31h R/W -- -- -- -- -- Y9MSK Y8MSK Y7MSK
Default 00h00000000
D2 : Y9MSK Z9 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z9 turns off.
D1 : Y8MSK Z8 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z8 turns off.
D0 : Y7MSK Z7 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z7 turns off.
• Please refer to page 38 for details.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
Register Name SLPTIME
AddressR/WD7D6D5D4D3D2D1D0
32h R/W -- -- -- FADTIM SLOPEEXTL[1:0] SLOPEEXTH[1:0]
Default 00h00000000
D4 : FADTIM Fade out time control.
[0] : T3 = T1 (default)
[1] : T3 = T1 2
D3-2 : SLOPEEXTL T4 time extent control.
[00] : T4 = T1 (default)
[01] : T4 = T1 0.25
[10] : T4 = T1 0.5
[11] : T4 = T1 2
D1-0 : SLOPEEXTH T2 time extent control.
[00] : T2 = T1 (default)
[01] : T2 = T1 0.25
[10] : T2 = T1 0.5
[11] : T2 = T1 2
T1 T3T2 T4
This bit also affect in PWM fade out mode. Fade out time becomes 2 times of fade in time when FADTIM = 1.
T1 time is controlled by the register #91h to #E1h.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
Register Name MLDCOM
AddressR/WD7D6D5D4D3D2D1D0
33h R/W -- -- -- -- -- MLDCOM[2:0]
Default 03h00000011
D2-0 : MLDCOM LED Turn on time compensation in melody mode
[000] : 0s
[001] : 1.94 µs
[010] : 3.87 µs
[011] : 5.80 µs (default)
[100] : 7.74 µs
[101] : 9.67 µs
[110] : 11.6 µs
[111] : 13.5 µs
Register Name SCANSET
AddressR/WD7D6D5D4D3D2D1D0
36h R/W -- -- -- -- SCANSET[3:0]
Default 08h00001000
D3-0 : SCANSET SCAN number control
[0000] : Only scan the first column.
[0001] : Only scan the first 2 column.
[0010] : Only scan the first 3 column.
[0011] : Only scan the first 4 column.
[0100] : Only scan the first 5 column.
[0101] : Only scan the first 6 column.
[0110] : Only scan the first 7 column.
[0111] : Only scan the first 8 column.
[1000] : Scan all column. (default)
All other values will scan all column.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
D7-0 : DTA1 A1 PWM duty control.
[0000_0000] : 0%. (default)
[0000_0001] : 0.39%. (1/256)
[0000_0010] : 0.78%. (2/256)
[0000_0011] : 1.17%. (3/256)
…
[1111_1100] : 98.8%. (253/256)
[1111_1110] : 99.2%. (254/256)
[1111_1111] : 99.6%. (255/256)
Register Name DTA1
AddressR/WD7D6D5D4D3D2D1D0
40h R/W DTA1[7:0]
Default 00h00000000
This duty setting is only effective when PWMA1 is High.
The definition for register addresses #41h to #90h is the same as address #40h.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
Register Name A1
AddressR/WD7D6D5D4D3D2D1D0
91h R/W BRTA1[3:0] -- SDTA1[2:0]
Default 00h00000000
D7-4 : BRTA1 Luminance set up of LED A1 (in case of IMAX [2:0] = [011])
[0000] : 0 mA (default)
[0001] : 2 mA
[0010] : 4 mA
[0011] : 6 mA
[0100] : 8 mA
[0101] : 10 mA
…
[1010] : 20 mA
[1011] : 22 mA
[1100] : 24 mA
[1101] : 26 mA
[1110] : 28 mA
[1111] : 30 mA
D2-0 : SDTA1 (SCANSET = [11], default setting)
(1) Firefly Operation (PWMA1 = 0)
[000] : Constant current mode (default)
[001] : 0.248 s
[010] : 0.495 s
[011] : 0.99 s
[100] : 1.484 s
[101] : 1.979 s
[110] : 2.473 s
[111] : 2.968 s
(2) PWM Fade-in/out Operation (PWMA1 = 1)
[000] : Instant change mode (default)
[001] : 1.939 ms
[010] : 3.879 ms
[011] : 7.758 ms
[100] : 11.636 ms
[101] : 15.515 ms
[110] : 19.394 ms
[111] : 23.273 ms
T1 T3T2 T4
In case of PWM duty change from 0 to 255, the longest time is 255 23.273 ms = 5.957 s.
T1 time is also controlled by SCANSET in register #36h. The calculation method is as follow:
SCANSET = 0000 : T1 = 0.111 T_default
SCANSET = 0001 : T1 = 0.222 T_default
…
SCANSET = 0111 : T1 = 0.888 T_default
The definition for register addresses #92h to #E1h is the same as address #91h.
OPERATION (Continued)
3. Register map Detailed Explanation (Continued)
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Product Standards
MTXON X* Y*MSK Y* PWM* SDT* Operation Mode
0xxxx xOFF
1 1 x x x x X*CNT constant mode
101xx xOFF
1001x xTurn on with all A1, A2, A3, A4
10001 xPWM mode
1 0 0 0 0 !=0 Blinking mode
1 0 0 0 0 0 Constant current mode
• * for X*, PWM*, SDT* = 1 ~ 10, * for Y*MSK, Y* = 1 ~ 9.
OPERATION (Continued)
4. Operation Mode priority
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Product Standards
START condition
SDA
SCL
STOP condition
START or
repetitive START
condition
STOP or
repetitive START
condition
SCL
SDA
MSB
ACK ACK
12 789 123 –89
Sr
or
P
Sr
P
S
or
Sr
ACK signal from slave ACK signal from receiver
Completion of Byte Transfer &
Slave interruption.
5.1 Basic Rules
5.2 START and STOP conditions
When SDA signal changes from "High" to "Low" while SCL is "High" will trigger START condition. Whereas,
STOP condition will be triggered when SDA signal changes from "Low" to "High" while SCL is "High".
START condition and STOP condition are always formed by the master. After the START condition occurs, the
bus becomes busy state. After STOP condition occurs, the bus becomes free again.
5.3 Data Transfer
Length of each byte output to SDA line is always 8 bits. There is no limitation in the number of bytes that can
be transmitted at 1 time. Many bytes can be sent. The acknowledge bit is necessary for each byte. Data is
sequentially transmitted from most significant bit (MSB).
This IC, I2C-bus, is designed to correspond to the Standard-mode (100 kbps), Fast-mode(400 kbps) and
Fast-mode plus (1 000 kbps) devices in the version 03 of NXP's specification. However, it does not correspond to
the HS-mode (to 3.4 Mbps).
This IC will operate as a slave device in the I2C-bus system. This IC will not operate as a master device.
The program operation check of this IC has not been conducted on the multi-master bus system and the mix-
speed bus system, yet. The connected confirmation of this IC to the CBUS receiver also has not been checked.
Please confirm with our company if it will be used in these mode systems.
The I2C is the brand of NXP.
5. I2C Bus Interface
OPERATION (Continued)
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Product Standards
S Slave address Sub address
Stop condition
ACK : 0
Start condition Write mode : 0
Sub address
X data
Sub address
X+1 data
W A A Data byte A P
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
S Slave address Sub address
ACK : 0
Start condition Write mode : 0
W A A Data byte A
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
Data byte
8-bit
Sub address
X+m-1 data
Sub address
X+m data
Data byte A
8-bit
ACK : 0
Data byte
8-bit
ACK : 0
AP
A
ACK : 0
: Data transmission from Master
: Data transmission from Slave
Data byte can be written in Sub address by transmitting data byte continuously.
Sub address is incremented automatically.
Sub address is not incremented automatically.
The next data byte is written in the same Sub address by transmitting data byte continuously.
5.4 I2C Interface - Data Format
SLAVSEL Slave address
Low 1011 100X
High 1011 101X
SCL 1011 110X
SDA 1011 111X
Write mode
Write mode (Auto increment mode)
5. I2C Bus Interface (Continued)
OPERATION (Continued)
In this IC, 4 different Slave addresses can be changed by selecting SLAVSEL ( "Low" or "High" or "SCL" or "SDA").
The slave addresses of this IC are as follow:
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Product Standards
S Slave address Data byte
Stop condition
ACK : 0
Start condition Read mode : 1
RA A P
7-bit 8-bit
NACK : 1
S Slave address Sub address
ACK : 0
Start condition Write mode : 0
W A Sr Slave address A
7-bit 8-bit 7-bit
ACK : 0
Data byte
8-bit
A
NACK : 1
A PR
Stop conditionRepeated start condition Read mode : 1
ACK : 0
Sub address
X+m–1 data
Sub address
X+m data
Data byte A
8-bit
ACK : 0
Data byte
8-bit
NACK : 1
AP
S Slave address Sub address
ACK : 0
Start condition
W A Sr Slave address A
7-bit 8-bit 7-bit
ACK : 0
Data byte
8-bit
A
ACK : 0
A R
Repeated start condition Read mode : 1
ACK : 0
Sub address
X data
Stop condition
Write mode : 0
: Data transmission from Master
: Data transmission from Slave
Sub address is not incremented automatically.
The next data byte reads the same Sub address by transmitting data byte continuously.
When Sub address 8 bit is not specified and data is read, this IC allows to read the value of adjacent Sub
address specified in the last Write mode.
The next data byte reads the same Sub address by transmitting data byte continuously.
It is possible to read data byte in continuous Sub address by transmitting data byte continuously.
Sub address is incremented automatically.
5.4 I2C Interface - Data Format (Continued)
Read mode (in case Sub address is not specified)
Read mode (in case Sub address is specified)
Read mode (Auto increment mode)
5. I2C Bus Interface (Continued)
OPERATION (Continued)
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Product Standards
Oscillator 2.4 MHz
(PAD) CLKIO
(Register) EXTCLK
Logic block
(Matrix)
*Matrix operation, PWM control
1
0
6.2 Distribution diagram of control / clock system
VCC2
VLDO
VDD
PGND1
PGND2
LOGIC SCAN
SW I2C
BGR LED
Driver
Music
Sync
(Register) CLKOUT
TSD
VCC1
AGND
6.1 Distribution diagram of power supply
6. Signal distribution diagram
OPERATION (Continued)
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Product Standards
Connected
pin name
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
4321
D
C
B
A
87659
H
G
F
E
I
LED matrix driver circuit individually drives LED of 9 9 matrix. In total, the IC can drive and light up 81 LED.
In this specification, LED's number controlled by each pin corresponds as follows.
The internal logic circuit is operated by using an internal clock or the external clock input to the terminal CLKIO.
7. Block Configuration of Matrix LED
OPERATION (Continued)
7.1 Matrix LED descriptions, Matrix LED’s numbers
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Product Standards
Actual driver configuration is shown in the following figure.
The anode and cathode of each LED are connected to different Z pin as shown in figure below.
Z10 pin consists of only Current Sink and Slope control timing driver. Thus, LED anodes are not to be
connected to Z10 pin.
Please do not remove any of the LED inside the matrix if it is not used. If LED are to be removed, it is advised
to remove the entire row (e.g: all LED in row A) instead of removing only 1 LED. If only one LED in the row is
removed instead of the whole row, user needs to avoid using LED of which reverse breakdown voltage is
lower than the operating VCC level.
Internal control logic according to user register settings is used to control Y1 to Y9CNT(PMOS ON/OFF Scan
Switches) as well as X1 to X10CNT (Current sink value as well as PWM/Slope timing for lighting effects)
VCC / External DCDC
PWM
PWM
PWM
Y3CNT
Y4CNT
Y2CNT
Y1CNT
PWM
PWM
X2CNT
X4CNT
X3CNT
X5CNT
Matrix SCAN Switches
Current Sink with
Slope control timing
Z5
Z4
Z3
Z2
Z1
Control
Logic
Y5CNT
X1CNT
1234
A
B
C
D
7. Block Configuration of Matrix LED (Continued)
OPERATION (Continued)
7.2 Driver Configuration
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Product Standards
Scan period : 2,331 clks (approx 1.031 kHz @ 2.4 MHz Clock)
255 clks
Y1CNT
Y2CNT
Y3CNT
Y4CNT
Y5CNT
Y6CNT
Y7CNT
Y8CNT
Y9CNT
X1~
X10CNT
4 clks
Y4CNT
Y5CNT
X*CNT
Min Duty : 1clk (0.416 µs)Max Duty : 255clks (106.08 µs)
The figure below shows the timing chart when in operation.
Timing can be controlled according to the external clock frequency input to CLKIO pin.
In default condition, it is controlled by internal 2.4 MHz clock.
Y1 to Y9CNT are scan timing which is turned on one at a time. The ON period of each pin is constant 255 clks
(106.08 µs) and includes the interval of 4 clks (1.664 µs).
81 LED (9 9 matrix) are controlled by X1 to X10CNT according to below figure.
When Yx = Xx = Low, the actual waveform of Zx is set to Hi-Z.
Duty can be set using register DT*[7:0] from registers #40h to #90h. Additional brightness control is provided
through register BRT*[3:0] (registers #91h to #E1h).
7. Block Configuration of Matrix LED (Continued)
OPERATION (Continued)
7.3 Timing Chart when in operation
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Product Standards
No. Features Setting Range
1 Constant current mode IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
2PWM mode and Fade-in/out
mode
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Adjustable detention Time for each step : (1.939 ms to 23.273 ms / step)
3 Firefly mode
Fixed Current at 100% Duty IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Adjustable detention Time for each step : (0.248 s to 2.968 s / step)
4 Melody mode
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Each LED can synchronize with Music Input from CLKIO pin
5 Bar Meter Mode
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Group LED can synchronize with Music Input from CLKIO pin
Bar Meter Mode has more priority than Melody mode.
Maximum current setting value can be set up as 60mA using register IMAX[2:0] (register 05h). Brightness can
be set through the register BRT*[3:0] (register #91h to #E1h) for individual LED.
Example)
E.g. If user sets register IMAX[2:0](#05h) = 011 and BRT*[3:0](#91h to #E1h) = 1111, the current will be 30 mA.
E.g. If user sets register IMAX[2:0](#05h) = 111 and BRT*[3:0](#91h to #E1h) = 1111, the current will be 60 mA.
E.g. If user sets register IMAX[2:0](#05h) = 111 and BRT*[3:0](#91h to #E1h) = 0111, the current will be 28 mA.
8.1 Constant Current Mode
60 mA (max)
t
Current value
Functions Table for LED Driver
8. LED Driver Block Function
OPERATION (Continued)
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Product Standards
This operation is characterized by PWM signal having variable duty depending on register DT*[7:0]
(registers #40h to #90h). However, any changes in duty are not instantaneous, but rather it will step to the new
duty at time determined by register SDT*[2:0].
Example)
Case 1 : LED*DT(new) > LED*DT(old) (PWM Mode without Fade in/out control)
Case 2 : LED*DT(new) > LED*DT(old) (PWM Mode with Fade in control)
In Case 1, PWM duty has been changed from low to high duty. But the register SDT*[2:0] setting is [000]
indicating that there is no Fade in/out control. Therefore, PWM duty changes instantaneously. Users can see
that LED becomes brighter instantaneously once PWM duty has been changed.
In Case 2, PWM duty has also been changed from low to high duty. Unlike in case 1, the register SDT*[2:0]
setting is not [000] in case 2. Therefore, PWM duty has changed according to the register SDT*[2:0] setting.
This is called PWM mode with Fade in control. Users can see that LED becomes brighter slowly according to
the timing set in register SDT*[2:0].
t
SDT*[2:0] = [000]
LED*DT(new)
LED*DT(old)
Duty
t
SDT*[2:0] (not [000])
LED*DT(new)
LED*DT(old)
Duty
8. LED Driver Block Function (Continued)
OPERATION (Continued)
8.2 PWM Mode and Fade-in/out Mode
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DT*[7:0] is set through register #40h to #90h. FADTIM is set through register #32h. SDT*[2:0] is set through
register #91h to #E1h.
Example) (continued)
Case 3 : LED*DT(new) < LED*DT(old), FADTIM = 0 (PWM Mode with Fade out control)
t
SDT*[2:0] (not [000])
LED*DT(old)
LED*DT(new)
Duty
In Case 3, PWM duty has been changed from high to low duty. Unlike in case 1, the register SDT*[2:0] setting
is not [000] in case 3. Therefore, PWM duty has changed according to the register SDT*[2:0] setting. This is
called PWM mode with Fade out control. Users can see that LED becomes dimmer slowly according to the
timing set in register SDT*[2:0].
Case 4 : LED*DT(new) < LED*DT(old), FADTIM = 1 (PWM Mode with Fade out control)
t
SDT*[2:0] 2 (not [000])
LED*DT(old)
LED*DT(new)
Duty
In Case 4, PWM duty has also been changed from high to low duty. Unlike in case 3, the register FADTIM is
not [0]. Again, the register SDT*[2:0] setting is also not [000] in case 4. PWM duty has changed according to
the register SDT*[2:0] setting. Users can see that LED becomes dimmer slowly. It is slower than Case3 as
FADTIM register is high (2 times slower than Case 3 Fade out control).
8. LED Driver Block Function (Continued)
OPERATION (Continued)
8.2 PWM Mode and Fade-in/out Mode (Continued)
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This operation is characterized by PWM signal cycling from minimum to maximum duty and vice versa with
auto repeat function at time step determined by register SDT*[2:0]. Unlike PWM Fade in/out mode, firefly is
auto repetition of the sequence and thus creating LED blinking function effect.
t
256/256
Duty
0/256
STATE = 0 STATE = 1 STATE = 2 STATE = 3
SDT
256 steps
SDTH
64 steps
128 steps
256 steps
512 steps
FADTIM
256 steps
SDTL
64 steps
128 steps
256 steps
512 steps
Example)
Example 1 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 0
Example 2 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 1 (SDT 2)
Example 3 : SDTH = 01 (SDT 0.25), SDTL = 11 (SDT 2), FADTIM = 0
The SDTH is controlled by SLOPEEXTH[1:0] register, SDTL is controlled by SLOPEEXTL[1:0] register. All
these register, SLOPEEXTH[1:0], SLOPEEXTL[1:0] and FADTIM can be set through register #32h.
SDT*[2:0] registers are set individually through register #91h to #E1h. All other combinations of SDTH, SDTL
and FADTIM is possible.
t
Duty
t
Duty
t
Duty
8. LED Driver Block Function (Continued)
OPERATION (Continued)
8.3 Firefly Control
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8. LED Driver Block Function (Continued)
Case 1 : CLKIO as output pin
CLKIO output internal frequency by using
CLKOUT register
Case 2 : CLKIO as input for external clock
CLKIO uses as external input by using
EXTCLK register
Case 3 : CLKIO as input for music signal during melody mode
CLKIO uses as music input when melody mode
is enabled by register MLDACT from register 04h.
Melody mode is to synchronize LED to external music signal. Melody mode can be set through register
MLDACT from register 04h. Each of the 16 LED matrix can be individually enabled for external music
synchronization through register data (address #08h to #09h when register address 04h is set as data 04h).
External Music Signal can be injected from CLKIO pin. CLKIO pin serve as both input and output. CLKIO pin
can output internal oscillator frequency by using CLKOUT register (register 04h).
CLKIO pin can be used as input for external signal by using EXTCLK register (register 04h). External clock
frequency is typically 2.4 MHz. It is advisable to use external clock frequency from 1.2 MHz to 4.8 MHz.
Please do not set MLDACT, EXTCLK and CLKOUT register to "High" at the same time. In such case, the
priority of operation will be EXTCLK then CLKOUT and then Melody Mode will have the least priority.
CLKIO
2.4 MHz
External
Signal
1.2 to 4.8MHz
CLKIO
AC music
signal
CLKIO
Note : If input CLKIO voltage is higher than VDD, there will be back flow current to VDD. It can be calculated as below :
(VCLKIO –0.7 V –VDD)
IBackFlow =
393 k
Cin
Note : Cin can be calculated as below : In case of that the applicable music frequency is 20 Hz.
1
Cin >= = 45.5 nF
( 20 Hz ) x 2 x 3.14 x 175 k
OPERATION (Continued)
8.4 Melody Mode Explanation
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AC music signal input from CLKIO pin will be compared with internal threshold setting. Based on the
comparison of music signal and threshold voltage, PWM driver control will change and control the LED
ON/OFF. Therefore, LED light ON/OFF control will synchronize with music tempo while LED brightness will
synchronize with music loudness. There are two threshold modes, one is auto threshold and the other is fixed
threshold mode.
There are 8 threshold voltage levels in this IC as defined in the register 2Bh (THOLD[7:0]). Auto threshold
mode means that the 8 threshold voltages will be scanned automatically from the lowest to highest threshold
voltages at a fixed frequency higher than audio frequency. Input music signal will be compared with these
scanning threshold voltages to control PWM Driver in order to have music synchronization effects. This mode
allows user to easily use music synchronize function without having the trouble of manually setting the
detection threshold. When melody mode is enabled, auto threshold mode will be the default mode.
Fixed threshold mode means that the threshold voltage is fixed at one threshold level. It can be set using
register 2Bh (THOLD[7:0]). Input music signal will be compared with this fixed threshold voltage set by the
user. During fixed threshold mode, do not set more than 1 register bit to logic "High" value at the same time. If
user set more register bits to logic "High" after setting 1 register bit to “High”, system will only recognise the
first "High" bit threshold that is set. In this mode, user can have the flexibility to configure different threshold
voltage levels to achieve the desired LED music synchronizing visual effect according to the system music
input level.
It is also advised that AC music signal peak to peak voltage to be at least 0.35 V and not more than 2.8 V.
Example of Fixed threshold mode
Additional brightness compensation in melody mode can be achieved by increasing or decreasing the turning
on period of LED. Using brightness compensation register MLDCOM[2:0] (#33h), LED turning on period can
be controlled and LED can become brighter or dimmer.
This additional brightness compensation will be effective only in auto threshold mode. If fixed threshold mode
is used, this register will not be able to control LED brightness.
PWM Driver
Constant current
AC music signal
& fixed
Threshold voltage
t
Brightness Compensation in Melody Mode
8. LED Driver Block Function (Continued)
OPERATION (Continued)
8.4 Melody Mode Explanation (Continued)
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In the above diagram, column 1 = group1, column 2 = group2, column 8 = group8 and column 9 = group9.
Each group can be enabled through register GRP9_1, 9_2, 9_8, 9_9 (address #2Ah). The LED in the all
groups will be synchronized to threshold signals as follow:
Bar Meter Mode operation is another method of external melody mode wherein a group of LEDs are used
instead of individual LED. Bar Meter Mode has higher priority than individual LED melody mode.
All other LEDs not in Bar Meter Mode can operate in individual external melody mode or other modes.
During Bar Meter Mode, auto threshold detection should be used. This IC does not support Bar Meter Mode
with fixed threshold setting. It is also recommended not to use other modes together with Bar Meter Mode of
LED in group 1, 2, 8 & 9 (i.e. LED A to I1, 2, 8, 9)
Threshold Signal Bar Meter Mode Group LED ON
Threshold 1 Row's I
Threshold 2 Row's H, I
Threshold 3 Row's G, H, I
Threshold 4 Row's F, G, H, I
Threshold 5 Row's E, F, G, H, I
Threshold 6 Row's D, E, F, G, H, I
Threshold 7 Row's C, D, E, F, G, H, I
Threshold 8 Row's A, B, C, D, E, F, G, H, I
Threshold 4
Threshold 5
Threshold 6
Threshold 7
Threshold 8
Threshold 8
GRP9_1
GRP9_2
GRP9_8
GRP9_9
Threshold 1
Threshold 2
Threshold 3
A
B
C
D
E
F
G
H
I
12 3 4 56 7 89
8. LED Driver Block Function (Continued)
OPERATION (Continued)
8.5 Bar Meter Mode Explanation
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Ghost images sometimes appear during LED matrix mode operation. Very dim light can appear in some LED
even during OFF condition. This is called Ghost Image. In this IC, Ghost Image Prevention Function is
included to reduce Ghost Image effect. Ghost Image Prevention Function can be enabled through register
ZPDEN (register 04h).
• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color combination
and LED connection method.
During normal operation, ghost discharge signal will be always low. When ghost image prevention function is
enabled through register 04h, ghost discharge signal will turn on for 2 clks cycle during 4 clks dead time
between each YCNT. During on period of 2 clks cycle, output Z pin will be forced to half of VCC.
Y1CNT
Y2CNT
Y3CNT
Y4CNT
Ghost
discharge
Signals
4 clks
Y4CNT
Y5CNT
Y5CNT
Y6CNT
2 clks
Ghost
discharge
Signals
Ghost Discharge Disabled Ghost Discharge Enabled
Ghost discharge signal turns on for 2 clks
during dead time between Y*CNT.
OPERATION (Continued)
9. Ghost Image Prevention Function
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9. Ghost Image Prevention Function (Continued)
Example of RGB LED connection
To minimize ghost image, it is recommended to use LED with same forward voltage drop in LED panel. If user
wants to use LED with different forward voltage drop in LED panel (e.g. RGB LED in LED panel), it is
recommended that all the cathodes of LED connected to the same pin must have same forward voltage drop.
(i.e. same colour LED sharing the same cathode). A recommended RGB LED connection to minimize ghost
image is shown in diagram below.
OPERATION (Continued)
Connected
pin name
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
LED1-B LED1-G LED1-R LED2-RLED2-GLED2-B LED3-B LED3-RLED3-G
LED5-R
LED5-B LED5-G
1
3
4
8
5 6
7
10
12
11
9
21
2013
15
19
17
16
14
18
22
LED4-R
LED4-B LED4-G
LED6-R
LED6-B LED6-G LED7-R
LED7-B LED7-G
LED10-R
LED10-B LED10-G LED9-R
LED9-B LED9-G
LED8-B LED8-R LED8-G
LED11-R
LED11-B LED11-G LED12-R
LED12-B LED12-G
LED13-R
LED13-B LED13-G LED14-R
LED14-B LED14-G
LED15-R LED15-G
LED15-B
LED16-R
LED16-B LED16-G
LED18-R
LED18-B LED18-G
LED21-R
LED21-B LED21-G LED22-R
LED22-B LED22-G
LED19-R
LED19-B LED19-G
LED17-R
LED17-G LED17-B
LED20-R
LED20-B LED20-G
2
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Product Standards
PACKAGE INFORMATION (Reference Data)
Unit:mm
Lead Finish Method : SnBi Plating
Lead Material : Cu Alloy
Body Material : Br/Sb Free Epoxy resin
Package Code : SSOP024-P-0300F
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Product Standards
IMPORTANT NOTICE
1. When using the IC for new models, verify the safety including the long-term reliability for each product.
2. When the application system is designed by using this IC, please confirm the notes in this book.
Please read the notes to descriptions and the usage notes in the book.
3. This IC is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which exceptional
quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automotive, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
Our company shall not be held responsible for any damage incurred as a result of or in connection with the IC being used for
any special application, unless our company agrees to the use of such special application.
However, for the IC which we designate as products for automotive use, it is possible to be used for automotive.
4. This IC is neither designed nor intended for use in automotive applications or environments unless the IC is designated by our
company to be used in automotive applications.
Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in
connection with the IC being used in automotive application, unless our company agrees to such application in this book.
5. Please use this IC in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage
incurred as a result of our IC being used by our customers, not complying with the applicable laws and regulations.
6. Pay attention to the direction of the IC. When mounting it in the wrong direction onto the PCB (printed-circuit-board),
it might be damaged.
7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins.
In addition, refer to the Pin Description for the pin configuration.
8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as
solder-bridge between the pins of the IC. Also, perform full technical verification on the assembly quality, because the same
damage possibly can happen due to conductive substances, such as solder ball, that adhere to the IC during transportation.
9. Take notice in the use of this IC that it might be damaged when an abnormal state occurs such as output pin-VCC short
(Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short). Safety measures such as
installation of fuses are recommended because the extent of the above-mentioned damage will depend on the current
capability of the power supply.
10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the IC might be
damaged before the thermal protection circuit could operate.
11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the
pins because the IC might be damaged, which could happen due to negative voltage or excessive voltage generated during
the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
12. Verify the risks which might be caused by the malfunctions of external components.
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Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-
provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
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