REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
PIN NAMES
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
Pin Name Function
A0 ~ A12 Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CB0 ~ CB7 Check bit (Data-in/data-out)
CLK0 Clock input
CKE0 Clock enable input
CS0 ~ CS3 Chip select input
RAS Row address strobe
CAS Colume address strobe
WE Write enable
DQM0 ~ 7 DQM
VDD Power supply (3.3V)
VSS Ground
*VREF Power supply for reference
REGE Register enable
SDA Serial data I/O
SCL Serial clock
SA0 ~ 2 Address in EEPROM
DU Don′t use
NC No connection
*WP Write protection
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
*VREF
*CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
*CLK2
NC
*WP
**SDA
**SCL
VDD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
*CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
DQ52
NC
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
*CLK3
NC
**SA0
**SA1
**SA2
VDD
The Samsung M390S2858DT1 is a 128M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung M390S2858DT1 consists of eighteen CMOS Stacked
128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil pack-
ages, three 18-bits Drive ICs for input control signal, one PLL
in 24-pin TSSOP package for clock and one 2K EEPROM in 8-
pin TSSOP package for Serial Presence Detect on a 168-pin
glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-
pling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The M390S2858DT1 is a Dual In-
line Memory Module and is intented for mounting into 168-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
GENERAL DESCRIPTION
M390S2858DT1 SDRAM DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
FEATURE
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
• Performance range
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,700mil), double sided component
Part No. Max Freq. (Speed)
M390S2858DT1-C7C 133MHz(7.5ns @ CL=2)
M390S2858DT1-C7A 133MHz (7.5ns @ CL=3)
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
REGE Register enable
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins.
CB0 ~ 7 Check bit Check bits for ECC.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
10Ω
CB4~7
10Ω
CB0~3
10Ω
DQ12~15
10Ω
DQ8~11
FUNCTIONAL BLOCK DIAGRAM
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D0L
10Ω
10Ω
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D0U
BCS1,B2CKE0
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D1L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D1U
DQ0~3
DQ4~7
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D9L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D9U
DQ32~35
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D10L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D10U
DQ36~39
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D2L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D2U
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D3L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D3U
PCLK2
BDQM1
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D4L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D4U
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D11L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D11U
DQ40~43
BDQM5
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D12L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D12U
DQ44~47
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D13L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D13U
10Ω
DQ28~31
10Ω
DQ24~27
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D5L
PCLK5
BDQM2
10Ω
10Ω
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D5U
CLK
CS1
CTL
Add
DQM
DQ0~3
D6L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D6U
DQ16~19
DQ20~23
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D14L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D14U
DQ48~51
BDQM6
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D15L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D15U
DQ52~55
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D7L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D7U
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D8L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D8U
PCLK7
BDQM3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D16L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D16U
DQ56~59
BDQM7
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D17L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D17U
DQ60~63
BDQM4
A3~A10,BA0 B0A3~B0A10,B0BA0
74ALVCF162835
CS2,CS3
CKE0
DQM2,3,6,7
VDD
10kΩ
OE
LE
74ALVCF162835
OE
LE
PCLK9
REGE
BCS2,BCS3
B0CKE0,B1CKE0
B2CKE0,B3CKE0
BDQM2,3,6,7
74ALVCF162835
OE
LE
A0,A1,A2
RAS,CAS,WE
CS0,CS1
DQM0,1,4,5
CDCF2510
G
AGND
AVDD
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
CLK
FBIN
VSS
10Ω
VDD
CLK0 12pF FBOUT
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9
PCLK8
PCLK6
PCLK1
PCLK3
PCLK4
BCS0,B0CKE0
BCS2,B1CKE0
B1A0~B1A12
B0RAS,B0CAS,B0WE,B0BA0,B0BA1
B0A0~B0A12
PCLK0
BDQM0
BCS3,B3CKE0
B1A3~B1A10,B1BA0
A11,A12,BA1 B0A11,B0A12.B0BA1
B1A11,B1A12.B1BA1
CS2,CS3
CKE0
DQM2,3,6,7
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0,BCS1
BDQM0,1,4,5
B
1RAS,B1CAS,B1WE,B1BA0,B1BA1
10Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
Serial PD
SDA
SCL
A1 A2A0
SA1 SA2SA0
WP
47K
Ω
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3 DOUT
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
*1. Register Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
ReadRow Active Command Row Active Write
Command Precharge
Command
1CLK
td tr td tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD36 W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 3.0 3.3 3.6 V
Input high voltage VIH 2.0 3.0 VDDQ+0.3 V1
Input low voltage VIL -0.3 00.8 V2
Output high voltage VOH 2.4 - - VIOH = -2mA
Output low voltage VOL - - 0.4 VIOL = 2mA
Input leakage current ILI -10 -10 uA 3
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Parameter Symbol Min Max Unit
Input capacitance (A0 ~ A12)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
Input capacitance (CLK0)
Input capacitance (CS0, CS2)
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance (DQ0 ~ DQ63)
Data input/output capacitance (CB0 ~ CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT1
-
-
-
-
-
-
-
-
-
15
15
15
20
15
15
15
22
22
pF
pF
pF
pF
pF
pF
pF
pF
pF
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
-7C -7A
Operating current
(One bank active) ICC1 Burst length =1
tRC ≥ tRC(min)
IO = 0 mA 2840 2660 mA 1
Precharge standby current in
power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 422 mA 3
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞74
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 1070 mA 3
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 362
Active standby current in
power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 566 mA 3
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞218
Active standby current in
non power-down mode
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 1430 mA 3
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 902 mA 3
Operating current
(Burst mode) ICC4
IO = 0mA
Page Burst
4 Banks activated
tCCD=2CLK
3020 3020 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 5000 4640 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 458 mA 3
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 3 Drive ICs.
4. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Notes :
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
Notes :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
-7C -7A
Row active to row active delay tRRD(min) 15 15 ns 1
RAS to CAS delay tRCD(min) 15 20 ns 1
Row precharge time tRP(min) 15 20 ns 1
Row active time tRAS(min) 45 45 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 60 65 ns 1
Last data in to row precharge tRDL(min) 2CLK 2,5
Last data in to Active delay tDAL(min) 2 CLK + tRP -5
Last data in to new col. address delay tCDL(min) 1CLK 2
Last data in to burst stop tBDL(min) 1CLK 2
Col. address to col. address delay tCCD(min) 1CLK 3
Number of valid output data CAS latency=3 2ea 4
CAS latency=2 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol -7C -7A Unit Note
Min Max Min Max
CLK cycle time CAS latency=3 tCC 7.5 1000 7.5 1000 ns 1
CAS latency=2 7.5 10
CLK to valid
output delay CAS latency=3 tSAC 5.4 5.4 ns 1,2
CAS latency=2 5.4 6
Output data
hold time CAS latency=3 tOH 3 3 ns 2
CAS latency=2 3 3
CLK high pulse width tCH 2.5 2.5 ns 3
CLK low pulse width tCL 2.5 2.5 ns 3
Input setup time tSS 1.5 1.5 ns 3
Input hold time tSH 0.8 0.8 ns 3
CLK to output in Low-Z tSLZ 1 1 ns 2
CLK to output
in Hi-Z CAS latency=3 tSHZ 5.4 5.4 ns
CAS latency=2 5.4 6
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A12,A11,
A9 ~ A0Note
Register Mode register set HXL L L L XOP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit LHLH H H X X 3
HX X X 3
Bank active & row addr. HXL L H H X V Row address
Read &
column address Auto precharge disable HXLHLHX V LColumn
address
(A0~A9, A11)
4
Auto precharge enable H4,5
Write &
Column Address Auto precharge disable HXLHLLX V LColumn
address
(A0~A9, A11)
4
Auto precharge enable H4,5
Burst stop HXLH H LX X 6
Precharge Bank selection HXL L HLXVLX
All banks XH
Clock suspend or
active power down Entry HLHX X X XX
LV V V
Exit LHX X X X X
Precharge power down mode
Entry HLHX X X X
X
LH H H
Exit LHHX X X X
LV V V
DQM HV X 7
No operation command HXHX X X X X
LH H H
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S510632D
- The used device is stacked 128Mx4 SDRAM
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
PACKAGE DIMENSIONS
5.250
5.014
Units : Inches (Millimeters)
0.254 Max
0.050 ± 0.0039
(1.270 ± 0.10)
R 0.079
(R 2.000)
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.100 Min
(2.540 Min)
0.700
(17.780)
.118DIA ± 0.004
(3.000DIA ± 0.100)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.700
(43.18)
0.118
(3.000)
0.157 Min
(3.99 Min)
(6.452 Max)
B
REG
REG PLLREG
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
0.100 Min
(2.540 Min)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
Byte # Function described Function Supported Hex value Note
-7C -7A -7C -7A
0# of bytes written into serial memory at module manufacturer 128bytes 80h
1Total # of bytes of SPD memory device 256bytes (2K-bit) 08h
2Fundamental memory type SDRAM 04h
3# of row address on this assembly 13 0Dh 1
4# of column address on this assembly 11 0Bh 1
5# of module Rows on this assembly 2 Rows 02h
6Data width of this assembly 72 bits 48h
7...... Data width of this assembly -00h
8Voltage interface standard of this assembly LVTTL 01h
9SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2
10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2
11 DIMM configuration type ECC 02h
12 Refresh rate & type 7.8us, support self refresh 82h
13 Primary SDRAM width x4 04h
14 Error checking SDRAM width x4 04h
15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h
16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh
17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h
18 SDRAM device attributes : CAS latency 2 & 3 06h
19 SDRAM device attributes : CS latency 0 CLK 01h
20 SDRAM device attributes : Write latency 0 CLK 01h
21 SDRAM module attributes Registered/Buffered DQM,
address & control inputs and
On-card PLL 1Fh
22 SDRAM device attributes : General +/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge 0Eh
23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 75h A0h 2
24 SDRAM access time @CAS latency of 2 5.4ns 6ns 54h 60h 2
25 SDRAM cycle time @CAS latency of 1 - - 00h 00h 2
26 SDRAM access time @CAS latency of 1 - - 00h 00h 2
27 Minimum row precharge time (=tRP)15ns 20ns 0Fh 14h
28 Minimum row active to row active delay (tRRD)15ns 15ns 0Fh 0Fh
29 Minimum RAS to CAS delay (=tRCD)15ns 20ns 0Fh 14h
30 Minimum activate precharge time (=tRAS)45ns 45ns 2Dh 2Dh
31 Module Row density 2 Rows of 512MB 80h
32 Command and Address signal input setup time 1.5ns 15h
33 Command and Address signal input hold time 0.8ns 08h
34 Data signal input setup time 1.5ns 15h
M390S2858DT1-C7A/C7C
•Organization : 128MX72
•Composition : 128MX4 * 18ea
•Used component part # : K4S510632D-TC75/C7C
•# of banks in module : 2 Rows
•# of banks in component : 4 banks
•Feature : 1,700 mil height & double sided
•Refresh : 8K/64ms
•Contents :
REV. 0.0 Jan. 2002
M390S2858DT1 PC133 Registered DIMM
SERIAL PRESENCE DETECT INFORMATION
Byte # Function described Function Supported Hex value Note
-7C -7A -7C -7A
35 Data signal input hold time 0.8ns 08h
36~61 Superset information (maybe used in future) -00h
62 SPD data revision code JEDEC 2 02h
63 Checksum for bytes 0 ~ 62 -ECh 2Dh
64 Manufacturer JEDEC ID code Samsung CEh
65~71 ...... Manufacturer JEDEC ID code Samsung 00h
72 Manufacturing location Onyang Korea 01h
73 Manufacturer part # (Memory module) M4Dh
74 Manufacturer part # (DIMM Configuration) 333h
75 Manufacturer part # (Data bits) Blank 20h
76 ...... Manufacturer part # (Data bits) 939h
77 ...... Manufacturer part # (Data bits) 030h
78 Manufacturer part # (Mode & operating voltage) S53h
79 Manufacturer part # (Module depth) 232h
80 ...... Manufacturer part # (Module depth) 838h
81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 535h
82 Manufacturer part # (Composition component) 838h
83 Manufacturer part # (Component revision) D44h
84 Manufacturer part # (Package type) T54h
85 Manufacturer part # (PCB revision & type) 131h
86 Manufacturer part # (Hyphen) " - " 2Dh
87 Manufacturer part # (Power) C43h
88 Manufacturer part # (Minimum cycle time) 7 7 37h 37h
89 Manufacturer part # (Minimum cycle time) CA43h 41h
90 Manufacturer part # (TBD) Blank 20h
91 Manufacturer revision code (For PCB) 131h
92 ...... Manufacturer revision code (For component) D-die (5th Gen.) 44h
93 Manufacturing date (Year) - - 3
94 Manufacturing date (Week) - - 3
95~98 Assembly serial # - - 4
99~125 Manufacturer specific data (may be used in future) Undefined -5
126 System frequency for 100MHz 100MHz 64h
127 Intel Specification details Detailed 100MHz Information 8Fh
128+ Unused storage locations Undefined -5
1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung’s own purpose.
Note :
