Intel-Based Electronic Classroom Student Computing Station Based on the Intel(R) CeleronTM Processor and Intel(R) 810 Chipset Reference Configuration August 2000 Order Number: 273292-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) CeleronTM and Pentium(R) II processors, 810 Chipset, and 82559 ethernet controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright(c) Intel Corporation, 2000 *Other brands and names are the property of their respective owners. Application Note Intel-Based Electronic Classroom Student Computing Station Contents 1.0 Introduction ......................................................................................................................5 1.1 1.2 1.3 Purpose .................................................................................................................5 Terminology........................................................................................................... 5 Revision History .................................................................................................... 5 2.0 Intel-Based Electronic Classroom Environment Overview ..........................................6 3.0 Intel-Based Electronic Classroom Setup and Operating Environment.......................7 3.1 Intel-Based Electronic Classroom Configuration................................................... 8 3.1.1 Network Environment ............................................................................... 8 3.1.2 Teacher Station Management System ..................................................... 9 3.1.3 Multimedia Teaching Software ................................................................. 9 3.1.4 Application Software............................................................................... 10 3.1.5 Remote Booting Intel-Based Electronic Classroom Student Computing Stations from Server ............................................................ 10 4.0 Recommended Motherboard Configuration for Intel-Based Electronic Classroom Student Computing Stations................................................... 11 5.0 Design Consideration of Intel-Based Electronic Classroom Student Computing Station Hardware .........................................................................13 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Intel(R) CeleronTM Processor ................................................................................. 13 5.1.1 Design Notes for the Intel(R) CeleronTM Processor .................................. 13 Intel(R) 810 Chipset ............................................................................................... 14 5.2.1 The Intel(R) 82810 Graphics Memory Controller Hub (GMCH0) ..............15 5.2.1.1 Design Notes for the Intel(R) 82810 GMCH0............................... 15 5.2.2 The Intel(R) 82801 I/O Controller Hub (ICH).............................................16 5.2.2.1 Design Notes for the Intel(R) 82801 ICH...................................... 16 IDE Connectors ................................................................................................... 17 AC'97 2.1 Compliant Components ...................................................................... 17 5.4.1 Design Notes for AC'97 Devices ............................................................ 18 Audio/Modem Riser Card (AMR).........................................................................18 5.5.1 Design Notes for the Audio/Modem Riser Card ..................................... 18 PCI ......................................................................................................................19 Network Controller -- Intel(R) 82559 Fast Ethernet Controller .............................. 19 5.7.1 Design Note for the Intel(R) 82559 Fast Ethernet Controller .................... 19 5.7.2 Wired for Management........................................................................... 21 5.7.2.1 Instrumentation.......................................................................... 21 5.7.2.2 Remote Service Boot ................................................................ 22 5.7.2.3 Remote Wake-Up ...................................................................... 22 5.7.2.4 Power Management ..................................................................22 Low Pin Count (LPC) Interface............................................................................ 22 6.0 Conclusion......................................................................................................................23 A References ......................................................................................................................25 B Intel-Based Electronic Classroom Schematics ...........................................................27 Application Note 3 Intel-Based Electronic Classroom Student Computing Station Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Typical Intel-Based Electronic Classroom Setup .................................................. 7 Building Block of the Intel-Based Electronic Classroom Student Computing Station Motherboard ......................................................................... 12 Topology for Single Processor Designs with Single End Termination (SET) ...... 13 Placement of Termination Resistor ..................................................................... 20 Trace Geometry .................................................................................................. 20 Cover Sheet Schematic ...................................................................................... 28 Block Diagram ..................................................................................................... 29 370-Pin Socket (Part 1) ....................................................................................... 30 370-Pin Socket (Part 2) ....................................................................................... 31 GTL Terminal Schematic .................................................................................... 32 Clock Synthesizer Schematic.............................................................................. 33 82810, Part 1: Host Interface Schematic ............................................................ 34 82810, Part 2: System Memory and Hub Interface Schematic ........................... 35 82810, Part 3: Graphics Schematic .................................................................... 36 System Memory Schematic ................................................................................ 37 82810AA, Part 1 Schematic ................................................................................ 38 82810AA, Part 2 Schematic ................................................................................ 39 Firmware Hub (FWH) Schematic ........................................................................ 40 Super I/O Schematic ........................................................................................... 41 PCI Connector Schematic ................................................................................... 42 ATA/33 IDE Connectors Schematic .................................................................... 43 USB Connectors Schematic................................................................................ 44 Parallel Port Header Schematic .......................................................................... 45 Serial Port/Com Headers Schematic .................................................................. 46 Keyboard/Mouse Ports, Floppy Disk Header, Game Post Header Schematic ... 47 Video Connectors Schematic .............................................................................. 48 Audio Riser Schematic ........................................................................................ 49 LAN Schematic ................................................................................................... 50 LAN Schematic ................................................................................................... 51 Voltage Regulators.............................................................................................. 52 Processor Voltage Regulator Schematic ............................................................ 53 System Schematic .............................................................................................. 54 System: Power Connector and Reset Control Schematic................................... 55 Pull-Up Resistors and Unused Gates Schematic................................................ 56 730-Pin Socket Decoupling Schematic ............................................................... 57 DRAM, Chipset and Bulk Power Decoupling Schematic .................................... 58 Revision History Schematic ................................................................................ 59 Tables 1 2 4 Intel-Based Electronic Classroom Hardware Descriptions and Recommended Configuration ............................................................................... 8 AC'97 Configuration Combinations ..................................................................... 17 Application Note Intel-Based Electronic Classroom Student Computing Station 1.0 Introduction 1.1 Purpose This application note describes how Intel(R) architecture processors, chipsets, and other components can be used in designs for Intel-based electronic classroom student computing stations. An Intel-based electronic classroom is an educational setting in which a network of computers is used as a primary teaching, learning, and assessment tool. A typical Intel-based electronic classroom contains an instructor's system that broadcasts application software to, and often receives data from, student computing stations. The student computing stations can be configured and administered at the server level. Intel architecture components are well-suited for Intel-based electronic classroom systems. Using PC-based building blocks in these designs provides flexibility, upgradability, ease of administration, and high performance for graphic-intensive and internet applications. In addition, Intel architecture processors are compatible with a wide variety of operating system and off-the-shelf application software. This application note describes a typical Intel-based electronic classroom network and provides a reference design for Intel architecture-based electronic classroom student computing stations. Schematics for the reference design are provided in Appendix B of this document. 1.2 Terminology The following terms are used in this document. 1.3 Term Definition Intel-Based Electronic Classroom An electronic teaching and learning environment that uses dedicated, connected student computing stations to implement a specific educational curriculum Remote boot A client operating system boot up from a server in a network environment TCO Total cost of ownership ISV Independent software vendor WfM Intel's Wired for Management initiative Revision History Revision Date Notes 001 October 15, 1999 Initial version. Application Note 5 Intel-Based Electronic Classroom Student Computing Station 2.0 Intel-Based Electronic Classroom Environment Overview An Intel-based electronic classroom is a teaching and learning environment that uses a server-client system in the classroom to implement the curriculum. Teaching and learning is done using a teacher station, student computing stations, and specific educational software applications and content. With this modern educational technology, educators can deliver intuitive online courses, training, demonstrations, and examinations. They can also incorporate access to the Internet and intranet to enrich the educational experience. An Intel-based electronic classroom LAN environment can consist of up to 60 student computing stations, a teacher station, and a network server. In an Intel-based electronic classroom, every student computing station is administered centrally. These student computing stations have high reliability and security, and low maintenance costs. The student computing stations have a subset of a PC feature set: they typically have a different motherboard configuration (described in Section 4.0) and are configured without a CD-ROM drive or hard disk. This solution provides a greater access to the necessary technology while simplifying maintenance and reducing the total cost of ownership. In schools, PCs can be used in teacher offices as productivity tools for administration and development of teaching materials. These materials may then be used in Intel-based electronic classrooms to teach subjects such as computer skills, languages, sciences, and mathematics. The teacher uses the teacher station in the Intel-based electronic classroom to guide students through the lesson, while each student follows the lesson on his/her own student computing station. The students can also use their student computing stations independently to practice lesson materials and learn other application software. Desirable features of Intel-based electronic classroom student computing stations include the following: * Ease of management and maintenance Primary and secondary schools typically do not have a full time Information Technology (IT) staff to manage the Intel-based electronic classroom. Most IT administration is done by teachers and student volunteers. Hence, the student computing stations used in the Intel-based electronic classroom must be easy to manage. Intel-based electronic classroom student computing stations can be configured without CD-ROM and floppy drives. This further simplifies the management of these student computing stations by preventing students from erasing files or corrupting the operating system and applications. * Low total cost of ownership (TCO) Schools have limited budgets for setting up Intel-based electronic classrooms. Therefore, a key consideration is affordability in terms of initial capital and ongoing maintenance costs, including the costs of off-the-shelf educational applications and teaching content. * Software availability and compatibility Establishing a productive Intel-based electronic classroom depends on the availability of system-compatible, off-the-shelf applications and teaching materials. It is important that schools have tools to develop customized content to meet the particular needs of their students. * Product life cycle support Schools use Intel-based electronic classroom student computing stations for several years before considering an upgrade. Therefore, replacement parts should be available for this duration. 6 Application Note Intel-Based Electronic Classroom Student Computing Station 3.0 Intel-Based Electronic Classroom Setup and Operating Environment A typical Intel-based electronic classroom setup is depicted in Figure 1. Figure 1. Typical Intel-Based Electronic Classroom Setup Home PC Internet School Network 15 - 60 Student Computing Stations Server Intel-Based Electronic Classroom Teacher Station A7490-02 The student and teacher stations are linked together in a LAN environment via a network hub or switch device. The LAN network enables the remote boot for diskless student computing stations and file sharing among all the student computing stations. The broadcasting capability is implemented through software using the existing LAN infrastructure. This solution reduces overall system cost, simplifies wiring and upgrade requirements, and enables the use of higher performance processors. The components of a typical Intel-based electronic classroom and their recommended configuration are described in Table 1. Application Note 7 Intel-Based Electronic Classroom Student Computing Station Table 1. Intel-Based Electronic Classroom Hardware Descriptions and Recommended Configuration Quantity (units) Item Recommended Configuration Teacher Station 1 Intel(R) Pentium(R) III processor, 64 -128 Mbyte SDRAM, Intel(R) 440BX AGPset, Hard-disk, Intel(R) Network Card, Video Capture Card Student Computing Station 15 - 60 Intel(R) CeleronTM processor 433 MHz or better (in 370-pin PPGA) and Intel(R) 810 chipset, 32 Mbyte SDRAM, Intel Network Card integrated on board, Hard-disk (optional) Server 1 Pentium III processor, 128 Mbyte SDRAM, Intel(R) L440GX motherboard, SCSI Hard-disk, Intel Network Card Switch 1-3 Intel Express 510T, 24 10/100Mbit Switching Port Router 1 Intel Express 9500 Router for Internet connection Multimedia teaching Software 1 From ISVs. Based on TCP/IP or IPX network protocol. Intel(R) LANSchool software site is a basic reference: http://www.intel.com/network/products/lanschool.htm 3.1 Intel-Based Electronic Classroom Configuration The configuration of the Intel-based electronic classroom depends on the size of the classroom, the network design, and the use of the multimedia broadcasting software. The following describes an example configuration that consists of five main parts: * * * * * Network environment Teacher Station management system Multimedia broadcasting software Application and education software Intel-based electronic classroom student computing stations that remote boot from server The following sections describe each component of the example Intel-based electronic classroom. 3.1.1 Network Environment The network can be set-up using Windows* NT 4.0 or Novell Netware* on the server. The teacher station and student computing stations run on Windows 95/98 operating systems. The Intel-based electronic classroom student computing stations boot up remotely from a server that is connected in a LAN environment. 8 Application Note Intel-Based Electronic Classroom Student Computing Station 3.1.2 Teacher Station Management System The teacher station in this example can perform the following functions: * Broadcasting the teacher station screen All teaching materials, including presentation, animations, and movies can be broadcast to the student computing stations. * Controlling student computing stations remotely The teacher can control, reset, and lock the student computing stations or receive the display from a particular Intel-based electronic classroom student computing station. * Providing online help The teacher can provide help through the network when students have difficulty with their assignment. The students would also be able to request assistance through the network. 3.1.3 Multimedia Teaching Software The multimedia teaching software utilizes a standard LAN network interface through TCP/IP protocol and typically offers the following features: * Screen broadcasting -- Each computing station (teacher's and student's) can broadcast its screen to some or all students. Only one screen can be broadcast at a time. -- The teacher can lock each student's keyboard and mouse and can broadcast any student's screen to the class. -- All graphics formats, such as MPEG and VCD can be broadcast in real time. * Audio/voice communication -- The teacher's voice can be broadcast to one, several, or all students. -- Conferencing is supported in teacher-student, student-student, or other combinations. -- The voice can be input through MIC or Line In on the sound card. * Remote access -- The teacher can view any student's screen remotely. * Grouping -- Student computing stations can be grouped in any combination for discussion (screen/audio). * Question -- Students can submit questions through MIC or keyboard (using a special function key). -- Two way or multi-way online questioning is supported, as in a "chat" mode. * Remote reset -- The teacher can reset any or all Intel-based electronic classroom student computing stations if an error occurs in the system. * Examinations can be administered and completed online. Application Note 9 Intel-Based Electronic Classroom Student Computing Station 3.1.4 Application Software Typically, application software, such as word processing and spreadsheet programs, and instructor-developed materials are taught in Intel-based electronic classrooms. In some Intel-based electronic classrooms, students are assessed using on-line examinations. 3.1.5 Remote Booting Intel-Based Electronic Classroom Student Computing Stations from Server During the remote boot process, the Intel-based electronic classroom student computing stations contact the server (using Preboot Execution Environment in the boot ROM of the network interface), install a boot image, and boot the operating system that is pre-configured on the server. Various operating systems can be remote booted from the server, including Windows 95/98 or Linux*. The setup is optimized through the availability of the Preboot Execution Environment (PXE) compliant boot ROM. PXE allows the server to set up each student computing station with a specific IP address using the Dynamic Host Communication Protocol (DHCP). The boot ROM then downloads the boot image from the server using the Trivial File Transfer (TFT) protocol. This boot image program then configures the student computing stations and boots the pre-configured operating system. If the Intel-based electronic classroom student computing station's operating system or applications are damaged, they can be recovered by downloading the new image from server when the system restarts. This reduces the total cost of maintenance. Refer to section Section 5.7.2.2, "Remote Service Boot" on page 22 for more information. 10 Application Note Intel-Based Electronic Classroom Student Computing Station 4.0 Recommended Motherboard Configuration for Intel-Based Electronic Classroom Student Computing Stations The motherboard of this reference design for Intel-based electronic classroom student computing stations is a highly integrated design that incorporates many features on the board. It is recommended that system designers use an LPX form factor or Flex ATX design. The LPX form factor enables the student computing stations to have a very slim casing, which is desirable for small Intel-based electronic classroom environments. Flex ATX helps reduce board size and cost. The components listed below provide an example of a motherboard design based on the Celeron processor and Intel 810 chipset. Main Components of Reference Motherboard for the Intel-Based Electronic Classroom Student Computing Station: * * * * * * * * * * Intel(R) CeleronTM Intel(R) 810 processor 300A/366/433 MHz in 370-pin PPGA Chipset Two DIMM sockets that support up to 512 Mbyte (128 Mbit technology) SDRAM Two IDE interfaces One floppy disk interface COM 1 and COM 2 serials ports and a parallel port PS/2 mouse and keyboard connectors Intel(R) Flash BIOS Super I/O* and USB ports 1 X PCI 2.2-compliant PCI slot Peripherals on Intel-Based Electronic Classroom Student Computing Station: Integrated audio in chipset * Audio Codec '97 2.1 extensions compliant * Stereo line level output * One audio out, audio in, and MIC jack Integrated Graphics * 3-D graphics with texturing and visual enhancements up to 1024x768x16 @85 Hz refresh * 2-D graphics up to 1600x1200x8 @85 Hz refresh * RGB output PCI-based 10/100 Mbps Network card * Intel(R) 82559-based card recommended * One RJ-45 port * Boot ROM which contains Intel(R) Preboot Execution Environment (PXE) Application Note 11 Intel-Based Electronic Classroom Student Computing Station Figure 2. Building Block of the Intel-Based Electronic Classroom Student Computing Station Motherboard Intel(R) CeleronTM Processor System Bus [66 MHz] Intel(R) 810 Chipset Display I/F Monitor SDRAM Memory 100 MHz 82810 241 BGA GD82559 2 IDE Port/ Ultra AT A66 82801AA USB USB SMBus Intel Network Controller Support 10/100 Mbit One RJ-45 port One Flash boot ROM 241 BGA PCI 33 82802AB 1 PCI REQ/GNT Low Pin Count Interface 4Mb AC'97 Riser AC'97 2.1 Super IO* COM1 & COM 2 Serial Ports Parallel Port PS/2 Mouse Floppy Disk Interface Keyboard Connectors A7493-01 12 Application Note Intel-Based Electronic Classroom Student Computing Station 5.0 Design Consideration of Intel-Based Electronic Classroom Student Computing Station Hardware 5.1 Intel(R) CeleronTM Processor This reference configuration supports the Intel Celeron processor at 300, 366 MHz and 433 MHz in a Plastic Pin Grid Array (PPGA) package. The Intel Celeron processor PPGA package implements a Dynamic Execution micro-architecture and executes MMXTM media technology instructions for enhanced media and communication performance. The Intel Celeron processor PPGA is based on the P6 family processor core and is provided in a PPGA package for use in low cost systems in the value PC and Intel-based electronic classroom student computing station market segments. The Intel Celeron processor PPGA utilizes the AGTL+ system bus used by the Pentium(R) II processor with support limited to single-processor systems. The Intel Celeron processor PPGA includes an integrated 128 Kbyte second level cache with separate 16 Kbyte instruction and 16 Kbyte data level-one caches. The second level cache is capable of caching 4 Gbytes of system memory. 5.1.1 Design Notes for the Intel(R) CeleronTM Processor The schematics use a Single Ended Termination (SET) network topology in which the termination resistors are located at only the PPGA (processor) side to reduce the system cost, solution space, and ringing effect. In the SET topology, the termination should be placed close to the processor either on the motherboard or on the processor substrate. No termination is present at the chipset end of the network. Figure 3. Topology for Single Processor Designs with Single End Termination (SET) VTT 370-Pin Socket L2 - L1 Intel(R) 810 Chipset 1.9" <L1 <5.0" 0.5" <L2 <2.0" A7494-01 Application Note 13 Intel-Based Electronic Classroom Student Computing Station 5.2 Intel(R) 810 Chipset Intel has developed technology that enhances the performance and value of Intel Celeron processor-powered systems. Built on the strong foundation of Intel 440BX AGPset technology, the Intel 810 chipset provides next generation features and great graphics performance at a lower cost. The Intel 810 chipset contains three core components: 1. Host Controller -- Graphics and Memory Controller Hub (GMCH0) The GMCH0 (82810) provides the interconnect between the SDRAM and the rest of the system logic: -- 421 Mini BGA -- Integrated Graphics controller -- 230 MHz RAMDAC -- Support for Intel Celeron processors with a 66 MHz system bus. -- 100 MHz SDRAM interface supporting 64/256/512 Mbyte with 16/64/128 Mbit SDRAM technology -- Downstream hub interface for access to the ICH 2. I/O Controller Hub -- 82810AA (ICH) The I/O Controller Hub provides the I/O subsystem with access to the rest of the system: -- 421 Mini BGA -- Upstream hub interface for access to the GMCH0 -- PCI 2.2-compliant interface (6 PCI Req/Grant Pairs for 82801AA ICH) -- Bus Master IDE controller; supports either Ultra ATA/33 or Ultra ATA/66 (82801AA) -- USB controller -- SMBus controller -- FWH interface -- LPC interface -- AC'97 2.1 interface -- Integrated System Management Controller -- Alert-on-LAN (82801AA ICH only) -- Interrupt controller 3. 82802 Firmware Hub (FWH) The 82802 FWH component is a key element to enabling a new security and manageability infrastructure for the PC platform. The device operates under the FWH interface and protocol. The hardware features of this device include: -- An integrated hardware Random Number Generator (RNG) -- Register-based locking -- Hardware-based locking -- 5 GPIs 14 Application Note Intel-Based Electronic Classroom Student Computing Station 5.2.1 The Intel(R) 82810 Graphics Memory Controller Hub (GMCH0) The Intel 810 chipset provides a rich and robust 2-D and 3-D graphics using an integrated chipset design that utilizes second-generation graphics technology. At the core of the 810 chipset is a memory controller with built-in graphics technology. The Intel 810 chip optimizes system memory arbitration, similar to AGP technology, resulting in a more responsive and cost-effective system. The 82810 Graphics Memory Controller Hub (GMCH0) features Intel graphics technology and software drivers and uses Direct AGP (integrated AGP) to create vivid 2-D and 3-D effects and images. The 82810 chip features integrated Hardware Motion Compensation to improve soft DVD video quality and a digital video out port that enables connection to traditional TVs or the new space-saving digital flat panel displays. Intel Dynamic Video Memory Technology (DVMT) is an architecture that offers breakthrough performance for the Value PC segment through efficient memory utilization and Direct AGP. The system OS uses the Intel software drivers and intelligent memory arbiter to support richer graphics applications. The System Manageability Bus allows networking equipment to monitor the 810-chipset platform. Using ACPI specifications, the system manageability function enables low-power sleep mode and conserves energy when the system is idle. 5.2.1.1 Design Notes for the Intel(R) 82810 GMCH0 The GMCH ball assignment and ICH ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals are routed directly from the GMCH0 to the ICH on the top signal layer. The hub interface has two signal groups: * Data Signals: HL[10:0] * Strobe Signals: HL_STB, HL_STB# (differential strobe pair) There are no pull-ups or pull-downs required on the hub interface. Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH0 and the ICH, the hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils within 0.3" of the GMCH0/ICH components. The maximum trace length for the hub interface data signals is 7". These signals should each be matched within 0.1" of the HL_STB and HL_STB# signals. Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The maximum length for the strobe signals is 7" and the two strobes should be the same length. Additionally, the trace length for each data signal should be matched to the trace length of the strobes with 0.1". HREF is the hub interface reference voltage. It is 0.5 * 1.8 V = 0.9 V 2%. It can be generated locally, or a single HREF divider can be used. Each divider consists of a DC element and an AC element. The resistors in the DC element should be equal in value and rated at 1% tolerance. The value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained over the entire input leakage specification. The resistors in the AC element of the resistor divider should be no greater than 80 and the capacitors should be 500 pF. Additionally, the reference voltage should be bypassed to ground at each component with a 0.1 uF capacitor. Application Note 15 Intel-Based Electronic Classroom Student Computing Station 5.2.2 The Intel(R) 82801 I/O Controller Hub (ICH) The 82801 I/O Controller Hub (ICH) employs the Intel Accelerated Hub Architecture to make a direct connection from the graphics and memory to the integrated AC97 controller, the IDE controllers, dual USB ports, and PCI add-in cards. The Accelerated Hub Architecture provides twice the bandwidth of the PCI bus at 266 MB per second. This allows a wider flow of rich information from the I/O controller to the memory controller, with optimized arbitration rules allowing more functions to run concurrently, enabling more life-like audio and video. The Integrated Audio-Codec 97 controller enables software audio and modem by using the processor to run sound and modem software. By reusing existing system resources, this feature adds flexibility, improves sound quality, and lowers the system BOM cost by eliminating components. The 82802 Firmware Hub (FWH) stores system BIOS and video BIOS, eliminating a redundant nonvolatile memory component. In addition, the 82802 contains a hardware Random Number Generator (RNG). The Intel RNG provides truly random numbers to enable fundamental security building blocks supporting stronger encryption, digital signing, and security protocols. 5.2.2.1 Design Notes for the Intel(R) 82801 ICH * ICH Placement: The ICH should be placed within 8" of the ATA connector(s). There are no minimum length requirements for this spacing. * Capacitance: The capacitance of each pin of the IDE connector on the host should be below 25 pF when the cables are disconnected from the host. * Series Termination: There is no need for series termination resistors on the data and control signals since series termination is integrated into these signal lines on the ICH. * * * * A 1 K pull-up to 5 V is required on PIORDY and SIORDY. A 470 pull-down resistor is required on pin 28 of each connector. A 5.6 K pull-down resistor is required on PDREQ and SDREQ. Support Cable Select (CSEL) is a PC99 requirement. The state of the cable select pin determines the master/slave configuration of the hard drive at the end of the cable. * Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15. * IRQ14 and IRQ15 each need an 8.2 K pull-up resistor to VCC. * Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1 of the IDE connectors as the IDE reset signal. Due to high loading, the PCI_RST# signal should be buffered. * There is no internal pull up or down on PDD7 or SDD7 of the ICH. Devices should not have a pull-up resistor on DD7. It is recommended that a host have a 10 K pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification). * If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals left as no connects. 16 Application Note Intel-Based Electronic Classroom Student Computing Station 5.3 IDE Connectors The 82801AA ICH supports Ultra ATA/66 and ATA/33 devices The ATA/66 cable is an 80-conductor cable; however the 40-pin connectors used on motherboards for 40-conductor cables do not change as a result of this new cable. The wires in the cable alternate: ground, signal, ground, signal, etc. All the ground wires are tied together at the connectors on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained from the Small Form Factor Committee. To determine if ATA/66 mode can be enabled, the Intel 810 chipset using the ICH requires the system BIOS to attempt to determine the cable type used in the system. If only one IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals left as no connects. This can be implemented to reduce the board space and cost. 5.4 AC'97 2.1 Compliant Components The ICH implements an Audio Codec '97 (AC'97) 2.1 compliant digital controller. Any codec attached to the ICH AC-link should also be AC'97 2.1 compliant. Contact your preferred codec vendor for information on AC'97 2.1 compliant products. The AC'97 2.1 specification is available on the Intel web-site: http://developer.intel.com/pc-supp/platform/ac97/index.htm The ICH supports the following combinations of codecs: Table 2. AC'97 Configuration Combinations Primary Secondary Audio (AC) None Modem (MC) None Audio (AC) Modem (MC) Audio/Modem (AMC) None The ICH does not support two codecs of the same type on the link. For example, if an AMC is on the link, it must be the only codec. If an AC is on the link, another AC cannot be present. Application Note 17 Intel-Based Electronic Classroom Student Computing Station 5.4.1 Design Notes for AC'97 Devices * Special consideration must be given for the ground return paths for the analog signals. If isolated ground planes are used, pin B2 on the AMR connector should be used as an isolated ground pin and should be connected to an isolated ground plane to reduce noise in the analog circuits. The AMR designer and motherboard designer should jointly address any EMI issues when implementing isolated grounds. * Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. * Partition the board with all analog components grouped together in one area and all digital components in the other. * Separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between the planes must be a minimum of 0.05" wide. * Keep digital signal traces, especially the clock, as far way from analog input and voltage reference pins as possible. * Do not completely isolate the analog/audio ground plane from the rest of the board ground plane. There should be a single point (1/4" to 1/2 " wide) where the analog/isolated ground plane connects to the main ground plane. The split between the planes must be a minimum of 0.05"wide. * Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground (i.e., there should not be any signals crossing the split/gap between the ground planes). Doing so will cause a ground loop. 5.5 Audio/Modem Riser Card (AMR) Intel is developing a common connector specification known as the Audio/Modem Riser (AMR). This specification defines a mechanism for allowing OEM plug-in card options. The AMR specification is available on the Intel developer website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The AMR specification provides a mechanism for AC'97 codecs to be on a riser card. This is important for modem codecs as it helps ease international certification of the modem. For the Intel-based electronic classroom student computing station, the audio codec is integrated on the motherboard to avoid compatibility issues and robustness. A modem codec is optional for electronics classroom. 5.5.1 Design Notes for the Audio/Modem Riser Card * Only one primary codec can be present on the link. A maximum of two present codecs can be supported in an ICH platform. * As the Intel-based electronic classroom student computing station motherboard implements an active primary codec (audio) on the motherboard and provides an AMR connector, it must tie PRI_DN# to ground. The PRI_DN# pin is provided to indicate that a primary codec is present on the motherboard. 18 Application Note Intel-Based Electronic Classroom Student Computing Station 5.6 PCI The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, please refer to the PCI Local Bus Specification, Revision 2.2. The 82801AA ICH supports 6 PCI bus masters (excluding ICH), by providing 6 REQ#/GNT# pairs. The PCI network controller (GD82559) is integrated on board; therefore, an extra PCI slot is expandable for a PCI network broadcasting card (if implemented). 5.7 Network Controller -- Intel(R) 82559 Fast Ethernet Controller The 82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer device is Intel's leading solution for PCI board LAN designs. It is designed for use in Network Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems, and networking system products. The 82559 combines a low power and small package design which is ideal for power- and space-constrained environments. It is compliant with Advanced Configuration and Power Interface (ACPI) 1.20A-based power management and with the Wired for Management (WfM) 2.0 Baseline specification. The 82559 is an integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY. It provides a glueless 32-bit PCI master interface and supports a 128 Kbyte Flash interface. The package is a thin BGA with a small footprint (15 mm X 15 mm). The 82559 supports the Intel Preboot Execution Environment (PXE) driver, which allows a new or existing system to boot over the network and download software or an image, including the operating system, stored on a server. The 82559 provides for operating system independent network booting, automating the setting up and configuration of new systems. If the operating system or applications software is damaged, the system can be recovered by downloading the original image from server again, reducing the total cost of maintenance. 5.7.1 Design Note for the Intel(R) 82559 Fast Ethernet Controller The differential transmit signal pair (TDP/TDN) is terminated with a 100 W (1%) resistor, and the differential receive signal pair (RDP/RDN) is terminated with a 120 W (1%) resistor. These termination resistors should be placed as close to the PHY as possible. These resistors terminate the entire impedance seen at the termination source (for example, the PHY), including the wire impedance reflected through the transformer. Figure 4 depicts the placement of the termination resistors. Application Note 19 Intel-Based Electronic Classroom Student Computing Station Placement of Termination Resistor PCI Interface Figure 4. R RJ-45 Magnetics Module 82559 R Place termination resistors as close to the 82559 as possible. A7495-01 The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals, such as the clock, and signal layers that are close to a ground plane or power plane should be as short and as wide as is practical. As shown in Figure 5, this ratio is ideally somewhere between 1:1 and 3:1. To maintain the impedance of a trace, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from a power or ground plane. Figure 5. Trace Geometry W 1< W <3 H H Ground A7496-01 NOTE: W= Trace Width, H= Height Above Ground Plane 20 Application Note Intel-Based Electronic Classroom Student Computing Station 5.7.2 Wired for Management Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop, mobile, server and embedded systems. The goal of WfM is to reduce the total cost of ownership (TCO) through improved manageability in the following four technology areas: * * * * Instrumentation Remote Service Boot Remote Wake-Up Power Management Manageability features in each of these four technology areas combine to form the Wired for Management Baseline Specification. A copy of the Wired for Management Baseline Specification, Version 2.0 can be obtained from: http://developer.intel.com/ial/wfm/wfmspecs.htm An on-line Design Guide is available at: http://developer.intel.com/ial/WfM/design/index.htm Future versions of the specification will be available at this site. In the Intel-based electronic classroom reference configuration, the NIC is WfM compliant, particularly in the Remote Service Boot features needed to support the student computing stations' remote boot from the server. 5.7.2.1 Instrumentation A component's instrumentation consists of code that maintains attributes with up-to-the-minute values and adjusts the component's operational characteristics based on these values. By providing instrumentation, the platform provides accurate data to management applications, so those applications can make the best decisions for managing a system or product. The WfM 2.0 Baseline requires that compliant desktop and mobile platforms utilize the DMI Version 2.00 Management Interface (MI) and Component Interface (CI) application programming interfaces and host a DMI v2.00 Service Provider, as defined by the DMTF. Intel's DMI 2.0 Service Provider Software Development Kit (SDK) provides a DMI Service Provider and binaries that support DMI Version 2.00. This kit is available at the following URL: http://developer.intel.com/ial/WfM/tools/sdk/index.htm Intel(R) LANDesk (R) Client Manager product includes the Service Provider and component instrumentation. Information regarding this product can be found at: http://developer.intel.com/ial/WfM/tools/ldcm/index.htm The WfM Baseline Instrumentation specification identifies specific DMI standard groups, including event generation groups, that must be instrumented for a Baseline-compliant platform. This specification provides support for the SMBIOS revision 2.0 specification that along with appropriate component instrumentation will supply some of the required data in the specified DMI 2.0 groups. Application Note 21 Intel-Based Electronic Classroom Student Computing Station 5.7.2.2 Remote Service Boot The WfM Baseline specifies the protocols by which a client requests and downloads an executable image from a server and the minimum requirements on the client execution environment when the downloaded image is executed. The Baseline specification includes a set of APIs for the particular network controller used. The code supporting the Preboot eXecution Environment (PXE) and the network controller is provided on the EtherExpressTM PRO/100 WfM adapters Option ROM. Two implementation options are available: * NIC with Option ROM and Wake on LAN Header * LAN on Motherboard implementation. For this option, the Preboot execution environment and the network controller code must be incorporated into the system BIOS. In addition, the BIOS must provide the _SYSID_ and _UUID_ data structures. The details of the BIOS requirements can be obtained from the Intel web site: http://developer.intel.com/ial/WfM/design/pxedt/index.htm 5.7.2.3 Remote Wake-Up If a student computing station supports a reduced power state, it is possible to bring the system to a fully powered state in which all power management interfaces are available. Typically, the LAN adapter recognizes a special packet as a signal to wake up the system. The system BIOS must enable the wake event and provide wake up status. The details of the BIOS requirements can be obtained from the Intel web site: http://developer.intel.com/ial/WfM/design/rwudt/index.htm 5.7.2.4 Power Management WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and Mechanical Off. A user accessible switch that will send a soft off request to the system usually provides Soft Off. A second optional "override" switch located in a less obvious place (or removal of the power cord) stops current flow forcing the platform into the mechanical off state without OS consent. Note that a second "override" switch is required for legal reasons in some jurisdictions (for example, some European countries). The BIOS may support the power management requirement either through the APM revision 1.2 or ACPI revision 1.0 specifications. See Intel's web site for additional information: http://developer.intel.com/ial/WfM/design/pmdt/index.htm. 5.8 Low Pin Count (LPC) Interface In the Intel 810 chipset platform, the Super I/O* (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, a floppy disk controller, and serial and parallel ports. In addition to the Super I/O features, an integrated game port is recommended because the AC'97 interface does not provide support for a game port. In systems that have ISA audio, the game port typically existed on the audio card. The fifteen pin game port connector provides for two joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a comprehensive list of devices offered and features supported. 22 Application Note Intel-Based Electronic Classroom Student Computing Station 6.0 Conclusion Traditional teaching media such as projector, video player, audio recorder, and black board are being replaced in the Intel-based electronic classroom by new computer-based teaching media. Audio, video and 2-D/3-D graphics can be introduced in the Intel-based electronic classroom. The classroom can be connected to the Internet by using modem or Intel router. Intel provides the building blocks for Intel-based electronic classroom systems that feature manageability, ease of maintenance, compatibility with operating systems and application software, and long life cycle support for the Intel components. The recommended motherboard configuration is designed to optimize the performance of the overall system, reducing board space, power consumption, and the total cost of ownership. Application Note 23 Intel-Based Electronic Classroom Student Computing Station Appendix A References Document Order Number / URL Intel Documents and Resources Intel(R) 810 Chipset Design Guide Order Number 290657 http://developer.intel.com/design/chipsets/designex/290657.htm Intel(R) 82810 Chipset: Intel 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) datasheet Order Number 290656 http://developer.intel.com/design/chipsets/datashts/290656.htm Intel(R) 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub datasheet Order Number 290655 http://developer.intel.com/design/chipsets/datashts/290655.htm Intel(R) 82801 FirmWare Hub (FWH) datasheet Order Number 290658 http://developer.intel.com/design/chipsets/datashts/290658.htm Intel(R) CeleronTM Processor datasheet Order Number 243658 http://developer.intel.com/design/celeron/datashts/243658.htm VRM 8.2 DC-DC Converter Design Guidelines Order Number 243733 http://developer.intel.com/design/pentiumii/xeon/designgd/243773 .htm AP-585 Pentium(R) II Processor GTL+ Guidelines Order Number 243330 http://developer.intel.com/design/pentiumii/applnots/243330.htm AP-587: Slot 1 Processor Power Distribution Guidelines Order Number http://developer.intel.com/design/celeron/applnots/243332.htm Pentium(R) II Processor Developer's Manual Order Number 243341 http://developer.intel.com/design/PentiumII/manuals/243502.htm Pentium(R) II Processor at 350 MHz, 400 MHz and 450 MHz datasheet Order Number 243657 http://developer.intel.com/design/PentiumII/datashts/243657.htm Intel(R) 82559 Fast Ethernet Multifunction PCI Controller http://developer.intel.com/design/network/82559.htm AP-399 82559 Printed Circuit Board Design Order Number 739073 http://developer.intel.com/design/network/applnots/739073.htm AP-392 82559 LAN on Motherboard (LOM) Design Guide Order Number 718213 http://developer.intel.com/design/network/applnots/718213.htm Intel(R) Networking LANSchool software site http://www.intel.com/network/products/lanschool.htm AC'97 Specifications on Intel web site http://developer.intel.com/pc-supp/platform/ac97/index.htm Wired for Management specifications and information http://developer.intel.com/ial/wfm/index.htm Non-Intel Documents and Resources PCI Local Bus Specification, Revision 2.2 http://www.pcisig.com/ Universal Serial Bus Specification, Revision 1.0 http://www.usb.org/ Application Note 25 Intel-Based Electronic Classroom Student Computing Station Appendix B Intel-Based Electronic Classroom Schematics Application Note 27 A USB Connectors Parallel Port Serial Ports Kybrd / Mse / F. Disk / Gme Connectors Graphics Connectors AC'97 Riser Connector LAN (82559) Voltage Regulators VRM 8.4 System Pullup Resistors and Unused Gates Decoupling Revision History TITLE Cover Sheet Block Diagram 370PGA Socket GTL Termination Clock Synthesizer 82810 System Memory 82801AA 82802AB (FWH) Super I/O PCI Connectors ATA 33/66 IDE Connectors 31 PAGE 1 2 3,4 5 6 7,8,9 10 11,12 13 14 15 16 17 18 19 20 21 22 23,24 25 26 27,28 29 30 A 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 APPLIED COMPUTING PRODUCTS DIVISION INTEL CORPORATION COVER SHEET Sheet: 1 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref Schematic * Other brands and names are the property of their respective owners. Copyright (c) Intel Corporation 2000 Intel may make changes to specifications and product descriptions at any time, without notice. The Intel (r) Celeron (tm) processor and Intel (r) 810 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving or life sustaining applications. THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLES. ** Please note these schematics are subject to change. Intel(R) CeleronTM Processor And Intel(R) 810 Based Electronic Classroom Student Computing Station Hardware Schematics A Rev 0.1 A PG. 16 PG. 22 AC'97 Link PG. 13 82802AB PG. 11-12 82801AA PG. 7-9 Keyboard Mouse PG. 14 SIO Floppy PCI ADDR/DATA PCI CNTRL PG. 10 One DIMM Module PG. 6 Clock LPC Bus Serial 1 Parallel A Game Port PCI ADDR/DATA PCI CNTRL PG. 5 Term PG. 15 AUDIO/MODEM RISER USB ADDR USB Port 1 PG. 17 USB Port 2 PG. 17 ADDR Ultra DMA 33/66 CTRL IDE Primary CTRL 82810 DATA IDE Secondary PG. 16 PG. 3-4 370-Pin Socket Processor DATA A VRM PG. 26 Block Diagram A PCI CONN 1 LAN PG. 23-24 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 APPLIED COMPUTING PRODUCTS DIVISION INTEL CORPORATION BLOCK DIAGRAM Sheet: 2 of 33 Last Revision Date: Electronic Clasroom Student Computing Station Ref. Schematic 0.1 REV A A 5,7 HD#[63:0] J1 HD#7 S1 HD#8 P6 HD#9 Q3 HD#10 M4 HD#11 Q1 HD#12 L1 HD#13 N3 HD#14 U3 HD#15 H4 HD#16 R4 HD#17 P4 HD#18 H6 HD#19 L3 HD#20 G1 HD#21 HD#10 HD#13 HD#16 HD#18 HD#20 K6 HD#24 E3 HD#25 E1 HD#26 F12 HD#27 A5 HD#28 A3 HD#29 J3 HD#30 C5 HD#31 HD#24 HD#26 HD#28 HD#30 C7 HD#34 B2 HD#35 C9 HD#36 A9 HD#37 D8 HD#38 D10 HD#39 C15 HD#40 D14 HD#41 D12 HD#42 A7 HD#43 A11 HD#44 C11 HD#45 A21 HD#46 HD#34 HD#36 HD#38 HD#41 HD#43 HD#45 C13 HD#49 C25 HD#50 A13 HD#51 D16 HD#52 A23 HD#53 C21 HD#54 C19 HD#55 C27 HD#56 A19 HD#57 C23 HD#58 C17 HD#59 A25 HD#60 A27 HD#61 HD#49 HD#51 HD#54 HD#56 HD#58 HD#60 HD#63 HD#62 HD#61 HD#59 HD#57 HD#55 HD#53 HD#52 HD#50 E25 HD#62 F16 HD#63 A15 HD#47 A17 HD#48 HD#48 HD#47 HD#46 HD#44 HD#42 HD#40 HD#39 HD#37 HD#35 HD#33 F6 HD#32 C1 HD#33 HD#32 HD#31 HD#29 HD#27 HD#25 HD#23 F8 HD#22 G3 HD#23 HD#22 HD#21 HD#19 HD#17 HD#15 HD#14 HD#12 HD#11 HD#9 HD#8 Part 1 370-Pin Socket VCC19 AJ5 VCC20 D6 VCC17 J5 VCC18 F2 Q5 GND17 L5 GND18 S3 HD#5 T6 HD#6 VCC21 B6 VCC22 AM8 G5 GND19 D4 GND20 HD#7 VCC23 AJ9 VCC24 E9 B4 GND21 AM6GND22 HD#6 VCC25 B10 VCC26 AM12 AJ7 GND23 E7 GND24 HD#5 VCC27 AJ13 VCC28 E13 B8 GND25 AM10 GND26 HD#4 VCC29 B14 VCC30 AM16 AJ11GND27 E11 GND28 N1 HD#2 M6 HD#3 U1 HD#4 VCC31 AJ17 VCC32 E17 B12 GND29 AM14 GND30 HD#3 VCC33 B18 VCC34 AM20 AJ15GND31 E15 GND32 HD#2 VCC35 AJ21 VCC36 D20 B16 GND33 AM18 GND34 VCC15 S5 VCC16 N5 Y5 GND15 U5 GND16 VCC13 AA5 VCC14 W5 AG5GND13 AC5GND14 AL3 GND11 AK4 GND12 VCC10 VCC8 K2 VCC9 F4 E5 D18 GND8 H2 GND9 VCC6 T2 VCC7 P2 V2 GND6 M2 GND7 VCC4 AF2 VCC5 AB2 AD2GND4 Z2 GND5 VCC2 C3 VCC3 AK2 AM34 GND2 AH2GND3 AM2GND1 HD#1 VCC37 F22 VCC38 AM24 AJ19GND35 E19 GND36 B26 VCC1 X2A VCC39 AJ25 VCC40 D24 F20 GND37 B20 GND38 W1 HD#0 T4 HD#1 VCC41 F26 VCC42 AM28 A AM22 GND39 AJ23GND40 HD#0 VCC43 AJ29 VCC44 D28 D22 GND41 F24 GND42 VCCVID VCC45 AK34 VCC46 F30 B24 GND43 AM26 GND44 Part 1 VCC47 B30 VCC48 AM32 AJ27GND45 D26 GND46 A VCC49 AH32 VCC50 Z32 F28 GND47 B28 GND48 370PGA Socket VCC11 AM4 VCC12 AE5 GND10 D2 VID0 VID1 VID2 VID3 RS#0 RS#1 RS#2 VID0 AL35 VID1 AM36 RS#0 AH26 RS#1 AH22 REQ#4 AL17 REQ#2 AH18 REQ#3 AL19 REQ#0 AK18 REQ#1 AH16 RS#2 AK28 VID2 AL37 VID3 AJ37 HA#30 AA3 HA#31 AD4 HA#28 AK6 HA#29 Z4 HA#26 Y3 HA#27 AA1 HA#24 AB4 HA#25 AF6 HA#22 AE3 HA#23 AB6 HA#20 AC3 HA#21 AJ1 HA#18 Z6 HA#19 AG3 HA#16 AN7 HA#17 AE1 HA#14 AK14 HA#15 AL5 HA#12 AN5 HA#13 AL7 HA#9 AL9 HA#10 AH6 HA#11 AK10 HA#7 AL15 HA#8 AH10 RSRVD18 AN13 RSRVD16 AL21 RSRVD17 AN11 RSRVD14 AL11 RSRVD15 AL13 RSRVD12 AK24 RSRVD13 AK30 RSRVD9 AC37 RSRVD10 AF4 RSRVD11 AK16 RSRVD7 AA35 RSRVD8 AC1 RSRVD5 A33 RSRVD6 AA33 RSRVD3 A29 RSRVD4 A31 5,7 5,7 5,7 26 HREQ#[4:0] RS#[2:0] VID[3:0] HA#[31:3] 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 APPLIED COMPUTING PRODUCTS DIVISION INTEL CORPORATION Sheet: 3 of 33 Last Revision Date: 370-PIN SOCKET (PART 1) Electronic Classroom Student Computing Station Ref. Schematic HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#5 AH8 HA#6 AN9 HA#3 AK8 HA#4 AH12 RSRVD1 AH20 RSRVD2 AH4 VCC51 V32 VCC52 R32 AM30 GND49 D30 GND50 0.1 REV. A A R104A 1% 150 R102A 1% 75 4N949 VTT1_5 6 0K R2A ITP_PON R_DBRST# 20 22 24 26 28 30 19 21 23 25 27 29 VCMOS GTLREF Place 0603 Package Near VCMOS Processor Pin. VCMOS Decoupling APICD0 18 17 240 29 6 R_TCK 4N639 VCCVID ITPRDY# ITPREQ# R_TMS 51 47 R4A RP2A Place site w / in 0.5" of clock pin (W37) 18PF C114A R76A 5 Do not stuff C114 PWRGOOD CPUHCLK 11,29 APICD1 6 APICCLK_CPU 11,29 16 15 ITPRDY# 14 13 R21A 12 R_ITPRDY# TDO 10 TRST# TDI 8 7 9 6 R7A 150 11 4 5 2 ITP30RA 3 1 J2A within 500 mils of Mendocino GTLREF Inputs (1 cap for every 2 inputs). Use 0603 Packages and distribute GTLREF Generation Circuit ITPCLK R_TMS R_TCK ITP_RST R8A 1K 7 2 8 1 R5A 680 EDGCTRL CPURST# 47 TMS R3A 6 3 VCMOS 5 4 TRST# V_CMOS AB36 VCMOS V1_5 AD36 V2_5 Z36 BP2# BCLK 4N859 EDGCTRL A C37 CPUPRES# AG1 AK26 PWRGOOD X4 RESET# W37 J35 PICD0 L35 PICD1 J33 PICCLK Q37 RSRVD38 S33 RSRVD39 N37 RSRVD35 Q33 RSRVD36 Q35 RSRVD37 L33 RSRVD32 N33 RSRVD33 N35 RSRVD34 F10 RSRVD29 G35 RSRVD30 G37 RSRVD31 E29 RSRVD27 E31 RSRVD28 C33 RSRVD25 E23 RSRVD26 C29 RSRVD23 C31 RSRVD24 AN23 RSRVD21 B36 RSRVD22 AN15 RSRVD19 AN21 RSRVD20 E37 BP3# C35 BPM0# E35 BPM1# G33 J37 PREQ# A35 PRDY# TCK AK32 TMS AN33 TCK AL33 AN35 TDI AN37 TDO X2B 330 4N677 X32 GND53 T32 GND54 4N329 VREF2 K4 VREF3 R6 P32 GND55 F32 GND56 VTT1_5 VREF0 E33 VREF1 F18 AF32GND51 AB32 GND52 GTLREF VREF4 V6 VREF5 AD6 B32 GND57 VCMOS VCCVID Part 2 370-Pin Socket VREF6 AK12 VREF7 AK22 AH34 GND58 AD34 GND59 29 VCC53 M32 Z34 GND60 V34 GND61 VTT1_5 VCC54 H32 VCC55 AF34 R34 GND62 M34GND63 VCC2_5 VCC56 AB34 VCC57 X34 H34 GND64 D34 GND65 CPURST# C206A VCC58 T34 VCC59 P34 AK36 GND66 AF36GND67 DBRESET# C209A VCC60 K34 VCC61 F34 X36 GND68 T36 GND69 5,7 0.1UF VCC62 B34 VCC63 AH36 P36 GND70 28 C204A VCC64 B22 VCC65 V36 4N101 AN19 AE37 AN31 AL27 BSEL# AJ33 BR0# AN29 FLUSH# ADS# DBSY# LOCK# AK20 AN27 DRDY# AL23 HITM# HIT# AL25 DEFER# BNR# AH14 BPRI# AN17 TRDY# AN25 JP1A 5,7 5,7 5,7 5,7 5,7 5,7 5 4N937 11,29 11,29 6,9 5,7 5,7 RTTCRTL 20% SLEWCTRL 33UF 1 + C123A 2 29 29 11,29 PLL1 11,29 IGNNE# PLL2 11, 29 11,13,29 NMI INIT# 11, 29 FERR# INTR VCC3_3 4N606 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 4 of 33 Last Revision Date: 370-PIN SOCKET (PART 2) Rev 0.5 9 VCCVID VCCDET 220 R171A 4.7UH L22A CPUSLP# 11, 29 SMI# 11, 29 STPCLK# A20M# BR0# FREQSEL HADS# DBSY# RSRVD50 R2 RSRVD51 S35 RSRVD52 X2 2 HITM# 5,7 HIT# 5,7 HLOCK# DRDY# DEFER# HTRDY# BNR# BPRI# RSRVD48 E21 RSRVD49 E27 RSRVD46 X6 RSRVD47 Y1 RSRVD44 W3 RSRVD45 W35 RSRVD42 U37 RSRVD43 V4 RSRVD40 S37 RSRVD41 U35 PLL1 W33 PLL2 U33 LINT1/NMI L37 AG33 INIT# AC35 FERR# AG37 IGNNE# IERR# AE35 SMI# AJ35 LINT0/INTR M36 AE33 A20M# STPCLK# AG35 SLP# AH30 THERMTRIP# AH28 1 JP5 is a Test Option Only. 220 R9A VCC2_5 THRMDP AL31 THRMDN AL29 VCC74 AA37 VCC75 Y35 Electronic Classroom Student Computing Station Ref. Schematic K36 GND71 F36 GND72 R1A 240 0.1UF VCC66 R36 VCC67 H36 A37 GND73 AC33 GND74 ITP Test Port Option C207A VCC68 D36 VCC69 D32 AJ3 GND75 AL1 GND76 Part 2 VCC70 AD32 VCC71 AH24 AN3GND77 Y37 GND78 A VCC72 F14 VCC73 K32 AJ31GND79 Y33 GND80 370PGA Socket 0.1UF 0.1UF C6A 0.1UF 4N642 A A 5N58 VTT1_5 6 5 3 4 56 7 2 7 6 5 3 4 6 5 3 4 5 4 7 6 5 2 3 4 7 6 5 2 3 4 56 8 1 56 RP21A 8 1 RP11A 6 3 56 7 2 5 4 8 6 3 1 7 2 56 RP7A 8 1 RP12A 7 2 56 8 1 56 RP20A 8 5 4 2 6 3 1 7 2 56 RP8A 8 1 RP18A 8 1 RP19A HA#27 HA#29 HA#26 HA#14 HA#4 HA#8 HA#7 HA#11 HA#9 HA#5 HA#16 HA#13 HA#28 HA#23 HA#20 HA#24 HA#30 HA#6 HA#3 HA#12 HA#15 HA#10 HA#25 HA#21 HA#18 HA#19 HA#31 HA#22 HA#17 3,7 4,7 3,7 4,7 CPURST# BNR# HREQ#1 HA#[31:3] GTL Termination 5N395 5N369 VTT1_5 6 5 3 4 6 5 3 4 7 6 5 3 4 56 8 5 4 2 6 3 1 7 2 56 RP3A 8 1 RP10A 7 56 8 5 4 2 6 3 56 RP5A 7 2 1 8 1 RP9A 7 2 56 8 RP6A 1 3,7 4,7 BR0# ITPRDY# HREQ#2 HREQ#3 4,7 4,7 4,7 4,7 3,7 4 4 3,7 3,7 3,7 4,7 4,7 4,7 3,7 HREQ#0 DEFER# HADS# HIT# RS#2 HITM# DBSY# DRDY# RS#0 HTRDY# HLOCK# 4,7 RS#1 3,7 HREQ#4 BPRI# 5N208 VTT1_5 5 4 5N250 4 HD#26 5 6 7 8 6 5 3 4 56 7 8 A 4 3 HD#35 HD#33 2 HD#19 56 5 6 7 8 RP42A 1 3 HD#25 HD#29 2 HD#32 56 RP40A 5 6 7 8 RP37A 56 5 6 7 8 56 RP39A 5 6 7 8 RP36A 56 5 6 7 8 56 RP32A 5 6 7 8 RP33A 56 5 6 7 8 RP38A RP41A 2 1 5 4 4 HD#2 1 3 HD#14 HD#31 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 HD#18 HD#13 HD#20 HD#11 HD#7 HD#30 HD#17 HD#10 HD#12 HD#3 HD#24 HD#21 HD#23 HD#16 HD#4 HD#9 HD#5 HD#8 HD#0 HD#15 56 6 3 HD#6 HD#1 VTT1_5 56 7 8 2 1 6 3 56 RP43A 7 8 RP25A 56 5 6 7 8 56 RP26A 5 6 7 8 RP24A 56 5 6 7 8 56 RP35A 5 6 7 8 RP23A 56 5 6 7 8 RP22A 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 A HD#59 HD#57 HD#50 HD#60 HD#61 HD#[63:0] 3,7 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION GTL TERMINATION Sheet: 5 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic HD#28 HD#38 HD#37 HD#39 HD#34 HD#43 HD#22 HD#36 HD#42 HD#41 HD#51 HD#49 HD#45 HD#44 HD#27 HD#47 HD#48 HD#63 HD#58 HD#53 HD#46 HD#62 HD#56 HD#40 HD#52 HD#55 HD#54 0.5 REV. A A ICH_CLK14 12 L18A VCC3_3 SIO_CLK14 14 - PCI_0/ICH pin has to go to the ICH. (This clock cannot be turned off through SMBus) - CPU_ITP pin has to go to the ITP. It is the only CPU CLK that can be shut off through the SMBUS interface. - Place all decoupling caps as close to VCC/GND pins as possible Notes: L_CKVDDA C53A .001UF C52A 0.1UF USBCLK DOTCLK PCLK_5 PCLK_6 24 13 12 9 PCLK_2 15 PCLK_0/ICH 14 PCLK_1 11 ICH_3V66 GMCH_3V66 Y1A 0.1UF C39A 33 R53A 33 R46A 33 33 R44A R43A 22 R42A USB_1 USB_0 PCI_6 in out 16 MHz 33 MHz APIC Clk Strap JP6A PCI_5 PCI_2 PCI_1 PCI_0 A 3V66_1 3V66_0 XTAL_OUT 14.318MHZ XTAL_IN C386A .1UF C40A C388A 22UF XTAL_OUT 3V66_1 3V66_0 10K R23A JP6A JP1 23 VSS_A 22 VDD_A 25 USB_0 26 USB_1 19 PCI_6 20 PCI_7 16 PCI_4 18 PCI_5 13 PCI_2 15 PCI_3 11 PCI_0/ICH 12 PCI_1 8 7 1 REF0 4 3 XTAL_IN U1A .001UF PCIV3 .001UF Minimize Stub Length from CLK14 trace to JP1A. 22 R47A 33 R51A 33 R50A 22 R49A 12PF C49A 12PF C51A C37A .001UF 0.1UF 2 C38A REFCLK 8 12 10 10 R48A R184A 22UF C158A 1 1 + 2 L13A XTAL VCC3_3 2 1 0.1UF MEMV3 1 USB PCI ICS9250-10 .1UF CPU Memory 34 56 DRAM_2 .001UF C46A DCLK DRAM_7 DRAM_6 DRAM_5 DRAM_4 DRAM_3 0.1UF C47A 22 22 R30A 22 R29A 22 R28A R27A 33 33 R26A R32A 4.7UF C56A 22 R40A 22 22 R39A 22 R38A 22 R37A R36A 33 R35A 2 VCC3_3 ITPCLK 7 4,9 L_VCC2_5 FREQSEL 24,27 20 20 CK_SMBCLK CK_SMBDATA 8 MEMCLK[7:0] CK_PWRDN# DCLK_WR MEMCLK7 MEMCLK6 MEMCLK5 MEMCLK4 MEMCLK3 MEMCLK2 MEMCLK1 4 GMCHHCLK 4 APICCLK_ICH CPUHCLK 4 11 APICCLK_CPU 22UF C48A L16A MEMCLK0 0.1UF C61A 33 R25A .001UF C64A 1 L15A VCC2_5 10 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION CLOCK SYNTHESIZER Sheet: 6 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic VSS2_5[0] 48 VSS2_5[1] VDD2_5[0] 51 VDD2_5[1] 53 SEL0 28 SDATA 30 SEL1 29 PWRDWN# 32 SCLK 31 DCLK SDRAM_6 37 SDRAM_7 36 SDRAM_4 40 SDRAM_5 39 SDRAM_2 43 SDRAM_3 42 DRAM_0 SDRAM_0 46 SDRAM_1 45 DRAM_1 CPU_2 33 R34A 0.1UF C63A CPU_2/ITP 49 CPU_0_1 CPU_0 52 CPU_1 50 APIC_1 APIC_0 .001UF C60A APIC_0 55 APIC_1 54 8.2K R41A C387A C385A .001UF 2 VCC3_3 APIC L17A CK_Whitney 3V66 REF USBV3 VDD3_3[2] 10 VDD3_3[3] 21 14 VSS3_3[2] 17 VSS3_3[3] 1 + 2 C50A VDD3_3[4] 27 VDD3_3[5] 33 24 VSS3_3[4] 35 VSS3_3[5] C55A VSS3_3[0] 5 2 VDD3_3[0] 2 VDD3_3[1] 9 VSS3_3[1] 6 1 VDD3_3[6] 38 VDD3_3[7] 44 41 VSS3_3[6] 47 VSS3_3[7] Clock Synthesizer SEL1_PU 1 + 2 A 1 + 2 2 1 Rev . 0.5 A A R81A 150 1% .001UF 0.1UF GMCHGTLREF RS#[2:0] HREQ#[4:0] V2 HA16# AC2 HA17# AA2 HA18# Y3 HA19# HA#16 HA#18 C161A T5 HA14# W2 HA15# HA#14 AA3 HA24# Y2 HA25# AB5 HA26# AC4 HA27# Y1 HA28# AC5 HA29# HA#24 HA#26 HA#28 Place site w/in 0.5" of clock ball (V6) 18PF N2 RS2# RS#2 RS#1 N5 RS0# P2 RS1# P4 HREQ2# R2 HREQ3# R5 HREQ4# R4 HREQ0# T2 HREQ1# RS#0 HREQ#4 HREQ#3 HREQ#2 HREQ#1 HREQ#0 HA#31 HA#30 HA#29 HA#27 HA#25 HA#23 Y4 HA30# AB1 HA31# AB2 HA22# AC3 HA23# HA#22 HA#21 AB3 HA20# AA1 HA21# HA#20 HA#19 HA#17 HA#15 HA#13 W3 HA12# W4 HA13# W1 HA10# U4 HA11# T4 HA7# U2 HA8# U3 HA9# V4 HA5# V1 HA6# U5 HA3# U1 HA4# P1 HIT# R1 HITM# N4 HTRDY# M4 DBSY# N1 DRDY# T3 BNR# T1 BPRI# R3 DEFER# N3 ADS# AB4 CPURST# P5 HLOCK# HA#12 HA#11 HA#10 HA#9 HA#8 HA#7 HA#6 HA#5 HA#4 HA#3 Do not Stuff C398 HA#[31:3] 4,5 HITM# 4,5 HTRDY# 3,5 3,5 DRDY# 4,5 HIT# DBSY# 4,5 4,5 BNR# BPRI# 4,5 4,5 HADS# DEFER# 4,5 4,5 HLOCK# CPURST# GMCHHCLK PCIRST# 4,5 4,5 6 3,5 11,13,14,15,16,23 V6 HTCLK M2 RESETB M5 GTLREFA W13 GTLREFB VCC1_8[1] P6 VCC1_8[2] U18 PART1 INTEL 82810 HOST INTERFACE K14 VSS[7] K13 VSS[8] C167A K12 VSS[9] K11 VSS[10] C166A VCC_CORE[0] V17 VCC_CORE[1] V16 K10 VSS[11] L14 VSS[12] VCC1_8 VCC_CORE[2] V15 VCC_CORE[3] V14 L13 VSS[13] L12 VSS[14] VCC1_8[0] B20 C19 VSS[5] E22 VSS[6] U2A Y22 VSS[0] VCC_CORE[4] V10 VCC_CORE[5] V9 A L11 VSS[15] L10 VSS[16] R80A 75 1% V18 VSS[1] N22 VSS[2] VCC_CORE[6] V8 VCC_CORE[7] V7 M14VSS[17] M13VSS[18] VTT1_5 VCC_CORE[8] F17 VCC_CORE[9] F16 M12VSS[19] J22 VSS[3] Y19 VSS[4] 82810, PART 1: HOST INTERFACE VCC_CORE[10] F14 VCC_CORE[11] F10 M11VSS[20] M10VSS[21] A VCC_CORE[12] F8 VCC_CORE[13] F7 N14 VSS[22] N13 VSS[23] HD62# AC18 HD63# AB17 HD60# AB19 HD61# Y18 HD58# AC19 HD59# Y16 HD56# W18 HD57# W16 HD54# W17 HD55# AA17 HD52# W15 HD53# AB18 HD50# AA18 HD51# AB15 HD48# AC17 HD49# AC16 HD46# Y17 HD47# Y15 HD44# AA14 HD45# AB14 HD42# Y14 HD43# AC13 HD40# AA15 HD41# AC15 HD38# Y12 HD39# AC14 HD36# AA13 HD37# Y13 HD34# W12 HD35# AA11 HD32# W11 HD33# AC11 HD30# Y9 HD31# AC12 HD28# AB12 HD29# Y11 HD26# Y10 HD27# AB16 HD24# AB9 HD25# AB11 HD22# AB13 HD23# AB10 HD20# AB8 HD21# AC10 HD18# Y7 HD19# AA10 HD16# W9 HD17# AC9 HD14# W7 HD15# AC6 HD12# AA7 HD13# Y8 HD10# AB7 HD11# AC8 HD8# V5 HD9# AC7 HD6# AA5 HD7# AA9 HD4# AB6 HD5# Y6 HD2# W8 HD3# AA6 HD0# Y5 HD1# W5 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 3,5 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION 82810 ,PART 1: HOST INTERFACE Sheet: 7 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic HD#[63:0] Rev . 0.5 A A 6 470PF C299A 470PF C300A DCLK_WR HUBREF_CG R176A 56 R177A 56 HUBREF_CV GMCH and ICH. Circuit in middle of Place HUBREF Generation HUBREF 22PF C168A 0K R31A R131A 301 1% R130A 301 1% VCC1_8 11 6 SM_CAS# 10 10 11 11 11 HLSTB# HLSTB HL[10:0] GMCH_3V66 SM_CKE[1:0] SM_WE# SM_RAS# 10 SM_CS#[3:0] 10 SM_BS[1:0] 10 SM_DQM[7:0] SM_MAA11 Place C241A as close as possible to GMCH 10 10 SM_MAA9 SM_MAA10 C241A 0.1UF 10 5 4 18PF C236A HUBREF HL10 HL9 HL8 HL7 HL6 HL5 HL4 HL3 HL2 HL1 HL0 SCLK SM_CKE1 SM_CKE0 SM_CS#3 SM_CS#2 SM_CS#1 SM_CS#0 SM_BS1 SM_BS0 SM_DQM7 SM_DQM6 SM_DQM5 SM_DQM4 SM_DQM3 SM_DQM2 SM_DQM1 SM_DQM0 6 3 7 RP77A 10 5 2 4 SM_MAA7 6 7 8 8 3 SM_MAA6 RP70A 1 2 SM_MAA5 SM_MAA8 1 SM_MAA4 SM_MAA3 SM_MAA2 SM_MAA1 A20 HLSTB# D18 HCOMP D20 HUBREF A21 HLSTB C20 HL9 A19 HL10 A18 HL7 A22 HL8 B18 HL5 C18 HL6 A23 HL3 B19 HL4 B23 HL1 B22 HL2 D19 HLCLK C21 HL0 E6 SCLK A3 SCKE0 A2 SCKE1 B11 SWE# D8 SRAS# A11 SCAS# B3 SCS2# C2 SCS3# C4 SCS0# C3 SCS1# C5 SBS0 E5 SBS1 C1 SDQM6 D2 SDQM7 B10 SDQM4 D9 SDQM5 B1 SDQM2 D1 SDQM3 C10 SDQM0 A10 SDQM1 B4 SMAB6# A4 SMAB7# B6 SMAB4# A6 SMAB5# A5 SMAA11 C6 SMAA9 D5 SMAA10 A7 SMAA7 D6 SMAA8 A8 SMAA5 B7 SMAA6 A9 SMAA2 D7 SMAA3 B8 SMAA4 HUB I/F HUB INTERFACE AND SYSTEM MEMORY PART 2 INTEL 82810 N10 VSS[26] P14 VSS[27] C9 SMAA0 E7 SMAA1 P13 VSS[28] P12 VSS[29] SM_MAA0 VCC3_3[3] C15 VCC3_3[4] L3 P11 VSS[30] P10 VSS[31] SM_MAA[11:0] VCC3_3[5] G3 VCC3_3[6] F15 AC1VSS[32] AA4 VSS[33] 10 VCC3_3[7] F9 VCC3_3[8] K6 A AA8 VSS[34] AA12 VSS[35] U2B VCC3_3[9] F6 VCC3_3[10] B2 AA16 VSS[36] W6 VSS[37] R82A 40 1% VCC3_3[0] D4 GHCOMP VCC3_3 W10VSS[38] W14VSS[39] Place Resistor as Close as possible to GMCH VCC3_3[1] C11 VCC3_3[2] C7 VCC3_3SBY V3 VSS[40] R6 VSS[41] VCC1_8 VCC3_3[14] J18 VCC3_3[15] R18 P3 VSS[42] M1 VSS[43] 82810, PART 2: SYSTEM MEMORY AND HUB INTERFACE N12 VSS[24] N11 VSS[25] L21 VCC3_3[11] VCC3_3[12] G21 F18 VCC3_3[13] A L4 VSS[44] J2 VSS[45] SMD62 K5 SMD63 L5 SMD60 H6 SMD61 J5 SMD58 H5 SMD59 H4 SMD56 F5 SMD57 G5 SMD54 F4 SMD55 J3 SMD52 E4 SMD53 E3 SMD50 G2 SMD51 H3 SMD48 F3 SMD49 F1 SMD46 E8 SMD47 C8 SMD44 E10 SMD45 E9 SMD42 D11 SMD43 D10 SMD40 B12 SMD41 C12 SMD38 D12 SMD39 B15 SMD36 E13 SMD37 E12 SMD34 D14 SMD35 E14 SMD32 D16 SMD33 E15 SMD30 M3 SMD31 K4 SMD28 L1 SMD29 L2 SMD26 K1 SMD27 K3 SMD24 J1 SMD25 K2 SMD22 H1 SMD23 J4 SMD20 D3 SMD21 H2 SMD18 G4 SMD19 G1 SMD16 E1 SMD17 F2 SMD14 A13 SMD15 A12 SMD12 D13 SMD13 C13 SMD10 B14 SMD11 A14 SMD8 A15 SMD9 C14 SMD6 A16 SMD7 B16 SMD4 C17 SMD5 A17 SMD2 D15 SMD3 D17 SMD0 E17 SMD1 C16 SM_MD0 SM_MD63 SM_MD62 SM_MD61 SM_MD60 SM_MD59 SM_MD58 SM_MD57 SM_MD56 SM_MD55 SM_MD54 SM_MD53 SM_MD52 SM_MD51 SM_MD50 SM_MD49 SM_MD48 SM_MD47 SM_MD46 SM_MD45 SM_MD44 SM_MD43 SM_MD42 SM_MD41 SM_MD40 SM_MD39 SM_MD38 SM_MD37 SM_MD36 SM_MD35 SM_MD34 SM_MD33 SM_MD32 SM_MD31 SM_MD30 SM_MD29 SM_MD28 SM_MD27 SM_MD26 SM_MD25 SM_MD24 SM_MD23 SM_MD22 SM_MD21 SM_MD20 SM_MD19 SM_MD18 SM_MD17 SM_MD16 SM_MD15 SM_MD14 SM_MD13 SM_MD12 SM_MD11 SM_MD10 SM_MD9 SM_MD8 SM_MD7 SM_MD6 SM_MD5 SM_MD4 SM_MD3 SM_MD2 SM_MD1 10 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 8 of 33 Last Revision Date: 82810, PART 2: SYSTEM MEMORY AND HUB INTERFACE Electronic Classroom Student Computing Station Ref. Schematic SM_MD[63:0] Rev . 0.5 A A 7 2 8 1 R_LTCLK E20 LMD17 E21 LMD18 N20 LMD14 M23 LMD15 F23 LMD16 P22 LMD11 N23 LMD12 N21 LMD13 P23 LMD10 R22 LMD8 R21 LMD9 K23 LMD5 R19 LMD6 R20 LMD7 K21 LMD4 L23 LMD2 L22 LMD3 M22 LMD0 M21 LMD1 M20 LMA10 L19 LMA11 Place R70A within 0.5" of the GMCH Ball. OCLK_FB 0K R128A 33 22PF C238A OCLK RCLK Do Not Populate C238 R129A 22 J20 LRCLK J23 LOCLK K22 LTCLK F21 LMD30 F22 LMD31 G22 LMD28 G23 LMD29 H23 LMD26 G20 LMD27 H21 LMD24 H22 LMD25 TBD R127A DC_MD26 DC_MD27 DC_MD28 H18 LMA7 G19 LMA8 F19 LMA9 JP13 RESVD DC_MD30 DC_MD29 H19 LMA5 H20 LMA6 P20 LMA2 N19 LMA3 J21 LMA4 M19 LMA0 P19 LMA1 J19 LWE# K19 LRAS# K20 LCAS# C23 LDQM2 F20 LDQM3 D21 LMD22 C22 LMD23 VCORE Detect Reads System Bus Freq. *OUT = Normal IN = Tri-state Mode 4,6 DC_MD31 4 Detects type of Processor I/O Buffers JP14 IOQ Depth Comment IN = XOR Tree *OUT = Normal JP13A JP14A JP15A JP16A 10K VCCDET N/A N/A System Bus Freq. 8 1 E23 LMD19 D22 LMD20 D23 LMD21 JP15 Tri-state 7 2 IN = IOQ Depth of 1 *Out = IOQ Depth of 4 JP16 Jumper 10K RP48A XOR Function RP46A 6 3 GRS_PU28 5 4 GRS_PU26 6 3 GRS_PU31 5 4 GRS_PU30 FREQSEL VSSHA T6 U6 VCCHA INTERFACE VIDEO DIGITAL OUT DISPLAY CACHE LTVDATA10 T22 LTVDATA11 T21 LTVDATA8 U21 LTVDATA9 T23 LTVDATA6 U23 LTVDATA7 U22 LTVDATA4 W21 LTVDATA5 V23 LTVDATA2 W23 LTVDATA3 W22 LTVDATA0 Y21 LTVDATA1 Y20 VCCDACA A W20 W19 A BLUE GREEN AC23 RED AC21 AC22 VSYNC AA20 HSYNC AB20 IREF AA23 DCLKREF AA21 IWASTE Y23 DDCCL DDCDA LTVCL T19 LTVDA T20 CLKOUT1 V22 TVVSYNC V20 TVHSYNC U19 V19 BLANK# TVCLKIN/SL_STALL U20 CLKOUT0 V21 GRAPHICS INTERFACE PART3 INTEL 82810 VCCBA E19 J6 VSS[46] G6 VSS[47] E2 VSS[48] A1 VSS[49] VCC3_3 B5 VSS[50] B9 VSS[51] L20 LCS# E11 VSS[52] B13 VSS[53] P21 LDQM0 R23 LDQM1 E16 VSS[54] B17 VSS[55] GMCH RESET STRAPS E18 VSSBA AC20 VCCDA AB23 VCCDACA1 AB21 VCCDACA2 B21 VSS[56] G18 VSS[57] U2C K18 VSS[58] P18 VSS[59] VCC1_8 T18 VSS[60] AA19 VSS[61] 82810, PART 3 AA22 VSSDA C217A R125A 174 1% IREFPD 0.01UF C216A 3VDDCCL CRT_HSYNC 21 21 21 VID_GREEN 21 VID_BLUE 21 VID_RED 21 6 CRT_VSYNC DOTCLK 68NH-0.3A L24A VCC1_8 Place site w / in 0.5" of clock ball (AA21). Do not Stuff C379A DOTCLK 18PF C379A Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 9 of 33 Last Revision Date: INTEL CORPORATION 82810, PART 3: GRAPHICS Electronic Classroom Student Computing Station Ref. Schematic Use Surface Mount Caps placed close as possible to power pins with short, wide direct connections 3VDDCDA 21 4.7K R64A VCC3_3SBY 0.1UF C222A Place as close as Possible to GMCH and via straight to VSS plane. 4.7K R62A 1 2 JP16 AB22 VSSDACA 33UF + Rev . 0.5 A A 8 8 8 VCC3_3SBY 6 8 SM_BS[1:0] SM_DQM[7:0] MEMCLK[7:0] SM_MAA[11:0] J11A VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 6 VCC1 18 26 40 41 90 102 110 124 49 59 73 84 133 143 157 168 12,21,24,29 SM_RAS# SM_WE# SM_CAS# SMBCLK SM_MAA5 DQ9 13 DQ10 14 34 A2 118 A3 SM_MAA3 DQ7 10 DQ8 11 33 A0 117 A1 SM_MAA1 79 CLK2 163 CLK3 MEMCLK3 42 CLK0 125 CLK1 MEMCLK1 MEMCLK0 MEMCLK2 SM_MAA0 SM_MAA2 SM_MAA4 SM_CS#[3:0] SMBDATA DQ11 15 DQ12 16 35 A4 119 A5 SM_MAA6 8 8 8 8 SM_CKE[1:0] DQ13 17 DQ14 19 36 A6 120 A7 SM_MAA7 SM_MAA8 8 12,21,24,29 DQ15 20 DQ16 55 37 A8 121 A9 SM_MAA9 SM_MAA10 DQ3 5 DQ4 7 DQ5 8 DQ6 9 130 DQMB6 131 DQMB7 SM_DQM7 112 DQMB4 113 DQMB5 SM_DQM5 DQ27 72 DQ28 74 46 DQMB2 47 DQMB3 SM_DQM3 DQ25 70 DQ26 71 28 DQMB0 29 DQMB1 SM_DQM1 122 BA0 39 BA1 SM_BS1 SM_BS0 SM_DQM0 SM_DQM2 SM_DQM4 DQ23 67 DQ24 69 A DIMM SOCKET 168 PIN DQ29 75 DQ30 76 DQ31 77 DQ32 86 DQ33 87 DQ34 88 DQ35 89 DQ36 91 DQ37 92 DQ38 93 DQ39 94 DQ40 95 DQ41 97 DQ42 98 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 VCC3_3SBY ECC6 136 ECC7 137 162 VSS1 1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 INTEL CORPORATION DQ53 149 DQ54 150 24 NC1 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63 ECC0 21 ECC1 22 ECC2 52 ECC3 53 ECC4 105 ECC5 106 VSS18 SYSTEM MEMORY Sheet: 10 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic 2.2K R63A DQ55 151 DQ56 153 25 NC2 31 NC3 A 30 S0# SM_CS#0 SM_DQM6 SM_MD[63:0] SM_MD0 DQ0 2 DQ17 56 DQ18 57 38 A10 123 A11 SM_MAA11 SM_CS#1 128 CKE0 63 CKE1 DQ43 99 DQ44 100 DQ45 101 DQ46 103 DQ57 154 DQ58 155 44 NC4 48 NC5 DQ61 159 DQ62 160 DQ63 161 SYSTEM MEMORY SM_MD1 DQ1 3 DQ2 4 DQ19 58 DQ20 60 126 A12 132 A13 DQ21 65 DQ22 66 114 S1# 45 S2# 129 S3# 27 WE# 111 CAS# 115 RAS# SM_CKE0 SM_CKE1 82 SMBDATA 83 SMBCLK DQ47 104 DQ48 139 147 REGE 165 SA0 DQ49 140 DQ50 141 166 SA1 167 SA2 DQ51 142 DQ52 144 81 WP DQ59 156 DQ60 158 50 NC6 51 NC7 61 NC8 62 NC9 80 NC10 108 NC11 109 NC12 134 NC13 135 NC14 145 NC15 146 NC16 164 NC17 REV 0.5 A A 29 15,23 29 29 PCI_PME# PAR SERR# PLOCK# STOP# PCIRST# REQ#B/GPIO1 GNT#B/GPIO17 PCPCI_REQ#A 15,23 15,23,29 15,29 15,23,29 7,13,14,15,16,23 GNT#B/GPIO17 REQ#B/GPIO1 GNT#A/GPIO16 REQ#A/GPIO0 PME# SERR# PAR PLOCK# PCIRST# STOP# TRDY# IRDY# DEVSEL# IRDY# TRDY# FRAME# FRAME# DEVSEL# 15,23,29 15,23,29 15,23,29 15,23,29 PCICLK C_BE#0 C_BE#0 C_BE#1 C_BE#1 C_BE#2 C_BE#2 C_BE#3 C_BE#3 AD0 AD0 AD1 AD1 AD2 AD2 AD3 AD3 AD4 AD4 AD5 AD5 AD6 AD6 AD7 AD7 AD8 AD8 AD9 AD9 AD10 AD10 AD11 AD11 AD12 AD12 AD13 AD13 AD14 AD14 AD15 AD15 AD16 AD16 AD17 AD17 AD18 AD18 AD19 AD19 AD20 AD20 AD21 AD21 AD22 AD22 AD23 AD23 AD24 AD24 AD25 AD25 AD26 AD26 AD27 AD27 AD28 AD28 AD29 AD29 AD30 AD30 AD31 AD31 PCLK_0/ICH C_BE#[3:0] AD[31:0] 6 15,23 15,23 R5 P4 P5 N6 K1 A1 A9 B9 J5 D5 C4 A2 D9 B3 C14 D6 A3 B2 D2 C7 D8 C9 B7 A8 A7 B8 D7 B6 A6 E7 B5 C6 C5 B4 A4 C3 D4 B1 C1 C2 E4 D3 D1 E2 E1 F5 F4 F3 F2 G4 G2 VCC3_3_4 T7 VCC3_3_5 U10 VCC3_3_2 G5 VCC3_3_3 P6 VCC3_3_6 R13 VCC3_3_7 T16 PC/PCI PCI VCC3_3_15 N5 PART 1 82801AA VCC3_3_8 M14 VCC3_3_9 C11 R2 VSS1 U14A VCC3_3_10 C8 VCC3_3_11 A5 G3 VSS2 H8 VSS3 VCC3_3_1 E3 VCC3_3 J8 VSS4 K8 VSS5 VCC1_8 IRQ15 PCI RESV[2] RESV[1] RESV[0] GNT#3 GNT#2 GNT#1 GNT#0 REQ#3 REQ#2 REQ#1 REQ#0 SERIRQ APICD0 APICD1 APICCLK IRQ14 INTERRUPTS PIRQ#D PIRQ#C PIRQ#B PIRQ#A HLSTB# HLSTB HL10 HL6 HUB I/F HL7 HL5 HL4 HL3 HL2 HL1 HL0 RCIN# STPCLK# SMI# CPU NMI INTR INIT# IGNNE# FERR# CPUSLP# VCC1_8_4 G15 VCC1_8_5 L15 82801AA , Part 1 VCC1_8_1 G13 J10 VSS10 K10 VSS11 VCC3_3_12 E6 VCC3_3_13 E5 VCC3_3_14 D16 H9 VSS6 J9 VSS7 VCC1_8_2 H14 VCC1_8_3 K14 G14 VSS12 K15 VSS13 VCC3_3_16 N13 VCC3_3_17 E13 K9 VSS8 H10 VSS9 VCC1_8_6 H16 VCC1_8_7 J16 A A A15 A17 F14 B16 E14 E15 B17 F15 E12 F13 HL6 K17 RESV0PU RESV1PU RESV2PD B11 F16 A20M# 4,29 4,29 4,13,29 4,29 4,29 4,29 4,29 8 14,29 16,29 15,29 15,29 15,29 15,23,29 8 8 8.2K R175A PGNT#2 PGNT#3 PGNT#1 PGNT#0 PREQ#3 PREQ#2 PREQ#1 PREQ#0 SERIRQ APICD0 8.2K R174A 29 23,29 29 15,29 23,29 29 29 15,29 14,29 4,29 IRQ15 16,29 APICCLK_ICH 6 APICD1 4,29 IRQ14 PIRQ#D PIRQ#C PIRQ#B PIRQ#A HLSTB# HLSTB HL[10:0] A20GATE SMI# 4,29 STPCLK# 4,29 RCIN# 14,29 INTR NMI INIT# IGNNE# FERR# CPUSLP# For Test/Debug Don't Stuff R181A R181A 0K IHCOMP_PU HL10 A11 C12 A12 C13 A13 D12 B12 B13 A14 R4 E16 C17 C16 N14 P11 C10 B10 A10 D10 HCOMP M17 HUBREF J13 H17 G17 HL9 HL5 K16 HL9 J17 J14 HL4 J15 HL7 HL3 G16 HL8 HL2 F17 H15 HL8 HL1 E17 L17 HL0 D17 A20GATE B15 A20M# 0.1UF C302A Place R189 as close as possible to ICH0. VCC3_3 Place C172 as close as possible to ICH0. HUBREF 8 Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 11 of 33 Last Revision Date: INTEL CORPORATION ICH0, PART 1 Electronic Classroom Student Computing Station Ref. Schematic R182A 40 1% VCC1_8 REV 0.5 A A X3 BAT17 IN JP17A Strap ICH_SPKR R209A 10K JP13_PD R187A 10K VCC3_3 JP18A Use CPU freq. strap setting in ICH/0 register. OUT JP17A 2 RTCRST# AC_SDOUT Minimize Stub Length to Jumpers C366A 12PF 32.768KHZ 1 Y3A 10M R220A 2 13,14 SMBCLK SMBDATA SUS_STAT# 6 6 16 16 16 16 16 OC#0 USBP0N USBP0P USBP1N USBP1P 18PF M4 OC#1 M3 OC#0 P1 USBP0P N2 USBP0N R1 USBP1P P2 USBP1N N3 LDRQ#1/GPIO8 LDRQ#1 T5 LAD2/FWH2 R6 LAD0/FWH0 U5 LAD1/FWH1 29 C293A GPIO26 GPIO23 GPIO22 GPIO21 GPIO13 GPIO12 M5 GPIO27 L5 GPIO28 K4 D15 D13 B14 L2 N4 E9 GPIO7 D11 GPIO5 E11 GPIO6 LDRQ#0 LAD3/FWH3 13,14 AC_RST# T3 AC_SYNC R3 AC_BITCLK T2 AC_SDOUT U1 AC_SDIN0 P3 AC_SDIN1/GPIO9 U3 SPKR T1 H4 RTCX2 H1 RTCRST# 14 LAD2/FWH2 13,14 CLK66 CLK48 CLK14 H2 VBIAS H3 RTCX1 A16 U2 U6 LFRAME#/FWH4 LAD1/FWH1 SMBALERT#/GPIO11 A A J4 INTRUDER#/GPIO10 M1 J1 SMBDATA J2 SMBCLK F1 RSMRST# L4 SUSSTAT#/GPIO25 J3 PWROK M2 PWRBTN# L3 RI# K2 SLP_S5 D14 THRM# K3 SLP_S3/GPIO24 U14B T4 LAD3/FWH3 U4 LFRAME#/FWH4 T6 LDRQ#0 LAD0/FWH0 13,14 GPIO28 24 13,14 GPIO27 24 GPIO26_FPLED 27 GPIO22 GPIO23_FPLED 29 GPIO21 27 29 29 29 GPIO13 GPIO7 GPIO12 15,29 LPC_PME# LPC_SMI# 14,29 14,29 AC_SDIN1 22,29 ICH_SPKR AC_SDIN0 22,29 27 22 AC_BITCLK AC_SDOUT 22 AC_SYNC AC_RST# RTCRST# RTCX2 RTCX1 VBIAS ICH_3V66 USBCLK ICH_CLK14 INTRUDER# SMBALERT# 22 22 6 29 29 10,21,24,29 10,21,24,29 24 RSMRST# JP20A Force CPU freq. strap to safe mode (1111) AC_SDOUT 3 1 THERM# SLP_S3# 24,28 JP24_PD 2-3 29 24,25,28 PWROK 27 PWRBTN# 19 ICH_RI# 25,28 10K R203 10K R85 VCC3SBY Normal Clear CMOS JP20A Config. 1-2 No Reboot on 2nd watchdog timeout Reboot on 2nd watchdog timeout Speaker 12PF C346A R216A 1K VBATC_DLY BAT17 C IN JP18A Strap OUT 10M R197A 0.047UF C347A R_VBIAS Socketed 3vdc Lithium equivalent to Rayovac BR2325 1K R202A 2.2UF C364A 8.2K R219A 1.0UF C349A 1K R206A A CR13A VCC3_3SBY + VBATC C A VBAT 1 2 CR14A + JP14_PU VCCRTC G1 VCCSUS1 L1 VCCSUS2 N1 USB LPC GPIO AC97 PART 2 IDE ICH5VREF SDD14 R17 SDD15 P16 SDD12 U17 SDD13 R15 SDD10 P14 SDD11 T15 SDD8 U14 SDD9 T14 SDD6 P13 SDD7 T13 SDD4 U15 SDD5 R14 SDD2 T17 SDD3 U16 SDD0 P15 SDD1 R16 PDD14 T10 PDD15 P10 PDD12 T9 PDD13 P9 PDD10 T8 PDD11 P8 PDD8 P7 PDD9 N7 PDD6 R7 PDD7 U7 PDD4 R8 PDD5 U8 PDD2 R9 PDD3 U9 PDD0 R10 PDD1 N9 PIORDY N11 SIORDY N17 PDIOW# T11 SDIOW# N15 PDIOR# R11 SDIOR# N16 SDDREQ P17 PDDACK# U12 SDDACK# M13 PDDREQ U11 SDA1 M15 SDA2 L13 PDA2 P12 SDA0 M16 PDA0 R12 PDA1 T12 PDCS#3 U13 SDCS#3 L16 PDCS#1 N12 SDCS#1 L14 1.0UF C290A SDD15 SDD14 SDD13 SDD12 SDD11 SDD10 SDD9 SDD8 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PDD9 PDD8 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 SDA2 SDA1 SDA0 PDA2 PDA1 PDA0 0.1UF C294A SDD[15:0] PDD[15:0] SIORDY PIORDY SDIOW# PDIOW# 16 16 16 16 16 16 16 SDIOR# 16 16 PDIOR# 16 SDDACK# 16 16 16 PDDACK# SDREQ PDREQ SDA[2:0] VCC5 R173A 1K 16 16 PDA[2:0] 16 SDCS#3 16 16 PDCS#3 SDCS#1 PDCS#1 BAT17 CR11A VCC3_3 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION 82801AA, PART 2 Sheet: 12 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic INTEL 82801AA (ICH) SYSTEM VRTC VCC3_3SBY C15 5VREF A C 82801AA , Part 2 SLP_S5# REV 0.5 A A VPP and WP# are tied to 3.3v in this configruation Write Protection is register based with the exception of the Boot Block. Notes: JP21A CONFIG IN Unlocked Default OUT Locked JP21A 0.1UF 0.1UF R223A 4.7K VCC3_3 C36A C353A R218A 0K VCC3_3 P66DETECT 16 4.7K R222A S66DETECT PCIRST# PCLK_6 16 7,11,14,15,16,23 6 8.2K TBLK_LCK WP ROT R_VPP IC_PD 4 5 FGPI4_PD 3 6 FGPI3_PD 2 7 FGPI2_PD 1 8 VCC3_3 VCC3_3 X4A RP63A A 20 TBL# 14 NC14 15 FGPI3 16 FGPI2 17 FGPI1 18 FGPI0 19 WP# 12 RST# 13 NC13 10 VCC10 11 VPP FGPI4 8 NC8 9 CLK 7 5 NC5 6 NC6 3 NC3 4 NC4 1 NC1 2 IC 33 34 35 36 37 38 39 40 ID2 22 21 ID3 ID0 24 ID1 23 FWH1 26 FWH0 25 FWH3 28 FWH2 27 GND30 30 GND29 29 RFU32 32 VCC31 31 RFU33 RFU34 RFU35 RFU36 INIT# FWH4 VCCA GNDA 40PIN_TSOP_SKT 0K FWH_ID0 FWH_ID1 FWH_ID2 FWH_ID3 0.1UF C361A 0.1UF C259A 0.1UF 12,14 12,14 12,14 LAD1/FWH1 LAD0/FWH0 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION FIRMWARE HUB (FWH) Sheet: 13 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic RP64A for Test/Debug RP64A 12,14 LAD2/FWH2 12,14 LAD3/FWH3 LFRAME#/FWH4 INIT# 4,11,29 Distribute close to each power pin. C355A 0.1UF C211A VCC3_3 4 5 NOTE: This is a Socketed Implementation 3 6 FirmWare Hub (82802AB) Socket 2 7 A 1 8 REV 0.5 A A IRRX IRTX 27 27 LAD1/FWH1 LAD0/FWH0 12,13 12,13 C371A 470PF C356A 470PF 20 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 19 19 19 19 19 TRK#0 SIO_CLK14 6 RDATA# DSKCHG# 20 20 INDEX# 20 20 WRTPRT# HDSEL# 20 20 WGATE# 20 STEP# DIR# DS#0 WDATA# 20 20 20 MTR#0 DRVDEN#0 20 20 TXD1 DSR#1 19 19 DRVDEN#1 RXD#1 19 RI#0 DTR#0 CTS#0 RTS#0 DCD#0 19 19 19 19 DSR#0 TXD0 RXD#0 A20GATE 19 19 19 19 20 11,29 RCIN# 19 11,29 KCLK 19 MDAT MCLK 19 KDAT 19 PCLK_1 SERIRQ 11,29 6 PCIRST# LPC_PME# 12,29 LDRQ#0 LAD2/FWH2 12,13 12 LAD3/FWH3 LFRAME#/FWH4 12,13 7,11,13,15,16,23 12,13 SUSSTAT_PU U15A 6 CLKI32 19 CLOCKI 16 RDATA# 4 DSKCHG# 14 TRK0# 15 WRTPRT# 12 HDSEL# 13 INDEX# 10 WDATA# 11 WGATE# 8 DIR# 9 STEP# 3 MTR0# 5 DS0# 2 DRVDEN1 1 DRVDEN0 94 DCD2# 99 CTS2# 100 DTR2# 92 RI2# 97 DSR2# 98 RTS2# 95 RXD2_IRRX 96 TXD2_IRTX 90 RI1# 91 DCD1# 88 CTS1# 89 DTR1# 86 DSR1# 87 RTS1# 84 RXD1 85 TXD1 61 IRRX2/GP34 62 IRTX2/GP35 63 KBDRST 64 A20GATE 58 MDAT 59 MCLK 56 KDAT 57 KCLK 30 SERIRQ 29 PCI_CLK 26 LRESET# 27 LPCPD# 17 PME# 20 LAD0 25 LDRQ# 22 LAD2 21 LAD1 24 LFRAME# 23 LAD3 4.7K R183A 44 CLOCKS FDC I/F SERIAL PORT 2 SERIAL PORT 1 INFRARED I/F KYBD/MSE I/F LPC47B27X SIO 18 18 SYSOPT GP24/SYSOPT 45 GP22/P12 43 GP20/P17 41 GP21/P16 42 GP16/J2X 38 GP17/J2Y 39 GP14/J1X 36 GP15/J1Y 37 GP12/J2B1 34 GP13/J2B2 35 GP10/J1B1 32 GP11/J1B2 33 GP26/MIDI_OUT 47 GP31/FAN_TACH1 52 GP25/MIDI_IN 46 GP27/IO_SMI# 50 GP30/FAN_TACH2 51 27 20 20 A R180A 4.7K Pulldown on SYSOPT for IO address of 0x02E SIO_GP22 JOY2Y 20 KEYLOCK# 27 SIO_GP21 JOY2X 20 20 20 JOY1Y JOY1X 20 20 J2BUTTON2 20 J2BUTTON1 J1BUTTON2 20 12,29 J1BUTTON1 MIDI_OUT MIDI_IN 27 TACH1 TACH2 LPC_SMI# SIO_GP61 SIO_GP60 27 27 PWM2 PWM1 STROBE# ALF# ACK# 18 ERROR# 18 PE 18 BUSY 18 SLCT# 18 18 PDR[7:0] GP60/LED1 48 GP61/LED2 49 PDR0 PD0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 SIO_GP43 FAN2/GP32 54 FAN1/GP33 55 STROBE# 83 ERROR# 81 ALF# 82 BUSY 79 ACK# 80 SLCT# 77 PE 78 PD1 69 68 PD3 71 PD2 70 PD5 73 PD4 72 PD7 75 PD6 74 18 18 SLCTIN# PAR_INIT# FDC_PP/DDRC/GP43 28 PARALLEL POR T I/F VTR 18 LPC I/F INIT# 66 SLCTIN# 67 VCC3_3 Decoupling J23A 2 4 6 1 3 5 Test/Debug Header Unused GPIOs C99A VCC3_3 0.1UF 0.1UF C229A 0.1UF C297A 0.1UF C246A VCC5 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION SUPER I/O VREF pin Place near Sheet: 14 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic Schematics Place 1 0.1UF cap near each power pin C287A VCC5 VCC1 53 60 GND3 76 GND4 2.2UF VCC3_3 A C323A Super I/O VCC2 65 VCC3 93 40 AVSS 1 + 2 VREF 7 GND1 31 GND2 0.1UF 0.5 REV. A A 23 11,29 29 11,23,29 11,23,29 11,23,29 PIRQ#B AD[31:0] PREQ#0 PCLK_2 PIRQ#D C_BE#[3:0] 6 PU1_ACK64# SERR# PERR# PLOCK# DEVSEL# IRDY# 11,23 11,23 11,29 11,29 11,29 VCC5 B21 B48 J17A PCI3_CON VCC12 AD28 AD26 A26 AD20 A29 AD16 AD11 A58 A59 A60 A61 A62 B58 B59 B60 B61 B62 A57 B57 AD1 A56 B56 A55 B55 B54 AD3 A54 B53 AD5 A53 B52 AD7 A52 A49 AD0 AD2 AD4 AD6 AD9 AD13 A47 A48 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 AD15 AD18 A32 A33 A31 A30 AD22 A28 A27 AD24 R_AD16 A25 A24 A23 AD30 VCC3_3SBY VCC3_3 VCC5 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AD8 B49 B47 AD10 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 AD12 AD14 C_BE#1 C_BE#2 AD17 B30 B31 B29 AD19 B28 B27 B26 AD21 AD23 C_BE#3 B24 AD25 B25 B23 AD27 B22 B20 AD29 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 VCC12- AD31 VCC3_3 PCI Connector 0 (DEV Ah) key 100 R168A AD[31:0] 7,11,13,14,16,23 11,23 11,23 11,29 29 11,23 11,23 29 PU1_REQ64# C_BE#0 PAR SBOP1 29 11,23,29 11,23,29 SDONEP1 STOP# TRDY# FRAME# 11,23,29 AD16 11,23 PCI_PME# PGNT#0 11,23,29 11,29 29 29 PCIRST# PIRQ#C PIRQ#A PTDI PTMS A A APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION PCI Connector Sheet: 15 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic REV 0.5 A A 12 27 12 PDA[2:0] IDEACTP# PDCS#1 PIORDY PDDACK# 11,29 IRQ14 12 PDIOR# 12 PDREQ PDIOW# 12 7,11,13,14,15,23 PDA2 PDA0 PDA1 PCIRST# R138A 12 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 5.6K 12 33 R_RSTP# PDD7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 R135A 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 5 A U11C VCC3_3 SN74LVC07A O 6 R141A 8.2K 0K R96A PCIRST_BUF# 15K R221A 16 PDCS#3 P66DETECT 12 13 For Host side 80-conductor Cable Detection: Populate R96A and R221A, Depopulate C187A For Drive side 80-conductor Cable Detection: Populate C187A, Depopulate R96A and R221A VCC3_3 R_P66DET PRI_PD1 PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PDD9 PDD8 R101A 16 PCIRST_BUF# J15A C187A R140A 470 PDD[15:0] A SDD[15:0] 12 SDA[2:0] 12 SDCS#1 27 IDEACTS# IRQ15 SIORDY SDDACK# 11,29 12 SDIOR# 12 12 SDREQ SDIOW# 12 12 16 PCIRST_BUF# 12 33 R139A SDA2 SDA0 SDA1 10K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J12A 1 15K R94A 0K R95A SDCS#3 S66DETECT 12 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 16 of 33 Last Revision Date: ULTRA ATA/33 IDE CONNECTORS 13 0.1 REV. For Host side 80-conductor Cable Detection: Populate R95A and R94A, Depopulate C186A For Drive side 80-conductor Cable Detection: Populate C186A, Depopulate R95A and R94A R_S66DET PRI_SD1 SDD15 SDD14 SDD13 SDD12 SDD11 SDD10 SDD9 SDD8 SECONDARY IDE CONN. Electronic Classroom Student Computing Station Ref. Schematic SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 R_RSTS# R134A 12 0.047UF R100A 1K R137A PRIMARY IDE CONN. 5.6K R133A 1K R132A 10K VCC5 C186A VCC5 A 470 ATA33/66 IDE CONNECTORS VCC 14 GND 7 0.047UF A A 22 12 OC#0 AC97_OC# .001UF C124A Do Not Stuff 0K R146A R147A A330K F3A 2 R201A 560K R72A 470K USBV5 2.5A POLYSWITCH RUSB250 VCC5 C202A C201A 1 VCC3_3 1 USBP1N USBP1P 12 12 L9A USBP0P 12 1 USBP0N 12 L23A 2 2 0.1UF 0.1UF 1 2 1 2 68UF 68UF C12A C9A AC97_USB+ 22 Do Not Stuff 0K R148A 0K R149A 47PF 47PF 15 R205A 15K R11A C357A 47PF C358A 47PF 15 R214A A 15 R211A R_USBP0P R_USBP0N R12A 15K Place R211A, R214A, C358A, and C357A within 1" of ICH0 C359A C348A 15 R204A Place R204A, R205A, C348A, and C359A within 1" of ICH0 AC97_USB- 22 A R63A 15K R14A 15K C15A 470PF C14A 470PF 0K 0K R15A R13A 2 1 2 USB Connectors + 1 + L10A L11A USBD0P 47PF C98A 47PF C8A 47PF C16A C13A J3A USB-CON2 DATA0- VCC0 GND 10 Place CAPs as close as possible to connector. GND1 GND 11 12 8 2 - USB Stack ed GND GND 9 VCC1 6 DATA17 DATA1+ 5 DATA0+ 4 GND0 3 2 1 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION USB CONNECTORS Sheet: 17 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic USBG1 USBD1P USBD1N USBV1 USBG0 USBD0N USBV0 47PF 0.1 REV. A A SLCTIN# PE SLCT# 14 BUSY 14 14 ACK# PDR[7:0] 14 14 14 ALF# STROBE# 14 PAR_INIT# 14 14 ERROR# 14 2 3 4 1 2 3 4 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 33 33 RP27A 5 6 7 8 5 6 7 8 5 4 1 6 PDR0 7 8 3 33 RP15A RP16A 2 1 VCC5 R_PDR7 R_PDR6 R_PDR5 R_PDR4 R_PDR3 R_PDR2 R_PDR1 R_PDR0 R_STROBE# R_ALF# R_PARINIT# 2.2K R224A PARV5 RP28A 8 C 1N4148 C197A CR1A R_SLCTIN# A 7 Parallel Port Header 6 1 A RP17A 2.2K 180PF 2 C196A 5 3 C194A 180PF 4 180PF C193A 7 8 RP13A 2.2K C192A 6 180PF 1 180PF 2 C190A 8 2.2K RP14A 2.2K 4 6 8 10 12 14 16 18 20 22 24 26 3 5 7 9 11 13 15 17 19 21 23 25 NOTE: J5A is pinned out for IDC (Flow Through) ribbon cable connector. 2 1 J5A APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION PARALLEL PORT HEADER Sheet: 18 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic C96A 7 180PF 6 1 180PF 2 C94A 5 3 C92A 180PF 4 180PF 3 C189A 8 C90A 7 C88A 1 180PF 6 180PF C89A 2 C93A 180PF 3 180PF C95A 5 4 180PF C97A 180PF 5 4 C91A 180PF A 180PF 0.5 REV. A A ICH_RI# do not stuff CR14A and Q2A. Serial Modem is not supported NOTE: If Wake from S3 on 12 2N7002LT1 Q10A 10K R230A VCC3_3SBY D S G ICHRI#_C 14 14 14 14 14 14 14 14 R229A 47K 14 14 14 14 14 14 14 14 RI#0 CTS#0 RTS#0 TXD0 DSR#0 DTR#0 DCD#0 RXD#0 RI#1 CTS#1 RTS#1 TXD1 DSR#1 DTR#1 RXD#1 DCD#1 C374A VCC5 47K R227A DY0 5 DY1 6 RA3 7 DY2 8 16 DA0 15 DA1 14 RY3 13 DA2 DY0 5 DY1 6 RA3 7 DY2 8 16 DA0 15 DA1 14 RY3 13 DA2 RA4 9 VCC-12 10 RA1 3 RA2 4 18 RY1 17 RY2 12 RY4 11 GND VCC12 1 RA0 2 GD75232 VCC12- 20 VCC 19 RY0 U16A RI#_CR_C RA4 9 VCC-12 10 RA1 3 RA2 4 18 RY1 17 RY2 12 RY4 11 GND VCC12 1 RA0 2 GD75232 20 VCC 19 RY0 3 2 1 VCC12 BAT54C CR15A VCC12 A 100PF U17A C325A C316A If not populated at all, remove CR14 and short RI#0_C to RI#CR 2nd COM Header Option C327A 100PF VCC12- 100PF 100PF VCC5 C328A C313A Serial Port/COM Headers C315A A 100PF 100PF C326A C312A 100PF C309A C314A 100PF C329A 100PF 100PF C330A C368A 100PF C311A 100PF 100PF C369A 100PF C310A 5 7 9 TXD#0_C CTS#0_C RTS#0_C 1 3 5 7 9 DTR#1_C TXD#1_C CTS#1_C RTS#1_C NOTE: J19A and J21A are pinned out for IDC (Flow Through) ribbon cable connector. J19A 10 8 6 4 2 Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 19 of 33 Last Revision Date: INTEL CORPORATION SERIAL PORT/ COM HEADERS Electronic Classroom Student Computing Station Ref. Schematic Place Close to Header RI#1_C 10 8 6 4 2 COM2 HEADER DSR#1_C RXD#1_C DCD#1_C J21A COM1 and COM2 are 2x5 pin Headers for a cabled port. 3 RI#0_C 1 DTR#0_C COM1 HEADER DSR#0_C RXD#0_C DCD#0_C Place Close to Header 100PF 100PF 1.0UF 0.5 REV. A 2 2 2 L_MCLK L_MDAT L_KCLK L_KDAT PS2V5 470PF 5 4 6 3 7 2 8 1 14 14 MIDI_IN MIDI_OUT R178A 4.7K R89A 4.7K 47 R179A VCC5 47 R88A NOTE: J7A is pinned out for IDC (Flow Through) ribbon cable connector. J7A R_MIDIIN R_MIDIOUT 1 2 VCC5 GAME PORT HEADER L6A L7A 2 2 3 A MCLK 1 1 1 L4A L5A 5 4 14 MDAT KCLK 14 1 L3A 7 8 14 KDAT 14 RP1A 4.7K C3A 1 9 0.1UF L2A 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 R_JOY2X R_JOY2Y R_JOY1Y R_JOY1X J1A 4 3 2 1 2.2K RP29A L1A PS2GND STACKED PS2 CONNECTOR PS/2 Kybd PS/2 Mse 1.25A C4A 470PF C5A 470PF C2A 470PF 13 14 C1A 2 1 PS2V5_F C178A 2 C179A 2 1 47PF F2A 5 6 7 8 RP30A VCC5 8 1 11 12 C176A 10 470PF 15 16 470PF 7 2 1 C79A 47PF 6 C177A C182A 47PF 6 3 VCC5 47PF 5 4 1K A C198A 0.01UF C191A 0.01UF C195A 0.01UF PS2_PD KEYBOARD/MOUSE PORTS A 0.01UF C199A RDATA# HDSEL# 14 14 14 14 JOY2X J2BUTTON2 J2BUTTON1 J1BUTTON2 14 14 14 14 14 14 JOY1Y JOY2Y JOY1X DSKCHG# TRK#0 WRTPRT# 14 14 WDATA# WGATE# 14 DIR# STEP# DS#0 14 14 14 14 MTR#0 INDEX# DRVDEN#1 DRVDEN#0 14 14 14 J1BUTTON1 14 14 7 6 5 3 4 1K 8 2 RP31A 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 J14A 2 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 20 of 33 Last Revision Date: KEYBOARD/MOUSE PORTS, FLOPPY DISK HEADER, GAME PORT HEADER Electronic Classroom Student Computing Station Ref. Schematic R143A 1K VCC5 FLOPPY DISK HEADER 0.5 REV. A 6 6 CK_SMBCLK CK_SMBDATA CRT_VSYNC 3VDDCCL CRT_HSYNC 9 9 9 3VDDCDA 9 1A1 13 BEB# 15 12 23 Do Not Populate 2.2K 2.2K R58A R59A GND 2B5 2B4 2B2 16 19 QSSDA 2B3 20 QSSCL 2B1 1B5 0K R120A 5VVSYNC 10 5VHSYNC 9 2 24 5 1B2 6 1B4 1B3 1B1 VCC QST3384 4 1A2 7 1A3 8 1A4 11 1A5 14 2A1 17 2A2 18 2A3 21 2A4 22 2A5 1 BEA# 3 U6A RP34A 0.1UF 5VDDCCL 5VDDCDA 2.2K 0K R119A 8 QS4_3V 7 1 5V to 3.3V Translation / Isolation 6 2 A 5 3 SMBCLK SMBDATA R115A 4.7K C CR4A 10,12,24,29 10,12,24,29 A VCC5 9 9 9 VID_BLUE VID_GREEN VID_RED 5VDDCDA A R66A 75 1% 5VVSYNC 5VDDCCL 5VHSYNC VCC5 BAT54S VCC1_8 1 2 1 2 3 R67A 75 1% CR8A 3 3 R69A 75 1% BAT54S 3 BAT54S CR5A BAT54S CR9A CR6A 1 2 1 2 VCC5 VCC1_8 Place R66A,R67A, & R69A Close to VGA Connector BAT54S 3 1 1 2 2 L19A BLM11B750S 1 2 Do Not Stuff C333 and C334 0K R64A Do Not Stuff C331 and C332 0K R71A BLM11B750S L20A BLM11B750S L21A BLM31A700S is rated at 70Ohms at 100MHz C111A C106A 1 C109A C105A C122A C102A C104A C227A C119A C100A C103A 3.3PF R65A 1K C116A F1A L12A 2.5A VCC5 2 L_VSYNC 15 5 10 4 14 MON2PU 9 3 FUSE_5 13 L_HSYNC 8 12 2 7 11 1 6 5 1 J6A L_BLUE L_GREEN MONOPU L_RED R74A 1K 10 6 15 11 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION VIDEO CONNECTORS Sheet: 21 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic 3.3PF CR10A C112A 2 10PF VCC1_8 C208A 1 2 1 10PF VGA Connector C101A 3.3PF 3.3PF 3.3PF 3.3PF 3.3PF 4 3.3PF 3.3PF 3.3PF Video Connectors 10PF A 10PF CRT5V_F 0.5 REV. A A AUDIO RISER 12 12 27 AC_RST# AC_SDOUT AC97SPKR VCC3_3 VCC12 VCC12- B2 B1 J18A AC97_MSTRCLK GND[6] AC97_SDATA_IN2 GND[5] AC97_SDATA_IN3 AC97_RESET# AC97_SDATA_OUT GND[4] RESV[4] RESV[3] GND[3] B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 +3.3VD KEY KEY B3 MONO_OUT/PC_BEEP B4 RESV[1] B5 RESV[2] B6 PRIMARY_DN# B7 -12V B8 GND[1] B9 +12V B10 GND[2] B11 +5VD GND[0] AUDIO_MUTE# VCC5 A AC97_BITCLK GND[14] AC97_SDATA_IN0 GND[13] AC97_SDATA_IN1 GND[12] AC97_SYNC GND[11] GND[10] S/P_DIF_IN GND[9] AMR_CONNECTOR USB- USB+ AC'97_RISER GND[8] USB_OC GND[7] RESV[7] RESV[6] RESV[5] A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VCC5 A23 A22 A21 A20 A19 A18 A17 A15 +3VDUAL/3VSBY A16 KEY KEY +5VDUAL/5VSBY AUDIO_PWRDWN MONO_PHONE A VCC3_3SBY AC97_OC# 12 12,29 12,29 12 16 16 16 Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 22 of 33 Last Revision Date: INTEL CORPORATION AC'97 RISER CONNECTOR Electronic Classroom Student Computing Station Ref. Schematic AC_BITCLK AC_SDIN0 AC_SDIN1 AC_SYNC AC97_USB- AC97_USB+ REV. 0.5 A A VCC3_3SBY C180A C261A C334A VCC3_3SBY C184A VCC3_3SBY C165A PERR# 24 7,11,13,14,15,16 PCLK_5 6 Y2A L_SMBD L_SMBCLK 24 24 LAN_RST# 24 LAN_ISOLATE# PGNT#3 PCIRST# 11,29 PREQ#3 11,29 SERR# AD20 15 PIRQ#A PAR STOP# DEVSEL# 11,15 11,15,29 11,15,29 11,15 11,15,29 11,15,29 IRDY# TRDY# FRAME# C_BE#[3:0] Close to Ball A10 25MHZ Place C68A/C255A 11,15,29 11,15,29 11,15,29 11,15 0.1UF 0.1UF 0.1UF 0.1UF 2 C68A 1 + 4.7UF 0.1UF 0.1UF 2 C255A 1 + C257A 4.7UF 100 R153A LAN_XTAL2 LAN_XTAL1 LAN Decoupling Distribute aroung Power Pins Close to 82559. C_BE#3 C_BE#2 VIO P11 X2 N11 X1 G2 VIO A10 SMBCLK C9 SMBD B9 ISOLATE# A9 ALTRST# C2 RST# G1 CLK A4 IDSEL C3 REQ# J3 GNT# A2 SERR# H2 INTA# J2 PERR# H1 STOP# J1 PAR G3 TRDY# H3 DEVSEL# F2 FRAME# F1 IRDY# F3 C/BE2# C4 C/BE3# M4 C/BE0# L3 C/BE1# C_BE#0 C_BE#1 AD31 A8 AD30 B8 AD31 C6 AD28 C7 AD29 B5 AD26 B6 AD27 B4 AD24 A5 AD25 B1 AD22 B2 AD23 D3 AD20 C1 AD21 D1 AD18 D2 AD19 N3 AD9 N2 AD10 M1 AD11 M2 AD12 M3 AD13 L1 AD14 L2 AD15 K1 AD16 E3 AD17 P4 AD6 N4 AD7 P3 AD8 N5 AD4 M5 AD5 VCCPP[4] N6 VCCPP[5] P2 VCCPP[2] E1 VCCPP[3] K3 M6 VSSPP[4] N1 VSSPP[5] VCCPP[0] A3 VCCPP[1] A7 E2 VSSPP[2] K2 VSSPP[3] VCCPT A11 B3 VSSPP[0] B7 VSSPP[1] VCCPL[2] N8 VCCPL[3] P12 C10 VSSPT P8 VSSPL[2] N12 VSSPL[3] AD0 AD1 P6 AD2 P5 AD3 VCC[0] E12 VCC[1] G5 D4 VSS[0] D5 VSS[1] N7 M7 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 R_LANIDS C269A 82559 VCC[2] G6 VCC[3] H5 D6 VSS[2] D7 VSS[3] AD1 C265A VCC[4] H6 VCC[5] H7 D8 VSS[4] D11 VSS[5] AD2 A E10 VSS[12] E11 VSS[13] U13A VCC[12] J10 VCC[13] J11 F4 VSS[14] F5 VSS[15] AD0 22PF VCC[6] H8 VCC[7] J5 E4 VSS[6] E5 VSS[7] VCC3_3SBY VCC[14] K4 VCC[15] K5 F6 VSS[16] F7 VSS[17] VCC3_3SBY VCC3_3SBY VCC[16] K6 VCC[17] K7 F8 VSS[18] F9 VSS[19] VCC3_3SBY VCC[18] K8 VCC[19] K9 F10 VSS[20] F11 VSS[21] R159A 4.7K 5% VCC[20] K10 VCC[21] K11 G7 VSS[22] G8 VSS[23] AD[31:0] 2 1 G13 VCCPL[0] VCCPL[1] K13 G14 VSSPL[0] K12 VSSPL[1] VCC[8] J6 VCC[9] J7 E6 VSS[8] E7 VSS[9] 11,15 C331A VCC[22] L4 VCC[23] L5 G9 VSS[24] G10 VSS[25] LAN 0.1UF VCC[10] J8 VCC[11] J9 E8 VSS[10] E9 VSS[11] CSTSCHG C5 PME# A6 RDP E13 RDN E14 SMBALRT# B10 TDN C14 SPEEDLED B11 TDP C13 LILED A12 C11 ACTLED FLD6_PD FLD5_PD P14 L8 D9 P1 NC2 H4 NC1 A1 NC3 NC4 NC5 NC6 NC11 D10 G4 NC10 A14 NC9 J4 NC8 NC7 L7 549 R156A 62K R154A Do Not Stuff 619 R162A 3K R164A 619 R155A 4.7K R152A 619 R163A VCC3_3SBY EECS EEDI EEDO EESK 24 EEDO EEDI 93C46 U18A NC1 6 NC2 7 11,15 VCC3_3SBY PCI_PME# 24 RDN 24 RDP TDN EESK 1 EECS 2 4 3 24 ACTLED 24 SPEEDLED 24 TDP 24 LILED APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION LAN Sheet: 23 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic RBIAS10 RBIAS10 B14 RBIAS100 RBIAS100 B13 VREF C12 TI D12 TO B12 TEXEC D13 TCK D14 FLWE# M9 LANCLKRUN CLKRUN# C8 LAN_TEST TEST A13 FLCS# N9 FLOE# M8 FLD7 J14 EECS P7 FLD5 H13 FLD6 H12 FLD3 G12 FLD4 H14 FLD1 F13 FLD2 F12 FLA16 P9 FLD0 F14 FLA14/EEDO N10 FLA15/EESK M10 FLA12/MCNTSM# M11 FLA13/EEDI P10 FLA10/MRING# N13 FLA11/MINT M12 FLA7 M13 FLA8/IOCHRDY N14 FLA9/MRST P13 FLA6 M14 FLA4 L13 FLA5 L12 FLA2 K14 FLA3 L14 FLA0/PCIMODE# J13 LANAPWR FLA1/AUXPWR J12 VCC[24] L9 VCC[25] L10 G11 VSS[26] H9 VSS[27] A H10 VSS[28] H11 VSS[29] VCC5 L6 VSS[30] L11 VSS[31] VCC 8 GND 5 22PF 0.5 REV. A A Place Termination near 82559 12,28 RSMRST# PWROK SUS_STAT# 12,25,28 12 Do Not Stuff TD_PD R157A 50 C266A RDN 0.1UF RDP R158A 50 RD_PD R160A 50 Do Not Stuff R198A 0K R198A 0K R210A 3 1 R161A 50 RJ45_PD 2 JP10A R110A 75 3 RJ-7 4 RJ-8 5 RJ-4 6 RJ-5 9 RD+ 7 RD- 470PF-1500V C210A DISABLE NORMAL Default LAN_RST# 23 1-2 2-3 LAN DISABLE - JP10A LAN_ISOLATE# 23 R109A 75 RJMAG_CONN R106A 75 TXC_PD Note: Chassis Ground, use plane for this signal Default Config: Do Not Stuff For EST Testing R107A 75 RJ78_PD Note: This circuit is for debug purpose only. C268A 23 1 23 0.1UF J9A TXC RJMAG RJ-45 LC2 14 LA2 13 LC1 16 LA1 15 Do Not Stuff 0.1UF C213A LI_CR 330 A 0.1UF 330 R112A C212A R111A Note: Chassis Ground, use plane for this signal 17 SHLD1 18 SHLD2 10 TD+ 12 TD- 11 TDC TDC TDP TDN RXC 2 RXC_PD RDC 8 RDC 23 23 ACT_CR VCC3_3SBY SPEEDLED LILED ACTLED 10,12,21,29 10,12,21,29 12 12 LILED ACTLED SPEEDLED 23 GPIO28 SMBDATA GPIO27 SMBCLK 23 23 3 1 2 0K R151A JP9_SMBD 0K R150A ICH 2-3 ICH0 1-2 Default Select JP8A/JP9A JP8_SMBC JP12A R145A 330 L_SMBD L_SMBCLK 23 23 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION LAN Sheet: 24 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic 4.7K R186A 2 JP8A JP11_PU JP9A 3 VCC3_3SBY R215A 4.7K 1 JP11A R144A 330 VCC3_3SBY JP7A R108A 330 VCC3_3SBY JP7_PU LAN A JP12_PU 0.5 REV. A A PWROK 12,24,28 VCC5SBY 7 1 3 IN LT1117-3_3 VR4A PLANE_CTL0 SN74LVC07A 2 U5A OUT2 V3SB Place C76A at the Regulator 0K R83A R87A 10K VCC5SBY SN74LVC07A has 5V input and output tolerance. PCTL_IN 14 VCC3_3SBY VCC 3.3VSB Regulat or 74LS132 A 3 2 B Y 1 VCC 14 GND 7 SLP_S3# 22UF U4A GND 1 V_GQ6 B 1 Q7A R61A 4.7K VCC12 VCC3_3 PLANE_CTL1 MMBT3904LT1 VCC5SBY C76A 1 12,28 C71A 1 2 + 2 + 100UF C59A 1 2 3 C 2 E C174A C75A 1 2 1 2 47UF V3SB 3 VIN 2 ADJ 1 VOUT LT1587ADJ VR2A A R54A 130 1% VR1_ADJ S 1 2 3 4 1 2 3 4 R55A 301 1% Q8A C CR2A D D 8 7 6 5 8 7 6 5 Place C260A at the Regulator VCC1_8 SI4410DY SI4410DY NDS356AP Do Not Populate NDS356AP A C173A 1 2 VCC3_3SBY C375A VCC3_3 3 VIN 2 ADJ 1 VOUT LT1587-1_5 VR5A VCC5 3 VIN ADJ VOUT LT1587ADJ VR3A 1 2 VR5_ADJ R57A 240 1% R56A 240 1% VCC2_5 VTT1_5 VTT 1.5V VOLTAGE REGULATOR VCC 2.5 VOLTAGE REGULATOR 1200uF + + Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 25 of 33 Last Revision Date: INTEL CORPORATION VOLTAGE REGULATORS Electronic Classroom Student Computing Station Ref. Schematic 1200uF 1 2 1N5822 Q9A Q6A S Q5A VCC 1.8 VOLTAGE REGULATOR 47UF C57A This generates 3.3V Standby Power which is on in S0,S1,S3,S4,&S5. It passes 3.3V from the ATX supply in S0/S1, and 3.3VSB (generate d by VR4 below) in S3/S4/S5. 100UF C43A VCC 3.3V Standby VOLTAGE SWITCH 1.0UF 1.0UF G G C159A 1 2 C270A 1 2 VCC3_3 C65A 100UF Voltage Regulators 0.1UF C225A 1 2 A 100UF 100UF + C74A 1 + + 2 + 22UF + + + REV. 0.5 A A VID[3:0] 4 3 2 1 VID0 VID1 VID2 VID3 0K RP4A 8 7 6 5 JP2A C22A 0.1UF JP4A 10UF JP5A C30A C27A VID Override Jumpers JP3A 1 L8A 1 2 1.0UH-6.8A C26A R_VID3 R_VID2 R_VID1 R_VID0 OUTEN 2 + 1200UF 1 + 2 Refer to VR supplier for layout guildlines. The LTC1753 incorporates internal pull-ups on VID[4:0]. If your VR IC does not incorporate these, they must go on the motherboard. 3 10K R17A 1 2 + 1200UF 5VIN C29A C18A + 1 VID2 VID1 VID0 OUTEN VR1A VID3 14 VID4 15 16 17 18 19 VRCOMP_PD SS_PD LTC1753 C7A R16A 8.2K 1200UF 150PF 1200UF 0.01UF C19A 5.1 R22A VCC12 PV12 SS 9 + R_VRCOMP VCC 5 SGND 4 PVCC 2 GND 3 2 C17A 10 COMP 0.1UF A 220PF Do Not Stuff C147A 0.1UF R_VCCVID C35A VFB_PD G2 G1 8 FAULT#_PU 20 R20A 2.7K 12 7 IMAX IMAX 13 0.01UF C20A G2 1 VFB 11 IFB G1 FAULT# PWRGD 1.0UF C21A C147A SENSE 6 VCC5 R19A 20 L_VCCVID R33A 220 VCC3_3 1 2 R18A 5.6K VCC5 6 C31A Processor Voltage Regulator C58A 5 2 + 2700UF SI4410DY SI4410DY D4 G1 4 5 D4 G1 4 1 + 7 D2 S2 2 8 D1 S1 1 D3 S3 3 6 D3 7 D2 S3 8 D1 S2 2 Q4A Q2A SI4410DY Q3A C24A 1.0UF Q1A 28 C25A 1.0UF VRM_PWRGD 0.8UH-20A L14A Place CAPs Close to FETs VCCVID Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 26 of 33 Last Revision Date: INTEL CORPORATION VRM 8.4 Electronic Classroom Student Computing Station Ref. Schematic C28A G1 4 G1 4 A C128A D4 5 D3 6 S3 3 D4 5 D3 6 S3 3 C54A S1 1 2 3 2700UF 1 + 2700UF S2 2 S2 + 2700UF SI4410DY 1 2 D2 7 D1 8 S1 1 D2 7 D1 8 S1 1 2 2 1 + 2700UF 0.5 REV. A 14 14 PWM1 TACH1 4.7K IDEACTS# KEYLOCK# AC97SPKR 16 14 22 2 3 2 3 PWM2 1 1 14 J25A J27A C362A 0.1UF VCC12 3 3 TACH2 2 2 14 1 1 C363A 0.1UF VCC12 FAN Headers ICH_SPKR IDEACTP# 16 12 PWRBTN# 12 J24A 5 4 J26A 6 3 VCC3_3 7 2 A 8 1 2 3 1 JP22A R93A 10K VCC5 0.1UF C365A VCC12 0.1UF C23A VCC12 R136A 10K VCC5 SPKR CR12A 330 VCC3_3 3 A SN74LVC07A U11B VCC3_3SBY R188A R231A 10K VCC3_3 No stuff. For test only 0K O 4 O SPKR_Q1G A 2 B 1 Q11A SN74LVC07A U11A IDE_ACTIVE A For Debug Only Hot-Swapping Memory. On-Board LED indicates the Standby Well is on to prevent Speaker Circuit 2.2K R235A 1 VCC3_3 VCC 14 R225A VCC 14 GND 7 C370A 1.0UF 3 C GND 7 SPKR_IN 12 68 68 R234A R233A 0.1UF C378A 220 R232A 82 470PF C373A 470 16V 4 GP23LED SN74LVC07A U5B KEY KEY KEY KEY KEY KEY 1 CR3A FNT_PNL_CONN 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 VCC3_3SBY SPEAKER KEYLOCK POWER LED H.D. LED POWER SW. INFRARED SN74LVC07A GP26LED 6 U5C 7 5 14 VCC3_3SBY SPKR_NEG VCC5 SP1A GPIO26_FPLED 1+ POS 2 NEG APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION SYSTEM Sheet: 27 of 33 Last Revision Date: Electronic Classroom Student Computing Station Ref. Schematic 7 3 14 J20A 1 VCC3_3SBY VCC5 R_IRTX VCC3_3SBY 470PF C258A R_SPKRIN PWRLED R212A R228A 4.7K R213A PBTN_IN R217A 100K GPIO23_FPLED VCC5 4 3 IRTX 14 2 IRRX 14 1 SW2 No stuff. For test only 2N3904 R226A 1M FP_PD C292A 0.1UF 4.7K 2 E C279A R172A 2 1 + 10UF VCC3_3 R97A VCC3_3SBY 330 ICH has internal pullup and debounce on PWRBTN# V3SBLED 2 1 330 A R98A SYSTEM RP62A 0.5 REV. 12 A A 26 5 A O 6 SN74LVC06A VCC5 VCC12- 2 22 R24A 5VSB 9 12V 10 GND7 7 PW_OK 8 DBRPOK SLP_S3# 5 4 CK_PWRD SN74LVC08A 6 U10B VCC3_3SBY Place JP23A near front panal header (J20) JP23A 4 1 2 3 SW1 1 RST_PD 19 5V19 20 5V20 17 GND17 18 -5V GND5 5 5V6 6 GND3 3 5V4 4 ATX 13 GND13 14 PS_0N 15 GND15 16 GND16 3_3V1 1 3_3V2 2 11 3_3V11 12 -12V J4A Reset Button 5VPSON VCC5- CLOCK POWERDOWN CONTROL SN74LVC06A is 5V output tolerance SLP_S3# VRM_PWRGD 12,25 U3C R62A 4.7K VCC5SBY VCC3_3SBY VCC 14 GND 7 CK_PWRDN# C185A 10UF Do not stuff R84A - For debug only. If R84A is populated, R86A must be de-populated. 0K R84A 8.2K R86A C45A 0.01UF 4 74LVC14A 1 U12A DBRESET# 6,25 3 74LVC14A ST23 Do not stuff 0K 0K A R90A 0K 3 DBRST DBRPOK_DLY Do not stuff C183A 1.0UF 2 1 VCC3_3SBY 22K R142A Schmitt Trigger Logic using a 22msec delay VCC5SBY A 6 5 B Y 4 U4B 74LS132 ST69 74LVC14A 9 U12D 8 VCC3_3SBY PWROK# R196A 1M RSMRST# PWROK Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 28 of 33 Last Revision Date: INTEL CORPORATION SYSTEM: POWER CONNECTOR AND RESET CONTROL 4 12,24,25 PWRGOOD Do Not Stuff For Debug Only 12,24 R199A 1M R200A 4.7K VCC3_3SBY R10A 330 VCC2_5 Do Not Stuff For Debug Only 3 A O 4 U3B VCC3_3SBY SN74LVC06A 1 A O 2 U3A SN74LVC06A SN74LVC06A has 5V input tolerance VCC3_3SBY Electronic Classroom Student Computing Station Ref. Schematic C264A 1.0UF 5 74LVC14A V3RSMRST 6 VCC3_3SBY U12C Resume Reset Circuitry R92A APOK_ST SN74LVC08A U10A VCC3_3SBY DBRPOK 4 R91A 74LVC14A is 5V input tolerant 2 U12B R99A 240 VCC3_3SBY ITP RESET CIRCUIT - FOR DEBUG ONLY A 220 Ohm Pull-up to 3.3V is on VRM Sheet ATX_PWOK VCC5SBY VCC12 VCC3_3 Power Good Circuit + 14 7 14 7 14 7 Power Connector and Reset Control 1 2 VCC 14 7 GND 14 7 14 VCC GND 7 SYSTEM 14 7 14 7 14 VCC GND 7 REV. 0.5 A A PIRQ#C 11,15 11 PGNT#3 11,23 13 A 11 A 9 A SN74LVC07A O 12 U11F SN74LVC07A O 10 U11E SN74LVC07A O 8 U11D VCC3_3 1 1 6 5 3 4 VCC3_3 VCC5 SN74LVC06A 9 A O 8 U3D SN74LVC06A 13 A O 12 U3F SN74LVC06A 11 A O 10 U3E VCC3_3SBY 7 8.2K 8 2 RP57A 9 PULLUP/DOWN RESISTOR PAK 2.7K RP45A VCC5 PU1_REQ64# 7 13 14 7 11 14 7 9 14 8 10 SN74LVC07A 12 U5F SN74LVC07A U5E SN74LVC07A U5D VCC5 VCC5 VCC5 U4C VCC5SBY SN74LVC08A 11 U10D SN74LVC08A 8 U10C 74LS132 12 A 11 13 B Y U4D 74LS132 9 A 8 10 B Y 13 74LVC14A 12 10 9 5 6 7 8 5 6 7 8 5 6 7 8 VCC3_3SBY 2.7K RP51A 5.6K RP58A 5.6K RP47A 12 4 3 2 1 4 3 2 1 4 3 2 1 U12F 74LVC14A 10 VCC3_3SBY 13 11 U12E VCC3_3SBY PU1_ACK64# PTMS 15 15 PTDI SBOP1 SDONEP1 15 15 15 15 PCI BUS 9 PULLUP/DOWN RESISTOR PAK 2.7K 1 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 UNUSED GATES PGNT#0 PGNT#1 PGNT#2 11 PREQ#1 PREQ#0 11,15 PREQ#2 11 PREQ#3 11 11,15 11,23 PIRQ#B PIRQ#A PIRQ#D FRAME# TRDY# IRDY# STOP# DEVSEL# SERR# PLOCK# 11,15 11,15 11,15,23 11,15,23 11,15,23 11,15,23 11,15,23 11,15,23 11,15 11,15,23 2 RP59A 12,22 PULL-UP RESISTORS AND UNUSED GATES VCC 14 GND 7 VCC 14 GND 7 VCC 14 GND 7 VCC 14 GND VCC 14 7 GND 7 14 VCC GND 7 14 14 7 7 14 7 14 7 VCC 14 GND 7 VCC 14 GND 7 A 12 IRQ15 IRQ14 12,14 AC_SDIN1 12 LPC_PME# GPIO21 GPIO22 GPIO7 LPC_SMI# RCIN# 12,14 12 11,14 PCPCI_REQ#A 12 THERM# A20GATE 12,22 AC_SDIN0 11,16 INTRUDER# SMBCLK SMBDATA 11,14 11 GPIO12 GPIO13 11 GNT#B/GPIO17 11,14 SERIRQ 11 12 10,12,21,24 12 12 LDRQ#1 SMBALERT# REQ#B/GPIO1 12 12 10,12,21,24 11,16 A 10K R166A 6 5 3 4 6 5 3 4 7 6 5 2 3 4 10K R170A 5 6 3 8.2K 7 2 4 8 1 RP55A 8 1 8.2K RP54A 7 2 8.2K 8 1 RP53A 7 2 8.2K 8 1 VCC5 SLEWCTRL RTTCTRL FERR# IGNNE# A20M# INTR INIT# RP50A 110 1% R70A 110 1% 330 R169 330 R68A 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 4 VCMOS VCMOS APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 29 of 33 Last Revision Date: PULL-UP RESISTORS AND UNUSED GATES Electronic Classroom Student Computing Station Ref. Schematic 4 4 For Future Compatibility Upgrade 4,11 4,11 4,11 4,11,13 4,11 STPCLK# 4,11 SMI# CPUSLP# NMI 150 RP49A 5 4 4,11 4,11 4,11 150 R6A R73A RP52A 6 3 APICD1 APICD0 330 7 2 VCC3_3 4,11 4,11 CPU 8.2K 8 1 RP56A 5 4.7K 6 4 7 8 3 2 1 RP60A 6 3 5 7 4 8 2 4.7K RP61A 1 VCC3_3SBY 82801AA 0.5 REV. A A C142A 1.0UF C121A 1.0UF 0805 Package 1.0UF 22 UF C384A VTT1_5 + C34A 0.1UF C33A 0.1UF 0.1UF C129A 0603 Package placed within 200mils of VTT Termination R-packs One Capacitor for every 2 R-Packs 1.0UF C118A C113A C152A 4.7UF C125A 4.7UF 1206 Packages Bulk Decoupling High Frequency Decoupling VTT Decoupling VCCVID VCCVID Place in 370 PGA Socket Cavity VCCVID Decoupling 370-pin Socket Decoupling 1 2 C136A 0.1UF C11A 1.0UF C120A 4.7UF C117A 0.1UF C32A 1.0UF C149A 4.7UF C110A 0.1UF C133A 1.0UF C145A 4.7UF C115A 0.1UF C144A 1.0UF C107A 4.7UF C153A 0.1UF C150A 1.0UF C154A 4.7UF A A C146A 0.1UF C157A 1.0UF C156A 4.7UF C126A 0.1UF C218A 1.0UF C148A 4.7UF C139A 0.1UF C220A 1.0UF C135A 4.7UF C155A 0.1UF C219A 1.0UF C132A 4.7UF C140A 0.1UF C205A 1.0UF C137A 4.7UF 0.1UF C221A 1.0UF C138A 1.0UF C108A 1.0UF C141A 1.0UF C143A 1.0UF C134A Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 30 of 33 Last Revision Date: INTEL CORPORATION 370-PIN SOCKET DECOUPLING Electronic Classroom Student Computing Station Ref. Schematic 0.1UF C42A 1.0UF C151A REV. 0.5 A A 1 0.01UF C343A 0.1UF 0.1UF 0.01UF C214A C233A 0.01UF C380A 0.01UF C381A 0.1UF C163A 0.1UF C383A 0.01UF 0.1UF C341A 0.1UF C350A 0.1UF C278A 0.1UF C288A and 3 near Display Cache Quadrant Place 3 near System Memory Quadrant 82810 3.3V IO Decoupling: C237A 0.01UF VCC1_8 VCC3_3 0.1UF C215A Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to omponent c if they fit. C242A 2 C234A C164A 0.01UF C131A 0.01UF 0.1UF 0.1UF 0.1UF C245A 0.1UF C248A 0.1UF C254A 0.1UF C181A 0.1UF C175A DIMM0 Decoupling: Distribute near DIMM0 Power Pins. C260A VCC3_3SBY System Memory Decoupling 0.1UF 0.1UF C296A 0.1UF C295A 0.1UF 0.1UF C10A 0.1UF C83A VCC5 C86A 0.1UF A C298A 0.1UF C352A 0.1UF VCC3_3 0.1UF C283A 0.1UF C291A 0.1UF C354A 0.1UF C87A 0.1UF C285A 3 VOLT Decoupling 0.1UF C82A VCC3_3 C69A 0.1UF C339A Bulk Power Decoupling C307A C319A VCC5- 0.1UF C345A 0.1UF C160A 0.1UF C250A 0.1UF 0.1UF C340A C289A 0.1UF C318A 0.1UF 0.1UF C172A 0.1UF 0.01UF C305A 0.01UF C41A 0.01UF VCC12 0.01UF C304A 0.1UF C376A 0.1UF C320A 0.1UF 0.1UF C240A 0.1UF VCC3_3SBY 0.1UF C256A C127A 0.1UF C67A 0.1UF 0.1UF C338A 0.1UF 0.1UF 0.1UF 0.1UF C171A VCC12- C303A C263A VCC1_8 Distribute near the VCCSUS power pins of the 82801A A 0.1UF C322A 0.1UF APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 INTEL CORPORATION Sheet: 31 of 33 Last Revision Date: DRAM, CHIPSET AND BULK POWER DECOUPLING Electronic Classroom Student Computing Station Ref. Schematic 0.1UF C78A 0.1UF C72A 0.01UF 0.01UF C66A C308A C332A C360A C382A 82810 Core Plane De coupling: 0.1UF C85A C239A C70A 0.1UF C62A C130A 2 10UF C333A C321A VCC3_3 2 1 C367A 0.1UF 0.1UF C44A 22UF 1 + 22UF Distribute near the 1.8V power pins of the 82801A A 2 1 82801AA 3.3V Plane Decoupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit. C84A VCC1_8 C162A C81A 82801AA Decoupling C372A 82810 Decoupling 1 2 2.2UF 1 + 2 C80A DRAM, CHIPSET, and BULK POWER DECOUPLING 22UF C324A A 2 1 + 22UF 22UF + 22UF + 1 + 2 C317A + + REV. 0.5 A A PAGE REVISION 0 A A Sheet: APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 32 of 33 Last Revision Date: INTEL CORPORATION REVISION HISTORY Electronic Classroom Student Computing Station Ref. Schematic REV. 0.5 A