Intel-Based Electronic
Classroom Student Computing
Station Based on the Intel®
Celeron™ Processor and Intel®
810 Chipset
Reference Configuration
August 2000
Order Number: 273292-002
Application Note
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®Celeron™and Pentium®II processors, 810 Chipset, and 82559 ethernet controller may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright© Intel Corporation, 2000
*Other brands and names are the property of their respective owners.
Application Note 3
Intel-Based Electronic Classroom Student Computing Station
Contents
1.0 Introduction ......................................................................................................................5
1.1 Purpose.................................................................................................................5
1.2 Terminology...........................................................................................................5
1.3 Revision History ....................................................................................................5
2.0 Intel-Based Electronic Classroom Environment Overview..........................................6
3.0 Intel-Based Electronic Classroom Setup and Operating Environment.......................7
3.1 Intel-Based Electronic Classroom Configuration...................................................8
3.1.1 Network Environment...............................................................................8
3.1.2 Teacher Station Management System.....................................................9
3.1.3 Multimedia Teaching Software.................................................................9
3.1.4 Application Software...............................................................................10
3.1.5 Remote Booting Intel-Based Electronic Classroom Student
Computing Stations from Server............................................................10
4.0 Recommended Motherboard Configuration for Intel-Based
Electronic Classroom Student Computing Stations...................................................11
5.0 Design Consideration of Intel-Based Electronic Classroom
Student Computing Station Hardware .........................................................................13
5.1 Intel®Celeron™ Processor.................................................................................13
5.1.1 Design Notes for the Intel®Celeron™ Processor..................................13
5.2 Intel®810 Chipset ...............................................................................................14
5.2.1 The Intel®82810 Graphics Memory Controller Hub (GMCH0) ..............15
5.2.1.1 Design Notes for the Intel®82810 GMCH0...............................15
5.2.2 The Intel®82801 I/O Controller Hub (ICH).............................................16
5.2.2.1 Design Notes for the Intel®82801 ICH......................................16
5.3 IDE Connectors...................................................................................................17
5.4 AC’97 2.1 Compliant Components......................................................................17
5.4.1 Design Notes for AC’97 Devices............................................................18
5.5 Audio/Modem Riser Card (AMR).........................................................................18
5.5.1 Design Notes for the Audio/Modem Riser Card.....................................18
5.6 PCI ......................................................................................................................19
5.7 Network Controller — Intel®82559 Fast Ethernet Controller..............................19
5.7.1 Design Note for the Intel®82559 Fast Ethernet Controller ....................19
5.7.2 Wired for Management...........................................................................21
5.7.2.1 Instrumentation..........................................................................21
5.7.2.2 Remote Service Boot ................................................................22
5.7.2.3 Remote Wake-Up......................................................................22
5.7.2.4 Power Management ..................................................................22
5.8 Low Pin Count (LPC) Interface............................................................................22
6.0 Conclusion......................................................................................................................23
A References......................................................................................................................25
B Intel-Based Electronic Classroom Schematics...........................................................27
4Application Note
Intel-Based Electronic Classroom Student Computing Station
Figures
1 Typical Intel-Based Electronic Classroom Setup..................................................7
2 Building Block of the Intel-Based Electronic Classroom Student
Computing Station Motherboard.........................................................................12
3 Topology for Single Processor Designs with Single End Termination (SET)......13
4 Placement of Termination Resistor.....................................................................20
5 Trace Geometry..................................................................................................20
6 Cover Sheet Schematic ......................................................................................28
7 Block Diagram.....................................................................................................29
8 370-Pin Socket (Part 1).......................................................................................30
9 370-Pin Socket (Part 2).......................................................................................31
10 GTL Terminal Schematic ....................................................................................32
11 Clock Synthesizer Schematic..............................................................................33
12 82810, Part 1: Host Interface Schematic ............................................................34
13 82810, Part 2: System Memory and Hub Interface Schematic ...........................35
14 82810, Part 3: Graphics Schematic ....................................................................36
15 System Memory Schematic ................................................................................37
16 82810AA, Part 1 Schematic................................................................................38
17 82810AA, Part 2 Schematic................................................................................39
18 Firmware Hub (FWH) Schematic ........................................................................40
19 Super I/O Schematic...........................................................................................41
20 PCI Connector Schematic...................................................................................42
21 ATA/33 IDE Connectors Schematic....................................................................43
22 USB Connectors Schematic................................................................................44
23 Parallel Port Header Schematic..........................................................................45
24 Serial Port/Com Headers Schematic ..................................................................46
25 Keyboard/Mouse Ports, Floppy Disk Header, Game Post Header Schematic ...47
26 Video Connectors Schematic..............................................................................48
27 Audio Riser Schematic........................................................................................49
28 LAN Schematic ...................................................................................................50
29 LAN Schematic ...................................................................................................51
30 Voltage Regulators..............................................................................................52
31 Processor Voltage Regulator Schematic ............................................................53
32 System Schematic ..............................................................................................54
33 System: Power Connector and Reset Control Schematic...................................55
34 Pull-Up Resistors and Unused Gates Schematic................................................56
35 730-Pin Socket Decoupling Schematic...............................................................57
36 DRAM, Chipset and Bulk Power Decoupling Schematic ....................................58
37 Revision History Schematic ................................................................................59
Tables
1 Intel-Based Electronic Classroom Hardware Descriptions and
Recommended Configuration ...............................................................................8
2 AC’97 Configuration Combinations.....................................................................17
Intel-Based Electronic Classroom Student Computing Station
Application Note 5
1.0 Introduction
1.1 Purpose
This application note describes how Intel®architecture processors, chipsets, and other components
can be used in designs for Intel-based electronic classroom student computing stations. An
Intel-based electronic classroom is an educational setting in which a network of computers is used
as a primary teaching, learning, and assessment tool. A typical Intel-based electronic classroom
contains an instructor’s system that broadcasts application software to, and often receives data
from, student computing stations. The student computing stations can be configured and
administered at the server level.
Intel architecture components are well-suited for Intel-based electronic classroom systems. Using
PC-based building blocks in these designs provides flexibility, upgradability, ease of
administration, and high performance for graphic-intensive and internet applications. In addition,
Intel architecture processors are compatible with a wide variety of operating system and
off-the-shelf application software. This application note describes a typical Intel-based electronic
classroom network and provides a reference design for Intel architecture-based electronic
classroom student computing stations.
Schematics for the reference design are provided in Appendix B of this document.
1.2 Terminology
The following terms are used in this document.
1.3 Revision History
Term Definition
Intel-Based
Electronic
Classroom
An electronic teaching and learning environment that uses dedicated, connected student
computing stations to implement a specific educational curriculum
Remote boot A client operating system boot up from a server in a network environment
TCO Total cost of ownership
ISV Independent software vendor
WfM Intel’s Wired for Management initiative
Revision Date Notes
001 October 15, 1999 Initial version.
Intel-Based Electronic Classroom Student Computing Station
6Application Note
2.0 Intel-Based Electronic Classroom Environment
Overview
An Intel-based electronic classroom is a teaching and learning environment that uses a server-client
system in the classroom to implement the curriculum. Teaching and learning is done using a
teacher station, student computing stations, and specific educational software applications and
content. With this modern educational technology, educators can deliver intuitive online courses,
training, demonstrations, and examinations. They can also incorporate access to the Internet and
intranet to enrich the educational experience.
An Intel-based electronic classroom LAN environment can consist of up to 60 student computing
stations, a teacher station, and a network server. In an Intel-based electronic classroom, every
student computing station is administered centrally. These student computing stations have high
reliability and security, and low maintenance costs. The student computing stations have a subset
of a PC feature set: they typically have a different motherboard configuration (described in
Section 4.0) and are configured without a CD-ROM drive or hard disk. This solution provides a
greater access to the necessary technology while simplifying maintenance and reducing the total
cost of ownership.
In schools, PCs can be used in teacher offices as productivity tools for administration and
development of teaching materials. These materials may then be used in Intel-based electronic
classrooms to teach subjects such as computer skills, languages, sciences, and mathematics. The
teacher uses the teacher station in the Intel-based electronic classroom to guide students through
the lesson, while each student follows the lesson on his/her own student computing station. The
students can also use their student computing stations independently to practice lesson materials
and learn other application software.
Desirable features of Intel-based electronic classroom student computing stations include the
following:
•Ease of management and maintenance
Primary and secondary schools typically do not have a full time Information Technology (IT)
staff to manage the Intel-based electronic classroom. Most IT administration is done by
teachers and student volunteers. Hence, the student computing stations used in the Intel-based
electronic classroom must be easy to manage.
Intel-based electronic classroom student computing stations can be configured without
CD-ROM and floppy drives. This further simplifies the management of these student
computing stations by preventing students from erasing files or corrupting the operating
system and applications.
•Low total cost of ownership (TCO)
Schools have limited budgets for setting up Intel-based electronic classrooms. Therefore, a key
consideration is affordability in terms of initial capital and ongoing maintenance costs,
including the costs of off-the-shelf educational applications and teaching content.
•Software availability and compatibility
Establishing a productive Intel-based electronic classroom depends on the availability of
system-compatible, off-the-shelf applications and teaching materials. It is important that
schools have tools to develop customized content to meet the particular needs of their students.
•Product life cycle support
Schools use Intel-based electronic classroom student computing stations for several years
before considering an upgrade. Therefore, replacement parts should be available for this
duration.
Intel-Based Electronic Classroom Student Computing Station
Application Note 7
3.0 Intel-Based Electronic Classroom Setup and
Operating Environment
A typical Intel-based electronic classroom setup is depicted in Figure 1.
The student and teacher stations are linked together in a LAN environment via a network hub or
switch device. The LAN network enables the remote boot for diskless student computing stations
and file sharing among all the student computing stations. The broadcasting capability is
implemented through software using the existing LAN infrastructure. This solution reduces overall
system cost, simplifies wiring and upgrade requirements, and enables the use of higher
performance processors.
The components of a typical Intel-based electronic classroom and their recommended
configuration are described in Table 1.
Figure 1. Typical Intel-Based Electronic Classroom Setup
A7490-02
Home
PC Internet
School Network
Server
15 - 60 Student
Computing Stations
Teacher Station
Intel-Based Electronic Classroom
Intel-Based Electronic Classroom Student Computing Station
8Application Note
3.1 Intel-Based Electronic Classroom Configuration
The configuration of the Intel-based electronic classroom depends on the size of the classroom, the
network design, and the use of the multimedia broadcasting software. The following describes an
example configuration that consists of five main parts:
•Network environment
•Teacher Station management system
•Multimedia broadcasting software
•Application and education software
•Intel-based electronic classroom student computing stations that remote boot from server
The following sections describe each component of the example Intel-based electronic classroom.
3.1.1 Network Environment
The network can be set-up using Windows* NT 4.0 or Novell Netware* on the server. The teacher
station and student computing stations run on Windows 95/98 operating systems. The Intel-based
electronic classroom student computing stations boot up remotely from a server that is connected
in a LAN environment.
Table 1. Intel-Based Electronic Classroom Hardware Descriptions and Recommended
Configuration
Item Quantity
(units) Recommended Configuration
Teacher Station 1 Intel®Pentium®III processor, 64 -128 Mbyte SDRAM, Intel®440BX AGPset, Hard-disk,
Intel®Network Card, Video Capture Card
Student Computing
Station 15 - 60 Intel®Celeron™processor 433 MHz or better (in 370-pin PPGA) and Intel®810 chipset,
32 Mbyte SDRAM, Intel Network Card integrated on board, Hard-disk (optional)
Server 1 Pentium III processor, 128 Mbyte SDRAM, Intel®L440GX motherboard, SCSI Hard-disk,
Intel Network Card
Switch 1-3 Intel Express 510T, 24 10/100Mbit Switching Port
Router 1 Intel Express 9500 Router for Internet connection
Multimedia teaching
Software 1From ISVs. Based on TCP/IP or IPX network protocol. Intel®LANSchool software site is a
basic reference: http://www.intel.com/network/products/lanschool.htm
Intel-Based Electronic Classroom Student Computing Station
Application Note 9
3.1.2 Teacher Station Management System
The teacher station in this example can perform the following functions:
•Broadcasting the teacher station screen
All teaching materials, including presentation, animations, and movies can be broadcast to the
student computing stations.
•Controlling student computing stations remotely
The teacher can control, reset, and lock the student computing stations or receive the display
from a particular Intel-based electronic classroom student computing station.
•Providing online help
The teacher can provide help through the network when students have difficulty with their
assignment. The students would also be able to request assistance through the network.
3.1.3 Multimedia Teaching Software
The multimedia teaching software utilizes a standard LAN network interface through TCP/IP
protocol and typically offers the following features:
•Screen broadcasting
— Each computing station (teacher’s and student’s) can broadcast its screen to some or all
students. Only one screen can be broadcast at a time.
— The teacher can lock each student’s keyboard and mouse and can broadcast any student’s
screen to the class.
— All graphics formats, such as MPEG and VCD can be broadcast in real time.
•Audio/voice communication
— The teacher’s voice can be broadcast to one, several, or all students.
— Conferencing is supported in teacher-student, student-student, or other combinations.
— The voice can be input through MIC or Line In on the sound card.
•Remote access
— The teacher can view any student’s screen remotely.
•Grouping
— Student computing stations can be grouped in any combination for discussion
(screen/audio).
•Question
— Students can submit questions through MIC or keyboard (using a special function key).
— Two way or multi-way online questioning is supported, as in a “chat” mode.
•Remote reset
— The teacher can reset any or all Intel-based electronic classroom student computing
stations if an error occurs in the system.
•Examinations can be administered and completed online.
Intel-Based Electronic Classroom Student Computing Station
10 Application Note
3.1.4 Application Software
Typically, application software, such as word processing and spreadsheet programs, and
instructor-developed materials are taught in Intel-based electronic classrooms. In some Intel-based
electronic classrooms, students are assessed using on-line examinations.
3.1.5 Remote Booting Intel-Based Electronic Classroom Student
Computing Stations from Server
During the remote boot process, the Intel-based electronic classroom student computing stations
contact the server (using Preboot Execution Environment in the boot ROM of the network
interface), install a boot image, and boot the operating system that is pre-configured on the server.
Various operating systems can be remote booted from the server, including Windows 95/98 or
Linux*.
The setup is optimized through the availability of the Preboot Execution Environment (PXE)
compliant boot ROM. PXE allows the server to set up each student computing station with a
specific IP address using the Dynamic Host Communication Protocol (DHCP). The boot ROM
then downloads the boot image from the server using the Trivial File Transfer (TFT) protocol. This
boot image program then configures the student computing stations and boots the pre-configured
operating system. If the Intel-based electronic classroom student computing station’s operating
system or applications are damaged, they can be recovered by downloading the new image from
server when the system restarts. This reduces the total cost of maintenance. Refer to section
Section 5.7.2.2, “Remote Service Boot” on page 22 for more information.
Intel-Based Electronic Classroom Student Computing Station
Application Note 11
4.0 Recommended Motherboard Configuration for
Intel-Based Electronic Classroom Student
Computing Stations
The motherboard of this reference design for Intel-based electronic classroom student computing
stations is a highly integrated design that incorporates many features on the board. It is
recommended that system designers use an LPX form factor or Flex ATX design. The LPX form
factor enables the student computing stations to have a very slim casing, which is desirable for
small Intel-based electronic classroom environments. Flex ATX helps reduce board size and cost.
The components listed below provide an example of a motherboard design based on the Celeron
processor and Intel 810 chipset.
Main Components of Reference Motherboard for the Intel-Based Electronic Classroom
Student Computing Station:
•Intel®Celeron™ processor 300A/366/433 MHz in 370-pin PPGA
•Intel®810 Chipset
•Two DIMM sockets that support up to 512 Mbyte (128 Mbit technology) SDRAM
•Two IDE interfaces
•One floppy disk interface
•COM 1 and COM 2 serials ports and a parallel port
•PS/2 mouse and keyboard connectors
•Intel®Flash BIOS
•Super I/O* and USB ports
•1 X PCI 2.2-compliant PCI slot
Peripherals on Intel-Based Electronic Classroom Student Computing Station:
Integrated audio in chipset
•Audio Codec ’97 2.1 extensions compliant
•Stereo line level output
•One audio out, audio in, and MIC jack
Integrated Graphics
•3-D graphics with texturing and visual enhancements up to 1024x768x16 @85 Hz refresh
•2-D graphics up to 1600x1200x8 @85 Hz refresh
•RGB output
PCI-based 10/100 Mbps Network card
•Intel®82559-based card recommended
•One RJ-45 port
•Boot ROM which contains Intel®Preboot Execution Environment (PXE)
Intel-Based Electronic Classroom Student Computing Station
12 Application Note
Figure 2. Building Block of the Intel-Based Electronic Classroom Student Computing Station
Motherboard
A7493-01
82802AB
4Mb
Super IO*
GD82559
Intel® Celeron™
Processor
SDRAM Memory
100 MHz
1 PCI
REQ/GNT
Monitor
AC'97 Riser
2 IDE Port/
Ultra AT A66
Display I/F
Intel® 810
Chipset
AC'97 2.1
Low Pin
Count Interface
SMBus
System Bus
[66 MHz]
Intel Network Controller
Support 10/100 Mbit
One RJ-45 port
One Flash boot ROM
PCI 33
COM1 & COM 2 Serial Ports
Parallel Port
PS/2 Mouse
Floppy Disk Interface
Keyboard Connectors
USB
USB
82801AA
241 BGA
82810
241 BGA
Intel-Based Electronic Classroom Student Computing Station
Application Note 13
5.0 Design Consideration of Intel-Based Electronic
Classroom Student Computing Station Hardware
5.1 Intel®Celeron™Processor
This reference configuration supports the Intel Celeron processor at 300, 366 MHz and 433 MHz
inaPlasticPinGridArray(PPGA)package.
The Intel Celeron processor PPGA package implements a Dynamic Execution micro-architecture
and executes MMX™ media technology instructions for enhanced media and communication
performance. The Intel Celeron processor PPGA is based on the P6 family processor core and is
provided in a PPGA package for use in low cost systems in the value PC and Intel-based electronic
classroom student computing station market segments. The IntelCeleron processor PPGA utilizes
the AGTL+ system bus used by the Pentium®II processor with support limited to single-processor
systems. The Intel Celeron processor PPGA includes an integrated 128 Kbyte second level cache
with separate 16 Kbyte instruction and 16 Kbyte data level-one caches. The second level cache is
capable of caching 4 Gbytes of system memory.
5.1.1 Design Notes for the Intel®Celeron™Processor
The schematics use a Single Ended Termination (SET) network topology in which the termination
resistors are located at only the PPGA (processor) side to reduce the system cost, solution space,
and ringing effect. In the SET topology, the termination should be placed close to the processor
either on the motherboard or on the processor substrate. No termination is present at the chipset end
of the network.
Figure 3. Topology for Single Processor Designs with Single End Termination (SET)
A7494-01
† - 1.9" <L1 <5.0"
†† - 0.5" <L2 <2.0"
L2††
L1†
VTT
Intel® 810
Chipset
370-Pin Socket
Intel-Based Electronic Classroom Student Computing Station
14 Application Note
5.2 Intel®810 Chipset
Intel has developed technology that enhances the performance and value of Intel Celeron
processor-powered systems. Built on the strong foundation of Intel 440BX AGPset technology, the
Intel 810 chipset provides next generation features and great graphics performance at a lower cost.
The Intel 810 chipset contains three core components:
1. Host Controller —Graphics and Memory Controller Hub (GMCH0)
The GMCH0 (82810) provides the interconnect between the SDRAM and the rest of the
system logic:
—421 Mini BGA
—Integrated Graphics controller
—230 MHz RAMDAC
—Support for Intel Celeron processors with a 66 MHz system bus.
—100 MHz SDRAM interface supporting 64/256/512 Mbyte with 16/64/128 Mbit SDRAM
technology
—Downstream hub interface for access to the ICH
2. I/O Controller Hub —82810AA (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system:
—421 Mini BGA
—Upstream hub interface for access to the GMCH0
—PCI 2.2-compliant interface (6 PCI Req/Grant Pairs for 82801AA ICH)
—Bus Master IDE controller; supports either Ultra ATA/33 or Ultra ATA/66 (82801AA)
—USB controller
—SMBus controller
—FWH interface
—LPC interface
—AC’97 2.1 interface
—Integrated System Management Controller
—Alert-on-LAN (82801AA ICH only)
—Interrupt controller
3. 82802 Firmware Hub (FWH)
The 82802 FWH component is a key element to enabling a new security and manageability
infrastructure for the PC platform. The device operates under the FWH interface and protocol.
The hardware features of this device include:
—An integrated hardware Random Number Generator (RNG)
—Register-based locking
—Hardware-based locking
—5GPIs
Intel-Based Electronic Classroom Student Computing Station
Application Note 15
5.2.1 The Intel®82810 Graphics Memory Controller Hub (GMCH0)
The Intel 810 chipset provides a rich and robust 2-D and 3-D graphics using an integrated chipset
design that utilizes second-generation graphics technology. At the core of the 810 chipset is a
memory controller with built-in graphics technology. The Intel 810 chip optimizes system memory
arbitration, similar to AGP technology, resulting in a more responsive and cost-effective system.
The 82810 Graphics Memory Controller Hub (GMCH0) features Intel graphics technology and
software drivers and uses Direct AGP (integrated AGP) to create vivid 2-D and 3-D effects and
images. The 82810 chip features integrated Hardware Motion Compensation to improve soft DVD
video quality and a digital video out port that enables connection to traditional TVs or the new
space-saving digital flat panel displays.
Intel Dynamic Video Memory Technology (DVMT) is an architecture that offers breakthrough
performance for the Value PC segment through efficient memory utilization and Direct AGP. The
system OS uses the Intel software drivers and intelligent memory arbiter to support richer graphics
applications.
The System Manageability Bus allows networking equipment to monitor the 810-chipset platform.
Using ACPI specifications, the system manageability function enables low-power sleep mode and
conserves energy when the system is idle.
5.2.1.1 Design Notes for the Intel®82810 GMCH0
The GMCH ball assignment and ICH ball assignment have been optimized to simplify hub
interface routing. It is recommended that the hub interface signals are routed directly from the
GMCH0 to the ICH on the top signal layer. The hub interface has two signal groups:
•Data Signals: HL[10:0]
•Strobe Signals: HL_STB, HL_STB# (differential strobe pair)
There are no pull-ups or pull-downs required on the hub interface.
Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of
20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for
navigation around components or mounting holes. To break out of the GMCH0 and the ICH, the
hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils.
The signals should be separated to a trace widthof 5 mils and a trace spacing of 20 mils within 0.3”
of the GMCH0/ICH components. The maximum trace length for the hub interface data signals is
7”. These signals should each be matched within ±0.1”of the HL_STB and HL_STB# signals.
Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed
20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The
maximum length for the strobe signals is 7”and the two strobes should be the same length.
Additionally, the trace length for each data signal should be matched to the trace length of the
strobes with ±0.1”.
HREF is the hub interface reference voltage. It is 0.5 * 1.8 V = 0.9 V ±2%. It can be generated
locally, or a single HREF divider can be used. Each divider consists of a DC element and an AC
element. The resistors in the DC element should be equal in value and rated at 1% tolerance. The
value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained
over the entire input leakage specification. The resistors in the AC element of the resistor divider
should be no greater than 80 Ωand the capacitors should be 500 pF. Additionally, the reference
voltage should be bypassed to ground at each component with a 0.1 uF capacitor.
Intel-Based Electronic Classroom Student Computing Station
16 Application Note
5.2.2 The Intel®82801 I/O Controller Hub (ICH)
The 82801 I/O Controller Hub (ICH) employs the Intel Accelerated Hub Architecture to make a
direct connection from the graphics and memory to the integrated AC97 controller, the IDE
controllers, dual USB ports, and PCI add-in cards.
The Accelerated Hub Architecture provides twice the bandwidth of the PCI bus at 266 MB per
second. This allows a wider flow of rich information from the I/O controller to the memory
controller, with optimized arbitration rules allowing more functions to run concurrently, enabling
more life-like audio and video.
The Integrated Audio-Codec 97 controller enables software audio and modem by using the
processor to run sound and modem software. By reusing existing system resources, this feature
adds flexibility, improves sound quality, and lowers the system BOM cost by eliminating
components.
The 82802 Firmware Hub (FWH) stores system BIOS and video BIOS, eliminating a redundant
nonvolatile memory component. In addition, the 82802 contains a hardware Random Number
Generator (RNG). The Intel RNG provides truly random numbers to enable fundamental security
building blocks supporting stronger encryption, digital signing, and security protocols.
5.2.2.1 Design Notes for the Intel®82801 ICH
•ICH Placement: The ICH should be placed within 8”of the ATA connector(s). There are no
minimum length requirements for this spacing.
•Capacitance: The capacitance of each pin of the IDE connector on the host should be below
25 pF when the cables are disconnected from the host.
•Series Termination: There is no need for series termination resistors on the data and control
signals since series termination is integrated into these signal lines on the ICH.
•A1KΩpull-up to 5 V is required on PIORDY and SIORDY.
•A 470 Ωpull-down resistor is required on pin 28 of each connector.
•A5.6KΩpull-down resistor is required on PDREQ and SDREQ.
•Support Cable Select (CSEL) is a PC99 requirement. The state of the cable select pin
determines the master/slave configuration of the hard drive at the end of the cable.
•Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15.
•IRQ14andIRQ15eachneedan8.2KΩpull-up resistor to VCC.
•Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1
of the IDE connectors as the IDE reset signal. Due to high loading, the PCI_RST# signal
should be buffered.
•There is no internal pull up or down on PDD7 or SDD7 of the ICH. Devices should not have a
pull-up resistor on DD7. It is recommended that a host have a 10 KΩpull-down resistor on
PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as
required by the ATA-4 specification).
•If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be
grounded and the output signals left as no connects.
Intel-Based Electronic Classroom Student Computing Station
Application Note 17
5.3 IDE Connectors
The 82801AA ICH supports Ultra ATA/66 and ATA/33 devices The ATA/66 cable is an
80-conductor cable; however the 40-pin connectors used on motherboards for 40-conductor cables
do not change as a result of this new cable. The wires in the cable alternate: ground, signal, ground,
signal, etc. All the ground wires are tied together at the connectors on the cable (and they are tied to
the ground on the motherboard through the ground pins in the 40-pin connector). This cable
conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained
from the Small Form Factor Committee. To determine if ATA/66 mode can be enabled, the Intel
810 chipset using the ICH requires the system BIOS to attempt to determine the cable type used in
the system.
If only one IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be
grounded and the output signals left as no connects. This can be implemented to reduce the board
space and cost.
5.4 AC’97 2.1 Compliant Components
The ICH implements an Audio Codec '97 (AC’97) 2.1 compliant digital controller. Any codec
attached to the ICH AC-link should also be AC’97 2.1 compliant. Contact your preferred codec
vendor for information on AC’97 2.1 compliant products. The AC’97 2.1 specification is available
on the Intel web-site:
http://developer.intel.com/pc-supp/platform/ac97/index.htm
The ICH supports the following combinations of codecs:
The ICH does not support two codecs of the same type on the link. For example, if an AMC is on
the link, it must be the only codec. If an AC is on the link, another AC cannot be present.
Table 2. AC’97 Configuration Combinations
Primary Secondary
Audio (AC) None
Modem (MC) None
Audio (AC) Modem (MC)
Audio/Modem (AMC) None
Intel-Based Electronic Classroom Student Computing Station
18 Application Note
5.4.1 Design Notes for AC’97 Devices
•Special consideration must be given for the ground return paths for the analog signals. If
isolated ground planes are used, pin B2 on the AMR connector should be used as an isolated
ground pin and should be connected to an isolated ground plane to reduce noise in the analog
circuits. The AMR designer and motherboard designer should jointly address any EMI issues
when implementing isolated grounds.
•Digital signals routed in the vicinity of the analogaudio signals must not cross the power plane
split lines. Analog and digital signals should be located as far as possible from each other.
•Partition the board with all analog components grouped together in one area and all digital
components in the other.
•Separate analog and digital ground planes should be provided, with the digital components
over the digital ground plane, and the analog components, including the analog power
regulators, over the analog ground plane. The split between the planes must be a minimum of
0.05”wide.
•Keep digital signal traces, especially the clock, as far way from analog input and voltage
reference pins as possible.
•Do not completely isolate the analog/audio ground plane from the rest of the board ground
plane. There should be a single point (¼” to ½”wide) where the analog/isolated ground plane
connects to the main ground plane. The split between the planes must be a minimum of
0.05”wide.
•Any signals entering or leaving the analog area must cross the ground split in the area where
the analog ground is attached to the main motherboard ground (i.e., there should not be any
signals crossing the split/gap between the ground planes). Doing so will cause a ground loop.
5.5 Audio/Modem Riser Card (AMR)
Intel is developing a common connector specification known as the Audio/Modem Riser (AMR).
This specification defines a mechanism for allowing OEM plug-in card options. The AMR
specification is available on the Intel developer website:
http://developer.intel.com/pc-supp/platform/ac97/index.htm
The AMR specification provides a mechanism for AC’97 codecs to be on a riser card. This is
important for modem codecs as it helps ease international certification of the modem.
For the Intel-based electronic classroom student computing station, the audio codec is integrated on
the motherboard to avoid compatibility issues and robustness. A modem codec is optional for
electronics classroom.
5.5.1 Design Notes for the Audio/Modem Riser Card
•Only one primary codec can be present on the link. A maximum of two present codecs can be
supportedinanICHplatform.
•As the Intel-based electronic classroom student computing station motherboard implements an
active primary codec (audio) on the motherboard and provides an AMR connector, it must tie
PRI_DN# to ground. The PRI_DN# pin is provided to indicate that a primary codec is present
on the motherboard.
Intel-Based Electronic Classroom Student Computing Station
Application Note 19
5.6 PCI
The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification,
Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH
is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus
interface, please refer to the PCI Local Bus Specification, Revision 2.2. The 82801AA ICH
supports 6 PCI bus masters (excluding ICH), by providing 6 REQ#/GNT# pairs. The PCI network
controller (GD82559) is integrated on board; therefore, an extra PCI slot is expandable for a PCI
network broadcasting card (if implemented).
5.7 Network Controller —Intel®82559 Fast Ethernet Controller
The 82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer
device is Intel’s leading solution for PCI board LAN designs. It is designed for use in Network
Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems, and
networking system products. The 82559 combines a low power and small package design which is
ideal for power- and space-constrained environments. It is compliant with Advanced Configuration
and Power Interface (ACPI) 1.20A-based power management and with the Wired for Management
(WfM) 2.0 Baseline specification.
The 82559 is an integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY. It provides
a glueless 32-bit PCI master interface and supports a 128 Kbyte Flash interface. The package is a
thin BGA with a small footprint (15 mm X 15 mm).
The 82559 supports the Intel Preboot Execution Environment (PXE) driver, which allows a new or
existing system to boot over the network and download software or an image, including the
operating system, stored on a server. The 82559 provides for operating system independent
network booting, automating the setting up and configuration of new systems. If the operating
system or applications software is damaged, the system can be recovered by downloading the
original image from server again, reducing the total cost of maintenance.
5.7.1 Design Note for the Intel®82559 Fast Ethernet Controller
The differential transmit signal pair (TDP/TDN) is terminated with a 100 W (1%) resistor, and the
differential receive signal pair (RDP/RDN) is terminated with a 120 W (1%) resistor. These
termination resistors should be placed as close to the PHY as possible. These resistors terminate the
entire impedance seen at the termination source (for example, the PHY), including the wire
impedance reflected through the transformer. Figure 4 depicts the placement of the termination
resistors.
Intel-Based Electronic Classroom Student Computing Station
20 Application Note
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width
to trace-height above the ground plane. To minimize trace inductance, high-speed signals, such as
the clock, and signal layers that are close to a ground plane or power plane should be as short and
as wide as is practical. As shown in Figure 5, this ratio is ideally somewhere between 1:1 and 3:1.
To maintain the impedance of a trace, the width of the trace should be modified when changing
from one board layer to another if the two layers are not equidistant from a power or ground plane.
Figure 4. Placement of Termination Resistor
A7495-01
82559 Magnetics
Module RJ-45
PCI Interface
R
R
Place termination resistors
as close to the 82559 as possible.
Figure 5. Trace Geometry
NOTE: W= Trace Width, H= Height Above Ground Plane
A7496-01
Ground
H
WW
H
1 < < 3
Intel-Based Electronic Classroom Student Computing Station
Application Note 21
5.7.2 Wired for Management
Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop,
mobile, server and embedded systems. The goal of WfM is to reduce the total cost of ownership
(TCO) through improved manageability in the following four technology areas:
•Instrumentation
•Remote Service Boot
•Remote Wake-Up
•Power Management
Manageability features in each of these four technology areas combine to form the Wired for
Management Baseline Specification. A copy of the Wired for Management Baseline Specification,
Version 2.0 can be obtained from:
http://developer.intel.com/ial/wfm/wfmspecs.htm
An on-line Design Guide is available at:
http://developer.intel.com/ial/WfM/design/index.htm
Future versions of the specification will be available at this site.
In the Intel-based electronic classroom reference configuration, the NIC is WfM compliant,
particularly in the Remote Service Boot features needed to support the student computing stations’
remote boot from the server.
5.7.2.1 Instrumentation
A component's instrumentation consists of code that maintains attributes with up-to-the-minute
values and adjusts the component's operational characteristics based on these values. By providing
instrumentation, the platform provides accurate data to management applications, so those
applications can make the best decisions for managing a system or product. The WfM 2.0 Baseline
requires that compliant desktop and mobile platforms utilize the DMI Version 2.00 Management
Interface (MI) and Component Interface (CI) application programming interfaces and host a DMI
v2.00 Service Provider, as defined by the DMTF. Intel's DMI 2.0 Service Provider Software
Development Kit (SDK) provides a DMI Service Provider and binaries that support DMI Version
2.00. This kit is available at the following URL:
http://developer.intel.com/ial/WfM/tools/sdk/index.htm
Intel®LANDesk®Client Manager product includes the Service Provider and component
instrumentation. Information regarding this product can be found at:
http://developer.intel.com/ial/WfM/tools/ldcm/index.htm
The WfM Baseline Instrumentation specification identifies specific DMI standard groups,
including event generation groups, that must be instrumented for a Baseline-compliant platform.
This specification provides support for the SMBIOS revision 2.0 specification that along with
appropriate component instrumentation will supply some of the required data in the specified
DMI 2.0 groups.
Intel-Based Electronic Classroom Student Computing Station
22 Application Note
5.7.2.2 Remote Service Boot
The WfM Baseline specifies the protocols by which a client requests and downloads an executable
image from a server and the minimum requirements on the client execution environment when the
downloaded image is executed. The Baseline specification includes a set of APIs for the particular
network controller used. The code supporting the Preboot eXecution Environment (PXE) and the
network controller is provided on the EtherExpress™PRO/100 WfM adapters Option ROM. Two
implementation options are available:
•NICwithOptionROMandWakeonLANHeader
•LAN on Motherboard implementation.
For this option, the Preboot execution environment and the network controller code must be
incorporated into the system BIOS.
In addition, the BIOS must provide the _SYSID_ and _UUID_data structures. The details of the
BIOS requirements can be obtained from the Intel web site:
http://developer.intel.com/ial/WfM/design/pxedt/index.htm
5.7.2.3 Remote Wake-Up
If a student computing station supports a reduced power state, it is possible to bring the system to a
fully powered state in which all power management interfaces are available. Typically, the LAN
adapter recognizes a special packet as a signal to wake up the system. The system BIOS must
enable the wake event and provide wake up status. The details of the BIOS requirements can be
obtained from the Intel web site:
http://developer.intel.com/ial/WfM/design/rwudt/index.htm
5.7.2.4 Power Management
WfM Baseline compliant systems have four distinct power states: Working,Sleeping, Soft Off, and
Mechanical Off. A user accessible switch that will send a soft off request to the system usually
provides Soft Off. A second optional “override”switch located in a less obvious place (or removal
of the power cord) stops current flow forcing the platform into the mechanical off state without OS
consent. Note that a second “override”switch is required for legal reasons in some jurisdictions
(for example, some European countries). The BIOS may support the power management
requirement either through the APM revision 1.2 or ACPI revision 1.0 specifications. See Intel's
web site for additional information:
http://developer.intel.com/ial/WfM/design/pmdt/index.htm.
5.8 Low Pin Count (LPC) Interface
In the Intel 810 chipset platform, the Super I/O* (SIO) component has migrated to the Low Pin
Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.
The LPC Super I/O component requires the same feature set as traditional Super I/O components.
It should include a keyboard and mouse controller, a floppy disk controller, and serial and parallel
ports. In addition to the Super I/O features, an integrated game port is recommended because the
AC’97 interface does not provide support for a game port. In systems that have ISA audio, the
game port typically existed on the audio card. The fifteen pin game port connector provides for two
joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a
comprehensive list of devices offered and features supported.
Intel-Based Electronic Classroom Student Computing Station
Application Note 23
6.0 Conclusion
Traditional teaching media such as projector, video player, audio recorder, and black board are
being replaced in the Intel-based electronic classroom by new computer-based teaching media.
Audio, video and 2-D/3-D graphics can be introduced in the Intel-based electronic classroom. The
classroom can be connected to the Internet by using modem or Intel router.
Intel provides the building blocks for Intel-based electronic classroom systems that feature
manageability, ease of maintenance, compatibility with operating systems and application
software, and long life cycle support for the Intel components. The recommended motherboard
configuration is designed to optimize the performance of the overall system, reducing board space,
power consumption, and the total cost of ownership.
Intel-Based Electronic Classroom Student Computing Station
Application Note 25
Appendix A References
Document Order Number / URL
Intel Documents and Resources
Intel®810 Chipset Design Guide Order Number 290657
http://developer.intel.com/design/chipsets/designex/290657.htm
Intel®82810 Chipset: Intel 82810/82810-DC100 Graphics
and Memory Controller Hub (GMCH) datasheet Order Number 290656
http://developer.intel.com/design/chipsets/datashts/290656.htm
Intel®82801AA (ICH) and Intel 82801AB (ICH0) I/O
Controller Hub datasheet Order Number 290655
http://developer.intel.com/design/chipsets/datashts/290655.htm
Intel®82801 FirmWare Hub (FWH) datasheet Order Number 290658
http://developer.intel.com/design/chipsets/datashts/290658.htm
Intel®Celeron™ Processor datasheet Order Number 243658
http://developer.intel.com/design/celeron/datashts/243658.htm
VRM 8.2 DC-DC Converter Design Guidelines Order Number 243733
http://developer.intel.com/design/pentiumii/xeon/designgd/243773
.htm
AP-585 Pentium®II Processor GTL+ Guidelines Order Number 243330
http://developer.intel.com/design/pentiumii/applnots/243330.htm
AP-587: Slot 1 Processor Power Distribution Guidelines Order Number
http://developer.intel.com/design/celeron/applnots/243332.htm
Pentium®II Processor Developer's Manual Order Number 243341
http://developer.intel.com/design/PentiumII/manuals/243502.htm
Pentium® II Processor at 350 MHz, 400 MHz and 450 MHz
datasheet Order Number 243657
http://developer.intel.com/design/PentiumII/datashts/243657.htm
Intel®82559 Fast Ethernet Multifunction PCI Controller http://developer.intel.com/design/network/82559.htm
AP-39982559PrintedCircuitBoardDesign Order Number 739073
http://developer.intel.com/design/network/applnots/739073.htm
AP-392 82559 LAN on Motherboard (LOM) Design Guide Order Number 718213
http://developer.intel.com/design/network/applnots/718213.htm
Intel®Networking LANSchool software site http://www.intel.com/network/products/lanschool.htm
AC’97 Specifications on Intel web site http://developer.intel.com/pc-supp/platform/ac97/index.htm
Wired for Management specifications and information http://developer.intel.com/ial/wfm/index.htm
Non-Intel Documents and Resources
PCI Local Bus Specification, Revision 2.2 http://www.pcisig.com/
Universal Serial Bus Specification, Revision 1.0 http://www.usb.org/
Intel-Based Electronic Classroom Student Computing Station
Application Note 27
Appendix B Intel-Based Electronic Classroom Schematics
A
A
A A
TITLE PAGE
Cover Sheet
Block Diagram
370PGA So cke t
GTL Termination
Clock Synthesizer
82810
System M e mory
82801AA
82802AB (FWH)
Super I/ O
PCI Connectors
2
3 , 4
5
6
7 , 8 , 9
13
14
15
17
18
1
10
11,12
** Please note these schemat ics are subject t o change.
THESE SCHEMATICS ARE PROV I D E D "AS IS " WITH NO W ARRANTI E S
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY , FITNE SS
FOR ANY PARTICULAR PURPOSE , O R ANY WARRANTY O T H E RW I S E ARIS I N G
OUT OF PROPOSAL, SPECIFICATION OR SA MPLES.
Intel may make changes to specifications and
product descriptions at any time, without
notice.
The Intel (r) Celeron (tm) processor and Intel (r) 810 chipset
may contain design defects or errors known as errata which
may cause the product to deviate from published
specifications. Current characterized errata are available on
request.
Copyright (c) Intel Corporation 2000
* Other brands and names are the property of their respective
owners.
Electronic Classroom Student Computing Station Ref Schematic Rev
Last Revision Date:
Sheet:
INTEL CORPORATION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
0.1
COVER SHEET
1 of 33
21
Voltage Regulators
Serial Ports
25
Decoupling 30
20
29
Pullup Resistors and Unused Gates
LAN (82559)
Parallel Port
23,24
16
AC’97 Riser Connector
19
System
USB Connectors
27,28
22
Graphics Connectors
VRM 8. 4 26
Kybrd / Mse / F. Disk / Gme Connectors
Revision History
ATA 33/66 IDE Connectors
31
Information in this document is provided in connection with
Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel’s Terms and Conditions
of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products
including liability or warranties relating to fitness for a
particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right. Intel
products are not intended for use in medical, life saving or life
sustaining applications.
Intel® Celeron™ Processor And Intel® 810
Based Electronic Classroom Student Computing Station Hardware
Schematics
APPL IE D C OM PU TI N G P RODUCTS DIVISION
A
A
A A
DATA
CTRL
ADDR
Term
VRM
82801AA
Keyboard
Mouse Floppy Parallel
Serial 1
SIO
Clock
PCI CONN 1
Block Diagram
One
DIMM
Module
USB Port 1
USB Port 2
PCI CNTRL
CTRL
DATA
ADDR
USB
PCI CNTRL
PCI ADDR/DAT A
AC’97 Link
82802AB
PCI ADDR/DAT A
LPC Bus
LAN
82810
Game Po r t
370-Pin Socket Processor
Ultra D M A 3 3 / 66
IDE Primary
Electronic Clasroom Student Computing Station Ref. Schematic REV
Last Revision Date:
Sheet:
INTEL CORPORATION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
0.1
BLOCK DIAGRAM
2 of 33
PG. 26
AUDIO/MODEM RISER
PG. 3-4
PG. 10
PG. 16
PG. 11-12
PG. 23-24
PG. 22
PG. 13
PG. 14
PG. 7-9
PG. 17
PG. 17
PG. 6
PG. 5
PG.
15
PG. 16
IDE Secondary
APPLI ED C OMP UT IN G P RODUCTS DIVISION
A
A
A A
Part 1
370-Pin Socket
Part 1
370PGA Socket
INTEL CORPORATION
0.1
CHANDLER, AZ 85226
370-PIN SOCKET (PART 1)
5000 W CHANDLER BLVD. CH6-236 Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic
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APPLI ED C OMP UT IN G P RODUCTS DIVISION
HA#17
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VID3
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VCCVID
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C23
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AK18
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AN13
AH4
A29
A31
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AC1
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B26
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AM16
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E17
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AJ25
AF2
D24
F26
AM28
AJ29
D28
AK34
F30
B30
AM32
AH32
AB2
Z32
V32
R32
T2
P2
K2
F4
AL35
AM36
AL37
AJ37
GND1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND2
GND20
GND21
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GND3
GND30
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GND4
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GND5
GND50
GND6
GND7
GND8
GND9
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HD#8
HD#9
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
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RS#1
RS#2
RSRVD1
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RSRVD2
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VCC9
VID0
VID1
VID2
VID3
A
A
A A
Part 2
370-Pin Socket
ITP Test Port Option
Part 2
JP5 is a Test Option Only.
GTLREF Inputs (1 cap for every 2 inputs).
Use 0603 Packages and distribute
within 500 mils of Mendocino
GTLREF Generation Circuit
Place 0603 Package
Near VCMOS Processor Pin.
VCMOS Decoupling
370PGA Socket
Do not stuff C114
Place site w / in 0.5"
of clock pi n ( W37)
INTEL CORPORATION
0.5
CHANDLER, AZ 85226
370-PIN SOCKET (PART 2)
5000 W CHANDLER BLVD. CH6-236
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic Rev
4 of 33
APPLIED COMPUTING PRODUCTS DIVISION
ITP_PON
R_TCK
R_TMS
ITP_RST
R_ITPRDY# R_TMS
R_DBRST#
R_TCK
VCMOS
4N642
4N859
GTLREF
EDGCTRL
PLL1
TCK
ITPRDY#
TDI
TDO
TRST#
4N937
4N639
ITPREQ#
VCMOS
PLL2
4N329
4N606
4N949
CPURST#
TMS
GTLREF
VCMOS
4N101
4N677
VCMOS29
NMI 11, 29
INTR 11, 29
SMI# 11, 29
A20M# 11,29
STPCLK# 11,29
CPUSLP# 11, 2 9
BR0# 5
BNR# 5,7
BPRI# 5,7
HTRDY# 5,7
DEFER# 5,7
HLOCK# 5,7
DRDY# 5,7
HITM# 5,7
HIT# 5,7
DBSY# 5,7
HADS# 5,7
FREQSEL 6,9
APICD011,29 APICD111,29
APICCLK_CPU6
CPUHCLK6
PWRGOOD29
ITPCLK6
DBRESET#
28
CPURST#5,7
VCCDET 9
FERR# 11,29
RTTCRTL 29
ITPRDY# 5
INIT# 11,13,29
SLEWCTRL 29
IGNNE# 11,29 VCCVID
VCCVID
VTT1_5
VCC2_5
VCCVID
VCC3_3
VTT1_5
VTT1_5
VCC2_5
EDGCTRL
0.1UF
C204A
0.1UF
C6A
R9A
220
RP2A
330
1
2
3
4 5
6
7
8
R171A
220
R2A
0K
J2A
ITP30RA
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29 30
4
5 6
7 8
9
3
1
R7A
150
R8A
1K
R1A
240
R3A
47
R4A
47
R21A
240
R5A
680
R102A
75
1%
R76A
51
R104A
150
1%
0.1UF
C207A
0.1UF
C209A
0.1UF
C206A
X2B
AE33
AN31
W37
AH14
G33
E37
C35
E35
AN17
AN29
AJ33
C37
AL27
AN19
AN27
AG1
AC35
AE37
AF32
AB32
X32
T32
P32
F32
B32
AH34
AD34
Z34
V34
R34
M34
H34
D34
AK36
AF36
X36
T36
P36
K36
F36
A37
AC33
AJ3
AL1
AN3
Y37
AJ31
Y33
AL25
AL23
AE35
AG37
AG33
M36
L37
AK20
J33
J35
L35
W33
U33
A35
J37
AK26
X4
AN15
AN21
AN23
B36
C29
C31
C33
E23
E29
E31
F10
G35
G37
L33
N33
N35
N37
Q33
Q35
Q37
S33 S37
U35
U37
V4
W3
W35
X6
Y1
E21
E27
R2
X2
AH30
AJ35
AG35
AL33
AN35
AN37
AH28
AL29
AL31
AK32
AN25AN33
AD36
Z36
M32
H32
AF34
AB34
X34
T34
P34
K34
F34
B34
AH36
B22
V36
R36
H36
D36
D32
AD32
AH24
F14
K32
AA37
E33
F18
K4
R6
V6
AD6
AK12
AK22
AB36
Y35
S35
A20M#
ADS#
BCLK
BNR#
BP2#
BP3#
BPM0#
BPM1#
BPRI#
BR0#
BSEL#
CPUPRES#
DBSY#
DEFER#
DRDY#
EDGCTRL
FERR#
FLUSH#
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
HIT#
HITM#
IERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI
LOCK#
PICCLK
PICD0
PICD1
PLL1
PLL2
PRDY#
PREQ#
PWRGOOD
RESET#
RSRVD19
RSRVD20
RSRVD21
RSRVD22
RSRVD23
RSRVD24
RSRVD25
RSRVD26
RSRVD27
RSRVD28
RSRVD29
RSRVD30
RSRVD31
RSRVD32
RSRVD33
RSRVD34
RSRVD35
RSRVD36
RSRVD37
RSRVD38
RSRVD39 RSRVD40
RSRVD41
RSRVD42
RSRVD43
RSRVD44
RSRVD45
RSRVD46
RSRVD47
RSRVD48
RSRVD49
RSRVD50
RSRVD52
SLP#
SMI#
STPCLK#
TCK
TDI
TDO
THERMTRIP#
THRMDN
THRMDP
TMS
TRDY#TRST#
V1_5
V2_5
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7
V_CMOS
VCC75
RSRVD51
JP1A
21
+
33UF
C123A
20%
12
L22A
4.7UH
18PF
C114A
A
A
A A
GTL Termination
INTEL CORPORATION
0.5
GTL TERMINATION
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic
REV.
5 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
5N395
5N250
5N208
5N58
HA#9
HA#11
HA#8
HA#4
HA#16
HA#3
HA#5
HA#6
HA#21
HA#23
HA#25
HA#10
HA#15
HA#12
HA#28
HA#13
HA#26
HA#29
HA#27
HA#30
HA#24
HA#20
HA#18
HA#14
HA#7
5N369
HA#19
HA#22
HA#31
HA#17
HD#50
HD#59
HD#1
HD#61
HD#57
HD#60
HD#6 HD#40
HD#22
HD#12
HD#42
HD#55
HD#32
HD#21
HD#45
HD#2
HD#13
HD#9
HD#27
HD#8
HD#14
HD#4
HD#53
HD#16
HD#48
HD#62
HD#28
HD#56
HD#34
HD#51
HD#24
HD#37
HD#5
HD#54
HD#36
HD#25
HD#33
HD#7
HD#19
HD#0
HD#26
HD#49
HD#11
HD#10
HD#31
HD#63
HD#3
HD#58
HD#46
HD#17
HD#43
HD#39
HD#41
HD#38
HD#15
HD#44
HD#35
HD#23
HD#52
HD#30
HD#18
HD#47
HD#20
HD#29
CPURST# 4,7
HREQ#1 3,7
BNR# 4,7
DEFER# 4,7
HREQ#0 3,7
HREQ#4 3,7
BPRI# 4,7
RS#0 3,7
HTRDY# 4,7
HIT# 4,7
HITM# 4,7
HADS# 4,7
DBSY# 4,7
DRDY# 4,7
RS#2 3,7
RS#1 3,7
HLOCK# 4,7
HREQ#2 3,7
HREQ#3 3,7
ITPRDY# 4
BR0# 4
HA#[31:3] 3,7
HD#[63:0] 3,7
VTT1_5 VTT1_5 VTT1_5 VTT1_5
RP12A
56
1
2
3
4 5
6
7
8
RP20A
56
1
2
3
4 5
6
7
8
RP8A
56
1
2
3
4 5
6
7
8
RP21A
56
1
2
3
4 5
6
7
8
RP18A
56
1
2
3
4 5
6
7
8
RP19A
56
1
2
3
4 5
6
7
8
RP24A
56
1
2
3
4 5
6
7
8
RP35A
56
1
2
3
4 5
6
7
8
RP22A
56
1
2
3
4 5
6
7
8
RP9A
56
1
2
3
4 5
6
7
8
RP5A
56
1
2
3
4 5
6
7
8
RP10A
56
1
2
3
4 5
6
7
8
RP11A
56
1
2
3
4 5
6
7
8
RP7A
56
1
2
3
4 5
6
7
8
RP39A
56
1
2
3
4 5
6
7
8
RP37A
56
1
2
3
4 5
6
7
8
RP40A
56
1
2
3
4 5
6
7
8
RP42A
56
1
2
3
4 5
6
7
8
RP41A
56
1
2
3
4 5
6
7
8
RP43A
56
1
2
3
4 5
6
7
8
RP25A
56
1
2
3
4 5
6
7
8
RP26A
56
1
2
3
4 5
6
7
8
RP38A
56
1
2
3
4 5
6
7
8
RP33A
56
1
2
3
4 5
6
7
8
RP32A
56
1
2
3
4 5
6
7
8
RP36A
56
1
2
3
4 5
6
7
8
RP23A
56
1
2
3
4 5
6
7
8
RP3A
56
1
2
3
4 5
6
7
8
RP6A
56
1
2
3
4 5
6
7
8
A
A
A A
Clock Synthesizer
- Place all decoupling caps as close to VCC/GND pins as possible
Notes:
Minimize Stub Length from
CLK14 trace to JP1A.
- PCI_0/ICH p i n h a s to g o t o t he IC H .
- CPU_ITP pin has to g o to th e I T P . It i s t h e o nly
CPU CLK th at ca n b e shut o f f t h rough the SMBUS interface.
(This cl o c k cannot be turned off through SMBus)
APIC Clk Strap JP6A
16 MHz
33 MHz
in
out
INTEL CORPORATION
0.5
CLOCK SYNTHESIZER
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic Rev .
6 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
MEMCLK1
MEMCLK2
MEMCLK3
MEMCLK4
MEMCLK5
MEMCLK6
MEMCLK7
XTAL_IN
DCLK
USB_1
USB_0
3V66_0
3V66_1
PCI_5
DRAM_7
DRAM_6
DRAM_5
DRAM_4
DRAM_3
DRAM_2
DRAM_1
APIC_0
SEL1_PU
L_CKVDDA
USBV3
PCIV3
REFCLK
PCI_0
PCI_1
PCI_2
PCI_6
APIC_1
DRAM_0
MEMCLK0
L_VCC2_5
CPU_2
XTAL_OUT CPU_0_1
MEMV3
JP1
DCLK_WR 8
FREQSEL 4,9
APICCLK_CPU 4
APICCLK_ICH 11
CPUHCLK 4
GMCHHCLK 7
ITPCLK 4
CK_PWRDN# 24,27
CK_SMBDATA 20
CK_SMBCLK 20
SIO_CLK14
14
ICH_CLK14
12
ICH_3V6612 GMCH_3V66
8
PCLK_0/ICH
11
DOTCLK9USBCLK12
PCLK_613 PCLK_524
PCLK_215 PCLK_114
MEMCLK[7:0] 10
VCC3_3
VCC3_3
VCC3_3
VCC2_5
VCC3_3
CPU
APIC
USB
REF
CK_Whitney
3V66
PCI Memory
ICS9250-10
U1A
7
8
55
54
52
50
49
11
12
13
15
16
18
19
20
1
31
30
46
45
43
42
40
39
37
36
28
29
25
26
51
53
2
9
10
21
27
33
38
44
22
48
56
5
6
14
17
24
35
41
47
23
3
4
34
32
3V66_0
3V66_1
APIC_0
APIC_1
CPU_0
CPU_1
CPU_2/ITP
PCI_0/ICH
PCI_1
PCI_2
PCI_3
PCI_4
PCI_5
PCI_6
PCI_7
REF0
SCLK
SDATA
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_7
SEL0
SEL1
USB_0
USB_1
VDD2_5[0]
VDD2_5[1]
VDD3_3[0]
VDD3_3[1]
VDD3_3[2]
VDD3_3[3]
VDD3_3[4]
VDD3_3[5]
VDD3_3[6]
VDD3_3[7]
VDD_A
VSS2_5[0]
VSS2_5[1]
VSS3_3[0]
VSS3_3[1]
VSS3_3[2]
VSS3_3[3]
VSS3_3[4]
VSS3_3[5]
VSS3_3[6]
VSS3_3[7]
VSS_A
XTAL_IN
XTAL_OUT
DCLK
PWRDWN#
.001UF
C388A
.1UF
C386A
0.1UF
C61A
.001UF
C64A
R44A
33
R41A
8.2K
R23A
10K
L16A
1 2
L13A
1 2
JP6A
R43A
33
R50A
33
R46A
33
R51A
33
R47A
22
R53A
33
Y1A
XTAL
14.318MHZ
1 2
0.1UF
C63A
0.1UF
C39A
0.1UF
C50A
.001UF
C53A
.001UF
C37A
0.1UF
C52A
0.1UF
C38A
12PF
C51A
.001UF
C60A
.001UF
C40A
+
22UF
C55A
12
0.1UF
C47A
.001UF
C46A
R36A
22
R42A
22
R49A
22
L17A
1 2
+
22UF
C48A
12
+
4.7UF
C56A
12
R40A
22
R30A
22
R39A
22
R29A
22
R38A
22
R28A
22
R37A
22
R27A
22
R184A
10
R48A
10
L18A
1 2
+
22UF
C158A
12
12PF
C49A
R35A
33
R32A
33
R34A
33
R26A
33
R25A
33
L15A
1 2
.001UF
C385A
.1UF
C387A
A
A
A A
82810, PART 1: HOST INTERFACE
Place site w/in 0.5"
of clock ball (V6)
Do not Stuff C398
INTEL CORPORATION
0.5
82810 ,PART 1: HOST INTERFACE
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic Rev .
7 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
HA#28
HA#4
HA#9
HD#53
HD#62
HREQ#1
HA#29
HA#31
HD#39
HA#5
HD#45
HD#9
HA#13
HA#14
HA#24
HA#6
HD#14
HD#31
HD#41
HD#49
HD#50
HD#54
RS#1
HA#18
HA#19
HD#0
HD#10
HD#13
HD#32
HD#48
HD#55
HREQ#4
HD#46
HD#8
RS#2
HA#8
HD#2
HD#28
HD#6
HD#63
HREQ#0
HA#16
HA#21
HD#23
HD#26
HD#35
HD#4
HD#5
HD#59
HA#23
HA#27
HA#30
HD#20
HD#27
HD#33
HD#56
RS#0
HA#20
HA#26
HA#3
HD#16
HD#18
HD#38
HA#12
HD#58
HD#60
HD#7
HD#15
HD#19
HD#3
HD#36
HD#37
HD#42
HD#52
HA#10
HA#7
HD#12
HD#24
HD#29
HD#34
HD#40
HD#51
HD#21
HD#30
HD#44
HD#47
HD#57
HD#61
HA#15
HA#17
HD#1
HD#11
HD#17
HD#22
HD#25
GMCHGTLREF
HA#11
HA#22
HD#43
HREQ#2
HA#25
HREQ#3
DEFER#4,5
HA#[31:3]3,5
HIT#4,5
RS#[2:0]3,5
BNR#4,5
PCIRST#
11,13,14,15,16,23
DBSY#4,5
HITM#4,5
GMCHHCLK6
HLOCK#4,5 CPURST#4,5
HADS#4,5
HREQ#[4:0]3,5
DRDY#4,5
HD#[63:0] 3,5
HTRDY#4,5
BPRI#4,5
VTT1_5 VCC1_8
18PF
C161A
HOST INTERFACE
U2A
INTEL 82810
PART1
N3
T3
T1
M4
R3
N1
M5
W13
W1
U4
W3
W4
T5
W2
V2
AC2
AA2
Y3
AB3
AA1
AB2
AC3
AA3
Y2
AB5
AC4
Y1
AC5
U5
Y4
AB1
U1
V4
V1
T4
U2
U3
Y5
W5
AB7
AC8
AA7
Y8
W7
AC6
W9
AC9
Y7
AA10
W8
AB8
AC10
AB13
AB10
AB9
AB11
Y10
AB16
AB12
Y11
AA6
Y9
AC12
W11
AC11
W12
AA11
AA13
Y13
Y12
AC14
AB6
AA15
AC15
Y14
AC13
AA14
AB14
Y17
Y15
AC17
AC16
Y6
AA18
AB15
W15
AB18
W17
AA17
W18
W16
AC19
Y16
AA5
AB19
Y18
AC18
AB17
AA9
V5
AC7
P1
R1
R4
T2
P4
R2
R5
N4
M2
N5
P2
N2
B20
P6
V17
F14
F10
F8
F7
V16
V15
V14
V10
V9
V8
V7
F17
F16
Y22
K11
K10
L14
L13
L12
L11
L10
M14
M13
M12
V18
M11
M10
N14
N13
N22
J22
Y19
C19
E22
K14
K13
K12
V6
U18
AB4
P5
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
GTLREFA
GTLREFB
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA3#
HA30#
HA31#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HD0#
HD1#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD2#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD3#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD4#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD5#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD6#
HD60#
HD61#
HD62#
HD63#
HD7#
HD8#
HD9#
HIT#
HITM#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HTRDY#
RESETB
RS0#
RS1#
RS2#
VCC1_8[0]
VCC1_8[1]
VCC_CORE[0]
VCC_CORE[10]
VCC_CORE[11]
VCC_CORE[12]
VCC_CORE[13]
VCC_CORE[1]
VCC_CORE[2]
VCC_CORE[3]
VCC_CORE[4]
VCC_CORE[5]
VCC_CORE[6]
VCC_CORE[7]
VCC_CORE[8]
VCC_CORE[9]
VSS[0]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[1]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
HTCLK
VCC1_8[2]
CPURST#
HLOCK#
R81A
150
1%
R80A
75
1%
0.1UF
C166A
.001UF
C167A
A
A
A A
82810, PART 2: SYSTEM MEMORY
AND HUB INTERFACE
as possible to GMCH
Place Resistor as Close
Place C241A as close
as possible to GMCH
Circuit in middle of
Place HUBREF Generation
GMCH and ICH.
INTEL CORPORATION
0.5
82810, PART 2: SYSTEM MEMORY AND HUB INTERFACE
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic Rev .
8 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
HUBREF_CV
HUBREF_CG
SM_MD14
SM_MD39
SM_MD51
SM_MAA5
HL3
HL5
HL8
SM_MD17
SM_MD24
SM_MD62
SM_CS#0
SM_DQM4
SM_DQM7
SM_MAA1
SM_MD1
SM_MD22
SM_MD23
SM_MD31
SM_MD38
SM_MD50
SM_MAA7
SM_MAA10
SM_MD52
SM_MD54
HL9
HUBREF
SM_DQM2
SM_MD10
SM_MD59
SM_MD12
SM_MD19
SM_MD48
SM_BS1
SM_CKE1
SM_MD21
SM_MD41
SM_MD47
SM_MD6
SM_MAA6
SM_MD29
SM_MD35
HL7
SM_MD11
SM_MD13
SM_MD16
SM_MD32
SM_MD36
SM_MD4
SM_MD40
SM_MD42
SM_MD53
HL6
SM_MAA2
SM_MAA3
SM_MD20
SM_MD26
SM_MD37
SM_MD63
SM_MD9
HL1
HL4
SM_CS#2
SM_DQM3
SM_MD15
SM_MD28
SM_MD60
SM_MD61
SM_MAA4
HL0
SM_DQM6
SM_MAA0
SM_MD0
SM_MD25
SM_MD34
GHCOMP
HL10
SM_BS0
SM_CS#1
SM_DQM0
SM_MAA11
SM_MD18
SM_MD33
SM_MD49
HL2
SM_CKE0
SCLK
SM_MAA9
SM_MD2
SM_MD30
SM_MD43
SM_MD27
SM_MD44
SM_MD46
SM_MD5
SM_MD55
SM_MD57
SM_MD8
SM_CS#3
SM_DQM1
SM_MAA8
SM_MD45
SM_MD56
SM_MD58
SM_MD7
SM_DQM5
SM_MD3
DCLK_WR6
SM_MD[63:0] 10
SM_CKE[1:0]
10
SM_WE#
10
HLSTB
11
HUBREF 11
SM_RAS#
10
HLSTB#11
HL[10:0]
11
SM_BS[1:0]
10
SM_CS#[3:0]
10
SM_CAS#10
GMCH_3V666
SM_DQM[7:0]
10
SM_MAA[11:0]10
VCC1_8
VCC1_8
VCC3_3
VCC3_3SBY
RP70A
10
1
2
3
4 5
6
7
8
RP77A
10
1
2
3
4 5
6
7
8
AND
SYST E M M E MO R Y
HUB INTERFACE
HUB I/F
U2B
INTEL 82810
PART 2
D18
C21
B23
A19
B22
A23
B19
B18
C18
A18
A22
C20
D19
A21
A20
D20
C5
A11
A3
A2
E6
C4
C3
B3
C2
C10
A10
B1
D1
B10
D9
C1
D2
C9
E7
D5
A5
A9
D7
B8
A8
B7
A7
D6
C6
B6
A6
B4
A4
E17
C16
B14
A14
D13
C13
A13
A12
E1
F2
G4
G1
D15
D3
H2
H1
J4
J1
K2
K1
K3
L1
L2
D17
M3
K4
D16
E15
D14
E14
E13
E12
D12
B15
C17
B12
C12
D11
D10
E10
E9
E8
C8
F3
F1
A17
G2
H3
E4
E3
F4
J3
F5
G5
H5
H4
A16
H6
J5
K5
L5
B16
A15
C14
D8
B11
D4
B2
L21
F18
J18
R18
C11
C7
C15
L3
G3
F15
F9
K6
F6
N12
N11
N10
P14
P13
P12
P11
P10
AC1
AA4
AA8
AA12
AA16
W6
W10
W14
V3
R6
P3
M1
L4
J2
E5
G21
HCOMP
HL0
HL1
HL10
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HLCLK
HLSTB
HLSTB#
HUBREF
SBS0
SCAS#
SCKE0
SCKE1
SCLK
SCS0#
SCS1#
SCS2#
SCS3#
SDQM0
SDQM1
SDQM2
SDQM3
SDQM4
SDQM5
SDQM6
SDQM7
SMAA0
SMAA1
SMAA10
SMAA11
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAB4#
SMAB5#
SMAB6#
SMAB7#
SMD0
SMD1
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD2
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD3
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD4
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD5
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD6
SMD60
SMD61
SMD62
SMD63
SMD7
SMD8
SMD9
SRAS#
SWE#
VCC3_3[0]
VCC3_3[10]
VCC3_3[11]
VCC3_3[13]
VCC3_3[14]
VCC3_3[15]
VCC3_3[1]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
VCC3_3[8]
VCC3_3[9]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
SBS1
VCC3_3[12]
R31A
0K
R82A
40
1%
22PF
C168A
0.1UF
C241A
18PF
C236A
R177A
56
R131A
301
1%
R130A
301
1%
470PF
C299A
470PF
C300A
R176A
56
A
A
A A
GMCH RESET STRAP S
82810, PART 3
Jumper Comment
Function
XO R IN = XOR T r e e
*OUT = Normal
Tri-state
JP16
JP15 IN = Tri-state Mode
*OUT = Normal
System
Bus Freq. N/A Reads Syste m
Bus Fr eq.
IOQ Depth JP14 IN = IOQ Depth of 1
*Out = IOQ Depth of 4
VCORE
Detect
RESVD
N/A
JP13
Detects ty p e of
Processor I / O Buff e rs
TBD
JP16
Do not Stuff C379A
VSS plane.
and via straight to
wide direct connections
placed close as possible to
Do Not Populate C238
Use Surface Mount Caps
power pins with short,
Possible to GMCH
Place R70A within 0.5" of
the GMCH Ball.
Place as close as
Place site w / in 0.5"
of clock ball (AA21).
INTEL CORPORATION
0.5
82810, PART 3: GRAPHICS
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic Rev
.
9 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
GRS_PU30
GRS_PU31
GRS_PU26
GRS_PU28
OCLK_FB
DC_MD26
DC_MD31
DC_MD30
DC_MD29
DC_MD28
OCLK
DOTCLK
IREFPD
DC_MD27
VCCDACA
R_LTCLK
RCLK
CRT_VSYNC 21
VID_BLUE 21
VCCDET 4
VID_GREEN 21
FREQSEL 4,6
3VDDCDA 21
VID_RED 21
3VDDCCL 21
DOTCLK 6
CRT_HSYNC 21
VCC3_3
VCC1_8 VCC1_8
VCC3_3SBY
R127A
22
R125A
174
1%
JP13A
JP14A
JP16A
JP15A
RP48A
10K
1
2
3
4 5
6
7
8
R62A
4.7K
+
33UF
C222A
12
R129A
33
L24A
68NH-0.3A
R128A
0K
R64A
4.7K
0.1UF
C216A
0.01UF
C217A
22PF
C238A
18PF
C379A
INTERFACE
VIDEO DIGITAL OUT
GRAPHICS INTERFACE
DISPLAY CACHE
U2C
INTEL 82810
PART3
V19
AC23
V21
V22
AA21
W20
W19
AC22
AB20
AA23
Y23
K20
L20
P21
R23
C23
F20
M19
P19
M20
L19
P20
N19
J21
H19
H20
H18
G19
F19
M22
M21
P23
P22
N23
N21
N20
M23
F23
E20
E21
E23
L23
D22
D23
D21
C22
H21
H22
H23
G20
G22
G23
L22
F21
F22
K21
K23
R19
R20
R22
R21
J23
K19
J20
K22
T19
T20
Y21
Y20
T22
T21
W23
W22
W21
V23
U23
U22
U21
T23
J19
AC21
U20
U19
V20
E19
AC20
AB23
AB21
U6
E18
AA22
AB22
T6
J6
G6
E2
A1
B5
B9
E11
B13
E16
B17
B21
G18
K18
P18
T18
AA19
AA20
BLANK#
BLUE
CLKOUT0
CLKOUT1
DCLKREF
DDCCL
DDCDA
GREEN
HSYNC
IREF
IWASTE
LCAS#
LCS#
LDQM0
LDQM1
LDQM2
LDQM3
LMA0
LMA1
LMA10
LMA11
LMA2
LMA3
LMA4
LMA5
LMA6
LMA7
LMA8
LMA9
LMD0
LMD1
LMD10
LMD11
LMD12
LMD13
LMD14
LMD15
LMD16
LMD17
LMD18
LMD19
LMD2
LMD20
LMD21
LMD22
LMD23
LMD24
LMD25
LMD26
LMD27
LMD28
LMD29
LMD3
LMD30
LMD31
LMD4
LMD5
LMD6
LMD7
LMD8
LMD9
LOCLK
LRAS#
LRCLK
LTCLK
LTVCL
LTVDA
LTVDATA0
LTVDATA1
LTVDATA10
LTVDATA11
LTVDATA2
LTVDATA3
LTVDATA4
LTVDATA5
LTVDATA6
LTVDATA7
LTVDATA8
LTVDATA9
LWE#
RED
TVCLKIN/SL_STALL
TVHSYNC
TVVSYNC
VCCBA
VCCDA
VCCDACA1
VCCDACA2
VCCHA
VSSBA
VSSDA
VSSDACA
VSSHA
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSYNC
RP46A
10K
1
2
3
4 5
6
7
8
A
A
A A
SYSTEM MEMORY
INTEL CORPORATION
0.5
SYSTEM MEMORY
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic REV
10 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
SM_MD40
SM_MD2
SM_MD26
SM_MD42
SM_MD32
SM_MD5
SM_MD25
SM_MD53
SM_MD43
SM_MD44
SM_MD51
SM_MD61
SM_MD12
SM_MD27
SM_MD16
SM_MD23
SM_MD41
SM_MD49
SM_MD8
SM_MD18
SM_MD28
SM_MD6
SM_MD54
SM_MD33
SM_MD31
SM_MD37
SM_MD45
SM_MD1
SM_MD13
SM_MD29
SM_MD9
SM_MD47
SM_MD50
SM_MD34
SM_MD38
SM_MD19
SM_MD55
SM_MD52
SM_MD30
SM_MD46
SM_MD24
SM_MD3
SM_MD0
SM_MD62
SM_MD7
SM_MD14
SM_MD59
SM_MD48
SM_MD11
SM_MD17
SM_MD39
SM_MD63
SM_MD21
SM_MD35
SM_MD20
SM_MD56
SM_MD36
SM_MD10
SM_MD58
SM_MD57
SM_MD22
SM_MD4
SM_MD60
SM_MD15
MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAA5
SM_MAA4
SM_MAA3
SM_MAA2
SM_MAA1
SM_MAA0
SM_BS1
SM_BS0
SM_DQM7
SM_DQM2
SM_DQM4
SM_DQM1
SM_DQM6
SM_DQM5
SM_DQM3
SM_DQM0
SM_CS#0
SM_CS#1
SM_CKE0
SM_CKE1
MEMCLK[7:0]
6
SM_MAA[11:0]
8
SM_BS[1:0]
8
SM_DQM[7:0]
8
SM_CS#[3:0]
8SM_WE#
8SM_CAS#8SM_RAS#
8
SM_CKE[1:0]
8
SMBDATA
12,21,24,29 SMBCLK
12,21,24,29
SM_MD[63:0]8
VCC3_3SBY
VCC3_3SBY
R63A
2.2K
SOCKETDIMM
168 PIN
J11A
33
117
38
123
126
132
34
118
35
119
36
120
37
121
122
39
111
128
63
125
79
163
2
3
14
15
16
17
19
20
55
56
57
58
4
60
65
66
67
69
70
71
72
74
75
5
76
77
86
87
88
89
91
92
93
94
7
95
97
98
99
103
104
139
140
8
141
142
149
153
154
155
156
9
158
161
10
11
28
29
46
47
112
113
130
131
21
22
52
53
105
106
136
137
115
147
30
114
45
129
165
166
167
83
82
27
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
24
25
31
44
48
50
51
61
62
80
81
108
109
134
135
145
146
164
144
42
6
18
26
40
41
90
102
110
124
49
59
73
84
133
143
157
168
13
100
101
150
151
159
160
A0
A1
A10
A11
A12
A13
A2
A3
A4
A5
A6
A7
A8
A9
BA0
BA1
CAS#
CKE0
CKE1
CLK1
CLK2
CLK3
DQ0
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ4
DQ40
DQ41
DQ42
DQ43
DQ46
DQ47
DQ48
DQ49
DQ5
DQ50
DQ51
DQ53
DQ56
DQ57
DQ58
DQ59
DQ6
DQ60
DQ63
DQ7
DQ8
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
RAS#
REGE
S0#
S1#
S2#
S3#
SA0
SA1
SA2
SMBCLK
SMBDATA
WE#
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
WP
NC11
NC12
NC13
NC14
NC15
NC16
NC17
DQ52
CLK0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
DQ9
DQ44
DQ45
DQ54
DQ55
DQ61
DQ62
A
A
A A
82801AA , Part 1
possible to ICH0.
as close as
as possible to ICH0.
Place C172 as close
Place R189
For Test/Debug
Don’t Stuff R181A
INTEL CORPORATION
0.5
ICH0, PART 1
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic REV
11 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
HL4
RESV2PD
HL9
HL6
RESV0PU
HL3
HL7
HL10
IHCOMP_PU
HL2
HL1
HL8
RESV1PU
HL5
HL0
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD13
AD14
AD3
AD12
AD11
AD9
AD7
AD5
AD6
AD4
AD2
AD10
AD20
AD16
AD8
AD19
AD15
AD21
AD1
AD17
AD0
AD18
C_BE#0
C_BE#1
C_BE#2
C_BE#3
A20M# 4,29
CPUSLP# 4,29
FERR# 4,29
IGNNE# 4,29
INTR 4,29
NMI 4,29
SMI# 4,29
STPCLK# 4,29
RCIN# 14,29
A20GATE 14,29
INIT# 4,13,29
HLSTB 8
HLSTB# 8
PIRQ#A 15,23,29
PIRQ#B 15,29
PIRQ#C 15,29
IRQ14 16,29
IRQ15 16,29
APICCLK_ICH 6
APICD1 4,29
APICD0 4,29
SERIRQ 14,29
PREQ#0 15,29
PREQ#1 29
PREQ#2 29
PREQ#3 23,29
PGNT#0 15,29
PGNT#1 29
PGNT#2 29
PGNT#3 23,29
PIRQ#D 15,29
PCLK_0/ICH6FRAME#
15,23,29 DEVSEL#
15,23,29 IRDY#
15,23,29 TRDY#15,23,29 STOP#15,23,29 PCIRST#7,13,14,15,16,23 PLOCK#15,29 PAR
15,23 SERR#15,23,29 PCI_PME#
15,23
PCPCI_REQ#A
29
REQ#B/GPIO129 GNT#B/GPIO17
29
AD[31:0]15,23
C_BE#[3:0]15,23
HL[10:0] 8
HUBREF 8
VCC1_8
VCC3_3
VCC1_8
VCC3_3
0.1UF
C302A
R182A
40
1%
U14A
CPU
HUB I/F
PCI
PART 1
PC/PCI
82801AA
INTERRUPTS
PCI
J13
E5
B15
F13G2
G4
E4
C2
C1
B1
D4
C3
A4
B4
C5
C6
F2
B5
E7
A6
B6
D7
B8
A7
A8
B7
C9
F3
D8
C7
F4
F5
E1
E2
D1
D3
C16
E16
C17
E12
D2
B2
A3
D6
D9
F15
B3
A13
C13
A12
C12
P5
R5
D17
E17
J14
F17
G16
J15
K16
K17
L17
G17
H17
B17
E15
E14
A2
P11
N14
B16
A9
C14
J5
D10
A10
B10
C10
B9
K1
A15
A14
B13
B12
D12
N6
P4
A11
B11
F16
R4
A1
F14
D5
A17
C4
G13
H14
K14
G15
L15
H16
J16
E3
A5
E6
G5
P6
T7
U10
R13
T16
M14
C11
C8
N5
N13
E13
R2
J10
K10
G14
K15
G3
H8
J8
K8
H9
J9
K9
H10
D16
M17
H15
J17
HUBREF
VCC3_3_13
A20GATE
A20M#AD0
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD2
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD3
AD30
AD31
AD4
AD5
AD6
AD7
AD8
AD9
APICCLK
APICD0
APICD1
CPUSLP#
C_BE#0
C_BE#1
C_BE#2
C_BE#3
DEVSEL#
FERR#
FRAME#
GNT#0
GNT#1
GNT#2
GNT#3
GNT#A/GPIO16
GNT#B/GPIO17
HL0
HL1
HL10
HL2
HL3
HL4
HL5
HL6
HL7
HLSTB
HLSTB#
IGNNE#
INIT#
INTR
IRDY#
IRQ14
IRQ15
NMI
PAR
PCICLK
PCIRST#
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
PLOCK#
PME#
RCIN#
REQ#0
REQ#1
REQ#2
REQ#3
REQ#A/GPIO0
REQ#B/GPIO1
RESV[0]
RESV[1]
RESV[2]
SERIRQ
SERR#
SMI#
STOP#
STPCLK#
TRDY#
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6
VCC1_8_7
VCC3_3_1
VCC3_3_11
VCC3_3_12
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_15
VCC3_3_16
VCC3_3_17
VSS1
VSS10
VSS11
VSS12
VSS13
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VCC3_3_14
HCOMP
HL8
HL9
R174A
8.2K
R175A
8.2K
R181A
0K
A
A
A A
82801AA , Part 2
Minimize Stub Length
to Jumpers
3vdc Lithium
equivalent to
Rayovac BR2325
Socketed
JP18A Strap
Speaker
IN
IN
OUT
OUT
JP17A Strap
No Reboot on 2nd watchdog timeout
Reboot on 2nd watchdog timeout
AC_SDOUT
Force CPU freq. strap to safe mode (1111)
Use CPU freq. strap se t ting i n ICH/ 0 r egis t e r.
JP20A Config.
1 - 2
2 - 3 Normal
Clear CMOS
INTEL CORPORATION
0.5
82801AA, PART 2
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic REV
12 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
VBATC
VBATC_DLY
JP13_PD
JP14_PU
R_VBIAS
JP24_PD
ICH_SPKR
AC_SDOUT
VBAT
VRTC
RTCX1
RTCRST#
RTCRST#
VBIAS
SLP_S5#
RTCX2
ICH5VREF
PDA2
SDA0
SDA2
PDA1
SDA1
PDA0
PDD11
PDD4
PDD7
PDD10
PDD14
PDD8
PDD6
PDD12
PDD1
PDD13
PDD0
PDD3
PDD5
PDD9
PDD2
PDD15
SDD2
SDD15
SDD11
SDD9
SDD13
SDD10
SDD14
SDD4
SDD5
SDD3
SDD1
SDD0
SDD7
SDD6
SDD8
SDD12
THERM#29 SLP_S3#25,28
PWROK24,25,28 PWRBTN#
27
ICH_RI#
19
RSMRST#
24,28
SUS_STAT#
24
SMBDATA
10,21,24,29
SMBCLK
10,21,24,29
SMBALERT#29
INTRUDER#
29
ICH_CLK146USBCLK6ICH_3V666
AC_RST#
22 AC_SYNC
22
AC_BITCLK
22 AC_SDOUT22 AC_SDIN022,29 AC_SDIN122,29 ICH_SPKR27
LPC_SMI#14,29 LPC_PME#
14,29
GPIO7
15,29 GPIO12
29 GPIO1329 GPIO2129 GPIO2229
GPIO23_FPLED27 GPIO26_FPLED27 GPIO2724 GPIO2824
LAD0/FWH013,14 LAD1/FWH113,14 LAD2/FWH213,14 LAD3/FWH313,14 LFRAME#/FWH413,14 LDRQ#014 LDRQ#129
USBP1P
16
USBP1N
16
USBP0P16 USBP0N16
OC#016
PDCS#1 16
SDCS#1 16
PDCS#3 16
SDCS#3 16
PDA[2:0] 16
SDA[2:0] 16
PDREQ 16
SDREQ 16
PDDACK# 16
SDDACK# 16
PDIOR# 16
SDIOR# 16
PDIOW# 16
SDIOW# 16
PIORDY 16
SIORDY 16
PDD[15:0] 16
SDD[15:0] 16
VCC3_3SBY
VCC3_3
VCC5VCC3_3
VCC3_3SBY
VCC3SBY
Y3A
32.768KHZ
1 2
CR11A
BAT17
AC
JP17A
JP18A
0.1UF
C294A
1.0UF
C290A
R187A
10K
R209A
10K
+
X3
0.047UF
C347A
R219A
8.2K
R202A
1K
R197A
10M
JP20A
12
3
CR14A
BAT17
A C
R216A
1K
1.0UF
C349A
R206A
1K
CR13A
BAT17
A C
18PF
C293A
12PF
C366A
U14B
IDE
SYSTEM
AC97
GPIO
LPC
USB
PART 2
INTEL 82801AA (ICH)
C15
R3
T1
U1
P3
T2
T3
U6
U2
A16
N4
L2
B14
D13
D15
K4
M5
L5
D11
E11
E9
J4
R6
U5
T5
T4
T6
N3
U4
M3
M4
R12
T12
P12
N12
U13
R10
N9
T8
P8
T9
P9
T10
P10
R9
U9
R8
U8
R7
U7
P7
N7
U12
U11
R11
T11
N11
M2
J3
L3
F1
H1
H3
H4
M16
M15
L13
L14
L16
P15
R16
P14
T15
U17
R15
R17
P16
T17
U16
U15
R14
P13
T13
U14
T14
M13
P17
N16
N15
N17
K3
K2
J2
J1
U3
D14
N2
P1
P2
R1
H2
G1
L1
N1
L4
M1
5VREF
AC_BITCLK
AC_RST#
AC_SDIN0
AC_SDIN1/GPIO9
AC_SDOUT
AC_SYNC
CLK14
CLK48
CLK66
GPIO12
GPIO13
GPIO21
GPIO22
GPIO23
GPIO26
GPIO27
GPIO28
GPIO5
GPIO6
GPIO7
INTRUDER#/GPIO10
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ#0
LDRQ#1/GPIO8
LFRAME#/FWH4
OC#0
OC#1
PDA0
PDA1
PDA2
PDCS#1
PDCS#3
PDD0
PDD1
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDDACK#
PDDREQ
PDIOR#
PDIOW#
PIORDY
PWRBTN#
PWROK
RI#
RSMRST#
RTCRST#
RTCX1
RTCX2
SDA0
SDA1
SDA2
SDCS#1
SDCS#3
SDD0
SDD1
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDDACK#
SDDREQ
SDIOR#
SDIOW#
SIORDY
SLP_S3/GPIO24
SLP_S5
SMBCLK
SMBDATA
SPKR
THRM#
USBP0N
USBP0P
USBP1N
USBP1P
VBIAS
VCCRTC
VCCSUS1
VCCSUS2
SUSSTAT#/GPIO25
SMBALERT#/GPIO11
+
2.2UF
C364A
12
12PF
C346A
R85
10K
R203
10K
R220A
10M
R173A
1K
A
A
A A
with the exception of the Boot Block.
in this configruation Write Protection is register based
Notes:
VPP and WP# are tied to 3.3v
Distribute close to each power pin.
RP64A for
Test/Debug
FirmWare Hub (82802AB) Socket
NOTE: This is a Socketed Implementation
JP21A CONFIG
IN
OUT Unlocked
Locked Default
INTEL CORPORATION
0.5
FIRMWARE HUB (FWH)
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic REV
13 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
FWH_ID0
FGPI2_PD
WPROT
R_VPP
FWH_ID3
TBLK_LCK
FWH_ID1
IC_PD
FWH_ID2
FGPI4_PD
FGPI3_PD
PCLK_66
PCIRST#7,11,14,15,16,23
INIT# 4,11,29
LAD2/FWH2 12,14
LAD0/FWH0 12,14
LAD1/FWH1 12,14
LAD3/FWH3 12,14
LFRAME#/FWH4 12,14
S66DETECT16 P66DETECT16
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
JP21A
0.1UF
C211A
R218A 0K
R223A
4.7K
0.1UF
C36A
0.1UF
C353A
0.1UF
C259A
0.1UF
C361A
X4A 40PIN_TSOP_SKT
1
3
4
5
6
8
2
9
10
11
12
13
14
19
20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
7
15
16
17
18
NC1
NC3
NC4
NC5
NC6
NC8
IC
CLK
VCC10
VPP
RST#
NC13
NC14
WP#
TBL# ID3
ID2
ID1
ID0
FWH0
FWH1
FWH2
FWH3
GND29
GND30
VCC31
RFU32
RFU33
RFU34
RFU35
RFU36
INIT#
FWH4
VCCA
GNDA
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
R222A
4.7K
RP64A
0K
1
2
3
45
6
7
8
RP63A
8.2K
1
2
3
45
6
7
8
0.1UF
C355A
A
A
A A
Pulldown on SYSOPT for IO
address of 0 x 02E
Super I/O
Decoupling
Place near
VREF pin
Place 1 0.1UF cap near each power pin
Test/Debug Header
Unused GPIOs
INTEL CORPORATION
0.5
SUPER I/O
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic
Schematics
REV.
14 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
PDR6
PDR5
PDR4
PDR2
PDR1
PDR0
PDR7
PDR3
SIO_GP43
SIO_GP21
SIO_GP22
SIO_GP61
SYSOPT
SIO_GP60
SUSSTAT_PU
PAR_INIT# 18
SLCTIN# 18
SLCT# 18
PE 18
BUSY 18
ACK# 18
ERROR# 18
ALF# 18
STROBE# 18
PWM2 27
PWM1 27
LPC_SMI# 12,29
TACH2 27
TACH1 27
MIDI_IN 20
MIDI_OUT 20
J1BUTTON1 20
J1BUTTON2 20
J2BUTTON1 20
J2BUTTON2 20
JOY1X 20
JOY1Y 20
JOY2X 20
KEYLOCK# 27
JOY2Y 20
LAD3/FWH312,13 LAD2/FWH212,13 LAD1/FWH112,13 LAD0/FWH012,13 LDRQ#012 PCIRST#
7,11,13,15,16,23
LPC_PME#12,29 SERIRQ11,29 PCLK_16
KDAT19 KCLK19 MDAT19 MCLK19 RCIN#11,29A20GATE11,29
RXD#019 TXD019 DSR#019 RTS#019 CTS#0
19 DTR#019 RI#0
19 DCD#019
RXD#119 TXD119 DSR#119 RTS#119 CTS#119 DTR#119 RI#119 DCD#119
DRVDEN#120 DRVDEN#020 MTR#020 DS#020 DIR#20 STEP#
20 WDATA#20 WGATE#20 HDSEL#20 INDEX#20 TRK#020 WRTPRT#
20 RDATA#20 DSKCHG#20
SIO_CLK146
IRRX
27 IRTX27
PDR[7:0] 18
LFRAME#/FWH412,13 VCC3_3 VCC5
VCC3_3 VCC5 VCC3_3
R183A
4.7K
470PF
C371A
470PF
C356A
R180A
4.7K
J23A
5
1
32
4
6
0.1UF
C297A
0.1UF
C229A
0.1UF
C323A
+
2.2UF
C99A
12
0.1UF
C287A
0.1UF
C246A
SERIAL PORT 1
SERIAL PORT 2
FDC I/F
LPC I/F
INFRARED I/ F
CLOCKS
KYBD/MSE I/F
PARALLEL POR T I/F
SIO
LPC47B27X
U15A
64
80
82
40
79
6
19
88
99
91
94
8
1
2
5
4
86
97
89
100
81
55
54
28
7
31
60
76
32
33
34
35
36
37
38
39
41
42
43
46
47
50
51
52
48
49
12
13
66
61
62
63
57
56
20
21
22
23
25
24
26
59
58
3
29 68
69
70
71
72
73
74
75
78
17
16
90
92
87
98
84
95
30
77
67
9
83
14
85
96
53
65
93
10
11
15
44
45
18
27
A20GATE
ACK#
ALF#
AVSS
BUSY
CLKI32
CLOCKI
CTS1#
CTS2#
DCD1#
DCD2#
DIR#
DRVDEN0
DRVDEN1
DS0#
DSKCHG#
DSR1#
DSR2#
DTR1#
DTR2#
ERROR#
FAN1/GP33
FAN2/GP32
FDC_PP/DDRC/GP43
GND1
GND2
GND3
GND4
GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
GP15/J1Y
GP16/J2X
GP17/J2Y
GP20/P17
GP21/P16
GP22/P12
GP25/MIDI_IN
GP26/MIDI_OUT
GP27/IO_SMI#
GP30/FAN_TACH2
GP31/FAN_TACH1
GP60/LED1
GP61/LED2
HDSEL#
INDEX#
INIT#
IRRX2/GP34
IRTX2/GP35
KBDRST
KCLK
KDAT
LAD0
LAD1
LAD2
LAD3
LDRQ#
LFRAME#
LRESET#
MCLK
MDAT
MTR0#
PCI_CLK PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
PME#
RDATA#
RI1#
RI2#
RTS1#
RTS2#
RXD1
RXD2_IRRX
SERIRQ
SLCT#
SLCTIN#
STEP#
STROBE#
TRK0#
TXD1
TXD2_IRTX
VCC1
VCC2
VCC3
WDATA#
WGATE#
WRTPRT#
VREF
GP24/SYSOPT
VTR
LPCPD#
A
A
A A
(DEV Ah)
PCI Connector 0
INTEL CORPORATION
0.5
PCI Connector
Sheet:
Last Revision Date:
Electronic Classroom Student Computing Station Ref. Schematic REV
15 of 33
CHANDLER, AZ 85226
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
AD2
AD26
AD28
AD30
AD13
AD20
AD4
AD0
AD9
R_AD16
AD16
AD15
AD11
AD22
AD24
AD18
AD6
AD31
AD29
AD27
AD25
AD23
AD21
AD19
AD17
AD14
AD12
AD10
AD8
AD7
AD5
AD3
AD1
C_BE#2
C_BE#3
C_BE#1
AD16 11,23
C_BE#0 11,23
PTMS 29
PTDI 29
PIRQ#A 11,23,29
PIRQ#C 11,29
PCIRST# 7,11,13,14,16,23
PGNT#0 11,29
FRAME# 11,23,29
TRDY# 11,23,29
STOP# 11,23,29
SDONEP1 29
SBOP1 29
PAR 11,23
PU1_REQ64# 29
PCI_PME# 11,23
PU1_ACK64#
29
PIRQ#B
11,29 PIRQ#D
11,29
PCLK_2
6
PREQ#0
11,29
IRDY#11,23,29
DEVSEL#11,23,29
PLOCK#
11,29 PERR#
23
SERR#
11,23,29
AD[31:0]
11,23
C_BE#[3:0]
11,23
AD[31:0] 11,23
VCC12-
VCC3_3SBY
VCC12
VCC3_3
VCC5
VCC3_3
VCC5
R168A
100
key
J17A
PCI3_CON
A2
A21
A27
A33
A39
A45
B25
B31
B36
B43
A53
B54
A5
A8
A10
A16
B5
B6
A59
A61
A62
B59
B61
B62
B19
B1
B60
A58B58
B48 A47B47 A46
B45 A44
A32B32 A31
B30
A57
A29B29 A28
B27
A25
B24 A23B23 A22
B21
B56
A20B20
A55B55 A54
B53
B52
A49
A52
B44
B33
B26
B16
A9
B37
A34
A12
A13
A18
A24
A30
A35
A37
A42
A48
B3
B12
B13
B15
B17
B22
B34
B38
B46
B49
A56
B57
B28
A17
A26
A6
B7 A7
B8
B35
B39
A43
B40
A19
B9
B11
B2
B4 A4
A3
A1
B18
A60
A11
A14
B10
B14 A15
A41
A40
B42
A38
A36
B41
A
A
A A
For Host side 80-conductor Cable Detection:
Populate R96A and R221A, Depopulate C187A
For Drive sid e 80-conductor Cable Detection:
Populate C187A, Depopulate R96A and R221A
ATA33/66 IDE CONNECTORS
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
0.1
ULTRA ATA/33 IDE CONNECTORS
16 of 33
For Host side 80-conductor Cable Detection:
Populate R95A and R94A, Depopulate C186A
For Drive sid e 80-conductor Cable Detection:
Populate C186A, Depopulate R95A and R94A
Electronic Classroom Student Computing Station Ref. Schematic
APPLIED COMPUTING PRODUCTS DIVISION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
PRI_PD1
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
R_RSTP#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDA2
PDA1
PDA0 R_P66DET R_S66DET
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
PRI_SD1
R_RSTS#
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
SDA2
SDA0
SDA1
P66DETECT 13
PDCS#3 12
PDA[2:0]12
PDREQ12 PDIOW#12 PDIOR#12 PIORDY12 PDDACK#12 IRQ14
11,29
PDCS#112 IDEACTP#27
PDD[15:0]12
PCIRST#7,11,13,14,15,23
S66DETECT 13
SDCS#3 12
SDA[2:0]12
SDREQ12 SDIOW#12 SDIOR#12 SIORDY12 SDDACK#12 IRQ1511,29
SDCS#112 IDEACTS#27
SDD[15:0]12
PCIRST_BUF#16 PCIRST_BUF#
16
PCIRST_BUF# 16
VCC5
VCC3_3 VCC3_3
VCC5
R94A
15K
SN74LVC07A
U11C
65
714
OA
GND VCC
R138A
10K
J15A
PRIMARY
IDE CON N.
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
4
5 6
7 8
9
1 2
4039
R140A
33
R101A
470
R133A
1K
R135A
5.6K
0.047UF
C187A
R221A
15K
R96A
0K
0.047UF
C186A
R137A
10K
R132A
470
R141A
8.2K
R100A
1K
R134A
5.6K
R95A
0K
R139A
33
J12A
SECONDARY
IDE CON N.
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
4
5 6
7 8
9
1 2
4039
A
A
A A
Do Not Stuff
2 - USB Stacked
possible to connector.
Place CAPs as close as
Place R211A, R214A, C358A, and C357A
within 1" of I C H 0
Place R204A, R205A, C348A, and C359A
within 1" of I C H 0
USB Connectors
Do Not Stuff
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
0.1
USB CONNECTORS
17 of 33
Electronic Classroom Student Computing Station Ref. Schematic
APPLIED COMPUTING PRODUCTS DIVISION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
USBD1P
USBD1N
USBV1
USBV0
USBG1
R_USBP0P USBD0P
USBG0
R_USBP0N
USBV5
USBD0N
AC97_OC#22
OC#012 USBP0N12
USBP0P12
USBP1N12
USBP1P12
AC97_USB+22
AC97_USB-22
VCC3_3 VCC5
2.5A
F3A
POLYSWITCH RUSB250
1 2
R147A
330K
A
R149A
0K
R148A
0K
USB-CON2
J3A
1
8
2
3
4
5
6
7
9
10
11
12
VCC0
GND1
DATA0-
DATA0+
GND0
VCC1
DATA1-
DATA1+
GND
GND
GND
GND
R72A
470K
R214A
15
R12A
15K R63A
15K
R201A
560K
R211A
15
R14A
15K
R11A
15K
R204A
15 R205A
15
R146A
0K
+
68UF
C202A
12
0.1UF
C12A
47PF
C359A
.001UF
C124A
+
68UF
C201A
12
470PF
C14A
470PF
C15A
47PF
C358A
0.1UF
C9A
47PF
C8A
47PF
C16A
47PF
C13A
47PF
C357A
47PF
C348A
47PF
C98A
L11A
1 2
L10A
1 2
L23A
1 2
L9A
1 2
R15A
0K
R13A
0K
A
A
A A
Parallel Port Header
NOTE: J5A is pinned out for IDC (Flow
Through) ribbon cable connector.
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
0.5
PARALLEL PORT HEADER
18 of 33
Electronic Classroom Student Computing Station Ref. Schematic
APPLIED COMPUTING PRODUCTS DIVISION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
R_SLCTIN#
R_PARINIT#
R_ALF#
R_STROBE#
R_PDR1
R_PDR2
R_PDR3
R_PDR4
R_PDR5
R_PDR6
R_PDR7
R_PDR0
PARV5
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
ERROR#14
SLCTIN#14 PAR_INIT#14 ALF#14
STROBE#14
ACK#14
BUSY14
PE14SLCT#
14
PDR[7:0]14
VCC5
180PF
C95A
180PF
C91A
RP27A
33
1
2
3
4 5
6
7
8
180PF
C196A
180PF
C192A
R224A
2.2K
J5A
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
3 4
5 6
7 8
9
180PF
C190A
180PF
C193A 180PF
C194A
180PF
C197A
180PF
C96A
180PF
C94A
180PF
C97A 180PF
C189A
180PF
C89A 180PF
C88A
180PF
C92A
180PF
C90A
180PF
C93A
RP28A
2.2K
1
2
3
4 5
6
7
8
RP16A
33
1
2
3
4 5
6
7
8
RP15A
33
1
2
3
4 5
6
7
8
1N4148
CR1A
A C
RP14A
2.2K
1
2
3
4 5
6
7
8
RP13A
2.2K
1
2
3
4 5
6
7
8
RP17A
2.2K
1
2
3
4 5
6
7
8
A
A
A A
Serial Port/COM Headers
Place Close to Header
Place Close to Header
COM1 and COM2 are 2x5 pin
Headers for a cabled port.
2nd COM Header Option
If not populated at all, remove CR14
and short RI#0_C to RI# C R
NOTE: If Wa k e fro m S 3 on
Serial Mode m is no t supported
do not stuff CR14A and Q2A.
NOTE: J19A and J21A are pinned out
for IDC (Flow Through) ribbon cable
connector.
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
0.5
SERIAL PORT/ COM HEADERS
19 of 33
Electronic Classroom Student Computing Station Ref. Schematic
APPLIED COMPUTING PRODUCTS DIVISION
5000 W CHANDLER BLVD. CH6-236
CHANDLER, AZ 85226
DCD#0_C
RXD#0_C
TXD#0_C
DTR#0_C
RI#0_C
RTS#0_C
DSR#0_C
CTS#0_C
ICHRI#_C
RXD#1_C
DSR#1_C
TXD#1_C
DTR#1_C
RTS#1_C
DCD#1_C
CTS#1_C
RI#1_C
RI#_CR_C
ICH_RI#12
DCD#014 RXD#014 DSR#014 DTR#014 TXD014 CTS#014 RTS#014 RI#0
14
DCD#114 RXD#114 DSR#114 DTR#114 TXD114 CTS#114 RTS#114 RI#114
VCC5
VCC12-VCC12
VCC3_3SBY
VCC5
VCC12- VCC12
100PF
C310A
1.0UF
C374A
R229A
47K
R230A
10K
100PF
C314A
100PF
C315A
100PF
C309A
100PF
C311A
100PF
C326A
100PF
C312A 100PF
C316A
GD75232
U16A
19
18
17
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
16
20
RY0
RY1
RY2
DA1
RY3
DA2
RY4
GND
VCC12
RA0
RA1
RA2
DY0
DY1
RA3
DY2
RA4
VCC-12
DA0
VCC
100PF
C329A
100PF
C328A 100PF
C327A
100PF
C325A
100PF
C369A 100PF
C368A
100PF
C330A
GD75232
U17A
19
18
17
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
16
20
RY0
RY1
RY2
DA1
RY3
DA2
RY4
GND
VCC12
RA0
RA1
RA2
DY0
DY1
RA3
DY2
RA4
VCC-12
DA0
VCC
R227A
47K
J21A
COM1 HEADER
1
10
2
3
5 6
7 8
9
4
2N7002LT1
Q10A
G
DS
BAT54C
CR15A
1
2
3
100PF
C313A
J19A
COM2 HEADER
1
10
2
3
5 6
7 8
9
4
A
A
A A
VCC5
KEYBOARD/MOUSE PORTS FLOPPY DISK HEADER
GAME PORT HEADER
NOTE: J7A is pinned out for IDC (Flow
Through) ribbon cable connector.
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
KEYBOARD/MOUSE PORTS, FLOPPY DISK HEADER, GAME
PORT HEADER
20 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
R_JOY1X
PS2V5_F
R_MIDIIN
PS2_PD
R_JOY2X
PS2GND
R_JOY2Y
L_MCLK
R_JOY1Y
R_MIDIOUT
L_MDAT
L_KCLK
L_KDAT
PS2V5
JOY1X 14
JOY1Y 14
JOY2Y 14
JOY2X 14
J1BUTTON1 14
J1BUTTON2 14
J2BUTTON2 14
J2BUTTON1 14
MIDI_OUT14
MIDI_IN14
DRVDEN#014
DRVDEN#114 INDEX#14 MTR#014
DS#014
DIR#14 STEP#14 WDATA#14 WGATE#14 TRK#014 WRTPRT#14 RDATA#14 HDSEL#14 DSKCHG#14
KDAT14
KCLK
14
MDAT14
MCLK14
VCC5
VCC5
VCC5
VCC5
0.1UF
C1A
470PF
C5A
470PF
C4A
L4A
1 2
47PF
C179A
470PF
C2A
L2A
1 2
47PF
C182A
L6A
1 2
J14A
1
10 1112 1314 1516 1718 19
2
20 2122 2324 2526 2728 29
3
30 3132 3334
456 78 9
J7A
1
10 1112 1314 1516
234 56 78 9
0.01UF
C195A
0.01UF
C191A
R179A
47
RP31A
1K
1
2
3
4 5
6
7
8
0.01UF
C199A
R143A
1K
L3A
1 2
L7A
1 2
470PF
C176A
470PF
C177A
L5A
1 2
1.25A
F2A
1 2
47PF
C178A
0.01UF
C198A
R88A
47
PS/2 KybdPS/2 Mse
J1A
STACKED PS2 CONNECTOR
1
2
3
4
5
6
7
8
9
10
11
12
17
16
15
14
13
47PF
C79A
R178A
4.7K
L1A
1 2
RP29A
2.2K
1
2
3
4 5
6
7
8
470PF
C3A
R89A
4.7K
RP1A
4.7K
1
2
3
4 5
6
7
8
RP30A
1K
1
2
3
4 5
6
7
8
A
A
A A
BLM31A700 S is ra t e d at
70Ohms at 100MHz
Do Not Populate
5V to 3.3V Translation / Isolation
Place R66A,R67A,&
R69A Close to VGA
Connector
VGA Connector
Do Not Stuff C331 and C332
Do Not Stuff C333 and C334
Video Connectors
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
VIDEO CONNECTORS
21 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
5VHSYNC
5VHSYNC
5VVSYNC
QSSCL
L_VSYNC
L_BLUE
L_HSYNC
5VDDCDA
L_RED
FUSE_5
MON2PU
MONOPU
QS4_3V
5VDDCDA
L_GREEN
5VDDCCL
5VVSYNC
CRT5V_F
5VDDCCL
QSSDA
SMBCLK 10,12,24,29
3VDDCDA93VDDCCL9CRT_HSYNC9CRT_VSYNC9
CK_SMBDATA6CK_SMBCLK6
VID_RED9
VID_GREEN9
VID_BLUE9
SMBDATA 10,12,24,29
VCC5
VCC5
VCC5
VCC5
VCC1_8
VCC1_8
VCC1_8
CR4A
AC
QST3384
U6A
123
20
16
15
1011 98 6
3
4 5
18 19
13
2
22
24
14
17
21
7
12
BEA# 2B5
2B4
2B2
2B1
1B51A5 1B41A4 1B3
1A1
1A2 1B2
2A3 2B3
BEB#
1B1
2A5
VCC
2A1
2A2
2A4
1A3
GND
BAT54S
CR10A
3
2
1
2.5A
F1A
1 2
BAT54S
CR9A
3
2
1
BAT54S
CR5A
3
2
1
15
510
6111
J6A
7
6
1
11
2
12
8
3
13
9
4
14
10
5
15
BAT54S
CR6A
3
2
1
BAT54S
CR8A
3
2
1
R119A
0K
R67A
75
1%
R120A
0K
R59A
2.2K
R71A
0K
R64A
0K
R66A
75
1%
R69A
75
1%
R65A
1K
R58A
2.2K
R115A
4.7K
3.3PF
C111A
R74A
1K
RP34A
2.2K
1
2
3
4 5
6
7
8
3.3PF
C106A
3.3PF
C103A
3.3PF
C105A
3.3PF
C109A
10PF
C208A
10PF
C116A
3.3PF
C119A
3.3PF
C104A
0.1UF
C227A
3.3PF
C122A
10PF
C112A
3.3PF
C102A
3.3PF
C100A
10PF
C101A
L19A
BLM11B750S
1 2
L12A
1 2
L20A
BLM11B750S
1 2
L21A
BLM11B750S
1 2
A
A
A A
AUDIO RISER
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
AC’97 RISER CONNECTOR
22 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
AC97_OC# 16
AC97_USB+ 16
AC97_USB- 16
AC_SYNC 12
AC_SDIN1 12,29
AC_SDIN0 12,29
AC_BITCLK 12
AC97SPKR
27
AC_SDOUT12 AC_RST#12
VCC3_3 VCC5VCC12
VCC12- VCC5
VCC3_3SBY
AC’97_RISER
AMR_CONNECTOR
J18A
KEY
KEY
KEY
KEY
B9
B15 A15
B11
A7B7
A23B23
B18
A21
A19
B21
B19
B17 A17
B1 A1
B2
A14
A16
A18
A20
A22
B8
B10
B12
B16
B20
B22
A6
A9
A12
B3 A2
B4
B5
B13
B14
A3
A4
A5
A13
B6
A10
A11
A8
+12V
+3.3VD +3VDUAL/3VSBY
+5VD
+5VDUAL/5VSBY-12V
AC97_BITCLKAC97_MSTRCLK
AC97_RESET#
AC97_SDATA_IN0
AC97_SDATA_IN1
AC97_SDATA_IN2
AC97_SDATA_IN3
AC97_SDATA_OUT AC97_SYNC
AUDIO_MUTE# AUDIO_PWRDWN
GND[0]
GND[10]
GND[11]
GND[12]
GND[13]
GND[14]
GND[1]
GND[2]
GND[3]
GND[4]
GND[5]
GND[6]
GND[7]
GND[8]
GND[9]
MONO_OUT/PC_BEEP MONO_PHONE
RESV[1]
RESV[2]
RESV[3]
RESV[4]
RESV[5]
RESV[6]
RESV[7]
S/P_DIF_IN
PRIMARY_DN#
USB+
USB-
USB_OC
A
A
A A
LAN
Do Not Stuff
Close to Ball A10
Place C68A/C255A
LAN Decoupling
Pins Close to 82559.
Distribute aroung Power
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
23 of 33
LAN
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
AD28
FLD5_PD
AD24
AD29
EEDI
EESK
AD16
RBIAS100
AD20
AD21
C_BE#2
LANAPWR
RBIAS10
AD11
AD7
C_BE#0
LANCLKRUN
AD1
AD3
R_LANIDS
AD17
AD4
AD6
FLD6_PD
LAN_TEST
AD30
EEDO
AD0
AD5
AD18
AD22
LAN_XTAL1
AD15
AD27
VIO
AD19
AD23
AD26
AD31
AD9
AD8
LAN_XTAL2
AD10
AD13
AD2
C_BE#1
AD12
AD14
AD25
C_BE#3 EECS
FRAME#11,15,29 IRDY#11,15,29 TRDY#11,15,29 DEVSEL#11,15,29 STOP#11,15,29 PAR11,15 PIRQ#A11,15,29 PERR#15 SERR#11,15,29 AD2011,15 PREQ#311,29 PGNT#3
11,29 PCIRST#7,11,13,14,15,16 PCLK_56
LAN_RST#24
L_SMBCLK24 L_SMBD24
LAN_ISOLATE#24
AD[31:0]11,15
C_BE#[3:0]11,15
RDN 24
TDN 24
RDP 24
SPEEDLED 24
ACTLED 24
TDP 24
LILED 24
PCI_PME# 11,15
VCC5
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY VCC3_3SBY VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
U18A
93C46
7
6
5
1
2
4
3
8
NC2
NC1
GND
EECS
EESK
EEDO
EEDI
VCC
R153A
100
25MHZ
Y2A
1 2
R163A
619
R162A
619
R154A
62K
R155A
619
R152A
4.7K
R156A
549
R159A
4.7K
5%
R164A
3K
0.1UF
C334A
0.1UF
C180A
+
4.7UF
C68A
12
+
4.7UF
C255A
12 0.1UF
C184A
0.1UF
C257A
0.1UF
C261A
U13A
82559
A1
H4
P14
L8
D9
P1
J4
A14
G4
C11
N7
M7
N2
M1
M2
M3
L1
L2
K1
E3
D1
D2
P6
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
P5
A8
B8
N5
M5
P4
N4
P3
N3
A9
M4
L3
F3
C4
G1
C8
C5
H3
P7
J13
J12
N13
M12
M11
P10
N10
M10
P9
K14
L14
L13
L12
M14
M13
N14
P13
N9
F14
F13
F12
G12
H14
H13
H12
J14
M8
M9
F2
J3
A4
H2
F1
B9
A12
J1
J2
A6
B14
E14
E13
C3
C2
A2
B10
A10
C9
B11
H1
D14
C14
C13
A13
D13
B12
G3
G13
K13
N8
P12
A3
A7
E1
K3
N6
P2
A11
E12
J8
J9
J10
J11
K4
K5
K6
K7
K8
K9
G5
K10
K11
L4
L5
L9
L10
G6
H5
H6
H7
H8
J5
J6
J7
G2
G14
K12
P8
N12
B3
B7
E2
K2
M6
N1
C10
D4
E8
E9
E10
E11
F4
F5
F6
F7
F8
F9
D5
F10
F11
G7
G8
G9
G10
G11
H9
H10
H11
D6
L6
L11
D7
D8
D11
E4
E5
E6
E7
N11
P11
C12
B13
D12
D10
L7
NC1
NC2
NC3
NC4
NC5
NC6
NC8
NC9
NC10
ACTLED
AD0
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD2
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD3
AD30
AD31
AD4
AD5
AD6
AD7
AD8
AD9
ALTRST#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
CLK
CLKRUN#
CSTSCHG
DEVSEL#
EECS
FLA0/PCIMODE#
FLA1/AUXPWR
FLA10/MRING#
FLA11/MINT
FLA12/MCNTSM#
FLA13/EEDI
FLA14/EEDO
FLA15/EESK
FLA16
FLA2
FLA3
FLA4
FLA5
FLA6
FLA7
FLA8/IOCHRDY
FLA9/MRST
FLCS#
FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7
FLOE#
FLWE#
FRAME#
GNT#
IDSEL
INTA#
IRDY#
ISOLATE#
LILED
PAR
PERR#
PME#
RBIAS10
RDN
RDP
REQ#
RST#
SERR#
SMBALRT#
SMBCLK
SMBD
SPEEDLED
STOP#
TCK
TDN
TDP
TEST
TEXEC
TO
TRDY#
VCCPL[0]
VCCPL[1]
VCCPL[2]
VCCPL[3]
VCCPP[0]
VCCPP[1]
VCCPP[2]
VCCPP[3]
VCCPP[4]
VCCPP[5]
VCCPT
VCC[0]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[1]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VIO
VSSPL[0]
VSSPL[1]
VSSPL[2]
VSSPL[3]
VSSPP[0]
VSSPP[1]
VSSPP[2]
VSSPP[3]
VSSPP[4]
VSSPP[5]
VSSPT
VSS[0]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[1]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[2]
VSS[30]
VSS[31]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
X1
X2
VREF
RBIAS100
TI
NC11
NC7
22PF
C269A
22PF
C331A
0.1UF
C265A
0.1UF
C165A
A
A
A A
use plane for this signal
Note: Chassis Ground,
Note: This circuit is for debug purpose only.
LAN
Do Not Stuff
Note: Chassis Ground,
use plane for this signal
Place Termination near 82559
Default Config:
Do Not Stuff
Do Not Stuff
For EST Testing
Select JP8A/JP9A
ICH0 1-2 Default
ICH 2-3
Do Not Stuff R198A LAN DISABLE - JP10A
NORMAL
DISABLE 1-2
2-3 Default
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
LAN
24 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
ACT_CR
RJMAG_CONN
JP9_SMBD
JP8_SMBC
RJ45_PD
RJ78_PD
RXC_PD
TXC_PD
JP7_PU
RDC
LI_CR ACTLED
LILED
SPEEDLED
TDC
RD_PDTD_PD
JP11_PU
JP12_PU
LAN_RST# 23
L_SMBD 23
L_SMBCLK 23
TDP23 TDN23 RDP
23 RDN
23
RSMRST#12,28
SMBCLK10,12,21,29
GPIO27
12
SMBDATA
10,12,21,29
GPIO2812
LILED
23
ACTLED23 SPEEDLED
23
LAN_ISOLATE# 23
SUS_STAT#12
PWROK
12,25,28
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
JP7A JP12A
JP8A
12
3
JP11A
JP10A
12
3
RJ-45
J9A
RJMAG
17
18
10
12
9
7
5
6
3
4
15
16
13
14
1
2
11
8
SHLD1
SHLD2
TD+
TD-
RD+
RD-
RJ-4
RJ-5
RJ-7
RJ-8
LA1
LC1
LA2
LC2
TXC
RXC
TDC
RDC
JP9A
12
3
R145A
330
R108A
330
R215A
4.7K
R186A
4.7K
R161A
50
R110A
75 R106A
75 R109A
75
R150A
0K
R151A
0K
R107A
75
R160A
50
R157A
50
R112A
330
R111A
330
R144A
330
0.1UF
C212A
470PF-1500V
C210A
0.1UF
C268A
R158A
50
0.1UF
C213A
0.1UF
C266A
R198A
0K
R210A
0K
A
A
A A
Voltage Regulators
VCC 2.5 VOLTAGE REGULATOR
VTT 1.5V VOLTAGE REGULATOR
Place C260A at the
Regulator
the Regulator
VCC 1.8 VOLTAGE REGULATOR
Do Not Populate
Place C76A at
VCC 3.3VSB Regulator
VCC 3.3V Standby VOLTAGE SWITCH
This generates 3.3V Standby Power which is
SN74LVC07A has 5V input and output tolerance.
by VR4 below) in S3/S4/S5.
the ATX supply in S0/S1, and 3.3VSB (generate d
on in S0,S1,S3,S4,&S5. It passes 3.3V from
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
VOLTAGE REGULATORS
25 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
V_GQ6
PLANE_CTL1
VR1_ADJ VR5_ADJ
PCTL_IN
PLANE_CTL0
SLP_S3#
12,28
PWROK
12,24,28
VCC5SBY
VCC5SBY
VCC12
VCC3_3 V3SB VCC3_3SBY
VCC3_3 VTT1_5
VCC2_5
VCC5
VCC1_8
VCC3_3VCC5SBY V3SB
VCC3_3SBY
U4A
74LS132
1
23
714
A
BY
GND VCC
+
1200uF
C375A
12
+
1200uF
C173A
12
R57A
240
1%
R87A
10K
R54A
130
1%
R55A
301
1%
R56A
240
1%
R61A
4.7K
R83A
0K
VR3A
LT1587ADJ
32
1
VIN VOUT
ADJ
MMBT3904LT1
Q7A
B
CE
1
32
NDS356AP
Q5A
G
DS
NDS356AP
Q6A
G
DS
CR2A
1N5822
A C
VR5A
LT1587-1_5
32
1
VIN VOUT
ADJ
0.1UF
C65A
SI4410DY
Q8A
8
7
6
54
3
2
1
SI4410DY
Q9A
8
7
6
54
3
2
1
VR2A
LT1587ADJ
32
1
VIN VOUT
ADJ
1.0UF
C57A
1.0UF
C43A
+
100UF
C76A
12
+
22UF
C71A
12
+
100UF
C270A
12
+
22UF
C74A
12
+
100UF
C159A
12
+
100UF
C59A
12
U5A
SN74LVC07A
1 2
14
7
+
47UF
C174A
12
+
47UF
C75A
12
+
100UF
C225A
12
VR4A
LT1117-3_3
1
3 2
GND
IN OUT
A
A
A A
VID Override Jumpers
Close to FETs
Place CAPs
Do Not Stuff C147A
go on the motherboard.
If your VR IC does not incorporate these, they must
Processor Voltage Regulator
The LTC1753 incorporates internal pull-ups on VID[4:0].
Refer to VR supplier for layout guildlines.
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
VRM 8.4
26 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
R_VID2
R_VID0
OUTEN
5VIN
IMAX
FAULT#_PU
G1
G2
L_VCCVIDR_VCCVID
SS_PD
VRCOMP_PD
R_VRCOMP
PV12
VID0
VID1
VID2
VID3 R_VID3
VFB_PD
R_VID1
VRM_PWRGD 28
VID[3:0]
3
VCC5 VCC12
VCC3_3 VCC5
VCCVID
L8A
1.0UH-6.8A
+
2700UF
C31A
12
SI4410DY
Q4A
4
1
2
3
8
7
6
5
G1
S1
S2
S3
D1
D2
D3
D4 SI4410DY
Q2A
4
1
2
3
8
7
6
5
G1
S1
S2
S3
D1
D2
D3
D4
R22A
5.1
R33A
220
R19A 20
+
2700UF
C128A
12
JP4A
JP3A
JP2A
R18A
5.6K
150PF
C18A
0.1UF
C147A
R20A
2.7K
R17A
10K
220PF
C35A
+
2700UF
C54A
12
SI4410DY
Q1A
4
1
2
3
8
7
6
5
G1
S1
S2
S3
D1
D2
D3
D4
SI4410DY
Q3A
4
1
2
3
8
7
6
5
G1
S1
S2
S3
D1
D2
D3
D4
L14A
0.8UH-20A
0.1UF
C19A
+
1200UF
C29A
12
+
2700UF
C58A
12
0.1UF
C22A
+
1200UF
C26A
12
+
1200UF
C30A
12
+
1200UF
C7A
12
1.0UF
C25A
1.0UF
C21A
0.01UF
C20A
+
10UF
C27A
12
0.01UF
C17A
1.0UF
C24A
R16A
8.2K
RP4A
0K
1
2
3
4 5
6
7
8
JP5A
+
2700UF
C28A
12
VR1A
LTC1753
6
9
4
3
5
2
10
14
15
16
17
18
19 7
13
12
20
1
8
11
SENSE
SS
SGND
GND
VCC
PVCC
COMP
VID4
VID3
VID2
VID1
VID0
OUTEN IMAX
PWRGD
FAULT#
G1
G2
IFB
VFB
A
A
A A
KEY
KEY
KEY
KEY
KEY
SPEAKER
KEYLOCK
H.D. LED
POWER SW.
INFRARED
SYSTEM
No stuff.
For test only
POWER LED
KEY
VCC5
For test only
No stuff.
On-Board LED indicates the
ICH has internal pullup and debounce on PWRBTN#
For Debug Only
FAN Headers
Speaker Circuit
Standby Well i s on to p reve n t
Hot-Swapping Memory.
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
SYSTEM
27 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
SPKR_NEG
R_SPKRINSPKR_IN
R_IRTX
FP_PD
PWRLED
GP26LED
GP23LED
V3SBLED
PBTN_IN
SPKR_Q1GSPKR
IDE_ACTIVE
GPIO26_FPLED 12
GPIO23_FPLED12
PWM214
TACH114
PWM114
IRRX14
IRTX14
TACH214
ICH_SPKR
12
PWRBTN#12
KEYLOCK#
14
AC97SPKR22
IDEACTP#16
IDEACTS#16
VCC3_3 VCC5
VCC3_3SBY VCC3_3SBY
VCC5
VCC3_3SBY VCC3_3SBY
VCC12
VCC3_3
VCC3_3
VCC3_3SBY
VCC12
VCC3_3VCC5
VCC3_3
VCC3_3SBY
VCC12
VCC12
VCC5
R97A
330
CR3A
21
R98A
330
U5B
SN74LVC07A
3 4
14
7
SN74LVC07A
U11A
21
714
OA
GND VCC
U5C
SN74LVC07A
56 14
7
SW2
1 2
3 4
R235A
2.2K
R188A
330
R93A
10K
R225A
0K
R226A
1M
R228A
470
J25A
1
2
3
J27A
1
2
3
0.1UF
C378A
R233A
68
JP22A
1
23
J24A
1
2
3
2N3904
Q11A
B
CE
1
32
SP1A
+
2
1
NEG
POS
J26A
1
2
3
RP62A
4.7K
1
2
3
4 5
6
7
8
R213A
4.7K
R212A
82
R231A
10K
0.1UF
C23A
R234A
68
+
10UF
C292A
16V
12
0.1UF
C363A
0.1UF
C365A
0.1UF
C362A
470PF
C258A
CR12A
21
0.1UF
C279A
R217A
100K
SN74LVC07A
U11B
43
714
OA
GND VCC
R136A
10K
1.0UF
C370A
470PF
C373A
R172A
4.7K
R232A
220
FNT_PNL_CONN
J20A
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
3
4
5
6
7
8
9
A
A
A A
Do Not Stuff
For Debug Only
For Debug Only
Do Not Stuff
SYSTEM
Power Connector and Reset Control
Schmit t T r igger Logic
using a 22msec delay
Resume Reset Circuitry
Power Good Circuit
ITP RESET CIRCUIT - FOR DEBUG ONLY
Reset Button
220 Ohm Pull-up to 3.3V is on VRM Sheet
SN74LVC06A has
5V input tolerance
74LVC14A i s 5V input
tolerant
SN74LVC06A is 5V output
tolerance
Do not stuff R84A - For debug only.
If R84A is populated, R86A must
be de-populated.
CLOCK POWERDOWN CONTROL
Place JP23A near front panal header (J20)
Do not stuff
Do not stuff
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
SYSTEM: POWER CONNECTOR AND RESET CONTROL
28 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
ST69
5VPSON
ST23
V3RSMRST
PWROK#
DBRST
APOK_ST
CK_PWRD
DBRPOK
DBRPOK_DLY
SLP_S3#
ATX_PWOK
DBRPOK
RST_PD
PWRGOOD 4
PWROK 12,24,25
RSMRST# 12,24
SLP_S3#
12,25
VRM_PWRGD26
DBRESET#4
CK_PWRDN# 6,25
VCC3_3SBY
VCC5SBY VCC5
VCC5-
VCC3_3VCC12
VCC5SBY
VCC3_3SBY
VCC3_3SBY
VCC5SBY
VCC3_3SBY VCC2_5
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY VCC3_3SBY VCC3_3SBY
VCC3_3SBY
VCC12-
JP23A 21
R92A
0K
1.0UF
C183A
U3A
SN74LVC06A
714
1 2
GND VCC
AO
R142A
22K
R86A
8.2K
U3B
SN74LVC06A
714
3 4
GND VCC
AO
U10A
SN74LVC08A
147
3
1
2
R196A
1M
R200A
4.7K
0.01UF
C45A
R90A
0K
R24A
22
R91A
0K
R99A
240
U10B
SN74LVC08A
147
6
4
5
U12D
74LVC14A
9 8
714
+
10UF
C185A
12
R62A
4.7K
U12A
74LVC14A
1 2
714
ATX
J4A
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
3_3V11
-12V
GND13
PS_0N
GND15
GND16
GND17
-5V
5V19
5V20
3_3V1
3_3V2
GND3
5V4
GND5
5V6
GND7
PW_OK
5VSB
12V
R199A
1M
R10A
330
U12C
74LVC14A
5 6
714
U12B
74LVC14A
3 4
714
1.0UF
C264A
R84A
0K
U3C
SN74LVC06A
714
5 6
GND VCC
AO
U4B
74LS132
4
56
714
A
BY
GND VCC
SW1
1 2
3 4
A
A
A A
PULL-UP RESISTORS AND UNUSED GATES
CPU
PCI BUS 82801AA
For Future Compatibility Upgrade
UNUSED GATES
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
PULL-UP RESISTORS AND UNUSED GATES
29 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
VCMOS4
APICD04,11
APICD14,11
SERR#11,15,23 PLOCK#11,15 STOP#
11,15,23
DEVSEL#
11,15,23
TRDY#
11,15,23 IRDY#11,15,23
FRAME#11,15,23
PIRQ#D11,15 PIRQ#C11,15 PIRQ#B11,15 PIRQ#A11,15,23 PREQ#311,23 PREQ#211 PREQ#111 PREQ#011,15
PGNT#0
11,15
PGNT#111 PGNT#211 PGNT#311,23
SDONEP1
15
SBOP115
PTDI15 PTMS15
PU1_ACK64#15
PU1_REQ64#15
SMBDATA
10,12,21,24
SMBCLK
10,12,21,24
SMBALERT#12
INTRUDER#12
LDRQ#112 GPIO1212 GPIO1312
RCIN#11,14A20GATE11,14
THERM#12PCPCI_REQ#A11
REQ#B/GPIO111
SERIRQ
11,14GNT#B/GPIO1711
GPIO712 LPC_SMI#12,14
LPC_PME#12,14 GPIO2112
GPIO2212
IRQ1411,16 IRQ15
11,16
A20M#4,11 IGNNE#
4,11 INIT#4,11,13 INTR
4,11
NMI
4,11
CPUSLP#4,11
STPCLK#4,11 SMI#4,11
FERR#4,11
RTTCTRL
4
SLEWCTRL4
AC_SDIN0
12,22
AC_SDIN112,22
VCMOS
VCC5
VCC5
VCC3_3
VCC5
VCC5 VCC3_3
VCC5
VCC3_3 VCC3_3SBY VCC3_3SBY
VCC5SBY
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
VCC5
RP49A
330
1
2
3
4 5
6
7
8
RP50A
330
1
2
3
4 5
6
7
8
RP60A
4.7K
1
2
3
4 5
6
7
8
RP61A
4.7K
1
2
3
4 5
6
7
8
RESISTOR PAK
9 PULLUP/DOWN
2.7K
RP59A
4
5
6
7
8
9
2
3
10
1
R70A
110
1%
R6A
150
RESISTOR PAK
9 PULLUP/DOWN
RP45A
2.7K
4
5
6
7
8
9
2
3
10
1
R73A
150
R68A
110
1%
RP47A
5.6K
1
2
3
4 5
6
7
8
RP51A
2.7K
1
2
3
4 5
6
7
8
RP58A
5.6K
1
2
3
4 5
6
7
8
RP57A
8.2K
1
2
3
4 5
6
7
8
SN74LVC07A
U11F
1213
714
OA
GND VCC
SN74LVC07A
U11E
1011
714
OA
GND VCC
SN74LVC07A
U11D
89
714
OA
GND VCC
RP55A
8.2K
1
2
3
4 5
6
7
8
U12E
74LVC14A
11 10
714
U10C
SN74LVC08A
147
8
9
10
U3F
SN74LVC06A
714
13 12
GND VCC
AO
U12F
74LVC14A
13 12
714
U3E
SN74LVC06A
714
11 10
GND VCC
AO
U5E
SN74LVC07A
11 10
14
7
R166A
10K
U4D
74LS132
12
13 11
714
A
BY
GND VCC
U4C
74LS132
9
10 8
714
A
BY
GND VCC
U10D
SN74LVC08A
147
11
12
13
R170A
10K
U5F
SN74LVC07A
13 12
14
7
RP53A
8.2K
1
2
3
4 5
6
7
8
RP54A
8.2K
1
2
3
4 5
6
7
8
R169
330
RP52A
8.2K
1
2
3
4 5
6
7
8
RP56A
8.2K
1
2
3
4 5
6
7
8
U3D
SN74LVC06A
714
9 8
GND VCC
AO
U5D
SN74LVC07A
9 8
14
7
A
A
A A
0603 Package p l aced within 200mils of VTT Termination R-packs
0805 Package
1206 Packages
370-pin Socket Decoupling
Bulk Decoupling
High Frequency Decoupling
VCCVID Decoupli ng
VTT Decoupling
One Capacitor for every 2 R-Packs
Place in 370 PGA Socket Cavity
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
370-PIN SOCKET DECOUPLING
30 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
VCCVID
VCCVID
VTT1_5
+
22 UF
C384A
12
1.0UF
C142A
1.0UF
C113A
1.0UF
C118A
0.1UF
C34A
0.1UF
C33A
1.0UF
C120A
1.0UF
C121A
0.1UF
C133A
0.1UF
C32A
0.1UF
C11A
0.1UF
C129A
0.1UF
C218A
0.1UF
C157A
0.1UF
C150A
0.1UF
C144A
0.1UF
C221A
0.1UF
C205A
0.1UF
C219A
0.1UF
C220A
1.0UF
C108A
1.0UF
C141A
1.0UF
C143A
1.0UF
C134A
1.0UF
C132A
1.0UF
C137A
1.0UF
C138A
1.0UF
C151A
1.0UF
C154A
1.0UF
C156A
1.0UF
C148A
1.0UF
C135A
4.7UF
C125A
1.0UF
C149A
1.0UF
C145A
1.0UF
C107A
4.7UF
C110A
4.7UF
C117A
4.7UF
C136A
4.7UF
C152A
4.7UF
C126A
4.7UF
C146A
4.7UF
C153A
4.7UF
C115A
0.1UF
C42A
4.7UF
C140A
4.7UF
C155A
4.7UF
C139A
A
A
A A
Place 3 near System Memory Quadran t
and 3 near Display Cache Quadrant
82810 3.3V IO Decoupling:
82810 Decoupling
82810 Core Plane Decoupling:
Place 1 .1uF/.01uF pair in each corner,
if they fit.
DRAM, CHIPSET, and BULK POWER DECOUPLING
Distribute near the VCCSUS
power pins of the
82801AA
power pins of the
82801AA
Distribute near the 1.8V
if they fit.
and 2 on opposite sides close to component
Place 1 .1uF/.01uF pair in each corner,
82801AA 3.3V Plane Decoupling:
Distribute near DIMM0 Power Pins.
DIMM0 Decoupling:
82801AA De coupling
and 2 on opposite sides close to component
System Memory Decoupli n g Bulk Pow er Decoupli n g
3 VOLT Decoupling
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
DRAM, CHIPSET AND BULK POWER DECOUPLING
31 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
VCC1_8
VCC1_8
VCC3_3
VCC3_3SBY
VCC3_3
VCC12-
VCC3_3 VCC1_8 VCC3_3SBY
VCC3_3 VCC5 VCC5- VCC12
+
10UF
C44A
12
+
22UF
C162A
12
+
22UF
C84A
1 2
0.1UF
C172A
0.1UF
C340A
0.1UF
C318A
+
2.2UF
C372A
12
0.1UF
C322A
0.1UF
C127A
0.1UF
C338A
0.1UF
C240A
0.1UF
C339A
0.1UF
C285A
0.1UF
C250A
0.1UF
C78A
0.1UF
C80A
0.1UF
C81A
0.1UF
C283A
0.1UF
C354A
0.1UF
C163A
0.1UF
C381A
0.01UF
C305A
0.1UF
C67A
0.1UF
C130A
0.1UF
C239A
0.1UF
C382A
0.1UF
C215A
0.1UF
C181A
0.1UF
C175A
0.1UF
C248A
0.1UF
C254A
0.01UF
C308A
0.1UF
C350A
0.1UF
C278A
0.1UF
C288A
0.1UF
C171A
0.01UF
C242A
0.01UF
C233A
0.1UF
C234A
0.1UF
C343A
0.01UF
C164A
0.01UF
C131A
0.01UF
C214A
0.01UF
C237A
0.1UF
C263A
0.01UF
C289A
0.01UF
C41A
0.01UF
C304A
0.1UF
C341A
0.1UF
C245A
0.1UF
C260A
0.1UF
C303A
0.1UF
C333A
0.1UF
C160A
0.1UF
C291A
0.1UF
C298A
0.1UF
C352A
0.1UF
C319A
0.1UF
C256A
0.1UF
C320A
0.1UF
C376A
0.1UF
C10A
0.1UF
C296A
0.1UF
C295A
0.1UF
C307A
0.1UF
C324A
0.01UF
C332A
0.1UF
C345A
0.1UF
C83A
0.1UF
C82A
0.1UF
C317A
+
22UF
C70A
12
0.1UF
C360A
0.1UF
C86A
+
22UF
C69A
1 2
+
22UF
C85A
12
0.1UF
C66A
0.1UF
C72A
0.1UF
C87A
+
22UF
C62A
12
0.1UF C321A
0.1UF C367A
0.01UF
C380A
0.01UF
C383A
A
A
A A
PAGE
REVISION 0
REV.
Last Revision Date:
Sheet:
INTEL CORPORATION
REVISION HISTORY
32 of 33
Electronic Classroom Student Computing Station Ref. Schematic
0.5
5000 W CHANDLER BLVD. CH6-236
APPLIED COMPUTING PRODUCTS DIVISION
CHANDLER, AZ 85226
