January 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
1/17/05, v 1.2 Alliance Semiconductor 1 of 19
2.5V 1M × 32/36 Flow-through synchronous SRAM
AS7C251MFT32A
AS7C251MFT36A
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE
access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
-75 -85 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.5 10 ns
Maximum operating current 325 300 275 mA
Maximum standby current 130 130 130 mA
Maximum CMOS standby current (DC) 90 90 90 mA
A
[19:0]
20 18 20
20
Q0
Q1 1M × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers Input
registers
Power
down
DQ[a:d]
4
32/36
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
ZZ
LBO
OE
CLK CLK
32/36
32/36
2
2
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AS7C251MFT32A
AS7C251MFT36A
®
2.5V 32 Mb Synchronous SRAM products list1,2
1 Core Power Supply: VDD = 2.5V + 0.125V
2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V
PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM
NTD1-PL : Pipelined Burst Synchronous SRAM with NTDTM
NTD-FT : Flow-through Burst Synchronous SRAM with NTDTM
Org Part Number Mode Speed
2MX18 AS7C252MPFS18A PL-SCD 200/166/133 MHz
1MX32
AS7C251MPFS32A PL-SCD 200/166/133 MHz
1MX36 AS7C251MPFS36A PL-SCD 200/166/133 MHz
2MX18
AS7C252MPFD18A PL-DCD 200/166/133 MHz
1MX32
AS7C251MPFD32A PL-DCD 200/166/133 MHz
1MX36 AS7C251MPFD36A PL-DCD 200/166/133 MHz
2MX18 AS7C252MFT18A FT 7.5/8.5/10 ns
1MX32 AS7C251MFT32A FT 7.5/8.5/10 ns
1MX36
AS7C251MFT36A FT 7.5/8.5/10 ns
2MX18
AS7C252MNTD18A NTD-PL 200/166/133 MHz
1MX32
AS7C251MNTD32A NTD-PL 200/166/133 MHz
1MX36
AS7C251MNTD36A NTD-PL 200/166/133 MHz
2MX18
AS7C252MNTF18A NTD-FT 7.5/8.5/10 ns
1MX32
AS7C251MNTF32A NTD-FT 7.5/8.5/10 ns
1MX36
AS7C251MNTF36A NTD-FT 7.5/8.5/10 ns
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
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AS7C251MFT32A
AS7C251MFT36A
®
Pin assignment
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A
1
A0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
TQFP 14 x 20mm
A
NC/DQPc
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
NC
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
NC/DQPd
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
SS
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQPa/NC
V
DD
NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
®
AS7C251MFT32A
AS7C251MFT36A
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Functional description
The AS7C251MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized
as 1,048,576 words × 32 or 36 bits.
Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion.
Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst
advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
LBO
driven low, the device uses a linear count
sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C251MFT32A and AS7C251MFT36A family operates from a core 2.5V power supply. These devices are available in 100-pin
TQFP package.
TQFP capacitance
*Guaranteed not tested
TQFP thermal resistance
Parameter Symbol Test conditions Min Max Unit
Input capacitance CIN*VIN = 0V - 5 pF
I/O capacitance CI/O*VOUT = 0V - 7 pF
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
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AS7C251MFT32A
AS7C251MFT36A
®
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Pin I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
CE0 ISYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE1, CE2 ISYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.
ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
ADV I SYNC Advance. Asserted low to continue burst read/write.
GWE ISYNC
Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write
enable.
BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
BW[a,b,c,d] ISYNC
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,
the cycle is a read cycle.
OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
LBO ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect
®
AS7C251MFT32A
AS7C251MFT36A
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Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function GWE BWE BWa BWb BWc BWd
Write All Bytes LXXXXX
HLLLLL
Write Byte a HLLHHH
Write Byte c and d HLHHLL
Read HHXXXX
HLHHHH
Operation ZZ OE I/O Status
Snooze mode H X High-Z
Read L L Dout
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
1st Address 0 00 11 01 1
1st Address 0 00 11 01 1
2nd Address 0 10 01 11 0
2nd Address 0 11 01 10 0
3rd Address 1 01 10 00 1
3rd Address 1 01 10 00 1
4th Address 1 11 00 10 0
4th Address 1 11 00 11 0
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AS7C251MFT32A
AS7C251MFT36A
®
Synchronous truth table[4]
CE01
1 X = don’t care, L = low, H = high
CE1 CE2 ADSP ADSC ADV
WRITE
[2]
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE
HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
OE Address accessed CLK Operation DQ
HXXXLX X X NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q
L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z
L H L H L X L X External L to H Begin write D3
3 For write operation following a READ,
OE
must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD
®
AS7C251MFT32A
AS7C251MFT36A
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Absolute maximum ratings
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
may affect reliability.
Recommended operating conditions
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.3 +3.6 V
Input voltage relative to GND (input pins) VIN –0.3 VDD + 0.3 V
Input voltage relative to GND (I/O pins) VIN –0.3 VDDQ + 0.3 V
Power dissipation Pd–1.8W
Short circuit output current IOUT – 20 mA
Storage temperature Tstg –65 +150 oC
Temperature under bias Tbias –65 +135 oC
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 2.375 2.5 2.625 V
Supply voltage for I/O VDDQ 2.375 2.5 2.625 V
Ground supply Vss 0 0 0 V
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AS7C251MFT32A
AS7C251MFT36A
®
DC electrical characteristics
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter Sym Conditions Min Max Unit
Input leakage current†|ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 1.7* VDD+0.3 V
I/O pins 1.7* VDDQ+0.3 V
Input low (logic 0) voltage VIL
Address and control pins -0.3** 0.7 V
I/O pins -0.3** 0.7 V
Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V
Parameter Sym Conditions -75 -85 -10 Unit
Operating power supply current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
325 300 275
mA
Standby power supply current
ISB
All VIN ≤ 0.2V or >
V
DD
– 0.2V,
Deselected,
f = fMax, ZZ < VIL
130 130 130
ISB1 Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V 90 90 90
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V,
all VIN ≤ VIL or ≥ VIH 80 80 80
®
AS7C251MFT32A
AS7C251MFT36A
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Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter Sym
–75 –85 –10
Unit Notes1
1 See “Notes” on page 16.
Min Max Min Max Min Max
Cycle time tCYC 8.5–10–12– ns
Clock access time tCD –7.5–8.5– 10ns
Output enable low to data valid tOE –3.5–4.0–4.0ns
Clock high to output low Z tLZC 2.5 – 2.5 – 2.5 – ns 2,3,4
Data output invalid from clock high tOH 2.5 – 2.5 – 2.5 – ns 2
Output enable low to output low Z tLZOE 0–0–0–ns2,3,4
Output enable high to output high Z tHZOE - 3.5 – 4.0 – 4.0 ns 2,3,4
Clock high to output high Z tHZC - 4.0 – 5.0 – 5.0 ns 2,3,4
Output enable high to invalid output tOHOE 0–0–0–ns
Clock high pulse width tCH 2.5 – 3.0 – 3.0 – ns 5
Clock low pulse width tCL 2.5 – 3.0 – 3.0 – ns 5
Address setup to clock high tAS 2.0 – 2.0 – 2.0 – ns 6
Data setup to clock high tDS 2.0 – 2.0 – 2.0 – ns 6
Write setup to clock high tWS 2.0 – 2.0 – 2.0 – ns 6,7
Chip select setup to clock high tCSS 2.0 – 2.0 – 2.0 – ns 6,8
Address hold from clock high tAH 0.5 – 0.5 – 0.5 – ns 6
Data hold from clock high tDH 0.5 – 0.5 – 0.5 – ns 6
Write hold from clock high tWH 0.5 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock high tCSH 0.5 – 0.5 – 0.5 – ns 6,8
ADV setup to clock high tADVS 2.0 – 2.0 – 2.0 – ns 6
ADSP setup to clock high tADSPS 2.0 – 2.0 – 2.0 – ns 6
ADSC setup to clock high tADSCS 2.0 – 2.0 – 2.0 – ns 6
ADV hold from clock high tADVH 0.5 – 0.5 – 0.5 – ns 6
ADSP hold from clock high tADSPH 0.5 – 0.5 – 0.5 – ns 6
ADSC hold from clock high tADSCH 0.5 – 0.5 – 0.5 – ns 6
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > VIH ISB2 80 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SNOOZE current tZZI 2cycle
ZZ inactive to exit SNOOZE current tRZZI 0
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AS7C251MFT32A
AS7C251MFT36A
®
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
don’t careFalling inputRising input Undefined
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
t
CSS
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV inserts wait states
A2A1 A3
Dout
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
t
HZC
t
LZOE
t
CSH
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Burst
Read
Q(A 2Ý01
)
Read
Q(A3) DSEL
Burst
Read
Q(A 2Ý10
)
Suspend
Read
Q(A 2Ý10
)
Burst
Read
Q(A 2Ý11
)
Burst
Read
Q(A 3Ý01
)
Burst
Read
Q(A 3Ý10
)
Burst
Read
Q(A 3Ý11
)
t
OE
CE1
®
AS7C251MFT32A
AS7C251MFT36A
1/17/05, v 1.2 Alliance Semiconductor 12 of 19
Timing waveform of write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Din
t
CSH
t
ADVH
D(A2Ý01)
D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
t
CH
CE1
BW[a:d]
Read
Q(A1)
Suspend
Write
D(A1)
Read
Q(A2)
Suspend
Write
D(A 2
)
ADV
Burst
Write
D(A 2Ý01
)
Suspend
Write
D(A 2Ý01
)
ADV
Burst
Write
D(A 2Ý10
)
Write
D(A 3
)
Burst
Write
D(A 3Ý01
)
ADV
Burst
Write
D(A 2Ý11
)
ADV
Burst
Write
D(A 3Ý10
)
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AS7C251MFT32A
AS7C251MFT36A
®
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
BWE
CE0, CE2
ADV
OE
Din
Dout
t
CD
t
ADVH
t
LZOE
t
OE
t
LZC
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
Suspend
Read
Q(A1)
Read
Q(A1)
Suspend
Write
D(A 2
)
ADV
Burst
Read
Q(A 3Ý01
)
Suspend
Read
Q(A 3Ý11
)
ADV
Burst
Read
Q(A 3Ý10
)
ADV
Burst
Read
Q(A 3Ý11
)
Read
Q(A2)
Read
Q(A3)
BW[a:d]
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AS7C251MFT32A
AS7C251MFT36A
®
Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
Note: ADV is don’t care here.
t
CYC
t
CH
t
CL
t
ADSCH
CLK
ADSC
ADDRESS
A2
A1
t
ADSCS
A3 A4 A6
A5 A7 A8 A9
t
AH
t
AS
BWE t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
t
LZOE
t
OE
t
HZOE
Q(A1) Q(A2) Q(A3) Q(A4) Q(A9) Q(A10)
t
CD
t
OH
D(A6) D(A7)
D(A5)
t
DS
t
DH
OE
Dout
Din
READ
Q(A1)
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
WRITE
D(A5)
WRITE
D(A6)
WRITE
D(A7)
WRITE
D(A8)
READ
Q(A10)
CE1
A10
D(A8)
READ
Q(A9)
BW[a:d]
1/17/05, v 1.2 Alliance Semiconductor 15 of 19
AS7C251MFT32A
AS7C251MFT36A
®
Timing waveform of power down cycle
t
CYC
t
CH
t
CL
t
ADSPS
CLK
ADSP
ADDRESS A1
t
ADSPS
A2
BWE
t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
ADV
t
LZOE
t
OE
t
HZOE
Q(A1) Q(A2)
OE
Dout
Din
ADSC
t
HZC
t
PDS
Sleep
ZZ Setup Cycle
t
PUS
ZZ Recovery Cycle Normal Operation Mode
CE1
ZZ
Q(A2(
Ý
01))
BW[a:d]
READ
Q(A1)
READ
Q(A1Ý01)
READ
Q(A2)
READ
Q(A2Ý01)
State
t
ZZI
I
SB2
t
RZZI
I
supply
®
AS7C251MFT32A
AS7C251MFT36A
1/17/05, v 1.2 Alliance Semiconductor 16 of 19
AC test conditions
Notes
1 For test conditions, see “AC test conditions”, Figures A, B, and C.
2 This parameter is measured with output load condition in Figure C.
3 This parameter is sampled but not 100% tested.
4t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5t
CH is measured as high if above VIH, and tCL is measured as low if below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to
GWE
,
BWE
, and
BW[a:d].
8 Chip select refers to
CE0
,
CE1
, and
CE2
.
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+2.5V
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 2.5V. See Figure A.
• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.25V.
V
L
= V
DDQ
/2
Thevenin equivalent:
353
Ω/1538Ω
5 pF*
319
Ω/1667Ω
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+2.5V
1/17/05, v 1.2 Alliance Semiconductor 17 of 19
AS7C251MFT32A
AS7C251MFT36A
®
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.85 16.15
He 21.80 22.20
L0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
α
®
AS7C251MFT32A
AS7C251MFT36A
1/17/05, v 1.2 Alliance Semiconductor 18 of 19
Ordering information
Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MFT32A-85TQCN)
Part numbering guide
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 25 = 2.5V
3.Organization: 1M = 1M
4.Flow-through mode
5.Organization: 32 = x 32; 36 = x 36
6.Production version: A = First production version
7.Clock access time: [-75 = 7.5 ns;-85 = 8.5 ns; -10 = 10.0 ns]
8.Package type: TQ = TQFP
9.Operating temperature: C = commercial (
0
°
C to 70
°
C); I = industrial (
-40
°
C to 85
°
C)
10. N = Lead free part
Package & Width -75 -85 -10
TQFP x32 AS7C251MFT32A-75TQC AS7C251MFT32A-85TQC AS7C251MFT32A-10TQC
AS7C251MFT32A-75TQI AS7C251MFT32A-85TQI AS7C251MFT32A-10TQI
TQFP x36 AS7C251MFT36A-75TQC AS7C251MFT36A-85TQC AS7C251MFT36A-10TQC
AS7C251MFT36A-75TQI AS7C251MFT36A-85TQI AS7C251MFT36A-10TQI
AS7C 25 1M FT 32/36 A–XX TQ C/I X
12345678910
®
AS7C251MFT32A
AS7C251MFT36A
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C251MFT32A
AS7C251MFT36A
Document Version: v 1.2
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®
