LTC6252/LTC6253/LTC6254
1
625234fa
TYPICAL APPLICATION
DESCRIPTION
720MHz, 3.5mA Power
Effi cient Rail-to-Rail
I/O Op Amps
The LTC
®
6252/LTC6253/LTC6254 are single/dual/quad low
power, high speed unity gain stable rail-to-rail input/output
operational amplifi ers. On only 3.5mA of supply current
they feature a 720MHz gain-bandwidth product, 280V/µs
slew rate and a low 2.75nV/√Hz of input-referred noise.
The combination of high bandwidth, high slew rate, low
power consumption and low broadband noise makes the
LTC6252 family unique among rail-to-rail input/output op
amps with similar supply currents. They are ideal for lower
supply voltage high speed signal conditioning systems.
The LTC6252 family maintains high effi ciency performance
from supply voltage levels of 2.5V to 5.25V and is fully
specifi ed at supplies of 2.7V and 5.0V.
For applications that require power-down, the LTC6252
and the LTC6253 in MS10 offer a shutdown pin which
disables the amplifi er and reduces current consumption
to 42µA.
The LTC6252 family can be used as a plug-in replacement
for many commercially available op amps to reduce power
or to improve input/output range and performance.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES
APPLICATIONS
n Gain Bandwidth Product: 720MHz
n –3dB Frequency (AV = 1): 400MHz
n Low Quiescent Current: 3.5mA Max
n High Slew Rate: 280V/μs
n Input Common Mode Range Includes Both Rails
n Output Swings Rail-to-Rail
n Low Broadband Voltage Noise: 2.75nV/√Hz
n Power-Down Mode: 42A
n Fast Output Recovery
n Supply Voltage Range: 2.5V to 5.25V
n Input Offset Voltage: 350µV Max
n Large Output Current: 90mA
n CMRR: 105dB
n Open Loop Gain: 60V/mV
n Operating Temperature Range: –40°C to 125°C
n Single in 6-Pin TSOT-23
n Dual in MS8, 2mm ¥ 2mm DFN, 8-Pin TS0T-23, MS10
n Quad in MS16
n Low Voltage, High Frequency Signal Processing
n Driving A/D Converters
n Rail-to-Rail Buffer Amplifi ers
n Active Filters
n Battery Powered Equipment
5V Single-Supply 16-Bit ADC Driver LTC6253 Driving LTC2393-16
16-Bit ADC 5V Single-Supply
Performance
5V
0.1µF10µF
5V
5V
~2.08V
0.1µF10µF
SER/PAR
BYTESWAP
OB/2C
CS
RD
BUSY
PARALLEL
OR
SERIAL
INTERFACE
OGND
625234 TA01
IN–
IN+
3900pF
249 100
249 100
VIN
27.4mV TO
(3.5V + 27.4mV)
GND
RESETCNVST
PD
SAMPLE CLOCK
REFOUT
REFIN
AVP DVP
LTC2393-16
OVP
1.8V TO 5V
16 BIT
VCM
1µF10µF
2.5k2.5k143Ω
845Ω
4.7µF
–
+
½ LTC6253
5V
–
+
½ LTC6253
FREQUENCY (kHz)
0
AMPLITUDE (dBFS)
0
–80
–20
–40
–60
–100
–120
–140
–160 200 400100 300
624678 TA01b
500
fS = 1Msps
F1 = 20.111kHz
F1 AMPLITUDE
= –1.032dBFS
SNR = 93.28dB
THD = –100.50dB
SINAD = 92.53dB
SFDR = 104.7dB
F2 = –106.39dBc
F3 = –104.70dBc
F4 = –114.13dBc
F5 = –105.48dBc
f
S
= 1
Msps
F1
=
20
.
111kHz
F
1 AMPLITUDE
= –1.032dBF
S
S
NR = 93.28dB
T
HD = –100.50d
B
D =
92.5
3dB
S
FDR = 104.7d
B
F
2 = –106.39dBc
F
3 = –104.70dBc
F
4 = –114.1
3d
B
c
F5 =
–10
5.48
dBc
LTC6252/LTC6253/LTC6254
2
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ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6252CS6#TRMPBF LTC6252CS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6252IS6#TRMPBF LTC6252IS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6252HS6#TRMPBF LTC6252HS6#TRPBF LTFRW 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6253CDC#TRMPBF LTC6253CDC#TRPBF LFRZ 8-Lead (2mm ¥ 2mm) Plastic DFN 0°C to 70°C
LTC6253IDC#TRMPBF LTC6253IDC#TRPBF LFRZ 8-Lead (2mm ¥ 2mm) Plastic DFN –40°C to 85°C
LTC6253CMS8#PBF LTC6253CMS8#TRPBF LTFRX 8-Lead Plastic MSOP 0°C to 70°C
LTC6253IMS8#PBF LTC6253IMS8#TRPBF LTFRX 8-Lead Plastic MSOP –40°C to 85°C
LTC6253CTS8#TRMPBF LTC6253CTS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 0°C to 70°C
LTC6253ITS8#TRMPBF LTC6253ITS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 –40°C to 85°C
LTC6253HTS8#TRMPBF LTC6253HTS8#TRPBF LTFRY 8-Lead Plastic TSOT-23 –40°C to 125°C
Total Supply Voltage (V+ to V–) ................................ 5.5V
Input Current (+IN, –IN, SHDN) (Note 2) ..............±10mA
Output Current (Note 3) .....................................±100mA
Operating Temperature Range (Note 4).. –40°C to 125°C
Specifi ed Temperature Range (Note 5) .. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Junction Temperature ........................................... 150°C
Lead Temperature (Soldering, 10 sec)
(MSOP, TSOT Packages Only) ............................... 300°C
OUT 1
V– 2
+IN 3
6 V+
5 SHDN
4 –IN
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
+–
TJMAX = 150°C, qJA = 192°C/W (NOTE 9)
TOP VIEW
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
DC PACKAGE
8-LEAD (2mm s 2mm) PLASTIC DFN
9
4
1
2
36
5
7
8
+
–
+
–
TJMAX = 125°C, qJA = 102°C/W (NOTE 9)
EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB
1
2
3
4
OUT A
–IN A
+IN A
V–
8
7
6
5
V+
OUT B
–IN B
+IN B
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
+
–
+
–
TJMAX = 150°C, qJA = 163°C/W (NOTE 9)
1
2
3
4
5
OUT A
–IN A
+IN A
V–
SHDNA
10
9
8
7
6
V+
OUT B
–IN B
+IN B
SHDNB
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
+
–
+
–
TJMAX = 150°C, qJA = 160°C/W (NOTE 9)
OUT A 1
–IN A 2
+IN A 3
V– 4
8 V+
7 OUT B
6 –IN B
5 +IN B
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
+
–
+
–
TJMAX = 150°C, qJA = 195°C/W (NOTE 9)
1
2
3
4
5
6
7
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
16
15
14
13
12
11
10
9
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
+
–
+
–
+
–
+
–
TJMAX = 150°C, qJA = 125°C/W (NOTE 9)
(Note 1)
LTC6252/LTC6253/LTC6254
3
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(VS = 5V) The l denotes the specifi cations which apply across the
specifi ed temperature range, otherwise specifi cations are at TA = 25°C. For each amplifi er VS = 5V, 0V; VSHDN = 2V; VCM = VOUT = 2.5V,
unless otherwise noted.
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6253CMS#PBF LTC6253CMS#TRPBF LTFSB 10-Lead Plastic MSOP 0°C to 70°C
LTC6253IMS#PBF LTC6253IMS#TRPBF LTFSB 10-Lead Plastic MSOP –40°C to 85°C
LTC6254CMS#PBF LTC6254CMS#TRPBF 6254 16-Lead Plastic MSOP 0°C to 70°C
LTC6254IMS#PBF LTC6254IMS#TRPBF 6254 16-Lead Plastic MSOP –40°C to 85°C
LTC6254HMS#PBF LTC6254HMS#TRPBF 6254 16-Lead Plastic MSOP –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = Half Supply
l
–350
–1000
50 350
1000
µV
µV
VCM = V+ – 0.5V, NPN Mode
l
–2.2
–3.3
0.1 2.2
–3.3
mV
mV
DVOS Input Offset Voltage Match
(Channel-to-Channel) (Note 8)
VCM = Half Supply
l
–350
–550
50 350
550
µV
µV
VCM = V+ – 0.5V, NPN Mode
l
–2.75
–4
0.1 2.75
4
mV
mV
VOS TCInput Offset Voltage Drift l–3.5 µV/°C
IBInput Bias Current (Note 7) VCM = Half Supply
l
–0.65
–1.0
–0.1 0.65
1.0
µA
µA
VCM = V+ – 0.5V, NPN Mode
l
0.9
0.7
1.4 2.5
4.0
µA
µA
IOS Input Offset Current VCM = Half Supply
l
–0.3
–0.4
–0.03 0.3
0.4
µA
µA
VCM = V+ – 0.5V, NPN Mode
l
–0.3
–0.4
–0.03 0.3
0.4
µA
µA
enInput Noise Voltage Density f = 1MHz 2.75 nV/√Hz
Input 1/f Noise Voltage f = 0.1Hz to 10Hz 2 µVP-P
inInput Noise Current Density f = 1MHz 4 pA/√Hz
CIN Input Capacitance Differential Mode
Common Mode
2.5
0.8
pF
pF
RIN Input Resistance Differential Mode
Common Mode
7.2
3
kΩ
MΩ
AVOL Large Signal Voltage Gain RL = 1k to Half Supply (Note 10)
l
35
16
60 V/mV
V/mV
RL = 100Ω to Half Supply (Note 10)
l
5
2.4
13 V/mV
V/mV
CMRR Common Mode Rejection Ratio VCM = 0V to 3.5V
l
85
82
105 dB
dB
LTC6252/LTC6253/LTC6254
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCMR Input Common Mode Range l0V
SV
PSRR Power Supply Rejection Ratio VS = 2.5V to 5.25V
VCM = 1V l
68
63
70 dB
dB
Supply Voltage Range (Note 6) l2.5 5.25 V
VOL Output Swing Low (VOUT – V–) No Load
l
25 40
65
mV
mV
ISINK = 5mA
l
60 90
120
mV
mV
ISINK = 25mA
l
150 200
320
mV
mV
VOH Output Swing High (V+ – VOUT) No Load
l
65 100
120
mV
mV
ISOURCE = 5mA
l
115 170
210
mV
mV
ISOURCE = 25mA
l
270 330
450
mV
mV
ISC Output Short-Circuit Current Sourcing
l
–90 –40
–32
mA
mA
Sinking
l
60
40
100 mA
mA
ISSupply Current per Amplifi er VCM = Half Supply
l
3.3 3.5
4.8
mA
mA
VCM = V+ – 0.5V
l
4.25 4.85
5.9
mA
mA
ISD Disable Supply Current VSHDN = 0.8V
l
42 55
75
µA
µA
ISHDNL SHDN Pin Current Low VSHDN = 0.8V
l
–3
–4
–1.6 0
0
µA
µA
ISHDNH SHDN Pin Current High VSHDN = 2V
l
–300
–600
35 300
600
nA
nA
VLSHDN Pin Input Voltage Low l0.8 V
VHSHDN Pin Input Voltage High l2V
IOSD Output Leakage Current in Shutdown VSHDN = 0.8V, Output Shorted to Either
Supply
100 nA
tON Turn-On Time VSHDN = 0.8V to 2V 3.5 µs
tOFF Turn-Off Time VSHDN = 2V to 0.8V 2 µs
BW –3dB Closed Loop Bandwidth AV = 1, RL = 1k to Half Supply 400 MHz
GBW Gain-Bandwidth Product f = 4MHz, RL = 1k to Half Supply
l
450
320
720 MHz
MHz
tS, 0.1% Settling Time to 0.1% AV = 1, VO = 2V Step RL = 1k 36 ns
SR Slew Rate AV = –1, 4V Step (Note 11) 280 V/µs
FPBW Full Power Bandwidth VOUT = 4VP-P (Note 13) 9.5 MHz
(VS = 5V) The l denotes the specifi cations which apply across the
specifi ed temperature range, otherwise specifi cations are at TA = 25°C. For each amplifi er VS = 5V, 0V; VSHDN = 2V; VCM = VOUT = 2.5V,
unless otherwise noted.
LTC6252/LTC6253/LTC6254
5
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
HD2/HD3 Harmonic Distortion
RL = 1k to Half Supply
fC = 100kHz, VO = 2VP-P
fC = 1MHz, VO = 2VP-P
fC = 2.5MHz, VO = 2VP-P
fC = 4MHz, VO = 2VP-P
99/109
97/104
83/82
77/71
dBc
dBc
dBc
dBc
RL = 100Ω to Half Supply fC = 100kHz, VO = 2VP-P
fC = 1MHz, VO = 2VP-P
fC = 2.5MHz, VO = 2VP-P
fC = 4MHz, VO = 2VP-P
97/90
95/70
87/65
78/59
dBc
dBc
dBc
dBc
DGDifferential Gain (Note 14) AV = 2, RL = 150, VS = ±2.5V
AV = 1, RL = 1k, VS = ±2.5V
0.1
0.02
%
Dq Differential Phase (Note 14) AV = 2, RL = 150, VS = ±2.5V
AV = 1, RL = 1k, VS = ±2.5V
0.25
0.05
Deg
Crosstalk AV = –1, RL = 1k to Half Supply,
VOUT = 2VP-P, f = 2.5MHz
–96 dB
ELECTRICAL CHARACTERISTICS
(VS = 5V) The l denotes the specifi cations which apply across the
specifi ed temperature range, otherwise specifi cations are at TA = 25°C. For each amplifi er VS = 5V, 0V; VSHDN = 2V; VCM = VOUT = 2.5V,
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
(VS = 2.7V) The l denotes the specifi cations which apply across the
specifi ed temperature range, otherwise specifi cations are at TA = 25°C. For each amplifi er VS = 2.7V, 0V; VSHDN = 2V; VCM = VOUT =
1.35V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = Half Supply
l
400
0
700 1000
1400
µV
µV
VCM = V+ – 0.5V, NPN Mode
l
–1.1
–2.0
0.9 2.6
3.4
mV
mV
DVOS Input Offset Voltage Match
(Channel-to-Channel) (Note 8)
VCM = Half Supply
l
–350
–750
10 350
750
µV
µV
VCM = V+ – 0.5V, NPN Mode
l
–2.8
–4
0.1 2.8
4
mV
mV
VOS TCInput Offset Voltage Drift l2.75 µV/°C
IBInput Bias Current (Note 7) VCM = Half Supply
l
–850
–1300
225 300
700
nA
nA
VCM = V+ – 0.5V, NPN Mode
l
0.65
0
1.175 2
3.5
µA
µA
IOS Input Offset Current VCM = Half Supply
l
–350
–450
–100 350
450
nA
nA
VCM = V+ – 0.5V, NPN Mode
l
–350
–450
–30 350
450
nA
nA
enInput Noise Voltage Density f = 1MHz 2.9 nV/√Hz
Input 1/f Noise Voltage f = 0.1Hz to 10Hz 2 µVP-P
inInput Noise Current Density f = 1MHz 3.6 pA/√Hz
CIN Input Capacitance Differential Mode
Common Mode
2.5
0.8
pF
pF
RIN Input Resistance Differential Mode
Common Mode
7.2
3
kΩ
MΩ
AVOL Large Signal Voltage Gain RL = 1k to Half Supply
(Note 12) l
16.5
7
36 V/mV
V/mV
RL = 100Ω to Half Supply
(Note 12) l
2.3
1.8
6.9 V/mV
V/mV
LTC6252/LTC6253/LTC6254
6
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ELECTRICAL CHARACTERISTICS
(VS = 2.7V) The l denotes the specifi cations which apply across the
specifi ed temperature range, otherwise specifi cations are at TA = 25°C. For each amplifi er VS = 2.7V, 0V; VSHDN = 2V; VCM = VOUT =
1.35V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMRR Common Mode Rejection Ratio VCM = 0V to 1.2V
l
80
77
105 dB
dB
VCMR Input Common Mode Range l0V
SV
PSRR Power Supply Rejection Ratio VS = 2.5V to 5.25V
VCM = 1V l
68
63
70 dB
dB
Supply Voltage Range (Note 6) l2.5 5.25 V
VOL Output Swing Low (VOUT – V–) No Load
l
22 28
40
mV
mV
ISINK = 5mA
l
80 100
140
mV
mV
ISINK = 10mA
l
110 150
190
mV
mV
VOH Output Swing High (V+ – VOUT) No Load
l
55 75
95
mV
mV
ISOURCE = 5mA
l
125 150
200
mV
mV
ISOURCE = 10mA
l
165 200
275
mV
mV
ISC Short-Circuit Current Sourcing
l
–35 –20
–15
mA
mA
Sinking
l
20
17
40 mA
mA
ISSupply Current per Amplifi er VCM = Half Supply
l
2.9 3.5
4.5
mA
mA
VCM = V+ – 0.5V
l
3.7 4.6
5.5
mA
mA
ISD Disable Supply Current VSHDN = 0.8V
l
24 35
50
µA
µA
ISHDNLSHDN Pin Current Low VSHDN = 0.8V
l
–1
–1.5
–0.5 0
0
µA
µA
ISHDNHSHDN Pin Current High VSHDN = 2V
l
–300
–600
45 300
600
nA
nA
VLSHDN Pin Input Voltage l0.8 V
VHSHDN Pin Input Voltage l2.0 V
IOSD Output Leakage Current Magnitude in Shutdown VSHDN = 0.8V, Output Shorted to Either Supply 100 nA
tON Turn-On Time VSHDN = 0.8V to 2V 5 µs
tOFF Turn-Off Time VSHDN = 2V to 0.8V 2 µs
BW –3dB Closed Loop Bandwidth AV = 1, RL = 1k to Half Supply 350 MHz
GBW Gain-Bandwidth Product f = 4MHz, RL = 1k to Half Supply 630 MHz
tS, 0.1 Settling Time to 0.1% AV = +1, VO = 2V Step RL = 1k 34 ns
SR Slew Rate AV = –1, 2V Step (Note 11) 170 V/µs
FPBW Full Power Bandwidth VOUT = 2VP-P (Note 13) 8.5 MHz
Crosstalk AV = –1, RL = 1k to Half Supply,
VOUT = 2VP-P, f = 2.5MHz
96 dB
LTC6252/LTC6253/LTC6254
7
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes. If any of
the input or shutdown pins goes 300mV beyond either supply or the
differential input voltage exceeds 1.4V the input current should be limited
to less than 10mA. This parameter is guaranteed to meet specifi ed
performance through design and/or characterization. It is not production
tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output current is high. This
parameter is guaranteed to meet specifi ed performance through design
and/or characterization. It is not production tested.
Note 4: The LTC6252C/LTC6253C/LTC6254C and LTC6252I/LTC6253I/
LTC6254I are guaranteed functional over the temperature range of –40°C
to 85°C. The LTC6252H/LTC6253H/LTC6254H are guaranteed functional
over the temperature range of –40°C to 125°C.
Note 5: The LTC6252C/LTC6253C/LTC6254C are guaranteed to meet
specifi ed performance from 0°C to 70°C. The LTC6252C/LTC6253C/
LTC6254C are designed, characterized and expected to meet specifi ed
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. The LTC6252I/LTC6253I/LTC6254I are guaranteed
to meet specifi ed performance from –40°C to 85°C. The LTC6252H/
LTC6253H/LTC6254H are guaranteed to meet specifi ed performance from
–40°C to 125°C.
Note 6: Supply voltage range is guaranteed by power supply rejection ratio
test.
Note 7: The input bias current is the average of the average of the currents
at the positive and negative input pins.
Note 8: Matching parameters are the difference between amplifi ers A and
D and between B and C on the LTC6254; between the two amplifi ers on the
LTC6253.
Note 9: Thermal resistance varies with the amount of PC board metal
connected to the package. The specifi ed values are with short traces
connected to the leads with minimal metal area.
Note 10: The output voltage is varied from 0.5V to 4.5V during
measurement.
Note 11: Middle 2/3 of the output waveform is observed. RL = 1k to half
supply.
Note 12: The output voltage is varied from 0.5V to 2.2V during
measurement.
Note 13: FPBW is determined from distortion performance in a gain of +2
confi guration with HD2, HD3 < –40dBc as the criteria for a valid output.
Note 14: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set.
VOS Distribution, VCM = VS/2
(MS, PNP Stage)
VOS Distribution, VCM = VS/2
(TSOT-23, PNP Stage)
VOS Distribution, VCM = V+ – 0.5V
(MS, NPN Stage)
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
40
30
20
5
0
35
25
15
10
625234 G01
25015050–50–150–250
VS = 5V, 0V
VCM = 2.5V
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
40
15
5
20
25
35
30
10
0–150 –50
625234 G02
15050 250–250
VS = 5V, 0V
VCM = 2.5V
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
16
12
8
2
14
10
6
4
0–1200 400–400
625234 G03
1200 2000–2000
VS = 5V, 0V
VCM = 4.5V
LTC6252/LTC6253/LTC6254
8
625234fa
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Voltage vs Output Current Warm-Up Drift vs Time
Input Bias Current
vs Common Mode Voltage
Offset Voltage
vs Input Common Mode Voltage
VOS vs Temperature,
VS = 2.7V, 0V (MS, PNP Stage)
VOS Distribution, VCM = V+ – 0.5V
(TSOT-23, NPN Stage)
VOS vs Temperature,
VS = 2.7V, 0V (MS, NPN Stage)
VOS vs Temperature, VS = 5V, 0V
(MS, PNP Stage)
VOS vs Temperature, VS = 5V, 0V
(MS, NPN Stage)
INPUT COMMON MODE VOLTAGE (V)
0
OFFSET VOLTAGE (µV)
600
400
–200
0
–1600
200
–400
–600
–800
–1200
–1000
–1400
–1800
–2000 1.5 3.51 2.5 4.5
625234 G09
530.5 2 4
–55°C
VS = 5V, 0V
25°C
125°C
OUTPUT CURRENT (mA)
–100
OFFSET VOLTAGE (mV)
3.0
1.5
0.5
–1.0
1.0
2.5
2.0
0
–0.5
–1.5
–2.0
–2.5
–3.0 –75 25–25 75
625234 G10
1000–50 50
–55°C
25°C 125°C
VS = ±2.5V
TIME AFTER POWER-UP (sec)
0
CHANGE IN OFFSET VOLTAGE (µV)
20
10
15
5
020 10060 140
625234 G11
1608040 120
VS = ±2.5V
TA = 25°C
COMMON MODE VOLTAGE (V)
0
INPUT BIAS CURRENT (nA)
3000
2000
–3000
1000
0
–1000
–2000
–4000
–5000 1.5 3.51 2.5 4.5
625234 G12
530.5 2 4
–55°C
25°C
125°C
VS = 5V, 0V
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
18
12
14
10
4
16
8
6
2
0–1200
625234 G04
400 1200–400 2000–2000
VS = 5V, 0V
VCM = 4.5V
TEMPERATURE (°C)
VOLTAGE OFFSET (µV)
300
0
100
–100
–400
200
–200
–300
–500
–600 –15–35
625234 G05
5 25 65 85 105 125–55
VS = 5V, 0V
VCM = 2.5V
6 DEVICES
45
TEMPERATURE (°C)
VOLTAGE OFFSET (µV)
2000
1000
1500
500
–1000
0
–500
–1500
–2000
–2500 –15–35
625234 G06
5 25 65 85 105 125–55 45
VS = 5V, 0V
VCM = 4.5V
6 DEVICES
TEMPERATURE (°C)
VOLTAGE OFFSET (µV)
1200
1000
1100
800
900
700
600
500
400 –15–35
625234 G07
5 25 65 85 105 125–55 45
VS = 2.7V, 0V
VCM = 1.35V
6 DEVICES
TEMPERATURE (°C)
VOLTAGE OFFSET (µV)
3200
2200
2700
1700
1200
700
200
–1300
–800
–300
–1800 –15–35
625234 G08
5 25 65 85 105 125–55 45
VS = 2.7V, 0V
VCM = 2.2V
6 DEVICES
LTC6252/LTC6253/LTC6254
9
625234fa
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current Per Amplifi er
vs SHDN Pin Voltage
SHDN Pin Current
vs SHDN Pin Voltage
Input Noise Voltage and Noise
Current vs Frequency
Input Bias Current vs Temperature
Supply Current
vs Supply Voltage (Per Amplifi er)
0.1Hz to 10Hz Voltage Noise
TIME (1s/DIV)
0
VOLTAGE NOISE (500nV/DIV)
2000
1500
1000
500
0
–1000
–500
–1500
–2000 1739
624678 G14
1045628
TOTAL SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
5.0
4.5
4.0
3.5
3.0
1.5
1.0
2.5
2.0
0.5
013
625234 G16
452
–55°C
25°C
125°C
TEMPERATURE (°C)
–55
INPUT BIAS CURRENT (nA)
3000
2000
0
2500
500
1500
1000
–500 355–25 95
624678 G13
12565
VS = 5V, 0V
VCM = 4.5V
VCM = 2.5V
FREQUENCY (Hz)
1
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
1000
100
10
1.0
0.1
10 1k 100M10M
624678 G15
10k 100k 1M100
in, VCM = 4.5V
in, VCM = 2.5V
en, VCM = 4.5V
en, VCM = 2.5V
Minimum Supply Voltage,
VCM = VS/2 (PNP Operation)
Minimum Supply Voltage,
VCM = V+ – 0.5V (NPN Operation)
Supply Current vs Input Common
Mode Voltage (Per Amplifi er)
COMMON MODE VOLTAGE (V)
0.25 1.25
SUPPLY CURRENT (mA)
5
4
3
23.25
625234 G17
4.25 4.752.25
125°C
25°C
VS = 5V, 0V
AV = 1
–55°C
SHDN PIN VOLTAGE (V)
0
SUPPLY CURRENT (mA)
5.0
4.0
4.5
2.5
2.0
3.5
3.0
1.5
1.0
0.5
02.521.510.5 3.5
625234 G18
54 4.53
TA = 125°C
TA = 25°C
VS = 5V, 0V
VCM = 2.5V
TA = –55°C
SHDN PIN VOLTAGE (V)
0
SHDN PIN CURRENT (µA)
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
–2.75
–2.50
–2.25
–3.00 2.521.510.5 3.5
625234 G19
54 4.53
TA = 125°C
TA = 25°C
VS = 5V, 0V
TA = –55°C
TOTAL SUPPLY VOLTAGE (V)
2
OFFSET VOLTAGE (mV)
16
10
12
14
8
6
4
2
0
–2 2.5 3.5
625234 G20
5.5
125°C
25°C
–55°C
4 4.5 53
VS = 5V, 0V
TOTAL SUPPLY VOLTAGE (V)
2
OFFSET VOLTAGE (mV)
16
10
12
14
8
6
4
2
0
–4
–2
2.5 3.5
625234 G21
5.5
125°C
–55°C
4 4.5 53
25°C
VS = 5V, 0V
LTC6252/LTC6253/LTC6254
10
625234fa
TYPICAL PERFORMANCE CHARACTERISTICS
Open Loop Gain and Phase
vs Frequency
Gain vs Frequency (AV = 1)
Gain vs Frequency (AV = 2)
Gain Bandwidth and Phase
Margin vs Supply Voltage
Open Loop Gain
Output Short-Circuit Current
vs Supply Voltage
Open Loop Gain
Output Saturation Voltage
vs Load Current (Output Low)
Output Saturation Voltage
vs Load Current (Output High)
LOAD CURRENT (mA)
OUTPUT HIGH SATURATION VOLTAGE (V)
625234 G22
10
1
0.1
0.01
0.01 10 10010.1
TA = 125°C
TA = 25°C
VS = ±2.5V
TA = –55°C
LOAD CURRENT (mA)
OUTPUT HIGH SATURATION VOLTAGE (V)
625234 G23
10
1
0.1
0.01
0.01 10 10010.1
TA = 125°C
VS = ±2.5V
TA = –55°C
TA = 25°C
TOTAL SUPPLY VOLTAGE (±V)
1.25
OUTPUT SHORT-CIRCUIT CURRENT (mA)
160
120
80
40
0
–40
–80
–120
–160 1.751.5
625234 G24
2.52 2.25
TA = 125°C
TA = 125°C
TA = –55°C
TA = –55°C
TA = 25°C
TA = 25°C
SINK
SOURCE
PULSE TESTED
OUTPUT VOLTAGE (V)
RL = 100 TO MID SUPPLY
VS = 5V, 0V
TA = 25°C
RL = 1k TO GND
RL = 1k TO MID SUPPLY
RL = 100 TO GND
0
INPUT OFFSET VOLTAGE (µV)
500
400
300
200
100
0
–100
–200
–300
–400
–500 2.5 3.5
625234 G25
54 4.521.510.5 3
OUTPUT VOLTAGE (V)
0
INPUT OFFSET VOLTAGE (µV)
1600
1400
600
800
1000
1200
400
200
0
–200
–400
–600 2.5
625234 G26
21.510.5
RL = 1k TO MID SUPPLY
VS = 2.7V, 0V
TA = 25°C
RL = 1k TO GND
RL = 100 TO MID SUPPLY
RL = 100 TO GND
FREQUENCY (MHz)
GAIN (dB)
625234 G27
2
0
–8
–6
–2
–4
–10
0.01 10 100 100010.1
VS = ±2.5V
TA = 25°C
RL = 1k
FREQUENCY (MHz)
GAIN (dB)
625234 G28
10
8
–4
–2
2
0
6
4
–6
0.01 10 100 100010.1
VS = ±2.5V
TA = 25°C
RL = 1k
RF = RG = 500
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEG)
625234 G29
75
5
15
25
35
45
55
65
–5
120
30
45
60
75
90
105
15
0
300k 100M 1G10M1M
GAIN
TA = 25°C
RL = 1k
PHASE
VS = ±2.5V
VS = ±1.35V
VS = ±2.5V
VS = ±1.35V
TOTAL SUPPLY VOLTAGE (V)
2.5
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
900
850
800
750
700
650
600
550
500
70
60
50
40
30
20
10
0
–10
3 3.5 4.5
625234 G30
5 5.254
TA = 25°C
RL = 1k
PHASE MARGIN
GAIN BANDWIDTH PRODUCT
LTC6252/LTC6253/LTC6254
11
625234fa
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Rejection Ratio
vs Frequency
Series Output Resistor
vs Capacitive Load (AV = 1)
Series Output Resistor
vs Capacitive Load (AV = 2)
Output Impedance vs Frequency
Common Mode Rejection Ratio
vs Frequency
Gain Bandwidth and Phase
Margin vs Temperature
Slew Rate vs Temperature
Distortion vs Frequency
(AV = 1, 5V)
Distortion vs Frequency
(AV = 1, 2.7V)
TEMPERATURE (°C)
–55
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
900
1000
1100
1200
800
700
600
500
60
80
70
50
40
30
20
10
–35 –15 4525
625234 G31
12565 85 1055
VS = ±2.5V
VS = ±1.35V
VS = ±2.5V
VS = ±1.35V
PHASE MARGIN
GAIN BANDWIDTH PRODUCT
TA = 25°C
RL = 1k
FREQUENCY (MHz)
OUTPUT IMPEDANCE ()
625234 G32
1000
10
100
1
0.1
0.01
0.0010.1 100 1000101
VS = ±2.5V
AV = 1
AV = 2
AV = 10
FREQUENCY (Hz)
COMMON MODE REJECTION RATIO (dB)
625234 G33
110
90
70
50
30
10
–10
10k 100k 1M 100M 1G10M
VS = ±2.5V
FREQUENCY (Hz)
10
POWER SUPPLY REJECTION RATIO (dB)
50
40
30
20
10
70
80
60
0
–10 100 1k 100k
625234 G34
1G100M10M1M10k
+PSRR
–PSRR
VS = ±2.5V
TEMPERATURE (°C)
–55
SLEW RATE (V/µs)
360
320
340
300
280
240
260
220
200
140
120
160
180
100 –30 4520570
625234 G35
12095
AV = –1, RL = 1k,
VOUT = 4VP-P (±2.5V), 2VP-P (±1.35V)
SLEW RATE MEASURED AT
MIDDLE 2/3 OF OUTPUT
FALLING, VS = ±2.5V
RISING, VS = ±1.35V
FALLING, VS = ±1.35V
RISING, VS = ±2.5V
VS = ±2.5V
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
80
70
60
50
40
30
20
10
0100 100001000
625234 G36
RS = 10Ω
RS = 20Ω
RS = 50Ω
+
–
VIN
RSVOUT
CL
VS = ±2.5V
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
100
70
80
90
60
50
40
30
20
10
0100 100001000
625234 G37
+
–
VIN
RS
500Ω
500Ω
VOUT
CL
RS = 10Ω
RS = 20Ω
RS = 50Ω
VS = ±2.5V
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–20
–50
–60
–30
–40
–70
–80
–90
–100
–110
–120
–130 0.1 100101
625234 G38
RL = 100Ω, 2ND
RL = 100Ω, 3RD
RL = 1k, 2ND
RL = 1k, 3RD
VS = ±2.5V
VOUT = 2VP-P
AV = 1
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–20
–50
–60
–30
–40
–70
–80
–90
–100
–110
–120
–130 0.1 100101
625234 G39
RL = 100Ω, 2ND
RL = 100Ω, 3RD
RL = 1k, 2ND
RL = 1k, 3RD
VS = ±1.35V
VOUT = 1VP-P
AV = 1
LTC6252/LTC6253/LTC6254
12
625234fa
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Response Small Signal Response Output Overdriven Recovery
0.1% Settling Time
vs Output Step (Noninverting)
0.1% Settling Time
vs Output Step (Inverting) SHDN Pin Response Time
Distortion vs Frequency
AV = 2, 2.7V)
Maximum Undistorted Output
Signal vs Frequency
Distortion vs Frequency
(AV = 2, 5V)
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–20
–50
–60
–30
–40
–70
–80
–90
–100
–110
–120
–130 0.1 100101
625234 G40
RL = 100Ω, 2ND
RL = 100Ω, 3RD
RL = 1k, 2ND
RL = 1k, 3RD
VS = ±2.5V
VOUT = 2VP-P
AV = 2
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–20
–50
–60
–30
–40
–70
–80
–90
–100
–110
–120
–130 0.1 100101
625234 G41
RL = 100Ω, 2ND
RL = 100Ω, 3RD
RL = 1k, 2ND
RL = 1k, 3RD
VS = ±1.35V
VOUT = 1VP-P
AV = 2
FREQUENCY (MHz)
0.01
OUTPUT VOLTAGE SWING (VP-P)
6
4
5
3
2
1
00.1 100101
625234 G42
VS = ±2.5V
TA = 25°C
RL = 1k
HD2, HD3 < –40dBc
AV = 2
AV = –1
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
50
45
40
35
10
15
20
25
30
5
0–3 –1
625234 G43
401 32–2
VS = ±2.5V
AV = 1
TA = 25°C
+
–
VOUT
1k
VIN
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
60
45
40
55
50
35
10
15
20
25
30
5
0–3 –1
625234 G44
401 32–2
VS = ±2.5V
AV = –1
TA = 25°C
+
–
VOUT
1k
500Ω
VIN
500Ω VOUT
0.8V/DIV
AV = 1
VS = ±2.5V
RL = 1k
VIN = 1.6V
VSHDN
2.5V/DIV
0V
0V
625234 G45
2µs/DIV
1V/DIV
0V
AV = 1
VS = ±2.5V
TA = 25°C
RL = 1k
625234 G46
100ns/DIV
INPUT
(50mV/DIV)
0V
OUTPUT
(50mV/DIV)
0V
VS = ±2.5V
RL = 1k
625234 G47
20ns/DIV
VOUT
2V/DIV
AV = ±2, TA = 25°C
VS = ±2.5V, VIN = 3VP-P
RL = 1k, RF = RG = 500Ω
VIN
1V/DIV
0V
0V
625234 G48
20ns/DIV
LTC6252/LTC6253/LTC6254
13
625234fa
APPLICATIONS INFORMATION
Circuit Description
The LTC6252/LTC6253/LTC6254 have an input and output
signal range that extends from the negative power supply
to the positive power supply. Figure 1 depicts a simplifi ed
schematic of the amplifi er. The input stage is comprised
of two differential amplifi ers, a PNP stage, Q1/Q2, and an
NPN stage, Q3/Q4 that are active over different common
mode input voltages. The PNP stage is active between
the negative supply to nominally 1.2V below the positive
supply. As the input voltage approaches the positive sup-
ply, the transistor Q5 will steer the tail current, I1, to the
current mirror, Q6/Q7, activating the NPN differential pair
and the PNP pair becomes inactive for the remaining input
common mode range. Also, at the input stage, devices Q17
to Q19 act to cancel the bias current of the PNP input pair.
When Q1/Q2 are active, the current in Q16 is controlled to
be the same as the current in Q1 and Q2. Thus, the base
current of Q16 is nominally equal to the base current of
the input devices. The base current of Q16 is then mirrored
by devices Q17 to Q19 to cancel the base current of the
input devices Q1/Q2. A pair of complementary common
emitter stages, Q14/Q15, enable the output to swing from
rail-to-rail.
Figure 1. LTC6252/LTC6253/LTC6254 Simplifi ed Schematic Diagram
–IN: Inverting Input of Amplifi er. Input range from V–
to V+.
+IN: Non-Inverting Input of Amplifi er. Input range from
V– to V+.
V+ : Positive Supply Voltage. Total supply voltage ranges
from 2.5V to 5.25V.
V– : Negative Supply Voltage. Typically 0V. This can be made
a negative voltage as long as 2.5V ≤ (V+ – V–) ≤ 5.25V.
SHDN: Active Low Shutdown. Threshold is typically 1.1V
referenced to V–. Floating this pin will turn the part on.
OUT: Amplifi er Output. Swings rail-to-rail and can typically
source/sink over 90mA of current at a total supply of 5V.
PIN FUNCTIONS
625234 F01
Q15
ESDD5
Q14
C2
C1
BUFFER
AND
OUTPUT BIAS
R5R4
Q13
Q12
I3
V–
+
CC
Q8
R3
Q11
Q9
Q10
R2R1
Q2Q1Q3Q4
I1
+
I2
+
VBIAS
Q5
Q6Q19 Q7
D8
D7
Q18
Q17
D6
D5
ESDD2
V–
ESDD1
V+
ESDD4
V–
ESDD3
V+
Q16
V–
V+
+IN
–IN
ESDD6
OUT
LTC6252/LTC6253/LTC6254
14
625234fa
APPLICATIONS INFORMATION
Input Offset Voltage
The offset voltage will change depending upon which
input stage is active. The PNP input stage is active from
the negative supply rail to approximately 1.2V below the
positive supply rail, then the NPN input stage is activated
for the remaining input range up to the positive supply
rail with the PNP stage inactive. The offset voltage mag-
nitude for the PNP input stage is trimmed to less than
350µV with 5V total supply at room temperature, and is
typically less than 150V. The offset voltage for the NPN
input stage is less than 2.2mV with 5V total supply at
room temperature.
Input Bias Current
The LTC6252 family uses a bias current cancellation cir-
cuit to compensate for the base current of the PNP input
pair. This results in a typical IB of about 100nA. When the
input common mode voltage is less than 200mV, the bias
cancellation circuit is no longer effective and the input
bias current magnitude can reach a value above 4µA. For
common mode voltages ranging from 0.2V above the
negative supply to 1.2V below the positive supply, the
low input bias current allows the amplifi ers to be used in
applications with high source resistances where errors
due to voltage drops must be minimized.
Output
The LTC6252 family has excellent output drive capability.
The amplifi ers can typically deliver 90mA of output drive
current at a total supply of 5V. The maximum output
current is a function of the total supply voltage. As the
supply voltage to the amplifi er decreases, the output
current capability also decreases. Attention must be paid
to keep the junction temperature of the IC below 150°C
(refer to the Power Dissipation Section) when the output
is in continuous short-circuit. The output of the amplifi er
has reverse-biased diodes connected to each supply. If
the output is forced beyond either supply, extremely high
current will fl ow through these diodes which can result
in damage to the device. Forcing the output to even 1V
beyond either supply could result in several hundred mil-
liamps of current through either diode.
Input Protection
The LTC6252/LTC6253/LTC6254 input stages are protected
against a large differential input voltage of 1.4V or higher by
2 pairs of back-to-back diodes to prevent the emitter-base
breakdown of the input transistors. In addition, the input
and shutdown pins have reverse biased diodes connected
to the supplies. The current in these diodes must be limited
to less than 10mA. The amplifi ers should not be used as
comparators or in other open loop applications.
ESD
The LTC6252 family has reverse-biased ESD protection
diodes on all inputs and outputs as shown in Figure 1.
There is an additional clamp between the positive and nega-
tive supplies that further protects the device during ESD
strikes. Hot plugging of the device into a powered socket
must be avoided since this can trigger the clamp resulting
in larger currents fl owing between the supply pins.
Capacitive Loads
The LTC6252/LTC6253/LTC6254 are optimized for high
bandwidth and low power applications. Consequently they
have not been designed to directly drive large capacitive
loads. Increased capacitance at the output creates an ad-
ditional pole in the open loop frequency response, wors-
ening the phase margin. When driving capacitive loads, a
resistor of 10 to 100 should be connected between the
amplifi er output and the capacitive load to avoid ringing
or oscillation. The feedback should be taken directly from
the amplifi er output. Higher voltage gain confi gurations
tend to have better capacitive drive capability than lower
gain confi gurations due to lower closed loop bandwidth
and hence higher phase margin. The graphs titled Series
Output Resistor vs Capacitive Load demonstrate the tran-
sient response of the amplifi er when driving capacitive
loads with various series resistors.
LTC6252/LTC6253/LTC6254
15
625234fa
APPLICATIONS INFORMATION
Figure 2. 5pF Feedback Cancels Parasitic Pole
Feedback Components
When feedback resistors are used to set up gain, care
must be taken to ensure that the pole formed by the
feedback resistors and the parasitic capacitance at the
inverting input does not degrade stability. For example
if the amplifi er is set up in a gain of +2 confi guration
with gain and feedback resistors of 5k, a parasitic ca-
pacitance of 5pF (device + PC board) at the amplifi er’s
inverting input will cause the part to oscillate, due to
a pole formed at 12.7MHz. An additional capacitor of
5pF across the feedback resistor as shown in Figure 2
will eliminate any ringing or oscillation. In general, if
the resistive feedback network results in a pole whose
frequency lies within the closed loop bandwidth of the
amplifi er, a capacitor can be added in parallel with the
feedback resistor to introduce a zero whose frequency is
close to the frequency of the pole, improving stability.
624678 F02
CPAR
5k
–
+
VOUT
VIN
5k
5pF
Power Dissipation
The LTC6252 and LTC6253 contain one and two amplifi ers
respectively. Hence the maximum on-chip power dis-
sipation for them will be less than the maximum on-chip
power dissipation for the LTC6254, which contains four
amplifi ers.
The LTC6254 is housed in a small 16-lead MS package and
typically has a thermal resistance (qJA) of 125°C/ W. It is
necessary to ensure that the die’s junction temperature
does not exceed 150°C. The junction temperature, TJ, is
calculated from the ambient temperature, TA, power dis-
sipation, PD, and thermal resistance, qJA:
T
J = TA + (PD • qJA)
The power dissipation in the IC is a function of the supply
voltage, output voltage and load resistance. For a given
supply voltage with output connected to ground or supply,
the worst-case power dissipation PD(MAX) occurs when
the supply current is maximum and the output voltage at
half of either supply voltage for a given load resistance.
PD(MAX) is approximately (since IS actually changes with
output load current) given by:
PD(MAX) =(VS•IS(MAX))+VS
2
⎛
⎝
⎜⎞
⎠
⎟
2
/R
L
Example: For an LTC6254 in a 16-lead MS package operating
on ±2.5V supplies and driving a 100 load to ground, the
worst-case power dissipation is approximately given by
P
D(MAX)/Amp = (5 • 4.8mA) + (1.25)2/100 = 39.6mW
If all four amplifi ers are loaded simultaneously then the
total power dissipation is 158mW.
At the Absolute Maximum ambient operating temperature,
the junction temperature under these conditions will be:
T
J = TA + PD • 125°C/W
= 125 + (0.158W • 125°C/W) = 145°C
which is less than the absolute maximum junction tem-
perature for the LTC6254 (150°C).
Refer to the Pin Confi guration section for thermal resis-
tances of various packages.
Shutdown
The LTC6252 and LTC6253MS have SHDN pins that can
shut down the amplifi er to 42µA typical supply current. The
SHDN pin needs to be taken within 0.8V of the negative
supply for the amplifi er to shut down. When left fl oating,
the SHDN pin is internally pulled up to the positive supply
and the amplifi er remains on.
LTC6252/LTC6253/LTC6254
16
625234fa
Figure 3. 5V Single Supply 16-Bit ADC Driver
TYPICAL APPLICATIONS
5V Single-Supply 16-Bit ADC Driver
Figure 3 shows the LTC6253 driving an LTC2393-16 16-bit
A/D converter on a single 5V supply. The low wideband
noise of the LTC6253 helps to achieve better than 93dB
SNR. A gain of 1.17V/V is taken in the fi rst amplifi er, giv-
ing an input voltage range of 3.5VP-P for a full-scale input
to the ADC. By taking a small amount of gain, a –1dBFS
Figure 4. LTC6253 Driving LTC2393-16
16b ADC 5V Single-Supply Performance
5V
0.1µF10µF
5V
5V
~2.08V
0.1µF10µF
SER/PAR
BYTESWAP
OB/2C
CS
RD
BUSY
PARALLEL
OR
SERIAL
INTERFACE
OGND
625234 F03
IN–
IN+
3900pF
249
249
100
100
VIN
27.4mV TO
(3.5V + 27.4mV)
GNDRESETCNVST PD
SAMPLE CLOCK
REFOUTREFIN
AVP DVP
LTC2393-16
OVP
1.8V TO 5V
16 BIT
VCM
1µF10µF
2.5k2.5k143Ω
845Ω
4.7µF
–
+
½ LTC6253
5V
–
+
½ LTC6253
FREQUENCY (kHz)
0
AMPLITUDE (dBFS)
0
–80
–20
–40
–60
–100
–120
–140
–160 200 400100 300
624678 F04
500
fS = 1Msps
F1 = 20.111kHz
F1 AMPLITUDE
= –1.032dBFS
SNR = 93.28dB
THD = –100.50dB
SINAD = 92.53dB
SFDR = 104.7dB
F2 = –106.39dBc
F3 = –104.70dBc
F4 = –114.13dBc
F5 = –105.48dBc
f
S
= 1Ms
p
s
F1 = 2
0
.111k
Hz
F1 AMPLITUD
E
= –1.032dBF
S
S
NR = 93.28d
B
THD = –100.5
0dB
S
INAD = 92.53d
B
SFD
R =
10
4.7
dB
F2 = –106.39d
Bc
F
3
= –1
0
4.7
0dBc
F4 = –114.13d
Bc
F5
= –
105
.48
dBc
output can be easily obtained without the amplifi er transi-
tioning between input regions, thus minimizing crossover
distortion. Furthermore, by driving VCM with 2.08V from
the ADC’s VCM pin, the LTC6253 is capable of driving the
LTC2393-16 to within 0.1dB of full scale. Figure 4 shows
an FFT obtained with a sampling rate of 1Msps and a
20kHz input waveform. Spurious free dynamic range is
an excellent 104.7dB.
LTC6252/LTC6253/LTC6254
17
625234fa
Low Noise Gain Block Using Channels in Parallel
Figure 5 shows the LTC6254 confi gured as a low noise
gain block. By confi guring each channel as a gain of 10
block and putting all four gain blocks in parallel, the input
referred noise can be reduced signifi cantly. 22 resistors
are hooked up to the outputs of each of the channels to
ensure even distribution of load currents.For a total sup-
ply current of 13.2mA, measured input referred noise
density (including contributions from the resistors) be-
tween 100kHz and 10MHz was less than 1.6nV/√Hz, with
input referred noise density at 1 MHz being 1.5nV/√Hz.
The measured –3dB frequency was 37MHz for a load
resistance of 1k.
TYPICAL APPLICATIONS
Multiplexing Channels
The LTC6252 and LTC6253 are available with shutdown
pins in the SOT-23 and MS10 packages. While this allows
for reduced power consumption, it also makes the parts
suitable for high output impedance applications such as
muxing. During shutdown, the bases of the amplifi er’s
output channels are hard tied to their emitters in order to
minimize leakage. Figure 6 shows the LTC6253 applied as a
mux, with the outputs simply shorted together. Depending
on which device is powered, either the VA or the VB input
is buffered to VOUT. The MOSFET Q1 provides a simple
logic inversion, so that pulling the gate high selects the
B path while the FET drain goes low shutting down the A
path. R3 is provided to speed up the drain rise time. The
LTC6253 turn-on time is longer than the turn-off time (3.5µs
vs < 2µs) avoiding cross conduction in the output stages.
Figure 5. Low Noise Gain Block Using Parallel Channels
Figure 6. Multiplexing Channels
¼ LTC6254
+
–
1pF
2.5V
–2.5V
900Ω
100Ω
22Ω
¼ LTC6254
+
–
1pF
900Ω
100Ω
22Ω
¼ LTC6254
+
–
1pF
900Ω
100Ω
22Ω
¼ LTC6254
+
–
1pF
900Ω
100Ω
VIN
22Ω
VOUT
625234 F05
625234 F06
+
–
5V
SHDNA
SHDNB
VA
½ LTC6253
R1
330Ω
+
–
VB
5V
Q1
2N7002
SEL_B
½ LTC6253
R2
330
R3
20k
VOUT
LTC6252/LTC6253/LTC6254
18
625234fa
TYPICAL APPLICATIONS
Figure 9. Instrumentation Amplifi er
Frequency Response
FREQUENCY (Hz)
10k
GAIN (dB)
40
35
25
15
30
20
10
5
0100k 10M1M
625234 F09
100M
FREQUENCY (Hz)
10k
CMRR (dB)
120
100
60
20
80
40
0100k 10M1M
625234 F10
100M
Figure 10. Instrumentation
Amplifi er CMRR
INPUT
25mV/DIV
OUTPUT
1V/DIV
0V
0V
625234 F11
100ns/DIV
Figure 11. Transient Response,
Instrumentation Amplifi er
Figure 8. High Speed Low Voltage Instrumentation Amplifi er
625234 F08
+
–
R4
750Ω
R5
750Ω
R6
750Ω
R7
750Ω
R2
1.2k
R1
60Ω
U1
½ LTC6253
VS+
VS–
R3
1.2k
AV = 41
BW = 15MHz
VS = ±1.5V
IS = 8.4mA
–
+
U2
½ LTC6253
IN+
IN–
VS+
VS–
+
–
U3
½ LTC6253 VOUT
See the oscillograph of Figure 7, showing the inputs VA
and VB, the SEL_B control, and the resulting output.
Note that there are protection diodes across the op amp
inputs, so large signals at the output will feed back into the
upstream off channel through the diodes. R1 and R2 were
put in place to reduce the loading on the output, as well
as to reduce the upstream feedback current and improve
reverse isolation. Some reverse crosstalk can be discerned
in the VA and VB traces during their respective off times,
however, as the reverse current works back into the 50
source impedance of the function generators.
High Speed Low Voltage Instrumentation Amplifi er
Figure 8 shows a three op amp instrumentation amplifi er
with a gain of 41V/V which can operate on low supplies.
Op amps U1 and U2 are channels from an LTC6253.
Op amp U3 can be an LTC6252 or one channel of an
LTC6253. Figure 9 shows the measured frequency re-
sponse of the instrumentation amplifi er for a load of 1k.
Figure 10 shows the measured CMRR of the instrumenta-
tion amplifi er, and Figure 11 shows the transient response
for a 50mVP-P input square wave applied to the positive
input, with the negative input grounded.
Figure 7. Oscilloscope Traces Showing
Multiplexing Channels
SEL_B
5V/DIV
VB
VA
VOUT
625234 F07
50µs/DIV
LTC6252/LTC6253/LTC6254
19
625234fa
DC8 Package
8-Lead Plastic DFN (2mm ¥ 2mm)
(Reference LTC DWG # 05-08-1719 Rev A)
PACKAGE DESCRIPTION
2.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
0.64 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
1.37 p0.10
(2 SIDES)
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC8) DFN 0106 REVØ
0.23 p 0.05
0.45 BSC
0.25 p 0.05
1.37 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.64 p0.05
(2 SIDES)
1.15 p0.05
0.70 p0.05
2.55 p0.05
PACKAGE
OUTLINE
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45o
CHAMFER
LTC6252/LTC6253/LTC6254
20
625234fa
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 p 0.152
(.193 p .006)
8765
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
LTC6252/LTC6253/LTC6254
21
625234fa
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
LTC6252/LTC6253/LTC6254
22
625234fa
PACKAGE DESCRIPTION
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
MSOP (MS16) 1107 REV Ø
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.1016 p 0.0508
(.004 p .002)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.280 p 0.076
(.011 p .003)
REF
4.90 p 0.152
(.193 p .006)
LTC6252/LTC6253/LTC6254
23
625234fa
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
PACKAGE DESCRIPTION
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC6252/LTC6253/LTC6254
24
625234fa
PACKAGE DESCRIPTION
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0710 REV A
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.40
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
LTC6252/LTC6253/LTC6254
25
625234fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 9/10 Revised ISD Parameters in Electrical Characteristics section 4, 5
LTC6252/LTC6253/LTC6254
26
625234fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
” LINEAR TECHNOLOGY CORPORATION 2010
LT 0910 REV A • PRINTED IN USA
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
Operational Amplifi ers
LT1818/LT1819 Single/Dual Wide Bandwidth, High Slew Rate Low Noise and
Distortion Op Amps
400MHz, 9mA, 6nV/√Hz, 2500V/µs, 1.5mV –85dBc at 5MHz
LT1806/LT1807 Single/Dual Low Noise Rail-to-Rail Input and Output Op Amps 325MHz, 13mA, 3.5nV/√Hz, 140V/µs, 550µV, 85mA Output Drive
LTC6246/LTC6247/
LTC6248
Single/Dual/Quad High Speed Rail-to-Rail Input and Output
Op Amps
180MHz, 1mA, 4.2nV/√Hz, 90V/µs, 0.5mV
LT6230/LT6231/
LT6232
Single/Dual/Quad Low Noise Rail-to-Rail Output Op Amps 215MHz, 3.5mA, 1.1nV/√Hz, 70V/µs, 350µV
LT6200/LT6201 Single/Dual Ultralow Noise Rail-to-Rail Input/Output Op Amps 165MHz, 20mA, 0.95nV/√Hz, 44V/µs, 1mV
LT6202/LT6203/
LT6204
Single/Dual/Quad Ultralow Noise Rail-to-Rail Op Amp 100MHz, 3mA, 1.9nV/√Hz, 25V/µs, 0.5mV
LT1468 16-Bit Accurate Precision High Speed Op Amp 90MHz, 3.9mA, 5nV/√Hz, 22V/µs, 175µV,
–96.5dB THD at 10VP-P, 100kHz
LT1801/LT1802 Dual/Quad Low Power High Speed Rail-to-Rail Input and
Output Op Amps
80MHz, 2mA, 8.5nV√Hz, 25V/µs, 350µV
LT1028 Ultralow Noise, Precision High Speed Op Amps 75MHz, 9.5mA, 0.85nV/√Hz, 11V/µs, 40µV
LTC6350 Low Noise Single-Ended to Differential Converter/ADC Driver 33MHz (–3dB), 4.8mA, 1.9nV/√Hz, 240ns Settling to 0.01% 8VP-P
ADCs
LTC2393-16 1Msps 16-Bit SAR ADC 94dB SNR
LTC2366 3Msps, 12-Bit ADC Serial I/O 72dB SNR, 7.8mW No Data Latency TSOT-23 Package
LTC2365 1Msps, 12-Bit ADC Serial I/O 73dB SNR, 7.8mW No Data Latency TSOT-23 Package
RELATED PARTS
2MHz, 1MΩ Single Supply Photodiode Amplifi er Photodiode Amplifi er Noise Spectrum
Photodiode Amplifi er Transient Response
LTC6252
+
–
625234 TA02a
VOUT ≈ 0.5V + IPD • 1M
3V
R1
1M, 1%
3V
3V
R2
1k
IPD
C3
0.1µF
C1
0.1pF
R5
20k
R4
10k
R3
1k
–3dB BW = 2MHz
ICC = 4.5mA
OUTPUT NOISE = 360µVRMS
MEASURED ON A 2MHz BW
C2
6.8nF
FILM
OR NPO
PD1
OSRAM
SFH213
Q1
NXP
BF862
50nV/√Hz
PER DIV
500
0
625234 TA02b
100kHz 2MHz
5kHz
0V
5V/DIV
LED DRIVER
VOLTAGE
625234 TA02c
200ns/DIV
500mV/DIV
OUTPUT
WAVEFORM