XRP9710 and XRP9711 Dual 6A Programmable Power Module Rev. 1.0.1 January 2014 GENERAL DESCRIPTION FEATURES The XRP9710 and XRP9711 are programmable step down power modules providing two 6A outputs. The module package contains the switching controller, power MOSFETs, inductors and support components. As a result, external components are minimal. A wide input voltage range (4.75V to 5.5V or 5.5V to 22V) allows for single supply operation from standard power rails. * XRP9710 - Dual 6A Outputs with Differential Sensing The modules measure only 12x12x2.75mm making it half the size of competing 12V capable 6Amp modules. The 2.75mm height allows them to be placed on the back of boards or under heat sinks where other solutions cannot, yet they contain two full 6A buck power stages and two Digital Pulse Width Modulator (DPWM) controllers with gate drivers. Designed to operate at a constant PWM switching frequency between 500kHz and 750kHz, the Digital Pulse Frequency Mode (DPFM) results in better than 80% efficiency at light load currents and low operating current allow for portable and Energy Star compliant applications. Each XRP9710 or XRP9711 output can be individually programmed to as low as 0.6V with a resolution as fine as 2.5mV, and configurable for precise soft start and soft stop sequencing, including delay and ramp control. The XRP9710/1 is fully controlled via a SMBuscompliant I2C interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as well as fault handling. Built-in output over-voltage, overtemperature, over-current and under voltage lockout protections insure safe operation under abnormal operating conditions. The XRP9710/1 is offered in a compliant, halogen-free LGA package. Exar Corporation 48720 Kato Road, Fremont CA 94538, USA * XRP9711 - Dual 6A Outputs with Control for Two External Power Stages * 12 x 12 x 2.75mm LGA Package * Wide Input Voltage Range: 4.75V to 22V - Low Range: 4.75V to 5.5V - High Range: 5.5V-22V * Output Voltage Range: 0.6V to 5.5V * SMBus Compliant - I2C Interface - Full Power Monitoring and Reporting * 3 x 15V Capable PSIOs + 2 x GPIOs * Full Start/Stop Sequencing Support * Built-in Thermal, Over-Current, UVLO and Output Over-Voltage Protections * On-Board 5V Standby LDO * On-Board Non-volatile Memory * CISPR22 Level B radiated emissions * PowerArchitectTM 5.1 or later Design Tool APPLICATIONS * * * * * * * Servers Base Stations Switches/Routers Broadcast Equipment Industrial Control Systems Automatic Test Equipment Video Surveillance Systems RoHS www.exar.com Tel. +1 510 668-7000 - Fax. +1 510 668-7001 XRP9710 and XRP9711 Dual 6A Programmable Power Module Rev. 1.0.1 January 2014 TYPICAL APPLICATION DIAGRAM Load VOUT3- VOUT3+ Cout PVOUT3 PGND3 PVIN PGND4 LX3 Cin Load PVOUT4 LX4 XRP9710 Cout 1uF GPIO1 SDA SCL VCC LDO5 PSIO0 PSIO1 PSIO3 GPIO0 ENABLE AGND (DAP) VOUT4VOUT4+ Figure 1 XRP9710 Application Diagram with differential voltage sensing VOUT3 Cout VIN BST2 + LX2 PGND3 PVIN LX3 GL2 GL_RTN2 + GH1 Cout XRP9711 LX4 BST1 PVOUT4 VIN Cin PGND4 + VOUT4 LX1 + SCL 1uF VCC LDO5 GPIO1 SDA GL_RTN1 ENABLE VOUT3 VOUT4 PSIO0 PSIO1 PSIO3 GPIO0 GL1 VOUT1 VOUT2 VOUT1 PVOUT3 GH2 AGND (DAP) VOUT2 Figure 2 XRP9711 Application Diagram Exar Corporation 48720 Kato Road, Fremont CA 94538, USA www.exar.com Tel. +1 510 668-7000 - Fax. +1 510 668-7001 XRP9710 and XRP9711 Dual 6A Programmable Power Module FEATURES AND BENEFITS System Integration Capabilities World's smallest 12V capable dual 6A module at 12x12x2.75mm * Single supply operation * I2C interface allows: - Communication with a System Controller or other Power Management devices for optimized system functionality Programmable Power Benefits * Fully Configurable - Access to modify or read internal registers that control or monitor: - Output set point - Feedback compensation - Output Current - Frequency set point - Input and Output Voltage - Under voltage lock out - Soft-Start/Soft-Stop Time - Input voltage measurement - `Power Good' - Gate drive dead time * - Part Temperature Reduced Development Time - Enable/Disable Outputs - Configurable and re-configurable for different Vout, Iout, Cout, and Inductor values - Over Current - Over Voltage - Temperature Faults - No need to change external passives for a new output specification. * - Adjusting fault limits and disabling/enabling faults Higher integration and Reliability - Packet Error Checking (PEC) on I2C communication - Lowest component count for a fully configurable module * PowerArchitectTM 5 Design and Configuration Software - Fault reporting (including UVLO Warn/Fault, OCP Warn/Fault, OVP, Temperature, Soft-Start in progress, Power Good, System Reset) - Wizard quickly generates a base design - Calculates all configuration registers - Projects can be saved and/or recalled - Allows a Logic Level interface with other non-digital IC's or as logic inputs to other devices - GPIOs can be configured easily and intuitively - "Dashboard" Interface can be used for real-time monitoring and debug * * * Frequency and Synchronization Capability - Selectable switching frequency between 124kHz and 1.23MHz (500kHz to 750kHz internal power stages) System Benefits * 5 GPIO pins with a wide range of configurability Reliability is enhanced via communication with the system controller which can obtain real-time data on an output voltage, input voltage and current. - Main oscillator clock and DPWM clock can be synchronized to external sources * System processors can communicate with the XRP9710/1 directly to obtain data or make adjustments to react to circuit conditions Internal MOSFET Drivers (XRP9711) - Internal FET drivers (4/2) per channel - Built-In Automatic Dead-time adjustment - 17ns Rise and 11ns Fall times System logging and history, diagnostics and remote reconfigurability. (c) 2013 Exar Corporation Confidential 3/36 Rev. A0.0.5 XRP9710 and XRP9711 Dual 6A Programmable Power Module ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Input Voltage Range VCC ............................... 5.5V to 25V PVIN Voltage Range .......................................3.0 to 22V Input Voltage Range VCC = LDO5 ................ 4.75V to 5.5V VOUT1, 2, 3, 4 ...................................................... 5.5V Junction Temperature Range ....................-40C to 125C Package Power Dissipation max at 25C .................. 5.5W JEDEC51-2A Package Thermal Resistance JA........ 18C/W Complies with CISPR22....................................... Level B LDO5, GLx, VOUTx .................................... -0.3V to 7.0V ENABLE .................................................... -0.3V to 7.0V GPIO0/1, SCL, SDA ............................................... 6.0V PSIO Inputs ........................................................... 18V Vcc ....................................................................... 28V LXx .............................................................. -1V to 28V BSTx, GHx .................................................... VLXx + 6V Storage Temperature .............................. -65C to 150C Power Dissipation ................................ Internally Limited Lead Temperature (Soldering, 10 sec) ................... 245C ESD Rating (HBM - Human Body Model) .................... 2kV ELECTRICAL SPECIFICATIONS Specifications with standard type are for an Operating Junction Temperature of TJ = 25C only; limits applying over the full Operating Junction Temperature range are denoted by a "*". Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise indicated, VCC = 5.5V to 22V. QUIESCENT CURRENT Parameter Min. VCC Supply Current in SHUTDOWN ENABLE Turn On Threshold ENABLE Pin Leakage Current Typ. Max. Units 10 20 A 0.95 V 10 uA 0.82 Conditions EN = 0V, VCC = 12V VCC = 12V Enable Rising EN=5V EN=0V -10 All channels disabled VCC Supply Current in STANDBY 440 600 A GPIOs programmed as inputs VCC=12V,EN = 5V VCC Supply Current 2ch PFM 3.1 mA 2 channels on set at 5V, VOUT forced to 5.1V, no load, non-switching, Ultra-sonic off, VCC=12 V, No I2C activity. VCC Supply Current 4ch PFM 4.0 mA 4 channels on set at 5V, VOUT forced to 5.1V, no load, non-switching, Ultra-sonic off, VCC=12V, No I2C activity. VCC Supply Current ON 18 mA All channels enabled, Fsw=600kHz, gate drivers unloaded, No I2C activity. INPUT VOLTAGE RANGE AND UNDERVOLTAGE LOCKOUT Parameter VCC Range PVIN Range (c) 2014 Exar Corporation Min. Max. Units 5.5 Typ. 25 V 4.75 5.5 V * * 3.0 22 V * 4/36 Conditions With VCC connected to LDO5 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module VOLTAGE FEEDBACK ACCURACY AND OUTPUT VOLTAGE SET POINT RESOLUTION Parameter Min. Typ. Max. Units mV mV mV mV Conditions VOUT Regulation Accuracy Low Output Range 0.6V to 1.6V PWM Operation -5 -20 -7.5 -22.5 5 20 7.5 22.5 VOUT Regulation Accuracy Mid Output Range 0.6V to 3.2V PWM Operation -15 -45 -20 -50 15 45 20 50 mV mV mV mV VOUT Regulation Accuracy High Output Range 0.6V to 5.5V PWM Operation -30 -90 -40 -100 30 90 40 100 mV mV mV mV * 5.5 V * VOUT Regulation Range 0.6 * * * * * 0.6 VOUT 1.6V 0.6 VOUT 1.6V VCC=LDO5 0.6 VOUT 3.2V 0.6 VOUT 3.2V VCC=LDO5 0.6 VOUT 5.5V 0.6 VOUT 4.2V VCC=LDO5 Without external divider network 12.5 25 50 mV Low Range Mid Range High Range VOUT Fine Set Point Resolution1 2.5 5 10 mV Low Range Mid Range High Range VOUT Input Resistance 120 90 75 k Low Range Mid Range High Range VOUT Input Resistance in PFM Operation 10 1 0.67 M Low Range Mid Range High Range VOUT Native Set Point Resolution Power Good and OVP Set Point Range (from set point) -155 -310 -620 157.5 315 630 mV Low Range Mid Range High Range Power Good and OVP Set Point Accuracy -5 -10 -20 5 10 20 mV Low Range Mid Range High Range Note 1: Fine Set Point Resolution not available in PFM (c) 2014 Exar Corporation 5/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module CURRENT AND AUX ADC (MONITORING ADCS) Parameter Current Sense Accuracy Min. Typ. Max. Units -3.75 -10 -5 -12.5 1.25 3.75 10 5 +12.5 mV mV mV mV LSB 2.5 Conditions * Low Range (120mV) -60mV applied * High Range (280mV) -150mV Current Sense ADC INL 0.4 DNL 0.27 Current Limit Set Point Resolution and Current Sense ADC Resolution 1.25 mV Low Range (120mV) 2.5 mV High Range (280mV) Current Sense ADC Range -120 20 -280 40 15 30 60 VOUT ADC Resolution VOUT ADC Accuracy VCC ADC Range mV Low Range (120mV) High Range (280mV) Low Range Mid Range High Range mV -1 1 LSB 4.6 25 V Note 2 UVLO WARN SET 4.4 4.72 V UVLO WARN set point 4.6V, VCC=LDO5 UVLO WARN CLEAR 4.4 4.72 V UVLO WARN set point 4.6V, VCC=LDO5 1 LSB VCC ADC Resolution VCC ADC Accuracy 200 Die Temp ADC Resolution Die Temp ADC Range mV -1 5 156 -44 Vcc <= 20V C C Output value is in Kelvin Note 2: Although Range of VCC ADC is technically 0V to 25V, below 4.55 the LDO5 hardware UVLO may have tripped. LINEAR REGULATOR Parameter Min. Typ. Max. Units Conditions LDO5 Output Voltage 4.85 5.0 5.15 V * 5.5V VCC 25V 0mA < ILDO5OUT < 130mA LDO5 Current Limit 135 155 180 mA * LDO5 Fault Set LDO5 UVLO 4.74 V * LDO5 PGOOD Hysteresis 375 Maximum total LDO loading during ENABLE start-up 30 (c) 2014 Exar Corporation 6/36 VCC Rising mV VCC Falling mA ENABLE transition from logic low to high. Once LDO5 in regulation above limits apply. Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module PWM GENERATORS AND OSCILLATOR Parameter Min. Typ. Max. Units Conditions Switching Frequency (fsw) Range, Channels 1 and 2 124 1230 kHz Switching Frequency (fsw) Range, Channels 3 and 4 500 750 kHz fsw Accuracy -5 5 % CLOCK IN Synchronization Frequency 20 25.7 31 MHz When synchronizing to an external clock (Range 1) CLOCK IN Synchronization Frequency 10 12.8 15.5 MHz When synchronizing to an external clock (Range 2) Min. Typ. Max. Units 0.8 V 1 A 0.4 V See Applications Information GPIOS3 Parameter Input Pin Low Level Input Pin High Level V 2.0 Input Pin Leakage Current Output Pin Low Level Output Pin High Level Conditions ISINK = 1mA V ISOURCE = 1mA 3.6 V ISOURCE = 0mA 10 A 1 mA Open Drain Mode 30 MHz I/O configured for clock synchronization input or output Max. Units 0.8 V 1 A Output Pin Low Level 0.4 V ISINK = 3mA Output Pin High Level 15 V Open Drain. External pull-up resistor to user supply Output Pin High-Z leakage Current (PSIO pins only) 10 A 5 MHz 2.4 Output Pin High Level 3.3 Output Pin High-Z leakage Current (GPIO pins only) Maximum Sink Current I/O Frequency Note 3: 3.3V CMOS logic compatible, 5V tolerant. PSIOS4 Parameter Min. Input Pin Low Level Input Pin High Level Input Pin Leakage Current I/O Frequency Typ. Conditions V 2.0 Note 4: 3.3V/5.0V CMOS logic compatible, maximum rating of 15.0V (c) 2014 Exar Corporation 7/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module SMBUS (I2C) INTERFACE Parameter Min. Typ. Input Pin Low Level, VIL Input Pin High Level, VIH Hysteresis of Schmitt Trigger inputs, Vhys 0.3 VIO Output fall time from VIHmin to VILmax Units Conditions V VIO = 3.3 V 10% 0.7 VIO V VIO = 3.3 V10% 0.05 VIO V VIO = 3.3 V10% 0.4 V ISINK = 3mA 10 A Input is between 0.1 VIO and 0.9 VIO 250 ns With a bus capacitance (Cb) from 10 pF to 400 pF 1 pF Max. Units Output Pin Low Level (open drain or collector), VOL Input leakage current Max. -10 20 + 0.1 Cb Internal Pin Capacitance GATE DRIVERS Parameter Min. Typ. GH, GL Rise Time 17 ns GH, GL Fall Time 11 ns GH, GL Pull-Up On-State Output Resistance 4 5 GH, GL Pull-Down On-State Output Resistance 2 2.5 GH, GL Pull-Down Resistance in Off-Mode Conditions At 10-90% of full scale, 1nF Cload 50 k VCC = VCCD = 0V. 9 @ 10mA Minimum On Time 50 ns 1nF of gate capacitance. Minimum Off Time Bootstrap diode forward resistance 125 ns 1nF of gate capacitance Minimum Programmable Dead Time 20 ns Maximum Programmable Dead Time Tsw Does not include dead time variation from driver output stage Tsw=switching period Programmable Dead Time Adjustment Step 607 (c) 2014 Exar Corporation ps 8/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module BLOCK DIAGRAMS PVIN BST3 Channel 3 VOUT3+ VOUT3- PreScaler 1/2/4 Feedback ADC GH3 Digital PID Dead Time VCC VREF DAC Gate Driver GL3 PVOUT3 + PGND3 Current ADC SS & PD VOUT4+ + LX3 Hybrid DPWM Channel 4 VOUT4- 4uA ENABLE GPIO 0-1 PSIO 0-2 SDA,SCL Internal POR Vout3 MUX GPIO NVM (FLASH) Sequencing PSIO Configuration Registers PWR Good I2C LOGIC CLOCK Fault Handling OTP UVLO OCP OVP Vout4 Vtj VCC 5V LDO LDO5 Figure 3 XRP9710 Block Diagram (c) 2014 Exar Corporation 9/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module BST1 Channel 1 VOUT1 PreScaler 1/2/4 Feedback ADC GH1 Dead Time VCC VREF DAC LX1 Hybrid DPWM Digital PID Gate Driver GL1 GL_RTN1 Current ADC SS & PD Channel 2 VOUT2 PVIN BST3 Channel 3 VOUT3 PreScaler 1/2/4 Feedback ADC GH3 Dead Time VCC VREF DAC + LX3 Hybrid DPWM Digital PID Gate Driver GL3 PVOUT3 + PGND3 Current ADC SS & PD Channel 4 VOUT4 Vout1 4uA Vout2 Vout3 Internal POR ENABLE MUX GPIO 0-1 GPIO NVM (FLASH) Sequencing PSIO 0-2 PSIO Configuration Registers PWR Good SDA,SCL I2C LOGIC CLOCK Fault Handling OTP UVLO OCP OVP Vout4 Vtj VCC 5V LDO LDO5 Figure 4 XRP9711 Block Diagram (c) 2014 Exar Corporation 10/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module 1 NC 2 4 NC 5 NC 6 NC NC PVOUT3 PGND3 30 31 28 LX3 LX3 PVIN PVIN 35 36 37 38 AGND AGND LX4 PGND4 40 41 LX4 PVOUT4 44 LX4 45 PVOUT4 PVIN PVIN 29 32 33 34 LDO5 7 8 9 39 NC 10 ENABLE 11 PSIO2 NC 27 PSIO1 NC 26 3 LX3 NC 25 24 NC PVOUT3 XRP9710 PIN ASSIGNMENT 42 43 14 15 16 17 18 19 20 21 22 23 VOUT3- VOUT4+ VOUT4- GPIO0 GPIO1 SDA SCL PSIO0 13 VOUT3+ 12 AGND VCC AGND AGND Figure 5 XRP9710 Pin Assignment, Top View (c) 2014 Exar Corporation 11/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module XRP9710 PIN DESCRIPTION Pin # Name Description 1-10 NC 11 ENABLE Enable. If ENABLE is pulled high or allowed to float high, the chip is powered up. The pin must be held low for the XRP9710 to be placed into shutdown. 12 VCC Controller Supply Voltage. Place a decoupling capacitor close to the controller IC. This input is used in UVLO fault generation. 13 AGND 14 AGND No Connect Analog Ground. This is the small signal ground connection. Analog Ground. This is the small signal ground connection. 15 VOUT3+ Feedback Pin. Positive input of remote sensing differential amplifier. Connect to the remote voltage load, positive terminal. 16 VOUT3- Feedback Pin. Negative input of remote sensing differential amplifier. Connect to the remote voltage load, negative terminal. 17 VOUT4+ Feedback Pin. Positive input of remote sensing differential amplifier. Connect to the remote voltage load, positive terminal. 18 VOUT4- Feedback Pin. Negative input of remote sensing differential amplifier. Connect to the remote voltage load, negative terminal. 19 GPIO0 I/O Logic Signal. Can be configured as input or output. 20 GPIO1 I/O Logic Signal. Can be configured as input or output. 21 SDA I2C Data. SMBus/I2C serial interface communication. 22 SCL I2C Clock. SMBus/I2C serial interface communication. 23 PSIO0 24 PVOUT3 25 PVOUT3 Channel Output Power. Output voltage for the internal channel. 26 PGND3 Channel Output Ground. Output ground for the internal channel. I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. Channel Output Power. Output voltage for the internal channel. 27 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 28 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 29 LX3 Switch Node. Switch node of the internal channel. 30 LX3 Switch Node. Switch node of the internal channel. 31 LX3 Switch Node. Switch node of the internal channel. 32 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 33 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 34 LDO5 5V LDO Output. Used internally for power and may also be used for external power. LDO that can remain active while the rest of the IC is in standby mode. 35 AGND Analog Ground. This is the small signal ground connection. 36 AGND Analog Ground. This is the small signal ground connection. 37 LX4 38 PGND4 Channel Output Ground. Output ground for the internal channel. 39 AGND Analog Ground. This is the small signal ground connection. 40 LX4 41 PVOUT4 42 PSIO1 I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. 43 PSIO2 I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. 44 LX4 45 PVOUT4 Switch Node. Switch node of the internal channel. Switch Node. Switch node of the internal channel. Channel Output Power. Output voltage for the internal channel. Switch Node. Switch node of the internal channel. Channel Output Power. Output voltage for the internal channel. (c) 2014 Exar Corporation 12/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module GH2 2 LX2 3 4 GL_RTN2 5 BST1 6 LX1 GL1 24 PVOUT3 PGND3 30 31 LX3 LX3 35 AGND 28 PVIN PVIN 32 33 PVIN PVIN 36 37 38 AGND LX4 PGND4 40 41 LX4 PVOUT4 44 LX4 45 PVOUT4 34 LDO5 7 8 9 39 GL_RTN1 10 ENABLE 11 PSIO2 GH1 27 PSIO1 GL2 26 25 29 1 LX3 BST2 PVOUT3 XRP9711 PIN ASSIGNMENT 42 43 14 15 16 17 18 19 20 21 22 23 VOUT2 VOUT3 VOUT4 GPIO0 GPIO1 SDA SCL PSIO0 13 VOUT1 12 AGND VCC AGND AGND Figure 6 XRP9711 Pin Assignment, Top View (c) 2014 Exar Corporation 13/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module XRP9711 PIN DESCRIPTION Pin # Name 1 BST2 Description 2 GH2 High Side Gate Drive Out. Connect directly to the gate of an external N-channel MOSFET. 3 LX2 Switch Node. Return for the high-side gate driver. Connect directly to the drain of the lower FET. Also used to measure voltage drop across bottom MOSFETs 4 GL2 Low Side Gate Drive Out. Connect directly to the gate of an external N-channel MOSFET. 5 GL_RTN2 6 BST1 7 GH1 High Side Gate Drive Out. Connect directly to the gate of an external N-channel MOSFET. 8 LX1 Switch Node. Return for the high-side gate driver. Connect directly to the drain of the lower FET. Also used to measure voltage drop across bottom MOSFETs 9 GL1 Low Side Gate Drive Out. Connect directly to the gate of an external N-channel MOSFET. 10 GL_RTN1 Low Side Gate Drive Return. This should be routed as a differential trace with GL. Connect to the source of the low side MOSFET. 11 ENABLE Enable. If ENABLE is pulled high or allowed to float high, the chip is powered up. The pin must be held low for the XRP9711 to be placed into shutdown. 12 VCC Controller Supply Voltage. Place a decoupling capacitor close to the controller IC. This input is used in UVLO fault generation. 13 AGND Analog Ground. This is the small signal ground connection. 14 AGND Analog Ground. This is the small signal ground connection. 15 VOUT1 Feedback Pin. Connect to the output of the corresponding power stage 16 VOUT2 Feedback Pin. Connect to the output of the corresponding power stage 17 VOUT3 Feedback Pin. Connect to the output of the corresponding power stage 18 VOUT4 Feedback Pin. Connect to the output of the corresponding power stage 19 GPIO0 I/O Logic Signal. Can be configured as input or output. 20 GPIO1 I/O Logic Signal. Can be configured as input or output. 21 SDA I2C Data. SMBus/I2C serial interface communication. 22 SCL I2C Clock. SMBus/I2C serial interface communication. 23 PSIO0 24 PVOUT3 25 PVOUT3 Channel Output Power. Output voltage for the internal channel. 26 PGND3 Channel Output Ground. Output ground for the internal channel. Boost pin. High side driver supply input. Low Side Gate Drive Return. This should be routed as a differential trace with GL. Connect to the source of the low side MOSFET. Boost pin. High side driver supply input. I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. Channel Output Power. Output voltage for the internal channel. 27 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 28 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 29 LX3 Switch Node. Switch node of the internal channel. 30 LX3 Switch Node. Switch node of the internal channel. 31 LX3 Switch Node. Switch node of the internal channel. 32 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 33 PVIN Channel Input Power. Internally connected to drain of upper switching MOSFET 34 LDO5 5V LDO Output. Used internally for power and may also be used for external power. LDO that can remain active while the rest of the IC is in standby mode. 35 AGND Analog Ground. This is the small signal ground connection. 36 AGND Analog Ground. This is the small signal ground connection. 37 LX4 38 PGND4 Channel Output Ground. Output ground for the internal channel. 39 AGND Analog Ground. This is the small signal ground connection. 40 LX4 41 PVOUT4 Switch Node. Switch node of the internal channel. Switch Node. Switch node of the internal channel. Channel Output Power. Output voltage for the internal channel. (c) 2014 Exar Corporation 14/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module Pin # Name Description 42 PSIO1 I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. 43 PSIO2 I/O Logic Signal, HV. Open drain, high voltage compliant. Can be configured as input or output. 44 LX4 45 PVOUT4 Switch Node. Switch node of the internal channel. Channel Output Power. Output voltage for the internal channel. ORDERING INFORMATION Part Number Temperature Range Marking Package Packing Quantity Note 1 I2C Default Address 9710EY Tray FWWYY XRP9710EYTR-F Lot # 12x12mm 2.5K/Tape & Reel 0x28 (7Bit) Halogen Free -40CTJ+125C LGA 9711EY XRP9711EY-F Tray FWWYY XRP9711EYTR-F 2.5K/Tape & Reel Lot # Evaluation kit includes XRP9710EVB-DEMO-1 Evaluation Board with Power XRP9710EVB-DEMO-1-KIT Architect software and controller board Evaluation kit includes XRP9711EVB-DEMO-1 Evaluation Board with Power XRP9711EVB-DEMO-1-KIT Architect software and controller board XRP9710EY-F "F" denotes "-F" part number suffix - "YY" = Year - "WW" = Work Week (c) 2014 Exar Corporation 15/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VCC = 12V, TJ = TA = 25C, unless otherwise specified - Schematic and BOM from XRP9711EVB. See XRP9711EVB-DEMO-1 Manual. Figure 7 PFM to PWM Transition Figure 8 PWM to PFM Transition Figure 9 0-6A Transient 300kHz PWM only Figure 10 0-6A Transient 300kHz with OVS 5.5% Figure 11 Sequential Start-up Figure 12 Sequential Shut Down (c) 2014 Exar Corporation 16/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module Figure 13 Simultaneous Start-up Figure14 Simultaneous Shut Down Figure15 PFM Zero Current Accuracy Figure16 LDO5 Brown Out Recovery, No Load 1.00 0.95 0.90 Vcc Vin=25V Rising 0.85 Vcc Vin=25V Falling 0.80 0.75 Vcc Vin=4.75 V Rising 0.70 Vcc Vin=4.75 V Falling 0.65 0.60 -40C 25C 85C 125C Figure 17 Enable Threshold Over Temp (c) 2014 Exar Corporation Figure 18 Package Thermal Derating 17/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module Power Dissipation (W) 3.0 2.0 Power Dissipation (W) 3.3 1.5 1.8 2.0 1.0 1.0 5.0 3.3 1.8 1.0 2.5 1.5 1.0 0.5 0.5 0.0 0.0 0 1 2 3 Io (A) 4 5 0 6 Figure 19 Vin = 5V Power Dissipation 1 2 3 Io (A) 4 5 6 Figure 20 Vin = 12V Power Dissipation Figure 21 Efficiency, 12VIN, 600kHz (c) 2014 Exar Corporation 18/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module FUNCTIONAL OVERVIEW The primary benefit of these modules is the ultra small footprint and height, but these come with a full suite of advanced power management capabilities. All outputs are independently programmable which provides the user full control of the delay, ramp rate, and sequence during power up and power down. The user may also control how the outputs interact and power down in the event of a fault. This includes active ramp down of the output voltages to take down an output voltage as quickly as possible. Another useful feature is that the outputs can be defined and controlled as groups. The XRP9710 is a digital pulse width modulation (DPWM) power module with two 6A converters. In addition, the XRP9711 provides two additional PWM controller outputs which can directly drive external power stage. Each output voltage can be programmed from 0.6V to 5.5V without the need for an external voltage divider. The wide range of programmable DPWM switching frequencies (from 124 kHz to 1.23 MHz) enables the user to optimize for efficiency or component sizes. Since the digital regulation loop requires no external passive components, loop performance is not compromised due to external component variation or operating conditions. The XRP9710/1 has two main types of programmable memory. The first type is runtime registers that contain configuration, control and monitoring information for the chip. The second type is rewritable NonVolatile Flash Memory (NVFM) that is used for permanent storage of the configuration data along with various chip internal functions. During power up, the run time registers are loaded from the NVFM allowing for standalone operation. The XRP9710/1 provides a number of critical safety features, such as Over-Current Protection (OCP), Over-Voltage Protection (OVP), Over-Temperature Protection (OTP) plus input Under-Voltage Lockout (UVLO). In addition, a number of key health monitoring features including warning level flags for the safety functions, Power Good (PGOOD), plus full monitoring of system voltages and currents. The above are all programmable and/or readable from the SMBus and many are steerable to the GPIOs for hardware monitoring. The XRP9710/1 brings an extremely high level of functionality and performance to a programmable power system. Ever decreasing product budgets require the designer to quickly analyze cost/performance tradeoffs to be truly successful. By incorporating four switching channels, a user LDO, and internal gate drivers, all in a single package, the XRP9710/1 allows for extremely cost effective power system designs. Another key cost factor that is often overlooked is the unanticipated Engineering Change Order (ECO). The programmable versatility of the XRP9710/1, along with the lack of hard wired, on board configuration components, allows for minor and major changes to be made on the board by simple reprogramming. For hardware communication, the XRP9710/1 has two logic level General Purpose InputOutput (GPIO) pins and three, 15V, opendrain, Power System Input-Output (PSIO) pins. Two pins are dedicated to the SMBus data (SDA) and clock (SCL). The 5V LDO is used for internal power and is also optionally available to power external circuitry. (c) 2014 Exar Corporation 19/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module THEORY OF OPERATION CHIP ARCHITECTURE REGULATION LOOPS Vin (VCC) Vref DAC VFB (VOUTx) Scalar /1,2,4 AFE Error Amp AFE ADC Window Comp. Fine Adjust Vin Feed Forward Error Register PID Vdrive (VCCD)x DPWM Gate Driver GHx GLx LXx Current ADC OVS PFM/ Ultrasonic PWMPFM Sel Figure 22 XRP9710 Regulation Loops Figure 22 shows a functional block diagram of the regulation loops for an output channel. There are four separate parallel control loops; Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), Ultrasonic, and Over Sampling (OVS). Each of these loops is fed by the Analog Front End (AFE) as shown at the left of the diagram. The AFE consist of an input voltage scaler, a programmable Voltage Reference (Vref) DAC, Error Amplifier, and a window comparator. (Please note that the block diagram shown is simplified for ease of understanding. Some of the functional blocks are common and shared by each channel by means of a multiplexer.) voltages up to 1.6V (low range) the scaler has a gain of 1. For output voltages from 1.6V to 3.2V (mid range) the scaler gain is 1/2 and for voltages greater than 3.2V (high range) the gain is 1/4. This results in the low range having a reference voltage resolution of 12.5mV, the mid range having a resolution of 25mV and the high range having a resolution of 50mV. The error amp has a gain of 4 and compares the output voltage of the scaler to Vref to create an error voltage on its output. This is converted to a digital error term by the AFE ADC and is stored in the error register. The error register has a fine adjust function that can be used to improve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mV, a mid range resolution of 5mV and a high range resolution of 10mV. The output of the error register is then used by the Proportional Integral Derivative (PID) controller to manage the loop dynamics. PWM Loop The PWM loop operates in Voltage Control Mode (VCM) with optional VIN feed forward based on the voltage at the VCC pin. The reference voltage (Vref) for the error amp is generated by a 0.15V to 1.6V DAC that has a 12.5mV resolution. In order to provide a full 0.6V to 5.5V output voltage range, an input scaler is used to reduce feedback voltages for higher output voltages to bring them within the 0.15V to 1.6V control range. So for output (c) 2014 Exar Corporation The XRP9710/1 PID is a 17-bit five-coefficient control engine that calculates the required duty cycle under the various operating conditions and feeds it to the Digital Pulse Width Modulator (DPWM). Besides the normal 20/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module coefficients the PID also uses the VIN voltage to provide a feed forward function. The PFM loop works in conjunction with the PWM loop and is entered when the output current falls below a programmed threshold level for a programmed number of cycles. When PFM mode is entered, the PWM loop is disabled and instead, the scaled output voltage is compared to Vref with a window comparator. The window comparator has three thresholds; normal (Vref), high (Vref + %high) and low (Vref - %low). The %high and %low values are programmable and track Vref. The XRP9710/1 DPWM includes a special delay timing loop that provides a timing resolution that is 16 times the master oscillator frequency (103MHz) for a timing resolution of 607ps for both the driver pulse width and dead time delays. The DWPM produces the Gate High (GH) and Gate Low (GL) signals for the driver. The maximum and minimum on-times and dead time delays are programmable by configuration resisters. In PFM mode, the normal comparator is used to regulate the output voltage. If the output voltage falls below the Vref level, the comparator is activated and triggers the DPWM to start a switching cycle. When the high side FET is turned on, the inductor current ramps up which charges up the output capacitors and increases their voltage. After the completion of the high side and low side on-times, the lower FET is turned off to inhibit any inductor reverse current flow. The load current then discharges the output capacitors until the output voltage falls below Vref and the normal comparator is activated. This triggers the DPWM to start the next switching cycle. The time from the end of the switching cycle to the next trigger is referred to as the dead zone. When PFM mode is initially entered the switching duty cycle is equal to the steady-state PWM duty cycle. This will cause the inductor ripple current to be the same level that it was in PWM mode. During operation the PFM duty cycle is calculated based on the ratio of the output voltage to VCC. This method ensures that the output voltage ripple is well controlled and is much lower than other architectures which use a "burst" methodology. To provide current information, the output inductor current is measured by a differential amplifier that reads the voltage drop across the RDS of the lower FET during its on time. There are two selectable ranges, a low range with a gain of 8 for a +20mV to -120 mV range, and a high range with a gain of 4 for a +40mV to -280mV range. The optimum range to use will depend on the maximum output current and the RDS of the lower FET. The measured voltage is then converted to a digital value by the current ADC block. The resulting current value is stored in a readable register, and also used to determine when PWM to PFM transitions should occur. PFM mode loop The XRP9710/1 has a PFM loop that can be enabled to improve efficiency at light loads. By reducing switching frequency and operating in the discontinuous conduction mode (DCM), both switching and I2R losses are minimized. Figure 23 shows a functional diagram of the PFM logic. # Cycles Reg Default = 20 A CHx Fsw PFM Current Threshold Reg A Clk COUNTER Clear A<B If the output voltage goes outside the high/low windows, PFM mode is exited and the PWM loop is reactivated. B A<B IADC B VOUT VREF HIGH + - - VREF + VREF LOW + S Q R Q PFM EXIT PWM MODE PFM MODE TRIGGER PULSE - Figure 23 PFM Enter/Exit Functional Diagram (c) 2014 Exar Corporation 21/36 Although the PFM mode is effective at improving efficiency at light load, at very light loads the dead zone time can increase to the point where the switching frequency can enter the audio hearing range. When this happens some components, like the output inductor and ceramic capacitors, can emit audible Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module noise. The amplitude of the noise depends mainly on the board design and on the manufacturer and construction details of the components. Proper selection of components can reduce the sound to very low levels. In general Ultrasonic Mode is not used unless required as it reduces light load efficiency. level. Depending on where in the switching cycle the load step happens there can be a delay of up to one switching cycle before the control loop can respond. With OVS enabled if the output voltage drops below the lower level, an immediate GH pulse will be generated and sent to the driver to increase the output inductor current toward the new load level without having to wait for the next cycle to begin. If the output voltage is still below the lower limit at the beginning of the next cycle, OVS will work in conjunction with the PID to insert additional GH pulses to quickly return the output voltage back within its regulation band. The result of this system is transient response capabilities on par or exceeding those of a constant on-time control loop. Ultrasonic Mode Ultrasonic mode is an extension of PFM to ensure that the switching frequency never enters the audible range. When this mode is entered, the switching frequency is set to 30kHz and the duty cycle of the upper and lower FETs, which are fixed in PFM mode, are decreased as required to keep the output voltage in regulation while maintaining the 30kHz switching frequency. Over Voltage OVS: When there is a step load current decrease, the output voltage will increase (bump up) as the excess inductor current that is no longer used by the load flows into the output capacitors causing the output voltage to rise. The voltage will continue to rise until the inductor current decreases to the new load current. With OVS enabled, if the output voltage exceeds the high limit of the window comparator, a blanking pulse is generated to truncate the GH signal. This causes inductor current to immediately begin decreasing to the new load level. The GH signal will continue to be blanked until the output voltage falls below the high limit. Again, since the output voltage is sampled at four times the switching frequency, over shoot will be decreased and the time required to get back into the regulation band is also decreased. Under extremely light or zero load currents, the GH on time pulse width can decrease to its minimum width. When this happens, the lower FET on time is increased slightly to allow a small amount of reverse inductor current to flow back into VIN to keep the output voltage in regulation while maintaining the switching frequency above the audio range. Oversampling OVS Mode Oversampling (OVS) mode is a feature added to the XRP9711 to improve transient response for the two external channels. This mode can only be enabled when the channel switching frequency is operating in 1x frequency mode. In OVS mode the output voltage is sampled four times per switching cycle and is monitored by the AFE window comparators. If the voltage goes outside the set high or low limits, the OVS control electronics can immediately modify the pulse width of the GH or GL drivers to respond accordingly, without having to wait for the next cycle to start. OVS has two types of response depending on whether the high limit is exceeded during an unloading transient (Over Voltage), or the low limit is exceeded during a loading transient (Under Voltage). OVS can be used in conjunction with both the PWM and PFM operating modes. When it is activated it can noticeably decrease output voltage excursions when transitioning between PWM and PFM modes. Under Voltage OVS: If there is an increasing current load step, the output voltage will drop until the regulator loop adapts to the new conditions to return the voltage to the correct (c) 2014 Exar Corporation 22/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module LDOS approximately 20mA and the rest is the gate drive currents. During initial power up, the maximum external load should be limited to 30mA. The XRP9710/1 has an internal Low Drop-Out (LDO) linear regulator that generates 5.0V (LDO5) for both internal and external use. LDO5 is the main power input to the device and is supplied by an external 5.5V to 25V VCC supply. The 5V output is used by the XRP9710/1 as a standby power supply and supply power to the 5V gate drivers. The total output current that the 5V LDO can provide is 130mA. The XRP9710/1 consumes For operation with a VCC of 4.75V to 5.5V, the LDO5 output needs to be connected directly to VCC on the board. CLOCKS AND TIMING /4//8 Reg Ext Clock Input GPIO0 PLL x4/x8 Reg Clock Divider Ext Clock Output GPIO1 Freg Mult Reg DPWM System Clock Base Frequency 2x Frequency Set Reg 4x SEL CH1 Timing Sequencer To Channels 24 Figure 24 XRP9710 Timing Block Diagram To set the base frequency for the output channels, an "Fsw_Set" value representing the base frequency shown in Table 1, is entered into the switching frequency configuration register. Note that Fsw_Set value is basically equal to the Sys_Clk divided by the base frequency. The system timing is then created by dividing down Sys_Clk to produce a base frequency clock, 2X and 4X times the base frequency clocks, and sequencing timing to position the output channels relative to each other. Each output channel then has its own frequency multiplier register that is used to select its final output switching frequency. Figure 24 shows a simplified block diagram of the XRP9710/1 timing. Again, please note that the function blocks and signal names used are chosen for ease of understanding and do not necessarily reflect the actual design. The system timing is generated by a 103MHz internal system clock (Sys_Clk). There are two ways that the 103MHz system clock can be generated. These include an internal oscillator and a Phase Locked Loop (PLL) that is synchronized to an external clock input. The basic timing architecture is to divide the Sys_Clk down to create a fundamental switching frequency (Fsw_Fund) for all the output channels that is settable from 124kHz to 306kHz. The switching frequency for a channel (Fsw_CHx) can then be selected as 1 time, 2 times or 4 times the fundamental switching frequency. (c) 2014 Exar Corporation Table 1 shows the available channel switching frequencies for the XRP9710/1 device. The shaded areas show the allowable frequencies of the internal power stages. In practice the PowerArchitectTM 5.1 (PA 5.1) design tool 23/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module handles all the details and the user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency multiplier for each channel. If an external clock is used, the frequencies in this table will shift accordingly. Base Frequency kHz Available 2x Frequencies kHz Available 4x Frequencies kHz 123.8 126.2 128.8 131.4 134.1 137.0 139.9 143.1 146.3 149.7 153.3 157.0 160.9 165.1 169.4 174.0 178.8 183.9 189.3 247.6 257.5 268.2 279.9 292.6 306.5 247.6 252.5 257.5 262.8 268.2 273.9 279.9 286.1 292.6 299.4 306.5 314.0 321.9 330.1 338.8 348.0 357.6 367.9 378.7 495.2 515.0 536.5 559.8 585.2 613.1 495.2 504.9 515.0 525.5 536.5 547.9 559.8 572.2 585.2 598.8 613.1 628.0 643.8 660.3 677.6 695.9 715.3 735.7 757.4 990.4 1030.0 1072.9 1119.6 1170.5 1226.2 Table 1 (c) 2014 Exar Corporation 24/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module SUPERVISORY AND CONTROL Configuring GPIO/PSIOs Power system design with XRP9710/1 is accomplished using PA 5.1 design tool. All figures referenced in the following sections are taken from PA 5.1. Furthermore, the following sections reference I2C commands. For more information on these commands, refer to ANP-38. XRP9710/1 is supported with the commands listed in ANP-38 with the exception of XRP9710 using only the channel 3 and 4 related commands. The following functions can be controlled from or forwarded to any GPIO/PSIO: DIGITAL I/O XRP9710/1 has two General Purpose Input Output (GPIO) and three Power System Input Output (PSIO) user configurable pins. * General Output - set with command an I2C * General Input - triggers an interrupt; state read with an I2C command * Power Group Enable - controls enabling and disabling of Group 1 and Group 2. * Power Channel Enable - controls enabling and disabling of an individual channel. * I2C Address Bit - controls an I2C address bit. * Power OK - indicates that selected channels have reached their target levels and have not faulted. Multiple channel selection is available, in which case the resulting signal is the AND logic function of all channels selected. * GPIOs are 3.3V CMOS logic compatible and 5V tolerant. * PSIOs which configured as outputs are open drain and require external pull-up resistors. These I/Os are 3.3V and 5V CMOS logic compatible, and up to 15V capable. * ResetOut - is delayed Power OK. Delay is programmable in 1msec increments with the range of 0 to 255 msecs. The polarity of the GPIO/PSIO pins is set in PA 5.1 or with an I2C command. * Low Vcc - indicates when Vcc has fallen below the UVLO fault threshold and when the UVLO condition clears (Vcc voltage rises above the UVLO warning level). * Interrupt - the controller generated interrupt selection and clearing is done through I2C commands. Interrupt, Low Vcc, Power OK and ResetOut signals can only be forwarded to a single GPIO/PSIO. In addition, the following are functions that are unique to GPIO0 and GPIO1. (c) 2014 Exar Corporation 25/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module voltage against its user defined Power Good threshold limits (Power Good minimum and maximum levels). It has no hysteresis. Multiple channel selections will be combined using the AND logic function of all channels selected. The Power Good minimum and maximum levels are expressed as percentages of the target voltage. * HW Flags - these are hardware monitoring functions forwarded to GPIO0 only. The functions include Under-Voltage Warning, OverTemperature Warning, Over-Voltage Fault, Over-Current Fault and Over Current Warning for every channel. Multiple selections will be combined using the OR logic function. "PGood Max" is the upper window and "PGood Min" is the lower window. The minimum and maximum for each of these values can be calculated with the following equation: (%) = * External Clock-in - enables the controller to lock to an external clock including one from another XRP9710/1 applied to the GPIO0 pin. There are two ranges of clock frequencies the controller accepts, selectable by a user. () 105 () Where N=1 to 63 for the PGOOD Max value and N=1 to 62 for the PGOOD Min value. For example, with the target voltage of 1.5V and set point resolution of 2.5mV (LSB), the Power Good min and max values can range from 0.17% to 10.3% and 0.17% to 10.5% respectively. A user can effectively double the range by changing to the next higher output voltage range setting, but at the expense of reduced set point resolution. * External Clock-out - clock sent out through GPIO1 for synchronizing with another XRP9710/1 (see the clock out section for more information). FAULT HANDLING There are six different types of fault handling: * HW Power Good - the Power Good hardware monitoring function. It can only be forwarded to GPIO1. This is an output voltage monitoring function that is a hardware comparison of channel output (c) 2014 Exar Corporation * Under Voltage Lockout (UVLO) monitors voltage supplied to the Vcc pin and will cause the controller to shut down 26/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module * * * * * all channels if the supply drops to critical levels. Over Temperature Protection (OTP) monitors temperature of the chip and will cause the controller to shut down all channels if temperature rises to critical levels. Over Voltage Protection (OVP) monitors regulated voltage of a channel and will cause the controller to react in a user specified way if the regulated voltage surpasses threshold level. Over Current Protection (OCP) monitors current of a channel and will cause the controller to react in a user specified way if the current level surpasses threshold level. Start-up Time-out Fault monitors whether a channel gets into regulation in a user defined time period LDO5 Over Current Protection (LDO5 OCP) monitors current drawn from the regulator and will cause the controller to be reset if the current exceeds LDO5 limit warning level), the Low Vcc signal will transition and the controller will be reset. Special attention needs to be paid in the case when Vcc = LDO5 = 4.75V to 5.5V. Since the input voltage ADC resolution is 200mV, the UVLO warning and fault set points are coarse for a 5V input. Therefore, setting the warning level at 4.8V and the fault level at 4.6V may result in the outputs not being re-enabled until a full 5.0V is reached on Vcc. Setting the warning level to 4.6V and the fault level at 4.4V would likely make UVLO handing as desired; however, at a fault level below 4.6V the device has a hardware UVLO on LDO5 to ensure proper shutdown of the internal circuitry of the controller. This means the 4.4V UVLO fault level may never occur. OTP User defined OTP warning, fault and restart levels are set at 5C increments in PA 5.1. UVLO When the warning level is reached controller will generate TEMP_WARNING_EVENT interrupt. addition, the host can be informed about event through HW Flags on GPIO0 (see Digital I/O section). Both UVLO warning and fault levels are user programmable and set at 200mV increments in PA 5.1. When the warning level is reached controller will generate UVLO_WARNING_EVENT interrupt. addition, the host can be informed about event through HW Flags on GPIO0 (see Digital I/O section). When an OTP fault condition occurs, the XRP9710/1 outputs are shut down and the TEMP_OVER_EVENT interrupt is generated. the the In the the Once temperature reaches a user defined OTP Restart Threshold level, the TEMP_UNDER_EVENT interrupt will be generated and the controller will reset. When an under voltage fault condition occurs, the XRP9710/1 outputs are shut down and the UVLO_FAULT_ACTIVE_EVENT interrupt is generated. In addition, the host can be informed by forwarding the Low Vcc signal to any GPIO/PSIO (see the Digital I/O section). This signal transitions when the UVLO fault occurs. When coming out of the fault, rising Vcc crossing the UVLO fault level will trigger the UVLO_FAULT_INACTIVE_EVENT interrupt. OVP A user defined OVP fault level is set in PA 5.1 and is expressed in percentages of a regulated target voltage. Resolution is the same as for the target voltage (expressed in percentages). The OVP minimum and maximum values are calculated Once the UVLO condition clears (Vcc voltage rises above or to the user-defined UVLO (c) 2014 Exar Corporation the the In the the 27/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module by the following equation where the range for N is 1 to 63: (%) = () 105 () When the OVP level is reached and the fault is generated, the host will be notified by the SUPPLY_FAULT_EVENT interrupt generated by the controller. The host then can use an I2C command to check which channel is at fault. In addition, OVP fault can be monitored through GPIO0. A user can choose one of three options in response to an OVP event: shutdown the faulting channel, shut down faulting channel and perform auto-restart of the channel, or restart the chip. Note: The Channel Fault Action response is the same for an OVP or OCP event. OCP A user defined OCP fault level is set with 10 mA increments in PA 5.1. PA 5.1 uses calculations to give the user the approximate DC output current entered in the current limit field. However the actual current limit trip value programmed into the part is limited to 280mV as defined in the electrical characteristics. The maximum value the user can program is limited by Rdson of the synchronous Power FET and current monitoring ADC range. For example, using a synchronous FET with RDSON of 30m, and the wider ADC range, the maximum current limit programmed would be: In the case of shutting down the faulting channel and auto-restarting, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. () = 280 = 9.33 30 The current is sampled approximately 30ns before the low side MOSFET turns off, so the actual measured DC output current in this example would be 9.33A plus approximately half the inductor ripple. An OCP Fault is considered to have occurred only if the fault threshold has been tripped in four consecutive switching cycles. When the switching frequency is set to the 4x multiplier, the current is sampled only every other cycle. As a result it can take as many as eight switching cycles for an over current event to (c) 2014 Exar Corporation 28/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module Start-up Time-out Fault be detected. When operating in 4x mode an inductor with a soft saturation characteristic is recommended. A channel will be at Startup Timeout Fault if it does not come-up in the time period specified in the "Startup Timeout" box. In addition, a channel is at Startup Timeout Fault if its prebias configuration voltage is within a defined value too close to the target. When the OCP level is reached and the fault is generated, the host will be notified by the SUPPLY_FAULT_EVENT interrupt generated by the controller. The host then can use an I2C command to check which channel is at fault. When the fault is generated, the host will be notified by the SUPPLY_FAULT_EVENT interrupt generated by the controller. The host then can use an I2C command to check which channel is at fault. In addition, OCP faults can be monitored through HW Flags on GPIO0. The host can also monitor the OCP warning flag through HW Flags on GPIO0. The OCP warning level is calculated by PA 5.1 as 85% of the OCP fault level. LDO5 OCP A user can choose one of three options in response to an OCP event: shutdown the faulting channel, shut down faulting channel and perform auto-restart of the channel, or restart the chip. When current is drawn from the LDO5 that exceeds the LDO5 current limit the controller will be reset. The output current reported by the XRP9710/1 is processed through a seven sample median filter in order to reduce noise. The OCP limit is compared against unfiltered ADC output. EXTERNAL CLOCK SYNCHRONIZATION XRP9710/1 can be run off an external clock available in the system or another XRP9710/1. The external clock must be in the ranges of 10.9MHz to 14.7MHz or 21.8MHz to 29.6MHz. Locking to the external clock is done through an internal Phase Lock Loop (PLL). The external clock must be routed to GPIO0. The GPIO0 setting must reflect the range of the external clock applied to it: Sys_Clock/8 corresponds to the range of 10.9MHz to 14.7MHz while Sys_Clock/4 setting corresponds to the range of 21.8Mhz to 29.6MHz. The functionality is enabled in PA 5.1 by selecting External Clock-in function under GPIO0. For the case of Shutdown and Auto-restart Channel, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. For more details on how to monitor PLL lock in-out, please contact Exar or your local Exar representative. Note: The Channel Fault Action response is the same for an OVP or OCP event. (c) 2014 Exar Corporation 29/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module CLOCK OUT XRP9710/1 can supply clock out to be used by another XRP9710/1 controller. The clock is routed out through GPIO1 and can be set to system clock divided by 8 (Sys_Clock/8) or system clock divided by 4 (Sys_Clock/4) frequencies. The functionality is enabled in PA 5.1 by selecting External Clock-Out function under GPIO1. CHANNEL CONTROL Channels can be controlled independently by any GPIO/PSIO or I2C command. Channels will start-up or shut-down following transitions of signals applied to GPIO/PSIOs set to control the channels. The control can always be overridden with an I2C command. Regardless of whether the channels are controlled independently or are in a group, the ramp rates will be followed as specified (see the Power Sequencing section). Regulated voltages and voltage drops across the synchronous FET on each switching channel can be read back using I2C commands. The regulated voltage read back resolution is 15mV, 30mV and 60mV per LSB depending on the target voltage range. The voltage drop across synchronous FET read back resolution is 1.25mV and 2.5mV per LSB depending on the range. POWER SEQUENCING All channels can be grouped together and will start-up and shut-down in a user defined sequence. Selecting none means the channel will not be assigned to any group and therefore will be controlled independently. Through an I2C command the host can check the status of the channels; whether they are in regulation or at fault. Group Selection Regulated voltages can be dynamically changed on switching channels using I2C commands with resolution of 2.5mV, 5mV and 10mV depending on the target voltage range (in PWM mode only). There are three groups: 2 For more information on I C commands please refer to ANP-38 or contact Exar or your local Exar representative. (c) 2014 Exar Corporation * Group 0 - is controlled by the chip ENABLE or an I2C command. Channels assigned to this group will come up with the ENABLE signal being high (plus additional delay needed to load configuration from Flash to run-time 30/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module Shut-down registers), and will go down with the ENABLE signal being low. The control can always be overridden with an I2C command. Since it is recommended to leave the ENABLE pin floating in the applications when Vcc = LDO5 = 4.75V to 5.5V, please contact Exar for how to configure the channels to come up at the power up in this scenario. For each channel within a group a user can specify the following shut-down characteristics: * Ramp Rate - expressed in milliseconds per volt. * Order - position of a channel to comedown within the group * Wait Stop Thresh? - selecting this option for a channel means the next channel in the order will not start ramping-down until this channel reaches the Stop Threshold level. The stop threshold level is fixed at 600mV. * Delay - additional time delay a user can specify to postpone a channel shut-down with respect to the previous channel in the order. The delay is expressed in milliseconds with a range of 0msec to 255msec. * Group 1 - can be controlled by any GPIO/PSIO or I2C command. Channels assigned to this group will start-up or shut-down following transitions of a signal applied to the GPIO/PSIO set to control the group. The control can always be overridden with an I2C command. * Group 2 - can be controlled by any GPIO/PSIO or I2C command. Channels assigned to this group will start-up or shut-down following transitions of a signal applied to the GPIO/PSIO set to control the group. The control can always be overridden with an I2C command. Start-up MONITORING VCC AND TEMPERATURE Through I2C commands, the host can read back the voltage applied to the Vcc pin and the die temperature respectively. The Vcc read back resolution is 200mV per LSB; the die temperature read back resolution is 5C per LSB. For more on I2C commands please refer to ANP-38. For each channel within a group, a user can specify the following start-up characteristics: * Ramp Rate - expressed in milliseconds per volt. * Order - position of a channel to come-up within the group * Wait PGOOD? - selecting this option for a channel means the next channel in the order will not start ramping-up until this channel reaches the target level and its Power Good flag is asserted. * Delay - an additional time delay a user can specify to postpone a channel start-up with respect to the previous channel in the order. The delay is expressed in milliseconds with a range of 0msec to 255msec. (c) 2014 Exar Corporation PROGRAMMING XRP9710/1 XRP9710/1 is a FLASH based device which means its configuration can be programmed into FLASH NVM and re-programmed a number of times. Programming of FLASH NVM is done through PA 5.1. 31/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module XRP9710 The XRP9710 differs from the XRP9711 in that it eliminates the two external power stages but adds differential voltage sensing of the two remaining outputs. However, the two remaining channels remain designated 3 and 4. Below in the PA 5.1 Dashboard, one can see Channels 1 and 2 grayed out when using a XRP9710. This methodology also ensures code development is easily ported between the two devices. By clicking on the Flash button, the user will start the programming sequence of the design configuration into the Flash NVM. After the programming sequence completes, the chip will reset (if automatically reset After Flashing box is checked) and boot the design configuration from the Flash. Users who wish to create their own programming procedure so they can reprogram Flash in-circuit using their system software should contact Exar for a list of needed I2C Flash Commands. (c) 2014 Exar Corporation 32/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module ENABLING XRP9710/1 XRP9710/1 has a weak internal pull-up ensuring it becomes enabled as soon as internal voltage supplies have ramped up and are in regulation. Driving the Enable pin low externally will keep the controller in the shut-down mode. A simple open drain pull down is the recommended way to shut XRP9710/1 down. If the Enable pin is driven high externally to control XRP9710/1 coming out of the shutdown mode, care must be taken to ensure the Enable pin is driven high after Vcc gets supplied to the controller. No load on LDO5, blue trace. Recovery time after the ENABLE logic high is approximately 40ms. In the configuration when Vcc = LDO5 = 4.75V to 5.5V, disabling the device by grounding the Enable pin is not recommended. It is recommended to leave the Enable pin floating and place the controller in the "Standby Mode" instead in this scenario. The standby mode is defined as the state when all switching channels are disabled, all GPIO/PSIOs are programmed as inputs, and the system clock is disabled. In this state the device consumes 440uA typically. Short duration Enable pin toggled low Short duration shutdown pulses to the ENABLE pin of the XRP9710/1, which do not provide sufficient time for the LDO5 voltage to fall below 3.5V, can result in significant delay in re-enabling of the device. Some examples below show LDO5 and ENABLE pins: Adding a 200 ohm load on LDO5 pulls the voltage below 3.5V and the restart is short. Note that as VCC increases, the restart time falls as well. A 5.5V input voltage is shown as the worst case. Since the ENABLE pin has an internal current source, a simple open drain pull down is the recommended way to shut down the XRP9710/1. A diode in series with a resistor between the LDO5 and ENABLE pins may offer a way to more quickly pull down the LDO5 output when the ENABLE pin is pulled low. (c) 2014 Exar Corporation 33/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module APPLICATION INFORMATION using Figure 18. Then, based on the design input voltage, use Figures 19 or 20 accordingly. THERMAL DESIGN For example: Proper thermal design is critical in controlling device temperatures and in achieving robust designs. There are a number of factors that affect the thermal performance. One key factor is the temperature rise of the devices in the package, which is a function of the thermal resistances of the devices inside the package and the power being dissipated (PDISS). Consider a two channel design that has a TAMB= 50C, VIN = 12V, VOUT3 = 1V, VOUT4 = 3.3V. Figure 18 shows PPKG max is 4.1 Watts at 50C. The result is that the sum of the power dissipation for both channels must be less than the 4.1W. Figure 20 shows the power dissipation for VIN = 12V designs. If the 1V output current is 6A, then its PDISS is 2.1W. This leaves 2W for the 3.3V channel. The graph shows that at 2W the maximum 3.3V output current would be 4.7A. The thermal resistance of the XRP9710/1 is shown in the "Operating Ratings" section of this datasheet. The JEDEC JA thermal resistance provided is based on tests that comply with the JESD51-2A "Integrated Circuit Thermal Test Method Environmental Conditions - Natural Convection" standard. JESD51-xx are a group of standards whose intent is to provide comparative data based on a standard test condition which includes a defined board construction. Since the actual board design in the final application will be different from the board defined in the standard, the thermal resistances in the final design may be different from those shown. EMI EMISSIONS The XRP9711 has been tested on the evaluation board and passes CISPR22 Level B radiated emissions. LAYOUT GUIDELINES Refer to application note ANP-32 "Practical Layout Guidelines for PowerXR Designs". These apply primarily to the two external power stages available on the XRP9711. The package thermal derating curve is shown in Figure 18. The total package power dissipation (PPKG) is dependent on the final application design for channels three and four, and is the sum of the losses for the two channels. The power losses for a channel will depend mainly on the input voltage, output voltage, and output current. Figure 19 and Figure 20 show the power losses for input voltages of 5V and 12V respectively. Also refer to the XRP9710 or XRP9711 Evaluation Board Manual for specifics in grounding and heat sinking. BOARD ASSEMBLY Detailed boards assembly information specifically to address the unique package requirement is available in ANP-45, LGA Module Assembly Application Note. First, determine the package power derating for a maximum ambient temperature (TAMB) (c) 2014 Exar Corporation 34/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module PACKAGE SPECIFICATION (c) 2014 Exar Corporation 12MMX12MM LGA 35/36 Rev. 1.0.1 XRP9710 and XRP9711 Dual 6A Programmable Power Module REVISION HISTORY Revision Date Description 1.0.0 12/18/2013 Initial Release [ECN: 1352-06] 1.0.1 01/03/2014 Fix minor typographical items for consistency. Formatting updates. [ECN: 1402-03] 1.0.2 01/14/2014 Updated marking information in ordering table FOR FURTHER ASSISTANCE Email: customersupport@exar.com powertechsupport@exar.com Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx? EXAR CORPORATION HEADQUARTERS AND SALES OFFICES 48720 Kato Road Fremont, CA 94538 - USA Tel.: +1 (510) 668-7000 Fax: +1 (510) 668-7030 www.exar.com NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. or its in all Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. (c) 2014 Exar Corporation 36/36 Rev. 1.0.1 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Exar: XRP9711EYTR-F XRP9711EY-F XRP9710EY-F XRP9710EYTR-F XRP9710EVB XRP9711EVB XRP9711EVBDEMO-1-KIT XRP9710EVB-DEMO-1-KITA XRP9710EVB-DEMO-1-KIT