1998 Microchip Technology Inc. DS21208C-page 1
93LC56A/B
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93LC56A)
• 128 x 16 bit organization (93LC56B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRI TE cycle s
• Seque nti al REA D functi on
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
BLOCK DIAGRAM
DESCRIPTION
The Microchip Technology Inc. 93LC56A/B are 2K-bit,
low-voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC56A) or
x16 bits (93LC56B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC56A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC56AX/BX are only offered in a
150-mil SOIC package.
PACKAGE TYPE
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
Vcc
Vss
DI
CS
CLK
DO
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
COUNTER
DATA
REGISTER OUTPUT
BUFFER
MODE
DECODE
CLOCK
GENERATOR
LOGIC
93LC56A/B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
Vcc
NC
NC
Vss
CS
CLK
DI
DO
VCC
NC
NC
Vss
93LC56A/B
NC
Vcc
CS
CLK
NC
Vss
DO
DI
93LC56A/BX
93LC56A/B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
Vcc
NC
NC
Vss
TSSOP
SOICSOIC
1
2
3
4
DIP
8
7
6
5
1
2
3
4
8
7
6
5
2K 2.5V Microwire® Serial EEPROM
Microwire is a registered trademark of National Semiconductor.
93LC56A/B
DS21208C-page 2 1998 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. Vss ...............-0.6V to Vcc +1.0V
Storage temperature..................................... -65°C to +15 0 °C
Ambient temp. with power applied................-65°C to +12 5 °C
Soldering temperature of leads (10 seconds).............+300°C
ESD protec tio n o n all pin s....... ......................... ................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above tho s e in dicated in th e o per ational list ings of this specifi ca ti on is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
VCC Power Supply
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified
operating ranges unless otherwise
noted
Comme rci al (C ): VCC = +2.5V to +6.0V Tamb = 0°C to +70°C
Industrial (I): VCC = +2.5V to +6.0V Tamb = -40°C to +85°C
Parameter Symbol Min. Max. Units Conditions
High level input voltage VIH1 2.0 Vcc +1 V 2.7V ≤ VCC ≤ 6.0V (Note 2)
VIH2 0.7 Vcc Vcc +1 V VCC < 2.7V
Low level input voltage VIL1-0.3 0.8 VVCC > 2.7V (Note 2)
VIL2 -0.3 0.2 Vcc V VCC < 2.7V
Low level output voltage VOL1—0.4 V IOL = 2.1 mA; Vcc = 4.5V
VOL2—0.2 V IOL =100 µA; Vcc = Vcc Min.
High level output voltage VOH12.4 —VIOH = -400 µA; Vcc = 4.5V
VOH2Vcc-0.2 —VIOH = -100 µA; Vcc = Vcc Min.
Input leakage current ILI -10 10 µA VIN = VSS
Output leakage current ILO -10 10 µA VOUT = VSS
Pin capacitance
(all inputs/o utp uts) CIN, COUT —7pF
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, Fclk = 1 MHz
Operating current ICC read —1
500 mA
µA FCLK = 2 MHz; VCC = 6.0V
FCLK = 1 MHz; VCC = 3.0V
ICC write —1.5 mA
Standby cur ren t ICCS —1µACS = VSS; DI = VSS
Clock freque ncy FCLK —2
1MHz
MHz VCC > 4.5V
VCC < 4.5V
Clock high time TCKH 250 —ns
Clock low time TCKL 250 —ns
Chip select setup time TCSS 50 —ns Relative to CLK
Chip select hold time TCSH 0—ns Relative to CLK
Chip select low time TCSL 250 —ns
Data input setup time TDIS 100 —ns Relative to CLK
Data input hold time TDIH 100 —ns Relative to CLK
Data output delay time TPD —400 ns Cl = 100 pF
Data output disable time TCZ —100 ns Cl = 100 pF (Note 2)
Status valid time TSV —500 ns Cl = 100 pF
Program cycle time
TWC —6msERASE/WRITE mode
TEC —6 ms ERAL mode
TWL —15 ms WRAL mode
Endurance —1M —cycles 25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on our website.
93LC56A/B
1998 Microchip Technology Inc. DS21208C-page 3
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects the
device and forces it into standby mode. However , a p ro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal . I f C S is brou gh t low duri ng a p rogra m c yc le, th e
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC56A/B.
Opcode, address, and data bits are clocked in on the
positiv e edge of CL K. Data bi ts are also clo cked o ut on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
dete cted, an y numbe r of cloc k cycles can be rec eived
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After dete ction of a ST AR T condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO )
Data Ou t is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initi ated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/ WRITE cycle, the data line will be hig h
to indicate the device is ready.
TABLE 2-1 INSTRUCTION SET FOR 93LC56A
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 —(RDY/BSY)12
ERAL 1 00 10XXXXXXX —(RDY/BSY)12
EWDS 1 00 00XXXXXXX —HIGH-Z 12
EWEN 1 00 11XXXXXXX —HIGH-Z 12
READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 —D7 - D0 20
WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20
WRAL 1 00 01XXXXXXXD7 - D0 (RDY/BSY)20
TABLE 2-2 INSTRUCTION SET FOR 93LC56B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 —(RDY/BSY)11
ERAL 1 00 10XXXXXX —(RDY/BSY)11
EWDS 1 00 00XXXXXX —HIGH-Z 11
EWEN 1 00 11XXXXXX —HIGH-Z 11
READ 1 10 X A6 A5 A4 A3 A2 A1 A0 —D15 - D0 27
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27
WRAL 1 00 01XXXXXXD15 - D0(RDY/BSY)27
93LC56A/B
DS21208C-page 4 1998 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Instr uct ion s, add res se s a nd w ri te d ata are clocked into
the DI pin on the rising edge of the clock (CLK ). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready . The DO will enter
the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a ST AR T condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START conditio n), without re sulting i n any dev ice oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any parti cular instru ction is cl ocke d in.
Afte r ex ecut ion of an i nstr ucti on ( i.e ., clo ck in or ou t of
the last required address or data bit) CLK and DI
bec ome do n’t care bits until a new START condition is
detected.
3.2 DATA IN (DI) AND DATA OUT (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a l ogi c-high le ve l, i t is po ss ib le for a “bus c onf lic t”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition, the voltage
level seen a t DO is undefined and wi ll depen d upon th e
relative impedances of DO and the signal source driv-
ing A0. The higher the current so urcing capability of A0,
the higher the voltage at the DO pin.
3.3 Data Pro tec ti on
During power-up, all programming modes of operation
are in hib ite d un til Vc c has reac he d a l ev el g reate r tha n
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2. 2V at nominal conditions.
The EWDS and EWEN c om mands gi ve additional pro-
tection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mod e. Therefore, an EWEN instruc tion must b e
performed before any ERASE or WRITE instruction
can be execu ted .
FIGURE 3-1: SYNCHRONOUS DATA TIMING
CS VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
TCSS
TDIS
TCKH TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note: AC Test Conditions: VIL = 0.4V, VIH - 2.4V.
93LC56A/B
1998 Microchip Technology Inc. DS21208C-page 5
3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
follow in g th e loading o f t he las t address b it. Thi s fal lin g
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle excep t for the d iff erent opcod e.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2: ERASE TIMING
FIGURE 3-3: ERAL TIMING
CS
CLK
DI
DO
TCSL
CHECK STATUS
111A
NAN-1 AN-2 ••• A0
TSV TCZ
BUSY READY HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STAT US
10010X
••• X
TSV TCZ
BUSY READY HIGH-Z
TEC
HIGH-Z
Guaranteed at Vcc = 4.5V to +6.0V.
93LC56A/B
DS21208C-page 6 1998 Microchip Technology Inc.
3.6 ERASE/WRITE Disable and Enable
(EWDS/EWEN)
The 93LC56A/B powers up in the ERASE/WRITE
Disable (EWDS) state. All programming modes must
be preceded by an ERASE/WRITE Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is ex ec ute d or VCC is rem oved from the devic e. To
prote ct against accide ntal data dis turbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent
of both the EWDS and EWEN instructions.
3.7 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93LC56A) or 16-bit
(93LC56B) output string. The output data bits will tog-
gle on the rising edge of the CLK and are stable after
the specified time delay (TPD). Sequential read is pos-
sible when CS is held high. Th e memory data wi ll aut o-
matically cycle to the next register and output
sequentially.
FIGURE 3-4: EWDS TIMING
FIGURE 3-5: EWEN TIMING
FIGURE 3-6: READ TIMING
CS
CLK
DI 10
000X ••• X
TCSL
1X
CS
CLK
DI 00 1 1X
TCSL
•••
CS
CLK
DI
DO
110An ••• A0
HIGH-Z 0Dx
••• D0 Dx ••• D0 •••
Dx D0
93LC56A/B
1998 Microchip Technology Inc. DS21208C-page 7
3.8 WRITE
The WRI TE in stru cti on i s f oll ow ed by 8 bi ts (9 3LC5 6A)
or 16 bits (93LC56B) of data which are written into the
specif ied address. After the la st data bit is put on the DI
pin, the falling edge of CS initiates the self-timed auto-
erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and be fore the enti re write c ycle is co mplete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
3.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL i nstruction d oes not require an ERAL inst ruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low ( TCSL).
FIGURE 3-7: WRITE TIMING
FIGURE 3-8: WRAL TIMING
CS
CLK
DI
DO
101An
••• A0 Dx ••• D0
BUSY READY HIGH-Z
HIGH-Z
Twc
TCSL
TCZ
TSV
CS
CLK
DI
DO HIGH-Z
10001X
••• XDx ••• D0
HIGH-Z BUSY READY
TWL
Guaranteed at Vcc = 4.5V to +6.0V.
TCSL
TSV TCZ
93LC56A/B
DS21208C-page 8 1998 Microchip Technology Inc.
NOTES:
93LC56A/B
1998 Microchip Technology Inc. DS21208C-page 9
NOTES:
93LC56A/B
DS21208C-page 10 1998 Microchip Technology Inc.
NOTES:
93LC56A/B
1998 Microchip Technology Inc. DS21208C-page 11
93LC56A/B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body), 8-lead
ST = TSSOP, 8-lead
Temperature Blank = 0°C to +70°C
Range: I=-40°C to +85°C
Device:
93LC56A 2K Microwire Serial EEPROM (x8)
93LC56AT 2K Microwire Serial EEP ROM (x 8) Tape and Reel
93LC56AX 2K Microwire Serial EEPROM (x8) in alternate
pinout (SN only)
93LC56AXT 2K Microwire Ser ial EEPROM (x8) in alternate
pinout, Tape and Reel (SN only)
93LC56B 2K Microwire Serial EEPROM (x16)
93LC56BT 2K Microwire Serial EEPROM (x16) Tape and Reel
93LC56BX 2K Microwire Serial EEPROM (x16) in alternate
pinout (SN only)
93LC56BXT 2K Microwire Serial EEPROM (x16) in alternate
pinout, Tape and Reel (SN only)
93LC56A/B — /P
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determ ine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip. com /cn) to receive the most current information on our products.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
assumed by M icroc hip Techno log y Incor porate d with respe ct t o the accur acy or use of such infor mation, or infrin gemen t of patents or other intellectua l
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual p roperty rights. The M icrochip logo an d name are reg istered tradema rks of Microchip Technolo gy Inc. in the U.S.A . and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21208C-page 12 Preliminary 2000 Microchip Technology Inc.
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 12/00 Printed on recycled paper.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://ww w.microchip .com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-6 40- 003 4 Fax: 770- 640 -03 07
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-6 92- 384 8 Fax: 978- 692 -38 21
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 7500 1
Tel: 972-8 18- 742 3 Fax: 972- 818 -29 24
Dayton
Two Prestige Pla c e, Sui te 130
Miamisburg, OH 45342
Tel: 937-2 91- 165 4 Fax: 937- 291 -91 75
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los A n ge les
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-2 63- 188 8 Fax: 949- 263 -13 38
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-2 73- 530 5 Fax: 631- 273 -53 35
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-4 36- 795 0 Fax: 408- 436 -79 55
Toronto
6285 Northam Drive, Suite 108
Mississ aug a, Ontario L4V 1X5, C ana da
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
China - Be ij ing
Microchip Technology Beijing Office
Unit 915
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East In ternational Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaiso n Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku -Ku, Yokohama -shi
Kanaga wa, 222 -0 033 , Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd.
200 Midd le Ro ad
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax : 65-334-8 850
Taiwan
Microc hip Technol o gy Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Et age
91300 Massy, France
Tel: 33-1-69-53- 63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
10/01/00
WORLDWIDE SALES AND SERVICE
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and T empe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
