DAC8812
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FEATURES DESCRIPTION
APPLICATIONS
16
DAC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
EN
A
B
SDI
CS
CLK
DGND RS MSB LDAC
R
R
Power-On
Reset
R
DAC B
Register
DAC A
Register
R
DAC A
DAC B
Decode
Input
Register
Input
Register
V A B
REF
R A
FB
R B
FB
I A
OUT
A A
GND
I B
OUT
A B
GND
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
Dual, Serial Input 16-Bit Multiplying Digital-to-Analog Converter
•Relative Accuracy: 1 LSB Max
The DAC8812 is a dual, 16-bit, current-output•Differential Nonlinearity: 1 LSB Max
digital-to-analog converter (DAC) designed to operatefrom a single +2.7 V to +5.5 V supply.•2-mA Full-Scale Current ±20%,with V
REF
=±10 V
The applied external reference input voltage V
REF•0.5 µs Settling Time
determines the full-scale output current. An internalfeedback resistor (R
FB
) provides temperature tracking•Midscale or Zero-Scale Reset
for the full-scale output when combined with an•Separate 4Q Multiplying Reference Inputs
external I-to-V precision amplifier.•Reference Bandwidth: 10 MHz
A double-buffered, serial data interface offers•Reference Dynamics: –105 dB THD
high-speed, 3-wire, SPI and microcontroller•SPI™-Compatible 3-Wire Interface:
compatible inputs using serial data in (SDI), clock50 MHz
(CLK), and a chip-select ( CS). A common•Double Buffered Registers Enable
level-sensitive load DAC strobe ( LDAC) input allowssimultaneous update of all DAC outputs from•Simultaneous Multichannel Change
previously loaded input registers. Additionally, an•Internal Power On Reset
internal power-on reset forces the output voltage to•Industry-Standard Pin Configuration
zero at system turn-on. An MSB pin allows systemreset assertion ( RS) to force all registers to zero codewhen MSB = 0, or to half-scale code when MSB = 1.•Automatic Test Equipment
The DAC8812 is available in an TSSOP-16 package.•Instrumentation
•Digitally Controlled Calibration
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI is a trademark of Motorola, Inc.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
RELATIVE DIFFERENTIAL SPECIFIED TRANSPORTACCURACY NONLINEARITY TEMPERATURE PACKAGE- PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) RANGE LEAD DESIGNATOR NUMBER QUANTITY
DAC8812ICPW Tube, 90DAC8812C ±1±1 –40 °C to +85 °C TSSOP-16 PW
DAC8812ICPWR Tape and Reel, 2500
DAC8812IBPW Tube, 90DAC8812B ±2±1 –40 °C to +85 °C TSSOP-16 PW
DAC8812IBPWR Tape and Reel, 2500
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, orsee the TI website at www.ti.com .
DAC8812 UNIT
V
DD
to GND – 0.3 to +8 VV
REF
to GND –18 to +18 VLogic inputs and output to GND – 0.3 to +8 VV(I
OUT
) to GND – 0.3 to V
DD
+0.3 VA
GND
X to DGND –0.3 to +0.3 VInput current to any pin except supplies ±50 mAPackage power dissipation (T
J
max – T
A
)/ θ
JA
WThermal resistance, θ
JA
100 °C/WMaximum junction temperature (T
J
max) +150 °COperating temperature range – 40 to +85 °CStorage temperature range – 65 to +150 °C
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
(1)
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unlessotherwise noted.
DAC8812
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
(2)
Resolution 16 BitsDAC8812B ±2 LSBRelative accuracy INL
DAC8812C ±1 LSBDifferential nonlinearity DNL DAC8812 ±1 LSBData = 0000h, T
A
= +25 °C 10 nAOutput leakage current I
OUT
X
Data = 0000h, T
A
= T
A
max 20 nAFull-scale gain error G
FSE
Data = FFFFh ±0.75 ±4 mVFull-scale tempco
(3)
TCV
FS
1 ppm/ °CFeedback resistor R
FB
X V
DD
= 5 V 5 k Ω
REFERENCE INPUT
V
REF
X range V
REF
X –15 15 VInput resistance R
REF
X 4 5 6 k ΩInput resistance match R
REF
X Channel-to-channel 1 %Input capacitance
(3)
C
REF
X 5 pF
ANALOG OUTPUT
Output current I
OUT
X Data = FFFFh 1.6 2.5 mAOutput capacitance
(3)
C
OUT
X Code-dependent 50 pF
LOGIC INPUTS AND OUTPUT
V
DD
= +2.7 V 0.6 VInput low voltage V
IL
V
DD
= +5 V 0.8 VV
DD
= +2.7 V 2.1 VInput high voltage V
IH
V
DD
= +5 V 2.4 VInput leakage current I
IL
1µAInput capacitance
(3)
C
IL
10 pFLogic output low voltage V
OL
I
OL
= 1.6 mA 0.4 VLogic output high voltage V
OH
I
OH
= 100 µA 4 V
INTERFACE TIMING
(3), (4)
Clock width high t
CH
25 nsClock width low t
CL
25 nsCS to Clock setup t
CSS
0 nsClock to CS hold t
CSH
25 nsClock to SDO prop delay t
PD
2 20 nsLoad DAC pulsewidth t
LDAC
25 nsData setup t
DS
20 nsData hold t
DH
20 nsLoad setup t
LDS
5 nsLoad hold t
LDH
25 ns
(1) Specifications subject to change without notice.(2) All static performance tests (except I
OUT
) are performed in a closed-loop system using an external precision OPA277 I-to-V converteramplifier. The DAC8812 R
FB
terminal is tied to the amplifier output. Typical values represent average readings measured at +25 °C.(3) These parameters are specified by design and not subject to production testing.(4) All input control signals are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
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PARAMETER MEASUREMENT INFORMATION
SDI
CLK
CS
LDAC
tCSStds tdh tch tcl
tcsh
Input REG. LD
tlds
tLDAC
tLDH
A1 A0 D14 D12 D10 D9 D1 D0
D11
D15 D13
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unlessotherwise noted.
DAC8812
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
Power supply range V
DD RANGE
2.7 5.5 VLogic inputs = 0 V, V
DD
= +4.5 V to +5.5 V 2 5 µAPositive supply current I
DD
Logic inputs = 0 V, V
DD
= +2.7 V to +3.6 V 1 2.5 µAPower dissipation P
DISS
Logic inputs = 0 V 0.0275 mWPower supply sensitivity P
SS
∆V
DD
=±5% 0.006 %
AC CHARACTERISTICS
(5)
To ±0.1% of full-scale, µs0.3Data = 0000h to FFFFh to 0000hOutput voltage settling time t
s
To ±0.0015% of full-scale, µs0.5Data = 0000h to FFFFh to 0000hReference multiplying BW BW –3 dB V
REF
X = 100 mV
RMS
, Data = FFFFh, C
FB
= 3 pF 10 MHzDAC glitch impulse Q V
REF
X = 10 V, Data = 7FFFh to 8000h to 7FFFh 5 nV/sFeedthrough error V
OUT
X/V
REF
X Data = 0000h, V
REF
X = 100 mV
RMS
, f = 100 kHz –70 dBCrosstalk error V
OUT
A/V
REF
B Data = 0000h, V
REF
B = 100 mV
RMS
, dB–100Adjacent channel, f = 100 kHzDigital feedthrough Q CS = 1 and f
CLK
= 1 MHz 1 nV/sTotal harmonic distortion THD V
REF
= 5 V
PP
, Data = FFFFh, f = 1 kHz –105 dBOutput spot noise voltage e
n
f = 1 kHz, BW = 1 Hz 12 nV/ √Hz
(5) All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.
Figure 1. DAC8812 Timing Diagram
4
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PIN CONFIGURATION
1
2
3
4
5
6
7
89
10
11
12
13
14
16
15
DGND
DAC8812
(TOP VIEW)
AGNDA
IOUTA
VREFA
RFBA
RFBB
VREFB
IOUTB
AGNDB
LDAC
MSB
RS
VDD
CS
CLK
SDI
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
PIN DESCRIPTION
PIN NAME DESCRIPTION
1 R
FB
A Establish voltage output for DAC A by connecting to external amplifier output.DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage. Can2 V
REF
A
be tied to V
DD
pin.3 I
OUT
A DAC A Current output.4 A
GND
A DAC A Analog ground.5 A
GND
B DAC B Analog ground.6 I
OUT
B DAC B Current output.DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage. Can7 V
REF
B
be tied to V
DD
pin.8 R
FB
B Establish voltage output for DAC B by connecting to external amplifier output.9 SDI Serial data input; data loads directly into the shift register.Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.10 RS Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 forDAC8812.
Chip-select; active low input. Disables shift register loading when high. Transfers serial11 CS
register data to input register when CS goes high. Does not affect LDAC operation.12 DGND Digital ground.13 V
DD
Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.MSB bit sets output to either 0 or midscale during a RESET pulse ( RS) or at system14 MSB power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pincan be permanently tied to ground or V
DD
.Load DAC register strobe; level sensitive active low. Transfers all input register data to the15 LDAC
DAC registers. Asynchronous active low input. See Table 2 for operation.16 CLK Clock input. Positive edge clocks data into shift register.
5
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TYPICAL CHARACTERISTICS: V
DD
= +5 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +85°C
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
At T
A
= +25 °C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 2. Figure 3.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 4. Figure 5.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 6. Figure 7.
6
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Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
T = +25 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
T 40- °
A=C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +85°C
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)At T
A
= +25 °C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 8. Figure 9.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 10. Figure 11.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 12. Figure 13.
7
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180
160
140
120
100
80
60
40
20
0
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Supply Current, IDD (mA)
Logic Input Voltage (V)
V = +5.0V
DD
V = +2.7V
DD
Time (0.2 s/div)m
Output Voltage (50mV/div)
LDAC Pulse
Code: 7FFFh to 8000h
Time (0.1 s/div)m
Output Voltage (5V/div)
Trigger Pulse
Voltage Output Settling
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)At T
A
= +25 °C, +V
DD
= +5 V, unless otherwise noted.
SUPPLY CURRENT REFERENCE MULTIPLYING BANDWIDTHvs LOGIC INPUT VOLTAGE
Figure 14. Figure 15.
DAC GLITCH DAC SETTLING TIME
Figure 16. Figure 17.
8
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TYPICAL CHARACTERISTICS: V
DD
= +2.7 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= 40°C-
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= 40-°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +85°C
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
At T
A
= +25 °C, +V
DD
= +2.7 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 18. Figure 19.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 20. Figure 21.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 22. Figure 23.
9
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Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= 40-°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= 40-°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
INL (LSB)
Code
TA= +85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
08192 16384 24576 32768 40960 49152 57344 65535
DNL (LSB)
Code
TA= +85°C
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: V
DD
= +2.7 V (continued)At T
A
= +25 °C, +V
DD
= +2.7 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 24. Figure 25.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 26. Figure 27.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 28. Figure 29.
10
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THEORY OF OPERATION
CIRCUIT OPERATION
Digital-to-Analog Converters
RRR
2R 2R 2R R5kW
S2 S1
DGND
V X
REF
VDD
R X
FB
I X
OUT
A X
GND
Digital interface connections omitted for clarity.
Switches S1 and S2 are closed, V must be powered.
DD
VOUT VREF D
65536
(1)
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
The DAC8812 contains two 16-bit, current-output, digital-to-analog converters (DACs). Each DAC has its ownindependent multiplying reference input. The DAC8812 uses a 3-wire, SPI-compatible serial data interface, with aconfigurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDACstrobe enables two channel simultaneous updates for hardware synchronized output voltage changes.
The DAC8812 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC. EachDAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R
FB
X pin isconnected to the output of the external amplifier. The I
OUT
X terminal is connected to the inverting input of theexternal amplifier. The A
GND
X pin should be Kelvin-connected to the load point in the circuit requiring the full16-bit accuracy.
Figure 30. Typical Equivalent DAC Channel
The DAC is designed to operate with both negative or positive reference voltages. The V
DD
power pin is onlyused by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with theinternal 5 k Ωfeedback resistor. If users are attempting to measure the value of R
FB
, power must be applied toV
DD
in order to achieve continuity. The DAC output voltage is determined by V
REF
and the digital data (D)according to Equation 1 :
Note that the output polarity is opposite of the V
REF
polarity for dc reference voltages.
The DAC is also designed to accommodate ac reference input signals. The DAC8812 accommodates inputreference voltages in the range of –15 V to +15 V. The reference voltage inputs exhibit a constant nominal inputresistance of 5 k Ω,±20%. On the other hand, DAC outputs I
OUT
A and B are code-dependent and producevarious output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8812on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor(C
FB
) may be needed to provide a critically damped output response for step changes in reference inputvoltages.
11
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+
+
Analog
Power
Supply
Load
15 V
2R
5 V
R
15 V
A1
RRR
2R 2R 2R R5kW
S2 S1
DGND DGND
V X
REF
VDD
R X
FB
I X
OUT
VOUT
VCC
VEE
A X
GND
Digital interface connections omitted for clarity.
Switches S1 and S2 are closed, V must be powered.
DD
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A
B
DAC
Decode
Input
Register R
Input
Register R
DAC A
Register R
DAC B
Register R
DAC A
DAC B
Set
MSB
Power-
on
Reset
DGND MSB LDAC RS
VDD
CS
CLK
SDI
V A B
REF
I A
OUT
A A
GND
R B
FB
I B
OUT
A B
GND
EN
Set
MSB
R B
FB
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF externalfeedback capacitor connected across the I
OUT
X and R
FB
X terminals. In order to maintain good analogperformance, power-supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,clean power supply with low ripple voltage capability should be used. Switching power supplies is usually notsuitable for this application due to the higher ripple voltage and P
SS
frequency-dependent characteristics. It isbest to derive the DAC8812 5-V supply from the system analog supply voltages (do not use the digital 5-Vsupply); see Figure 31 .
Figure 31. Recommended Kelvin-Sensed Hookup
Figure 32. System Level Digital Interfacing
12
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SERIAL DATA INTERFACE
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
The DAC8812 uses a 3-wire ( CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8812 isclocked into the serial input register in an 18-bit data-word format. MSB bits are loaded first. Table 1 defines the18 data-word bits for the DAC8812.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the datasetup and data hold time requirements specified in the Interface Timing specifications of the ElectricalCharacteristics . Data can only be clocked in while the CS chip select pin is active low. For the DAC8812, onlythe last 18 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to theDAC8812. Keeping the CS line low between the first, second, and third byte transfers will result in a successfulserial register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of newdata to the target DAC register, determined by the decoding of address bits A1 and A0. For the DAC8812,Table 1 ,Table 2 ,Table 3 , and Figure 1 define the characteristics of the software serial interface.
Table 1. Serial Input Register Data Format, Data Loaded MSB First
(1)
B17 B0Bit (MSB) B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB)
Data A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns tologic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D15-D0) to the decodedDAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8812 shift register are ignored; only thelast 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 2. Control Logic Truth Table
(1)
CS CLK LDAC RS MSB SERIAL SHIFT REGISTER INPUT REGISTER DAC REGISTER
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L↑+ H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
↑+ L H H X No effect Selected DAC updated with current SR contents Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X ↑+ H X No effect Latched Latched
H X H L 0 No effect Latched data = 0000h Latched data = 0000h
H X H L H No effect Latched data = 8000h Latched data = 8000h
(1) ↑+= Positive logic transition; X= Do not care
Table 3. Address Decode
A1 A0 DAC DECODE
0 0 None0 1 DAC A1 0 DAC B1 1 DAC A and DAC B
13
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A
B
Address
Decoder
Shift Register
EN
To Input Register
CS
CLK
SDI
POWER ON RESET
ESD Protection Circuits
250 W
DGND
DIGITAL
INPUTS
VDD
PCB LAYOUT
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
Figure 33 shows the equivalent logic interface for the key digital control pins for the DAC8812.
Figure 33. DAC8812 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. Ifthese functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces allinput and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
When the V
DD
power supply is turned on, an internal reset strobe forces all the Input and DAC registers to thezero-code state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smoothpositive ramp without drooping, in order to have consistent results, especially in the region of V
DD
= 1.5 V to2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V
DD
asshown in Figure 34 .
Figure 34. Equivalent ESD Protection Circuits
The DAC8812 is a high-accuracy DAC that can have its performance compromised by grounding and printedcircuit board (PCB) lead trace resistance. The 16-bit DAC8812 with a 10-V full-scale range has an LSB value of153 mV. The ladder and associated reference and analog ground currents for a given channel can be as high as2 mA. With this 2-mA current level, a series wiring and connector resistance of only 76 m Ωwill cause 1 LSB ofvoltage drop. The preferred PCB layout for the DAC8812 is to have all A
GND
X pins connected directly to ananalog ground plane at the unit. The noninverting input of each channel I/V converter should also either connectdirectly to the analog ground plane or have an individual sense trace back to the A
GND
X pin connection. Thefeedback resistor trace to the I/V converter should also be kept short and have low resistance in order to preventIR drops from contributing to gain error. This attention to wiring ensures the optimal performance of theDAC8812.
14
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APPLICATION INFORMATION
VOUT D
32,768 1VREF
(2)
10 V
VREF
10 kW
10 kW
5kW
VDD
I X
OUT
A X
GND
OPA277
OPA277
One Channel
DAC8812
VOUT
Digital interface connections omitted for clarity.
-10 V < VOUT < +10 V
VREFXRFBX
Cross-Reference
DAC8812
SBAS349A – AUGUST 2005 – REVISED DECEMBER 2005
The DAC8812, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of thefull-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 35 .An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implementedby using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation(Equation 2 ), input data (D) from code 0 to full scale produces output voltages of V
OUT
= –10 V to V
OUT
= 10 V.
Figure 35. Four-Quadrant Multiplying Application Circuit
The DAC8812 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIEDINL DNL TEMPERATURE PACKAGE PACKAGE CROSS-REFERENCEPRODUCT (LSB) (LSB) RANGE DESCRIPTION OPTION PART NUMBER
16-Lead Thin ShrinkDAC8812ICPW ±1±1 –40 °C to +85 °C TSSOP-16 N/ASmall-Outline Package16-Lead Thin ShrinkDAC8812IBPW ±2±1 –40 °C to +85 °C TSSOP-16 AD5545BRUSmall-Outline Package
15
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DAC8812IBPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812IBPWR ACTIVE TSSOP PW 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812IBPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812IBPWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI
DAC8812ICPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812ICPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812ICPWR ACTIVE TSSOP PW 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812ICPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC8812ICPWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2006
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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