Contents
Arria V GX, GT, SX, and ST Device Datasheet..................................................................................................... 1-1
Electrical Characteristics.................................................................................................................................................................................................... 1-1
Operating Conditions............................................................................................................................................................................................. 1-1
Switching Characteristics..................................................................................................................................................................................................1-23
Transceiver Performance Specications............................................................................................................................................................. 1-23
Core Performance Specications.........................................................................................................................................................................1-43
Periphery Performance......................................................................................................................................................................................... 1-49
HPS Specications................................................................................................................................................................................................. 1-58
Conguration Specications............................................................................................................................................................................................1-75
POR Specications.................................................................................................................................................................................................1-75
FPGA JTAG Conguration Timing.................................................................................................................................................................... 1-76
FPP Conguration Timing...................................................................................................................................................................................1-77
AS Conguration Timing..................................................................................................................................................................................... 1-80
DCLK Frequency Specication in the AS Conguration Scheme..................................................................................................................1-81
PS Conguration Timing......................................................................................................................................................................................1-81
Initialization........................................................................................................................................................................................................... 1-83
Conguration Files................................................................................................................................................................................................1-83
Minimum Conguration Time Estimation........................................................................................................................................................1-84
Remote System Upgrades..................................................................................................................................................................................... 1-86
User Watchdog Internal Oscillator Frequency Specications......................................................................................................................... 1-86
I/O Timing..........................................................................................................................................................................................................................1-86
Programmable IOE Delay.....................................................................................................................................................................................1-87
Programmable Output Buer Delay................................................................................................................................................................... 1-87
Glossary...............................................................................................................................................................................................................................1-88
Document Revision History.............................................................................................................................................................................................1-94
Arria V GZ Device Datasheet................................................................................................................................ 2-1
Electrical Characteristics.................................................................................................................................................................................................... 2-1
TOC-2
Altera Corporation
Operating Conditions .............................................................................................................................................................................................2-1
Switching Characteristics .................................................................................................................................................................................................2-21
Transceiver Performance Specications ............................................................................................................................................................ 2-21
Core Performance Specications ........................................................................................................................................................................2-37
Periphery Performance ........................................................................................................................................................................................ 2-44
Conguration Specication .............................................................................................................................................................................................2-56
POR Specications ................................................................................................................................................................................................2-56
JTAG Conguration Specications .................................................................................................................................................................... 2-57
Fast Passive Parallel (FPP) Conguration Timing ........................................................................................................................................... 2-57
Active Serial Conguration Timing ................................................................................................................................................................... 2-65
Passive Serial Conguration Timing ..................................................................................................................................................................2-67
Initialization .......................................................................................................................................................................................................... 2-69
Conguration Files ...............................................................................................................................................................................................2-69
Remote System Upgrades Circuitry Timing Specication ..............................................................................................................................2-70
User Watchdog Internal Oscillator Frequency Specication ..........................................................................................................................2-71
I/O Timing .........................................................................................................................................................................................................................2-71
Programmable IOE Delay ....................................................................................................................................................................................2-72
Programmable Output Buer Delay .................................................................................................................................................................. 2-72
Glossary ..............................................................................................................................................................................................................................2-73
Document Revision History ............................................................................................................................................................................................2-78
TOC-3
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Arria V GX, GT, SX, and ST Device Datasheet 1
2016.12.09
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is datasheet describes the electrical characteristics, switching characteristics, conguration specications, and I/O timing for Arria® V devices.
Arria V devices are oered in commercial and industrial grades. Commercial devices are oered in –C4 (fastest), –C5, and –C6 speed grades.
Industrial grade devices are oered in the –I3 and –I5 speed grades.
Related Information
Arria V Device Overview
Provides more information about the densities and packages of devices in the Arria V family.
Electrical Characteristics
e following sections describe the operating conditions and power consumption of Arria V devices.
Operating Conditions
Arria V devices are rated according to a set of dened parameters. To maintain the highest possible performance and reliability of the Arria V
devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
is section denes the maximum operating conditions for Arria V devices. e values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms.
e functional operation of the device is not implied for these conditions.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other
countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for products
or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Caution: Conditions outside the range listed in the following table may cause permanent damage tothe device. Additionally, device operation at
the absolute maximum ratings for extended periods of time may have adverse eects on the device.
Table 1-1: Absolute Maximum Ratings for Arria V Devices
Symbol Description Minimum Maximum Unit
VCC Core voltage power supply –0.50 1.43 V
VCCP Periphery circuitry, PCIe® hardIP block, and transceiver physical
coding sublayer (PCS) power supply
–0.50 1.43 V
VCCPGM Conguration pins power supply –0.50 3.90 V
VCC_AUX Auxiliary supply –0.50 3.25 V
VCCBAT Battery back-up power supply for design security volatile key
register
–0.50 3.90 V
VCCPD I/O pre-driver power supply –0.50 3.90 V
VCCIO I/O power supply –0.50 3.90 V
VCCD_FPLL Phase-locked loop (PLL) digital power supply –0.50 1.80 V
VCCA_FPLL PLL analog power supply –0.50 3.25 V
VCCA_GXB Transceiver high voltage power –0.50 3.25 V
VCCH_GXB Transmitter output buer power –0.50 1.80 V
VCCR_GXB Receiver power –0.50 1.50 V
VCCT_GXB Transmitter power –0.50 1.50 V
VCCL_GXB Transceiver clock network power –0.50 1.50 V
VIDC input voltage –0.50 3.80 V
VCC_HPS HPS core voltage and periphery circuitry power supply –0.50 1.43 V
VCCPD_HPS HPS I/O pre-driver power supply –0.50 3.90 V
VCCIO_HPS HPS I/O power supply –0.50 3.90 V
VCCRSTCLK_HPS HPS reset and clock input pins power supply –0.50 3.90 V
1-2 Absolute Maximum Ratings AV-51002
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Symbol Description Minimum Maximum Unit
VCCPLL_HPS HPS PLL analog power supply –0.50 3.25 V
VCC_AUX_SHARED HPS auxiliary power supply –0.50 3.25 V
IOUT DC output current per pin –25 40 mA
TJOperating junction temperature –55 125 °C
TSTG Storage temperature (no bias) –65 150 °C
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100
mA and periods shorter than 20 ns.
e maximum allowed overshoot duration is specied as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this
amounts to 1.5 years.
Table 1-2: Maximum Allowed Overshoot During Transitions for Arria V Devices
is table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
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2016.12.09 Maximum Allowed Overshoot and Undershoot Voltage 1-3
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Symbol Description Condition (V) Overshoot Duration as % of High Time Unit
Vi (AC) AC input voltage
3.8 100 %
3.85 68 %
3.9 45 %
3.95 28 %
4 15 %
4.05 13 %
4.1 11 %
4.15 9 %
4.2 8 %
4.25 7 %
4.3 5.4 %
4.35 3.2 %
4.4 1.9 %
4.45 1.1 %
4.5 0.6 %
4.55 0.4 %
4.6 0.2 %
Recommended Operating Conditions
is section lists the functional operation limits for the AC and DC parameters for Arria V devices.
Recommended Operating Conditions
Table 1-3: Recommended Operating Conditions for Arria V Devices
is table lists the steady-state voltage values expected from Arria V devices. Power supply ramps must all be strictly monotonic, without plateaus.
1-4 Recommended Operating Conditions AV-51002
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Symbol Description Condition Minimum(1) Typical Maximum(1) Unit
VCC Core voltage power supply –C4, –I5, –C5, –C6 1.07 1.1 1.13 V
–I3 1.12 1.15 1.18 V
VCCP Periphery circuitry, PCIe hard IP block,
and transceiver PCS power supply
–C4, –I5, –C5, –C6 1.07 1.1 1.13 V
–I3 1.12 1.15 1.18 V
VCCPGM Conguration pins power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
VCC_AUX Auxiliary supply — 2.375 2.5 2.625 V
VCCBAT(2) Battery back-up power supply
(For design security volatile key register)
— 1.2 — 3.0 V
VCCPD(3) I/O pre-driver power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
(1) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(2) If you do not use the design security feature in Arria V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Arria V power-on reset
(POR) circuitry monitors VCCBAT. Arria V devices do not exit POR if VCCBAT is not powered up.
(3) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is
3.3 V.
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Symbol Description Condition Minimum(1) Typical Maximum(1) Unit
VCCIO I/O buers power supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V 1.283 1.35 1.418 V
1.25 V 1.19 1.25 1.31 V
1.2 V 1.14 1.2 1.26 V
VCCD_FPLL PLL digital voltage regulator power
supply
— 1.425 1.5 1.575 V
VCCA_FPLL PLL analog voltage regulator power
supply
— 2.375 2.5 2.625 V
VIDC input voltage — –0.5 — 3.6 V
VOOutput voltage — 0 — VCCIO V
TJOperating junction temperature Commercial 0 — 85 °C
Industrial –40 — 100 °C
tRAMP(4) Power supply ramp time Standard POR 200 µs — 100 ms —
Fast POR 200 µs — 4 ms —
(1) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(4) is is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specications for standard POR when HPS_PORSEL = 0 and tRAMP
specications for fast POR when HPS_PORSEL = 1.
1-6 Recommended Operating Conditions AV-51002
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Transceiver Power Supply Operating Conditions
Table 1-4: Transceiver Power Supply Operating Conditions for Arria V Devices
Symbol Description Minimum(5) Typical Maximum(5) Unit
VCCA_GXBL Transceiver high voltage power (le side) 2.375 2.500 2.625 V
VCCA_GXBR Transceiver high voltage power (right side)
VCCR_GXBL GX and SX speed grades—receiver power (le
side) 1.08/1.12 1.1/1.15(6) 1.14/1.18 V
VCCR_GXBR GX and SX speed grades—receiver power (right
side)
VCCR_GXBL GT and ST speed grades—receiver power (le
side) 1.17 1.20 1.23 V
VCCR_GXBR GT and ST speed grades—receiver power (right
side)
VCCT_GXBL GX and SX speed grades—transmitter power (le
side) 1.08/1.12 1.1/1.15(6) 1.14/1.18 V
VCCT_GXBR GX and SX speed grades—transmitter power
(right side)
VCCT_GXBL GT and ST speed grades—transmitter power (le
side) 1.17 1.20 1.23 V
VCCT_GXBR GT and ST speed grades—transmitter power (right
side)
VCCH_GXBL Transmitter output buer power (le side) 1.425 1.500 1.575 V
VCCH_GXBR Transmitter output buer power (right side)
(5) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(6) For data rate <=3.2 Gbps, connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps,
connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin
Connection Guidelines.
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2016.12.09 Transceiver Power Supply Operating Conditions 1-7
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Symbol Description Minimum(5) Typical Maximum(5) Unit
VCCL_GXBL GX and SX speed grades—clock network power
(le side) 1.08/1.12 1.1/1.15(6) 1.14/1.18 V
VCCL_GXBR GX and SX speed grades—clock network power
(right side)
VCCL_GXBL GT and ST speed grades—clock network power
(le side) 1.17 1.20 1.23 V
VCCL_GXBR GT and ST speed grades—clock network power
(right side)
Related Information
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
Provides more information about the power supply connection for dierent data rates.
HPS Power Supply Operating Conditions
Table 1-5: HPS Power Supply Operating Conditions for Arria V SX and ST Devices
is table lists the steady-state voltage and current values expected from Arria V system-on-a-chip (SoC) devices with ARM®-based hard processor
system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria V
Devices table for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices.
Symbol Description Condition Minimum(7) Typical Maximum(7) Unit
VCC_HPS
HPS core
voltage and
periphery
circuitry
power
supply
–C4, –I5, –C5, –C6 1.07 1.1 1.13 V
–I3 1.12 1.15 1.18 V
(5) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(7) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
1-8 HPS Power Supply Operating Conditions AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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Symbol Description Condition Minimum(7) Typical Maximum(7) Unit
VCCPD_HPS (8)
HPS I/O
pre-driver
power
supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
VCCIO_HPS
HPS I/O
buers
power
supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V (9) 1.283 1.35 1.418 V
1.2 V 1.14 1.2 1.26 V
VCCRSTCLK_HPS
HPS reset
and clock
input pins
power
supply
3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3.0 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
VCCPLL_HPS HPS PLL
analog
voltage
regulator
power
supply
— 2.375 2.5 2.625 V
(7) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(8) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when
VCCIO_HPS is 3.3 V.
(9) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.
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Symbol Description Condition Minimum(7) Typical Maximum(7) Unit
VCC_AUX_SHARED HPS
auxiliary
power
supply
— 2.375 2.5 2.625 V
Related Information
Recommended Operating Conditions on page 1-4
Provides the steady-state voltage values for the FPGA portion of the device.
DC Characteristics
Supply Current and Power Consumption
Altera oers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus® Prime PowerPlay Power
Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. e EPE provides a magnitude estimate of the
device power because these currents vary greatly with the resources you use.
e Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specics of the design aer you complete place-and-
route. e PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yields very accurate power estimates.
Related Information
•PowerPlay Early Power Estimator User Guide
Provides more information about power estimation tools.
•PowerPlay Power Analysis chapter, Quartus Prime Handbook
Provides more information about power estimation tools.
(7) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
1-10 DC Characteristics AV-51002
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I/O Pin Leakage Current
Table 1-6: I/O Pin Leakage Current for Arria V Devices
Symbol Description Condition Min Typ Max Unit
IIInput pin VI = 0 V to VCCIOMAX –30 — 30 µA
IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA
Bus Hold Specications
Table 1-7: Bus Hold Parameters for Arria V Devices
e bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter Symbol Condition
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold,
low,
sustaining
current
ISUSL VIN > VIL
(max)
8 — 12 — 30 — 50 — 70 — 70 — µA
Bus-hold,
high,
sustaining
current
ISUSH VIN < VIH
(min)
–8 — –12 — –30 — –50 — –70 — –70 — µA
Bus-hold,
low,
overdrive
current
IODL 0 V < VIN
< VCCIO
— 125 — 175 — 200 — 300 — 500 — 500 µA
Bus-hold,
high,
overdrive
current
IODH 0 V <VIN
<VCCIO
— –125 — –175 — –200 — –300 — –500 — –500 µA
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Parameter Symbol Condition
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold
trip point
VTRIP — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
OCT Calibration Accuracy Specications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration
block.
Table 1-8: OCT Calibration Accuracy Specications for Arria V Devices
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions change aer calibration, the tolerance may change.
Symbol Description Condition (V)
Calibration Accuracy
Unit
–I3, –C4 –I5, –C5 –C6
25-Ω RSInternal series termination with
calibration (25-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
50-Ω RSInternal series termination with
calibration (50-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
34-Ω and 40-Ω RSInternal series termination with
calibration (34-Ω and 40-Ω
setting)
VCCIO = 1.5, 1.35, 1.25,
1.2
±15 ±15 ±15 %
48-Ω, 60-Ω, and 80-
Ω RS
Internal series termination with
calibration (48-Ω, 60-Ω, and
80-Ω setting)
VCCIO = 1.2 ±15 ±15 ±15 %
50-Ω RTInternal parallel termination
with calibration (50-Ω setting)
VCCIO = 2.5, 1.8, 1.5, 1.2 –10 to +40 –10 to +40 –10 to +40 %
20-Ω, 30-Ω, 40-Ω,60-
Ω, and 120-Ω RT
Internal parallel termination
with calibration (20-Ω, 30-Ω,
40-Ω, 60-Ω, and 120-Ω setting)
VCCIO = 1.5, 1.35, 1.25 –10 to +40 –10 to +40 –10 to +40 %
1-12 OCT Calibration Accuracy Specications AV-51002
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Symbol Description Condition (V)
Calibration Accuracy
Unit
–I3, –C4 –I5, –C5 –C6
60-Ω and 120-Ω RTInternal parallel termination
with calibration (60-Ω and 120-
Ω setting)
VCCIO = 1.2 –10 to +40 –10 to +40 –10 to +40 %
25-Ω RS_le_shi Internal le shi series
termination with calibration
(25-Ω RS_le_shi setting)
VCCIO = 3.0, 2.5, 1.8, 1.5,
1.2
±15 ±15 ±15 %
OCT Without Calibration Resistance Tolerance Specications
Table 1-9: OCT Without Calibration Resistance Tolerance Specications for Arria V Devices
is table lists the Arria V OCT without calibration resistance tolerance to PVT changes.
Symbol Description Condition (V)
ResistanceTolerance
Unit
–I3, –C4 –I5, –C5 –C6
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 3.0, 2.5 ±30 ±40 ±40 %
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.8, 1.5 ±30 ±40 ±40 %
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.2 ±35 ±50 ±50 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 3.0, 2.5 ±30 ±40 ±40 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.8, 1.5 ±30 ±40 ±40 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.2 ±35 ±50 ±50 %
100-Ω RDInternal dierential termination
(100-Ω setting)
VCCIO = 2.5 ±25 ±40 ±40 %
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Figure 1-1: Equation for OCT Variation Without Recalibration
e denitions for the equation are as follows:
•e ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
• RSCAL is the OCT resistance value at power-up.
• ΔT is the variation of temperature with respect to the temperature at power up.
• ΔV is the variation of voltage with respect to the VCCIO at power up.
• dR/dT is the percentage change of RSCAL with temperature.
• dR/dV is the percentage change of RSCAL with voltage.
OCT Variation after Power-Up Calibration
Table 1-10: OCT Variation after Power-Up Calibration for Arria V Devices
is table lists OCT variation with temperature and voltage aer power-up calibration. e OCT variation is valid for a VCCIO range of ±5% and a
temperature range of 0°C to 85°C.
Symbol Description VCCIO (V) Value Unit
dR/dV OCT variation with voltage without recalibration
3.0 0.100
%/mV
2.5 0.100
1.8 0.100
1.5 0.100
1.35 0.150
1.25 0.150
1.2 0.150
1-14 OCT Variation after Power-Up Calibration AV-51002
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Symbol Description VCCIO (V) Value Unit
dR/dT OCT variation with temperature without
recalibration
3.0 0.189
%/°C
2.5 0.208
1.8 0.266
1.5 0.273
1.35 0.200
1.25 0.200
1.2 0.317
Pin Capacitance
Table 1-11: Pin Capacitance for Arria V Devices
Symbol Description Maximum Unit
CIOTB Input capacitance on top/bottom I/O pins 6 pF
CIOLR Input capacitance on le/right I/O pins 6 pF
COUTFB Input capacitance on dual-purpose clock output/feedback pins 6 pF
CIOVREF Input capacitance on VREF pins 48 pF
Hot Socketing
Table 1-12: Hot Socketing Specications for Arria V Devices
Symbol Description Maximum Unit
IIOPIN (DC) DC current per I/O pin 300 μA
IIOPIN (AC) AC current per I/O pin 8(10) mA
IXCVR-TX (DC) DC current per transceiver transmitter (TX) pin 100 mA
AV-51002
2016.12.09 Pin Capacitance 1-15
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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Symbol Description Maximum Unit
IXCVR-RX (DC) DC current per transceiver receiver (RX) pin 50 mA
Internal Weak Pull-Up Resistor
All I/O pins, except conguration, test, and JTAG pins, have an option to enable weak pull-up.
Table 1-13: Internal Weak Pull-Up Resistor Values for Arria V Devices
Symbol Description Condition (V)(11) Value(12) Unit
RPU
Value of the I/O pin pull-up resistor before and during
conguration, as well as user mode if you have enabled the
programmable pull-up resistor option.
VCCIO = 3.3 ±5% 25 kΩ
VCCIO = 3.0 ±5% 25 kΩ
VCCIO = 2.5 ±5% 25 kΩ
VCCIO = 1.8 ±5% 25 kΩ
VCCIO = 1.5 ±5% 25 kΩ
VCCIO = 1.35 ±5% 25 kΩ
VCCIO = 1.25 ±5% 25 kΩ
VCCIO = 1.2 ±5% 25 kΩ
Related Information
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
(10) e I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew
rate.
(11) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(12) Valid with ±10% tolerances to cover changes over PVT.
1-16 Internal Weak Pull-Up Resistor AV-51002
2016.12.09
Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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I/O Standard Specications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various
I/O standards supported by Arria V devices.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards
Table 1-14: Single-Ended I/O Standards for Arria V Devices
I/O Standard
VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL(13)
(mA) IOH(13) (mA)
Min Typ Max Min Max Min Max Max Min
3.3-V
LVTTL
3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.45 2.4 4 –4
3.3-V
LVCMOS
3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2
3.0-V
LVTTL
2.85 3 3.15 –0.3 0.8 1.7 3.6 0.4 2.4 2 –2
3.0-V
LVCMOS
2.85 3 3.15 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 0.1 –0.1
3.0-V PCI 2.85 3 3.15 — 0.3 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5
3.0-V
PCI-X
2.85 3 3.15 — 0.35 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5
2.5 V 2.375 2.5 2.625 –0.3 0.7 1.7 3.6 0.4 2 1 –1
1.8 V 1.71 1.8 1.89 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO – 0.45 2 –2
1.5 V 1.425 1.5 1.575 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2
1.2 V 1.14 1.2 1.26 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2
(13) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specication (4
mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
AV-51002
2016.12.09 I/O Standard Specications 1-17
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications
Table 1-15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications for Arria V Devices
I/O Standard
VCCIO (V) VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2
Class I, II
2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF – 0.04 VREF VREF + 0.04
SSTL-18
Class I, II
1.71 1.8 1.89 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15
Class I, II
1.425 1.5 1.575 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-135
Class I, II
1.283 1.35 1.418 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-125
Class I, II
1.19 1.25 1.26 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
HSTL-18
Class I, II
1.71 1.8 1.89 0.85 0.9 0.95 — VCCIO/2 —
HSTL-15
Class I, II
1.425 1.5 1.575 0.68 0.75 0.9 — VCCIO/2 —
HSTL-12
Class I, II
1.14 1.2 1.26 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO — VCCIO/2 —
HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO — — —
1-18 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications
Table 1-16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications for Arria V Devices
I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL(14)
(mA) IOH(14) (mA)
Min Max Min Max Max Min Max Min
SSTL-2
Class I
–0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.608 VTT + 0.608 8.1 –8.1
SSTL-2
Class II
–0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.81 VTT + 0.81 16.2 –16.2
SSTL-18
Class I
–0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 VTT – 0.603 VTT + 0.603 6.7 –6.7
SSTL-18
Class II
–0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 0.28 VCCIO – 0.28 13.4 –13.4
SSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8 –8
SSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 –16
SSTL-135 — VREF – 0.09 VREF + 0.09 — VREF – 0.16 VREF + 0.16 0.2 × VCCIO 0.8 × VCCIO — —
SSTL-125 — VREF – 0.85 VREF + 0.85 — VREF – 0.15 VREF + 0.15 0.2 × VCCIO 0.8 × VCCIO — —
HSTL-18
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-18
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
(14) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specication (8
mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
AV-51002
2016.12.09 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications 1-19
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL(14)
(mA) IOH(14) (mA)
Min Max Min Max Max Min Max Min
HSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-12
Class I
–0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 8 –8
HSTL-12
Class II
–0.15 VREF – 0.08 VREF + 0.08 VCCIO+ 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 16 –16
HSUL-12 — VREF – 0.13 VREF + 0.13 — VREF – 0.22 VREF + 0.22 0.1 × VCCIO 0.9 × VCCIO — —
Dierential SSTL I/O Standards
Table 1-17: Dierential SSTL I/O Standards for Arria V Devices
I/O Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max
SSTL-2
Class I, II
2.375 2.5 2.625 0.3 VCCIO + 0.6 VCCIO/2 – 0.2 — VCCIO/2
+ 0.2
0.62 VCCIO + 0.6
SSTL-18
Class I, II
1.71 1.8 1.89 0.25 VCCIO + 0.6 VCCIO/2 –
0.175
— VCCIO/2
+ 0.175
0.5 VCCIO + 0.6
SSTL-15
Class I, II
1.425 1.5 1.575 0.2 (15) VCCIO/2 –
0.15
— VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
SSTL-135 1.283 1.35 1.45 0.18 (15) VCCIO/2 –
0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
(14) To meet the IOL and IOH specications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specication (8
mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specications in the
datasheet.
(15) e maximum value for VSWING(DC) is not dened. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
1-20 Dierential SSTL I/O Standards AV-51002
2016.12.09
Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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I/O Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max
SSTL-125 1.19 1.25 1.31 0.18 (15) VCCIO/2 –
0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) – VREF)
Dierential HSTL and HSUL I/O Standards
Table 1-18: Dierential HSTL and HSUL I/O Standards for Arria V Devices
I/O Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Max
HSTL-18
Class I, II
1.71 1.8 1.89 0.2 — 0.78 — 1.12 0.78 — 1.12 0.4 —
HSTL-15
Class I, II
1.425 1.5 1.575 0.2 — 0.68 — 0.9 0.68 — 0.9 0.4 —
HSTL-12
Class I, II
1.14 1.2 1.26 0.16 VCCIO
+ 0.3
— 0.5 ×
VCCIO
— 0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.3 VCCIO + 0.48
HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.44 0.44
Dierential I/O Standard Specications
Table 1-19: Dierential I/O Standard Specications for Arria V Devices
Dierential inputs are powered by VCCPD which requires 2.5 V.
AV-51002
2016.12.09 Dierential HSTL and HSUL I/O Standards 1-21
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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I/O Standard
VCCIO (V) VID (mV)(16) VICM(DC) (V) VOD (V)(17) VOCM (V)(17)(18)
Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max
PCML Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and
reference clock I/O pin specications, refer to Transceiver Specications for Arria V GX and SX Devices and Transceiver Specications
for Arria V GT and ST Devices tables.
2.5 V
LVDS(19) 2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 DMAX ≤
1.25 Gbps
1.80
0.247 — 0.6 1.125 1.25 1.375
— 1.05 DMAX >
1.25 Gbps
1.55
RSDS
(HIO)(20)
2.375 2.5 2.625 100 VCM =
1.25 V
— 0.25 — 1.45 0.1 0.2 0.6 0.5 1.2 1.4
Mini-LVDS
(HIO)(21)
2.375 2.5 2.625 200 — 600 0.300 — 1.425 0.25 — 0.6 1 1.2 1.4
LVPECL(22) — — — 300 — —
0.60 DMAX ≤
700 Mbps
1.80
————— —
1.00 DMAX >
700 Mbps
1.60
Related Information
•Transceiver Specications for Arria V GX and SX Devices on page 1-23
Provides the specications for transmitter, receiver, and reference clock I/O pin.
(16) e minimum VID value is applicable over the entire common mode range, VCM.
(17) RL range: 90 ≤ RL ≤ 110 Ω.
(18) is applies to default pre-emphasis setting only.
(19) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 1.25 Gbps and 0 V to
1.85 V for data rates below 1.25 Gbps.
(20) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
(21) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V.
(22) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45
V to 1.95 V for data rates below 700 Mbps.
1-22 Dierential I/O Standard Specications AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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•Transceiver Specications for Arria V GT and ST Devices on page 1-29
Provides the specications for transmitter, receiver, and reference clock I/O pin.
Switching Characteristics
is section provides performance characteristics of Arria V core and periphery blocks.
Transceiver Performance Specications
Transceiver Specications for Arria V GX and SX Devices
Table 1-20: Reference Clock Specications for Arria V GX and SX Devices
Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Supported I/O standards 1.2 V PCML, 1.4 V PCML,1.5 V PCML, 2.5 V PCML, Dierential LVPECL(23), HCSL, and LVDS
Input frequency from
REFCLK input pins
— 27 — 710 27 — 710 MHz
Rise time Measure at ±60 mV of
dierential signal(24)
— — 400 — — 400 ps
Fall time Measure at ±60 mV of
dierential signal(24)
— — 400 — — 400 ps
Duty cycle — 45 — 55 45 — 55 %
Peak-to-peak dierential
input voltage
— 200 — 300(25)/
2000
200 — 300(25)/
2000
mV
(23) Dierential LVPECL signal levels must comply to the minimum and maximum peak-to-peak dierential input voltage specied in this table.
(24) REFCLK performance requires to meet transmitter REFCLK phase noise specication.
(25) e maximum peak-to peak dierential input voltage of 300 mV is allowed for DC coupled link.
AV-51002
2016.12.09 Switching Characteristics 1-23
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Spread-spectrum
modulating clock
frequency
PCI Express® (PCIe) 30 — 33 30 — 33 kHz
Spread-spectrum
downspread
PCIe — 0 to –0.5% — — 0 to –0.5% — —
On-chip termination
resistors
— — 100 — — 100 — Ω
VICM (AC coupled) — — 1.1/1.15(26) — — 1.1/1.15(26) — V
VICM (DC coupled) HCSL I/O standard for
the PCIe reference
clock
250 — 550 250 — 550 mV
Transmitter REFCLK phase
noise(27)
10 Hz — — –50 — — –50 dBc/Hz
100 Hz — — –80 — — –80 dBc/Hz
1 KHz — — –110 — — –110 dBc/Hz
10 KHz — — –120 — — –120 dBc/Hz
100 KHz — — –120 — — –120 dBc/Hz
≥1 MHz — — –130 — — –130 dBc/Hz
RREF — — 2000 ±1% — — 2000 ±1% — Ω
(26) For data rate ≤3.2 Gbps, connect VCCR_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps, connect VCCR_GXBL/R to a 1.15-V
power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines.
(27) e transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12.
1-24 Transceiver Specications for Arria V GX and SX Devices AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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Table 1-21: Transceiver Clocks Specications for Arria V GX and SX Devices
Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
fixedclk clock frequency PCIe Receiver Detect — 125 — — 125 — MHz
Transceiver Recongura‐
tion Controller IP (mgmt_
clk_clk) clock frequency
— 75 — 125 75 — 125 MHz
Table 1-22: Receiver Specications for Arria V GX and SX Devices
Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Supported I/O standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate(28) — 611 — 6553.6 611 — 3125 Mbps
Absolute VMAX for a
receiver pin(29)
— — — 1.2 — — 1.2 V
Absolute VMIN for a
receiver pin
— –0.4 — — –0.4 — — V
Maximum peak-to-peak
dierential input voltage
VID (di p-p) before device
conguration
— — — 1.6 — — 1.6 V
Maximum peak-to-peak
dierential input voltage
VID (di p-p) aer device
conguration
— — — 2.2 — — 2.2 V
(28) To support data rates lower than the minimum specication through oversampling, use the CDR in LTR mode only.
(29) e device cannot tolerate prolonged operation at this absolute maximum.
AV-51002
2016.12.09 Transceiver Specications for Arria V GX and SX Devices 1-25
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Minimum dierential eye
opening at the receiver
serial input pins(30)
— 100 — — 100 — — mV
VICM (AC coupled) — — 0.7/0.75/
0.8(31)
— — 0.7/0.75/
0.8 (31)
— mV
VICM (DC coupled) ≤ 3.2Gbps(32) 670 700 730 670 700 730 mV
Dierential on-chip
termination resistors
85-Ω setting — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — Ω
tLTR(33) — — — 10 — — 10 µs
tLTD(34) — 4 — — 4 — — µs
tLTD_manual(35) — 4 — — 4 — — µs
tLTR_LTD_manual(36) — 15 — — 15 — — µs
Programmable ppm
detector(37)
— ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
(30) e dierential eye opening specication at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable
the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(31) e AC coupled VICM = 700 mV for Arria V GX and SX in PCIe mode only. e AC coupled VICM = 750 mV for Arria V GT and ST in PCIe mode
only.
(32) For standard protocol compliance, use AC coupling.
(33) tLTR is the time required for the receive CDR to lock to the input reference clock frequency aer coming out of reset.
(34) tLTD is time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high.
(35) tLTD_manual is the time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(36) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode aer the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
1-26 Transceiver Specications for Arria V GX and SX Devices AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Run length — — — 200 — — 200 UI
Programmable equaliza‐
tion AC and DC gain AC gain setting = 0 to
3(38)
DC gain setting = 0 to 1
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC
Gain and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE
Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC
Gain for Arria V GX, GT, SX, and ST Devices diagrams.
dB
Table 1-23: Transmitter Specications for Arria V GX and SX Devices
Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Supported I/O standards 1.5 V PCML
Data rate — 611 — 6553.6 611 — 3125 Mbps
VOCM (AC coupled) — — 650 — — 650 — mV
VOCM (DC coupled) ≤ 3.2Gbps(32) 670 700 730 670 700 730 mV
Dierential on-chip
termination resistors
85-Ω setting — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — Ω
Intra-dierential pair skew TX VCM = 0.65 V (AC
coupled) and slew rate
of 15 ps
— — 15 — — 15 ps
Intra-transceiver block
transmitter channel-to-
channel skew
×6 PMA bonded mode — — 180 — — 180 ps
(37) e rate match FIFO supports only up to ±300 parts per million (ppm).
(38) e Quartus Prime soware allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
AV-51002
2016.12.09 Transceiver Specications for Arria V GX and SX Devices 1-27
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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Symbol/Description Condition
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Typ Max Min Typ Max
Inter-transceiver block
transmitter channel-to-
channel skew(39)
×N PMA bonded mode — — 500 — — 500 ps
Table 1-24: CMU PLL Specications for Arria V GX and SX Devices
Symbol/Description
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Unit
Min Max Min Max
Supported data range 611 6553.6 611 3125 Mbps
fPLL supported data range 611 3125 611 3125 Mbps
Table 1-25: Transceiver-FPGA Fabric Interface Specications for Arria V GX and SX Devices
Symbol/Description
Transceiver Speed Grade 4 and 6
Unit
Min Max
Interface speed (single-width mode) 25 187.5 MHz
Interface speed (double-width mode) 25 163.84 MHz
Related Information
•CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 1-35
•CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 1-36
•Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
Provides more information about the power supply connection for dierent data rates.
(39) is specication is only applicable to channels on one side of the device across two transceiver banks.
1-28 Transceiver Specications for Arria V GX and SX Devices AV-51002
2016.12.09
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Transceiver Specications for Arria V GT and ST Devices
Table 1-26: Reference Clock Specications for Arria V GT and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Supported I/O standards 1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Dierential LVPECL(40), HCSL, and LVDS
Input frequency from REFCLK input
pins
— 27 — 710 MHz
Rise time Measure at ±60 mV of
dierential signal(41)
— — 400 ps
Fall time Measure at ±60 mV of
dierential signal(41)
— — 400 ps
Duty cycle — 45 — 55 %
Peak-to-peak dierential input voltage — 200 — 300(42)/2000 mV
Spread-spectrum modulating clock
frequency
PCI Express (PCIe) 30 — 33 kHz
Spread-spectrum downspread PCIe — 0 to –0.5% — —
On-chip termination resistors — — 100 — Ω
VICM (AC coupled) — — 1.2 — V
VICM (DC coupled) HCSL I/O standard for the PCIe
reference clock
250 — 550 mV
(40) Dierential LVPECL signal levels must comply to the minimum and maximum peak-to-peak dierential input voltage specied in this table.
(41) REFCLK performance requires to meet transmitter REFCLK phase noise specication.
(42) e maximum peak-to peak dierential input voltage of 300 mV is allowed for DC coupled link.
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Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Transmitter REFCLK phase noise(43)
10 Hz — — –50 dBc/Hz
100 Hz — — –80 dBc/Hz
1 KHz — — –110 dBc/Hz
10 KHz — — –120 dBc/Hz
100 KHz — — –120 dBc/Hz
≥ 1 MHz — — –130 dBc/Hz
RREF — — 2000 ±1% — Ω
Table 1-27: Transceiver Clocks Specications for Arria V GT and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
fixedclk clock frequency PCIe Receiver Detect — 125 — MHz
Transceiver Reconguration
Controller IP (mgmt_clk_clk) clock
frequency
— 75 — 125 MHz
Table 1-28: Receiver Specications for Arria V GT and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Supported I/O Standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate (6-Gbps transceiver)(44) — 611 — 6553.6 Mbps
(43) e transmitter REFCLK phase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma.
(44) To support data rates lower than the minimum specication through oversampling, use the CDR in LTR mode only.
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Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Data rate (10-Gbps transceiver)(44) — 0.611 — 10.3125 Gbps
Absolute VMAX for a receiver pin(45) — — — 1.2 V
Absolute VMIN for a receiver pin — –0.4 — — V
Maximum peak-to-peak dierential
input voltage VID (di p-p) before
device conguration
— — — 1.6 V
Maximum peak-to-peak dierential
input voltage VID (di p-p) aer
device conguration
— — — 2.2 V
Minimum dierential eye opening
at the receiver serial input pins(46)
— 100 — — mV
VICM (AC coupled) — — 750(47)/800 — mV
VICM (DC coupled) ≤ 3.2Gbps(48) 670 700 730 mV
Dierential on-chip termination
resistors
85-Ω setting 85 Ω
100-Ω setting 100 Ω
120-Ω setting 120 Ω
150-Ω setting 150 Ω
tLTR(49) — — — 10 µs
tLTD(50) — 4 — — µs
(45) e device cannot tolerate prolonged operation at this absolute maximum.
(46) e dierential eye opening specication at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable
the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(47) e AC coupled VICM is 750 mV for PCIe mode only.
(48) For standard protocol compliance, use AC coupling.
(49) tLTR is the time required for the receive CDR to lock to the input reference clock frequency aer coming out of reset.
(50) tLTD is time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high.
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Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
tLTD_manual(51) — 4 — — µs
tLTR_LTD_manual(52) — 15 — — µs
Programmable ppm detector(53) — ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
Run length — — — 200 UI
Programmable equalization AC and
DC gain AC gain setting = 0 to 3(54)
DC gain setting = 0 to 1
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain
and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at
Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V
GX, GT, SX, and ST Devices diagrams.
Table 1-29: Transmitter Specications for Arria V GT and ST Devices
Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Supported I/O standards 1.5 V PCML
Data rate (6-Gbps transceiver) — 611 — 6553.6 Mbps
Data rate (10-Gbps transceiver) — 0.611 — 10.3125 Gbps
VOCM (AC coupled) — — 650 — mV
VOCM (DC coupled) ≤ 3.2 Gbps(48) 670 700 730 mV
(51) tLTD_manual is the time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(52) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode aer the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(53) e rate match FIFO supports only up to ±300 ppm.
(54) e Quartus Prime soware allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
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Symbol/Description Condition
Transceiver Speed Grade 3
Unit
Min Typ Max
Dierential on-chip termination
resistors
85-Ω setting — 85 — Ω
100-Ω setting — 100 — Ω
120-Ω setting — 120 — Ω
150-Ω setting — 150 — Ω
Intra-dierential pair skew TX VCM = 0.65 V (AC coupled)
and slew rate of 15 ps
— — 15 ps
Intra-transceiver block transmitter
channel-to-channel skew
×6 PMA bonded mode — — 180 ps
Inter-transceiver block transmitter
channel-to-channel skew(55)
×N PMA bonded mode — — 500 ps
Table 1-30: CMU PLL Specications for Arria V GT and ST Devices
Symbol/Description
Transceiver Speed Grade 3
Unit
Min Max
Supported data range 0.611 10.3125 Gbps
fPLL supported data range 611 3125 Mbps
(55) is specication is only applicable to channels on one side of the device across two transceiver banks.
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Table 1-31: Transceiver-FPGA Fabric Interface Specications for Arria V GT and ST Devices
Symbol/Description
Transceiver Speed Grade 3
Unit
Min Max
Interface speed (PMA direct mode) 50 153.6(56), 161(57) MHz
Interface speed (single-width mode) 25 187.5 MHz
Interface speed (double-width mode) 25 163.84 MHz
Related Information
•CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 1-35
•CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 1-36
(56) e maximum frequency when core transceiver local routing is selected.
(57) e maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected.
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CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain
Figure 1-2: Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX,
GT, SX, and ST Devices
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2016.12.09 CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1-35
Arria V GX, GT, SX, and ST Device Datasheet Altera Corporation
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CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain
Figure 1-3: CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices
1-36 CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain AV-51002
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Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet
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Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω
Table 1-32: Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω
Symbol VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV)
VOD dierential peak-to-peak
typical
6(59) 120 34 680
7(59) 140 35 700
8(59) 160 36 720
9 180 37 740
10 200 38 760
11 220 39 780
12 240 40 800
13 260 41 820
14 280 42 840
15 300 43 860
16 320 44 880
17 340 45 900
18 360 46 920
19 380 47 940
20 400 48 960
21 420 49 980
22 440 50 1000
23 460 51 1020
24 480 52 1040
(58) Convert these values to their binary equivalent form if you are using the dynamic reconguration mode for PMA analog controls.
(59) Only valid for data rates ≤ 5 Gbps.
AV-51002
2016.12.09 Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω 1-37
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Symbol VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV)
25 500 53 1060
26 520 54 1080
27 540 55 1100
28 560 56 1120
29 580 57 1140
30 600 58 1160
31 620 59 1180
32 640 60 1200
33 660
Transmitter Pre-Emphasis Levels
e following table lists the simulation data on the transmitter pre-emphasis levels in dB for the rst post tap under the following conditions:
• Low-frequency data pattern—ve 1s and ve 0s
• Data rate—2.5 Gbps
e levels listed are a representation of possible pre-emphasis levels under the specied conditions only and the pre-emphasis levels may change
with data pattern and data rate.
Arria V devices only support 1st post tap pre-emphasis with the following conditions:
•e 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st
post tap pre-emphasis setting.
• |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.
• (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
Exception for PCIe Gen2 design: VOD setting = 43 and pre-emphasis setting = 19 are allowed for PCIe Gen2 design with transmit de-emphasis –
6dB setting (pipe_txdeemp = 1’b0) using Altera PCIe Hard IP and PIPE IP cores.
(58) Convert these values to their binary equivalent form if you are using the dynamic reconguration mode for PMA analog controls.
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For example, when VOD = 800 mV, the corresponding VOD value setting is 40. e following conditions show that the 1st post tap pre-emphasis
setting = 2 is valid:
• |B| + |C| ≤ 60→ 40 + 2 = 42
• |B| – |C| > 5→ 40 – 2 = 38
• (VMAX/VMIN – 1)% < 600%→ (42/38 – 1)% = 10.52%
To predict the pre-emphasis level for your specic data rate and pattern, run simulations using the Arria V HSSI HSPICE models.
Table 1-33: Transmitter Pre-Emphasis Levels for Arria V Devices
Quartus Prime 1st
Post Tap Pre-
Emphasis Setting
Quartus Prime VOD Setting
Unit
10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV)
0 0 0 0 0 0 0 0 dB
1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 dB
2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 dB
3 5.35 2.48 1.49 1.2 1 0.83 0.69 dB
4 7.27 3.31 2 1.63 1.36 1.14 0.96 dB
5 — 4.19 2.55 2.1 1.76 1.49 1.26 dB
6 — 5.08 3.11 2.56 2.17 1.83 1.56 dB
7 — 5.99 3.71 3.06 2.58 2.18 1.87 dB
8 — 6.92 4.22 3.47 2.93 2.48 2.11 dB
9 — 7.92 4.86 4 3.38 2.87 2.46 dB
10 — 9.04 5.46 4.51 3.79 3.23 2.77 dB
11 — 10.2 6.09 5.01 4.23 3.61 — dB
12 — 11.56 6.74 5.51 4.68 3.97 — dB
13 — 12.9 7.44 6.1 5.12 4.36 — dB
14 — 14.44 8.12 6.64 5.57 4.76 — dB
15 — — 8.87 7.21 6.06 5.14 — dB
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Quartus Prime 1st
Post Tap Pre-
Emphasis Setting
Quartus Prime VOD Setting
Unit
10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV)
16 — — 9.56 7.73 6.49 — — dB
17 — — 10.43 8.39 7.02 — — dB
18 — — 11.23 9.03 7.52 — — dB
19 — — 12.18 9.7 8.02 — — dB
20 — — 13.17 10.34 8.59 — — dB
21 — — 14.2 11.1 — — — dB
22 — — 15.38 11.87 — — — dB
23 — — — 12.67 — — — dB
24 — — — 13.48 — — — dB
25 — — — 14.37 — — — dB
26 — — — — — — — dB
27 — — — — — — — dB
28 — — — — — — — dB
29 — — — — — — — dB
30 — — — — — — — dB
31 — — — — — — — dB
Related Information
SPICE Models for Altera Devices
Provides the Arria V HSSI HSPICE models.
Transceiver Compliance Specication
e following table lists the physical medium attachment (PMA) specication compliance of all supported protocol for Arria V GX, GT, SX, and ST
devices. For more information about the protocol parameter details and compliance specications, contact your Altera Sales Representative.
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Table 1-34: Transceiver Compliance Specication for All Supported Protocol for Arria V GX, GT, SX, and ST Devices
Protocol Sub-protocol Data Rate (Mbps)
PCIe
PCIe Gen1 2,500
PCIe Gen2 5,000
PCIe Cable 2,500
XAUI XAUI 2135 3,125
Serial RapidIO® (SRIO)
SRIO 1250 SR 1,250
SRIO 1250 LR 1,250
SRIO 2500 SR 2,500
SRIO 2500 LR 2,500
SRIO 3125 SR 3,125
SRIO 3125 LR 3,125
SRIO 5000 SR 5,000
SRIO 5000 MR 5,000
SRIO 5000 LR 5,000
SRIO_6250_SR 6,250
SRIO_6250_MR 6,250
SRIO_6250_LR 6,250
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Protocol Sub-protocol Data Rate (Mbps)
Common Public Radio Interface (CPRI)
CPRI E6LV 614.4
CPRI E6HV 614.4
CPRI E6LVII 614.4
CPRI E12LV 1,228.8
CPRI E12HV 1,228.8
CPRI E12LVII 1,228.8
CPRI E24LV 2,457.6
CPRI E24LVII 2,457.6
CPRI E30LV 3,072
CPRI E30LVII 3,072
CPRI E48LVII 4,915.2
CPRI E60LVII 6,144
CPRI E96LVIII(60) 9,830.4
Gbps Ethernet (GbE) GbE 1250 1,250
OBSAI
OBSAI 768 768
OBSAI 1536 1,536
OBSAI 3072 3,072
OBSAI 6144 6,144
Serial digital interface (SDI)
SDI 270 SD 270
SDI 1485 HD 1,485
SDI 2970 3G 2,970
(60) You can achieve compliance with TX channel restriction of one HSSI channel per six-channel transceiver bank.
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Protocol Sub-protocol Data Rate (Mbps)
SONET
SONET 155 155.52
SONET 622 622.08
SONET 2488 2,488.32
Gigabit-capable passive optical network (GPON)
GPON 155 155.52
GPON 622 622.08
GPON 1244 1,244.16
GPON 2488 2,488.32
QSGMII QSGMII 5000 5,000
Core Performance Specications
Clock Tree Specications
Table 1-35: Clock Tree Specications for Arria V Devices
Parameter
Performance
Unit
–I3, –C4 –I5, –C5 –C6
Global clock and Regional clock 625 625 525 MHz
Peripheral clock 450 400 350 MHz
PLL Specications
Table 1-36: PLL Specications for Arria V Devices
is table lists the Arria V PLL block specications. Arria V PLL block does not include HPS PLL.
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Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency
–3 speed grade 5 — 800(61) MHz
–4 speed grade 5 — 800(61) MHz
–5 speed grade 5 — 750(61) MHz
–6 speed grade 5 — 625(61) MHz
fINPFD Integer input clock frequency to the
phase frequency detector (PFD)
— 5 — 325 MHz
fFINPFD Fractional input clock frequency to the
PFD
— 50 — 160 MHz
fVCO(62) PLL voltage-controlled oscillator
(VCO) operating range
–3 speed grade 600 — 1600 MHz
–4 speed grade 600 — 1600 MHz
–5 speed grade 600 — 1600 MHz
–6 speed grade 600 — 1300 MHz
tEINDUTY Input clock or external feedback clock
input duty cycle
— 40 — 60 %
fOUT Output frequency for internal global or
regional clock
–3 speed grade — — 500(63) MHz
–4 speed grade — — 500(63) MHz
–5 speed grade — — 500(63) MHz
–6 speed grade — — 400(63) MHz
(61) is specication is limited in the Quartus Prime soware by the I/O maximum frequency. e maximum I/O frequency is dierent for each I/O
standard.
(62) e VCO frequency reported by the Quartus Prime soware takes into consideration the VCO post-scale counter K value. erefore, if the counter K
has a value of 2, the frequency reported can be lower than the fVCO specication.
(63) is specication is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
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Symbol Parameter Condition Min Typ Max Unit
fOUT_EXT Output frequency for external clock
output
–3 speed grade — — 670(63) MHz
–4 speed grade — — 670(63) MHz
–5 speed grade — — 622(63) MHz
–6 speed grade — — 500(63) MHz
tOUTDUTY Duty cycle for external clock output
(when set to 50%)
— 45 50 55 %
tFCOMP External feedback clock compensation
time
— — — 10 ns
tDYCONFIGCLK Dynamic conguration clock for mgmt_
clk and scanclk — — — 100 MHz
tLOCK Time required to lock from end-of-
device conguration or deassertion of
areset
— — — 1 ms
tDLOCK Time required to lock dynamically
(aer switchover or reconguring any
non-post-scale counters/delays)
— — — 1 ms
fCLBW PLL closed-loop bandwidth
Low — 0.3 — MHz
Medium — 1.5 — MHz
High(64) — 4 — MHz
tPLL_PSERR Accuracy of PLL phase shi — — — ±50 ps
tARESET Minimum pulse width on the areset
signal
— 10 — — ns
tINCCJ(65)(66) Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p)
FREF < 100 MHz — — ±750 ps (p-p)
(64) High bandwidth PLL settings are not supported in external feedback mode.
(65) A high input jitter directly aects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(66) FREF is fIN/N, specication applies when N = 1.
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Symbol Parameter Condition Min Typ Max Unit
tOUTPJ_DC(67) Period jitter for dedicated clock output
in integer PLL
FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tFOUTPJ_DC(67) Period jitter for dedicated clock output
in fractional PLL
FOUT ≥ 100 MHz — — 250(68), 175(69) ps (p-p)
FOUT < 100 MHz — — 25(68), 17.5(69) mUI (p-p)
tOUTCCJ_DC(67) Cycle-to-cycle jitter for dedicated clock
output in integer PLL
FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tFOUTCCJ_DC(67) Cycle-to-cycle jitter for dedicated clock
output in fractional PLL
FOUT ≥ 100 MHz — — 250(68), 175(69) ps (p-p)
FOUT < 100 MHz — — 25(68), 17.5(69) mUI (p-p)
tOUTPJ_IO(67)(70) Period jitter for clock output on a
regular I/O in integer PLL
FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tFOUTPJ_IO(67)(68)(70) Period jitter for clock output on a
regular I/O in fractional PLL
FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tOUTCCJ_IO(67)(70) Cycle-to-cycle jitter for clock output on
a regular I/O in integer PLL
FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tFOUTCCJ_IO(67)(68)(70) Cycle-to-cycle jitter for clock output on
a regular I/O in fractional PLL
FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
(67) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% condence level). e output jitter specication applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. e external memory interface clock output jitter specications use a dierent
measurement method and are available in Memory Output Clock Jitter Specication for Arria V Devices table.
(68) is specication only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(69) is specication only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
(70) External memory interface clock output jitter specications use a dierent measurement method, which are available in Memory Output Clock Jitter
Specication for Arria V Devices table.
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Symbol Parameter Condition Min Typ Max Unit
tCASC_OUTPJ_DC(67)(71) Period jitter for dedicated clock output
in cascaded PLLs
FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tDRIFT Frequency dri aer PFDENA is disabled
for a duration of 100 µs
— — — ±10 %
dKBIT Bit number of Delta Sigma Modulator
(DSM)
— 8 24 32 bits
kVALUE Numerator of fraction — 128 8388608 2147483648 —
fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz
Related Information
Memory Output Clock Jitter Specications on page 1-57
Provides more information about the external memory interface clock output jitter specications.
(71) e cascaded PLL specication is only applicable with the following conditions:
• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
• Downstream PLL: Downstream PLL BW > 2 MHz
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DSP Block Performance Specications
Table 1-37: DSP Block Performance Specications for Arria V Devices
Mode
Performance
Unit
–I3, –C4 –I5, –C5 –C6
Modes using One DSP
Block
Independent 9 × 9 multiplication 370 310 220 MHz
Independent 18 × 19 multiplication 370 310 220 MHz
Independent 18 × 25 multiplication 370 310 220 MHz
Independent 20 × 24 multiplication 370 310 220 MHz
Independent 27 × 27 multiplication 310 250 200 MHz
Two 18 × 19 multiplier adder mode 370 310 220 MHz
18 × 18 multiplier added summed with 36-
bit input
370 310 220 MHz
Modes using Two
DSP Blocks
Complex 18 × 19 multiplication 370 310 220 MHz
Memory Block Performance Specications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus Prime soware to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
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Table 1-38: Memory Block Performance Specications for Arria V Devices
Memory Mode
Resources Used Performance
Unit
ALUTs Memory –I3, –C4 –I5, –C5 –C6
MLAB
Single port, all supported widths 0 1 500 450 400 MHz
Simple dual-port, all supported widths 0 1 500 450 400 MHz
Simple dual-port with read and write at
the same address
0 1 400 350 300 MHz
ROM, all supported width — — 500 450 400 MHz
M10K
Block
Single-port, all supported widths 0 1 400 350 285 MHz
Simple dual-port, all supported widths 0 1 400 350 285 MHz
Simple dual-port with the read-during-
write option set to Old Data, all supported
widths
0 1 315 275 240 MHz
True dual port, all supported widths 0 1 400 350 285 MHz
ROM, all supported widths 0 1 400 350 285 MHz
Internal Temperature Sensing Diode Specications
Table 1-39: Internal Temperature Sensing Diode Specications for Arria V Devices
Temperature Range Accuracy Oset Calibrated
Option
Sampling Rate Conversion
Time
Resolution Minimum Resolution with no
Missing Codes
–40 to 100°C ±8°C No 1 MHz < 100 ms 8 bits 8 bits
Periphery Performance
is section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specic factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specic design and system setup to determine the maximum achievable frequency in your system.
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High-Speed I/O Specications
Table 1-40: High-Speed I/O Specications for Arria V Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
e Arria V devices support the following output standards using true LVDS output buer types on all I/O banks.
• True RSDS output standard with data rates of up to 360 Mbps
• True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol Condition
–I3, –C4 –I5, –C5 –C6
Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in (input clock frequency) True
Dierential I/O Standards
Clock boost factor W
= 1 to 40(72)
5 — 800 5 — 750 5 — 625 MHz
fHSCLK_in (input clock frequency)
Single-Ended I/O Standards(73)
Clock boost factor W
= 1 to 40(72)
5 — 625 5 — 625 5 — 500 MHz
fHSCLK_in (input clock frequency)
Single-Ended I/O Standards(74)
Clock boost factor W
= 1 to 40(72)
5 — 420 5 — 420 5 — 420 MHz
fHSCLK_OUT (output clock frequency) — 5 — 625(75) 5 — 625(75) 5 — 500(75) MHz
Transmitter
True Dierential I/O
Standards - fHSDR (data
rate)
SERDES factor J =3 to
10(76)
(77) — 1250 (77) — 1250 (77) — 1050 Mbps
(72) Clock boost factor (W) is the ratio between the input data rate and the input clock rate.
(73) is applies to DPA and so-CDR modes only.
(74) is applies to non-DPA mode only.
(75) is is achieved by using the LVDS clock network.
(76) e Fmax specication is based on the fast clock used for serial data. e interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
(77) e minimum specication depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. e I/O dierential buer and input register do not have a minimum toggle rate.
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Symbol Condition
–I3, –C4 –I5, –C5 –C6
Unit
Min Typ Max Min Typ Max Min Typ Max
SERDES factor J ≥
8(76)(78), LVDS TX with
RX DPA
(77) — 1600 (77) — 1500 (77) — 1250 Mbps
SERDES factor J = 1
to 2, Uses DDR
Registers
(77) —(79) (77) —(79) (77) —(79) Mbps
Emulated Dierential I/
O Standards with ree
External Output Resistor
Network - fHSDR (data
rate)(80)
SERDES factor J = 4
to 10(81)
(77) — 945 (77) — 945 (77) — 945 Mbps
Emulated Dierential I/
O Standards with One
External Output Resistor
Network - fHSDR (data
rate)(80)
SERDES factor J = 4
to 10(81)
(77) — 200 (77) — 200 (77) — 200 Mbps
tx Jitter -True Dierential
I/O Standards
Total Jitter for Data
Rate 600 Mbps – 1.25
Gbps
— — 160 — — 160 — — 160 ps
Total Jitter for Data
Rate < 600 Mbps
— — 0.1 — — 0.1 — — 0.1 UI
(78) e VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface.
(79) e maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT), provided you can close the design timing and
the signal integrity simulation is clean.
(80) You must calculate the leover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leover timing margin.
(81) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
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Symbol Condition
–I3, –C4 –I5, –C5 –C6
Unit
Min Typ Max Min Typ Max Min Typ Max
tx Jitter -Emulated
Dierential I/O
Standards with ree
External Output Resistor
Network
Total Jitter for Data
Rate 600 Mbps – 1.25
Gbps
— — 260 — — 300 — — 350 ps
Total Jitter for Data
Rate < 600 Mbps
— — 0.16 — — 0.18 — — 0.21 UI
tx Jitter -Emulated
Dierential I/O
Standards with One
External Output
Resistor Network
— — — 0.15 — — 0.15 — — 0.15 UI
tDUTY TX output clock duty
cycle for both True
and Emulated
Dierential I/O
Standards
45 50 55 45 50 55 45 50 55 %
tRISE and tFALL
True Dierential I/O
Standards(82)
— — 160 — — 180 — — 200 ps
Emulated Dierential
I/O Standards with
ree External Output
Resistor Network
— — 250 — — 250 — — 300 ps
Emulated Dierential
I/O Standards with
One External Output
Resistor Network
— — 500 — — 500 — — 500 ps
(82) is applies to default pre-emphasis and VOD settings only.
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Symbol Condition
–I3, –C4 –I5, –C5 –C6
Unit
Min Typ Max Min Typ Max Min Typ Max
TCCS
True Dierential I/O
Standards
— — 150 — — 150 — — 150 ps
Emulated Dierential
I/O Standards
— — 300 — — 300 — — 300 ps
Receiver
True Dierential I/O
Standards - fHSDRDPA
(data rate)
SERDES factor J =3 to
10(76)
150 — 1250 150 — 1250 150 — 1050 Mbps
SERDES factor J ≥ 8
with DPA(76)(78)
150 — 1600 150 — 1500 150 — 1250 Mbps
fHSDR (data rate)
SERDES factor J = 3
to 10
(77) —(83) (77) —(83) (77) —(83) Mbps
SERDES factor J = 1
to 2, uses DDR
registers
(77) —(79) (77) —(79) (77) —(79) Mbps
DPA Mode DPA run length — — — 10000 — — 10000 — — 10000 UI
So-CDR
Mode
So-CDR ppm tolerance — — — 300 — — 300 — — 300 ±ppm
Non-DPA
Mode
Sampling Window — — — 300 — — 300 — — 300 ps
(83) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
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DPA Lock Time Specications
Figure 1-4: Dynamic Phase Alignment (DPA) Lock Time Specications with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 Data
Transitions
96 Slow
Clock Cycles
256 Data
Transitions
256 Data
Transitions
96 Slow
Clock Cycles
Table 1-41: DPA Lock Time Specications for Arria V Devices
e specications are applicable to both commercial and industrial grades. e DPA lock time is for one channel. One data transition is dened as
a 0-to-1 or 1-to-0 transition.
Standard Training Pattern Number of Data
Transitions in One
Repetition of the Training
Pattern
Number of Repetitions per
256 Data Transitions(84)
Maximum Data Transition
SPI-4 00000000001111111111 2 128 640
Parallel Rapid I/O 00001111 2 128 640
10010000 4 64 640
Miscellaneous 10101010 8 32 640
01010101 8 32 640
(84) is is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specications
Figure 1-5: LVDS Soft-Clock Data Recovery (CDR)/DPA Sinusoidal Jitter Tolerance Specication for a Data Rate Equal to 1.25 Gbps
F1 F2 F3 F4
Jitter Frequency (Hz)
Jitter Amphlitude (UI)
0.1
0.35
8.5
25
Table 1-42: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1 10,000 25.000
F2 17,565 25.000
F3 1,493,000 0.350
F4 50,000,000 0.350
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Figure 1-6: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specication for a Data Rate Less than 1.25 Gbps
0.1 UI
P-P
baud/1667 20 MHz Frequency
Sinusoidal Jitter Amplitude
20db/dec
DLL Frequency Range Specications
Table 1-43: DLL Frequency Range Specications for Arria V Devices
Parameter –I3, –C4 –I5, –C5 –C6 Unit
DLL operating frequency range 200 – 667 200 – 667 200 – 667 MHz
DQS Logic Block Specications
Table 1-44: DQS Phase Shift Error Specications for DLL-Delayed Clock (tDQS_PSERR) for Arria V Devices
is error specication is the absolute maximum and minimum error.
Number of DQS Delay Buer –I3, –C4 –I5, –C5 –C6 Unit
2 40 80 80 ps
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Memory Output Clock Jitter Specications
Table 1-45: Memory Output Clock Jitter Specications for Arria V Devices
e memory output clock jitter measurements are for 200 consecutive clock cycles, as specied in the JEDEC DDR2/DDR3 SDRAM standard.
e memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.
Parameter Clock Network Symbol
–I3, –C4 –I5, –C5 –C6
Unit
Min Max Min Max Min Max
Clock period jitter PHYCLK tJIT(per) –41 41 –50 50 –55 55 ps
Cycle-to-cycle period jitter PHYCLK tJIT(cc) 63 90 94 ps
OCT Calibration Block Specications
Table 1-46: OCT Calibration Block Specications for Arria V Devices
Symbol Description Min Typ Max Unit
OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz
TOCTCAL Number of OCTUSRCLK clock cycles required for RS
OCT/RT OCT calibration
— 1000 — Cycles
TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT
code to shi out
— 32 — Cycles
TRS_RT Time required between the dyn_term_ctrl and oe
signal transitions in a bidirectional I/O buer to
dynamically switch between RS OCT and RT OCT
— 2.5 — ns
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Figure 1-7: Timing Diagram for oe and dyn_term_ctrl Signals
TX RXRX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Tristate Tristate
Duty Cycle Distortion (DCD) Specications
Table 1-47: Worst-Case DCD on Arria V I/O Pins
e output DCD cycle only applies to the I/O buer. It does not cover the system DCD.
Symbol
–I3, –C4 –C5, –I5 –C6
Unit
Min Max Min Max Min Max
Output Duty Cycle 45 55 45 55 45 55 %
HPS Specications
is section provides HPS specications and timing for Arria V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of
HPS_CLK1.
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HPS Clock Performance
Table 1-48: HPS Clock Performance for Arria V Devices
Symbol/Description –I3 –C4 –C5, –I5 –C6 Unit
mpu_base_clk (microprocessor unit clock) 1050 925 800 700 MHz
main_base_clk (L3/L4 interconnect clock) 400 400 400 350 MHz
h2f_user0_clk 100 100 100 100 MHz
h2f_user1_clk 100 100 100 100 MHz
h2f_user2_clk 200 200 200 160 MHz
HPS PLL Specications
HPS PLL VCO Frequency Range
Table 1-49: HPS PLL VCO Frequency Range for Arria V Devices
Description Speed Grade Minimum Maximum Unit
VCO range
–C5, –I5, –C6 320 1,600 MHz
–C4 320 1,850 MHz
–I3 320 2,100 MHz
HPS PLL Input Clock Range
e HPS PLL input clock range is 10 – 50 MHz. is clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.
Related Information
Clock Select, Booting and Conguration chapter
Provides more information about the clock range for dierent values of clock select (CSEL).
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HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. e divide value (N) is the value
programmed into the denominator eld of the VCO register for each PLL. e PLL input reference clock is divided by this value. e range of the
denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
Table 1-50: Examples of Maximum Input Jitter
Input Reference Clock Period Divide Value (N) Maximum Jitter Unit
40 ns 1 0.8 ns
40 ns 2 1.6 ns
40 ns 4 3.2 ns
Quad SPI Flash Timing Characteristics
Table 1-51: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices
Symbol Description Min Typ Max Unit
Fclk SCLK_OUT clock frequency (External clock) — — 108 MHz
Tqspi_clk QSPI_CLK clock period (Internal reference
clock)
2.32 — — ns
Tdutycycle SCLK_OUT duty cycle 45 — 55 %
Tdssfrst Output delay QSPI_SS valid before rst clock
edge
— 1/2 cycle of
SCLK_OUT
— ns
Tdsslst Output delay QSPI_SS valid aer last clock
edge
–1 — 1 ns
Tdio I/O data output delay –1 — 1 ns
Tdin_start Input data valid start — — (2 + Rdelay) ×
Tqspi_clk – 7.52 (85)
ns
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Symbol Description Min Typ Max Unit
Tdin_end Input data valid end (2 + Rdelay) ×
Tqspi_clk – 1.21 (85)
— — ns
Figure 1-8: Quad SPI Flash Timing Diagram
is timing diagram illustrates clock polarity mode 0 and clock phase mode 0.
QSPI_SS
SCLK_OUT
QSPI_DATA
Tdin_start
Tdsslst
Tdio
Tdin_end
Tdssfrst
Data Out Data In
Related Information
Quad SPI Flash Controller Chapter, Arria V Hard Processor System Technical Reference Manual
Provides more information about Rdelay.
SPI Timing Characteristics
Table 1-52: SPI Master Timing Requirements for Arria V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 16.67 — ns
Tsu SPI Master-in slave-out (MISO) setup time 8.35 (86) — ns
(85) Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS soware version 13.1 and later, Altera provides automatic Quad SPI
calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Arria V Hard Processor System
Technical Reference Manual.
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Symbol Description Min Max Unit
ThSPI MISO hold time 1 — ns
Tdutycycle SPI_CLK duty cycle 45 55 %
Tdssfrst Output delay SPI_SS valid before rst clock edge 8 — ns
Tdsslst Output delay SPI_SS valid aer last clock edge 8 — ns
Tdio Master-out slave-in (MOSI) output delay –1 1 ns
(86) is value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_
OUT. ese timings are based on rx_sample_dly of 1. is delay can be adjusted as needed to accommodate slower response times from the slave.
Note that a delay of 0 is not allowed. e setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_
sample_dly value because each SPI slave device may have dierent output delay and each application board may have dierent path delay. For more
information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual.
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Figure 1-9: SPI Master Timing Diagram
SPI_SS
SPI_CLK (scpol = 0)
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdssfrst
SPI_CLK (scpol = 1)
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdio
Tdio
Tdsslst
Tsu Th
Tsu Th
Table 1-53: SPI Slave Timing Requirements for Arria V Devices
e setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol Description Min Max Unit
Tclk CLK clock period 20 — ns
TsMOSI Setup time 5 — ns
ThMOSI Hold time 5 — ns
Tsuss Setup time SPI_SS valid before rst clock edge 8 — ns
Thss Hold time SPI_SS valid aer last clock edge 8 — ns
TdMISO output delay — 6 ns
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Figure 1-10: SPI Slave Timing Diagram
SPI_SS
SPI_CLK (scpol = 0)
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
SPI_CLK (scpol = 1)
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tsuss
Td
Td
Ts
Th
TsTh
Thss
Related Information
SPI Controller, Arria V Hard Processor System Technical Reference Manual
Provides more information about rx_sample_delay.
SD/MMC Timing Characteristics
Table 1-54: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices
Aer power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters
the Identication Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum
of 400 kHz (Identication Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL
setting. e value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz.
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Aer the Boot ROM code exits and control is passed to the preloader, soware can adjust the value of drvsel and smplsel via the system manager.
drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT
increase to a maximum of 200 MHz and 50 MHz respectively.
e SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS soware update.
Symbol Description Min Max Unit
Tsdmmc_clk (internal reference
clock)
SDMMC_CLK clock period
(Identication mode)
20 — ns
SDMMC_CLK clock period
(Default speed mode)
5 — ns
SDMMC_CLK clock period
(High speed mode)
5 — ns
Tsdmmc_clk_out (interface output
clock)
SDMMC_CLK_OUT clock
period (Identication mode)
2500 — ns
SDMMC_CLK_OUT clock
period (Default speed mode)
40 — ns
SDMMC_CLK_OUT clock
period (High speed mode)
20 — ns
Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 %
TdSDMMC_CMD/SDMMC_D
output delay
(Tsdmmc_clk × drvsel)/2
– 1.23 (87)
(Tsdmmc_clk × drvsel)/2
+ 1.69 (87)
ns
Tsu Input setup time 1.05 – (Tsdmmc_clk ×
smplsel)/2 (88)
— ns
ThInput hold time (Tsdmmc_clk × smplsel)/
2 (88)
— ns
(87) drvsel is the drive clock phase shi select value.
(88) smplsel is the sample clock phase shi select value.
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Figure 1-11: SD/MMC Timing Diagram
Command/Data In
SDMMC_CLK_OUT
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tsu
Td
Th
Related Information
Booting and Conguration Chapter, Arria V Hard Processor System Technical Reference Manual
Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table.
USB Timing Characteristics
PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the
MicroChip USB3300 PHY device that has been proven to be successful on the development board.
Table 1-55: USB Timing Requirements for Arria V Devices
Symbol Description Min Typ Max Unit
Tclk USB CLK clock period — 16.67 — ns
TdCLK to USB_STP/USB_DATA[7:0] output delay 4.4 — 11 ns
Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 — — ns
ThHold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 — — ns
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Figure 1-12: USB Timing Diagram
USB_CLK
USB_STP
USB_DATA[7:0]
USB_DIR & USB_NXT
To PHY From PHY
Tsu Th
Td
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 1-56: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria V Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period — 8 — ns
Tclk (100Base-T) TX_CLK clock period — 40 — ns
Tclk (10Base-T) TX_CLK clock period — 400 — ns
Tdutycycle TX_CLK duty cycle 45 — 55 %
TdTX_CLK to TXD/TX_CTL output data delay –0.85 — 0.15 ns
Figure 1-13: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
TX_CTL
Td
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Table 1-57: RGMII RX Timing Requirements for Arria V Devices
Symbol Description Min Typ Unit
Tclk (1000Base-T) RX_CLK clock period — 8 ns
Tclk (100Base-T) RX_CLK clock period — 40 ns
Tclk (10Base-T) RX_CLK clock period — 400 ns
Tsu RX_D/RX_CTL setup time 1 — ns
ThRX_D/RX_CTL hold time 1 — ns
Figure 1-14: RGMII RX Timing Diagram
RX_CLK
RX_D[3:0]
RX_CTL
Tsu Th
Table 1-58: Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices
Symbol Description Min Typ Max Unit
Tclk MDC clock period — 400 — ns
TdMDC to MDIO output data delay 10 — 20 ns
TsSetup time for MDIO data 10 — — ns
ThHold time for MDIO data 0 — — ns
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Figure 1-15: MDIO Timing Diagram
MDC
MDIO_OUT
MDIO_IN
Tsu
Th
Td
I2C Timing Characteristics
Table 1-59: I2C Timing Requirements for Arria V Devices
Symbol Description
Standard Mode Fast Mode
Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — µs
Tclkhigh SCL high time 4.7 — 0.6 — µs
Tclklow SCL low time 4 — 1.3 — µs
TsSetup time for serial data line (SDA) data to SCL 0.25 — 0.1 — µs
ThHold time for SCL to SDA data 0 3.45 0 0.9 µs
TdSCL to SDA output data delay — 0.2 — 0.2 µs
Tsu_start Setup time for a repeated start condition 4.7 — 0.6 — µs
Thd_start Hold time for a repeated start condition 4 — 0.6 — µs
Tsu_stop Setup time for a stop condition 4 — 0.6 — µs
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Figure 1-16: I2C Timing Diagram
Data In
Td
Data Out
I2C_SCL
I2C_SDA
Ts
Th
Tsu_start Thd_start
Tsu_stop
NAND Timing Characteristics
Table 1-60: NAND ONFI 1.0 Timing Requirements for Arria V Devices
e NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. is table lists the
requirements for ONFI 1.0 mode 5 timing. e HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL
and timing registers provided in the NAND controller.
Symbol Description Min Max Unit
Twp(89) Write enable pulse width 10 — ns
Twh(89) Write enable hold time 7 — ns
Trp(89) Read enable pulse width 10 — ns
Treh(89) Read enable hold time 7 — ns
Tclesu(89) Command latch enable to write enable setup time 10 — ns
Tcleh(89) Command latch enable to write enable hold time 5 — ns
Tcesu(89) Chip enable to write enable setup time 15 — ns
Tceh(89) Chip enable to write enable hold time 5 — ns
Talesu(89) Address latch enable to write enable setup time 10 — ns
Taleh(89) Address latch enable to write enable hold time 5 — ns
Tdsu(89) Data to write enable setup time 10 — ns
(89) Timing of the NAND interface is controlled through the NAND conguration registers.
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Symbol Description Min Max Unit
Tdh(89) Data to write enable hold time 5 — ns
Tcea Chip enable to data access time — 25 ns
Trea Read enable to data access time — 16 ns
Trhz Read enable to data high impedance — 100 ns
Trr Ready to read enable low 20 — ns
Figure 1-17: NAND Command Latch Timing Diagram
Command
NAND_CLE
NAND_CE
NAND_WE
NAND_DQ[7:0]
Tclesu
Tcesu Tcleh
Tceh
Twp
Talesu Taleh
Tdsu Tdh
NAND_ALE
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Figure 1-20: NAND Data Read Timing Diagram
NAND_RE
NAND_RB
NAND_DQ[7:0]
NAND_CE
Dout
Tcea
Trp Treh
Trea
Trhz
Trr
ARM Trace Timing Characteristics
Table 1-61: ARM Trace Timing Requirements for Arria V Devices
Most debugging tools have a mechanism to adjust the capture point of trace data.
Description Min Max Unit
CLK clock period 12.5 — ns
CLK maximum duty cycle 45 55 %
CLK to D0 –D7 output data delay –1 1 ns
UART Interface
e maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
e minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. e pulse width is based on a debounce clock frequency of 1 MHz.
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HPS JTAG Timing Specications
Table 1-62: HPS JTAG Timing Parameters and Values for Arria V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30 — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 2 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 12(90) ns
tJPZX JTAG port high impedance to valid output — 14(90) ns
tJPXZ JTAG port valid output to high impedance — 14(90) ns
Conguration Specications
is section provides conguration specications and timing for Arria V devices.
POR Specications
Table 1-63: Fast and Standard POR Delay Specication for Arria V Devices
POR Delay Minimum Maximum Unit
Fast 4 12(91) ms
(90) A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or
14 ns if it equals 1.8 V.
(91) e maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize aer the POR trip.
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POR Delay Minimum Maximum Unit
Standard 100 300 ms
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each conguration scheme.
FPGA JTAG Conguration Timing
Table 1-64: FPGA JTAG Timing Parameters and Values for Arria V Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30, 167(92) — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 2 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 12(93) ns
tJPZX JTAG port high impedance to valid output — 14(93) ns
tJPXZ JTAG port valid output to high impedance — 14(93) ns
(92) e minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
(93) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if
it equals 1.8 V.
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FPP Conguration Timing
DCLK-to-DATA[] Ratio (r) for FPP Conguration
Fast passive parallel (FPP) conguration requires a dierent DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
Table 1-65: DCLK-to-DATA[] Ratio for Arria V Devices
Conguration Scheme Encryption Compression DCLK-to-DATA[] Ratio (r)
FPP (8-bit wide)
O O 1
On O 1
O On 2
On On 2
FPP (16-bit wide)
O O 1
On O 2
O On 4
On On 4
FPP Conguration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-
to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria V Devices table.
Table 1-66: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — µs
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Symbol Parameter Minimum Maximum Unit
tSTATUS nSTATUS low pulse width 268 1506(94) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(95) µs
tCF2CK(96) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(96) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz
tCD2UM CONF_DONE high to user mode(97) 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4× maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
FPP Conguration Timing
Provides the FPP conguration timing waveforms.
(94) You can obtain this value if you do not delay conguration by extending the nCONFIG or the nSTATUS low pulse width.
(95) You can obtain this value if you do not delay conguration by externally holding the nSTATUS low.
(96) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(97) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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FPP Conguration Timing when DCLK-to-DATA[] >1
Table 1-67: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices
Use these timing parameters when you use the decompression and design security features.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — µs
tSTATUS nSTATUS low pulse width 268 1506(98) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(99) µs
tCF2CK(100) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(100) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK N – 1/fDCLK(101) — s
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz
tRInput rise time — 40 ns
tFInput fall time — 40 ns
tCD2UM CONF_DONE high to user mode(102) 175 437 µs
(98) is value can be obtained if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(99) is value can be obtained if you do not delay conguration by externally holding nSTATUS low.
(100) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(101) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
(102) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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Symbol Parameter Minimum Maximum Unit
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
FPP Conguration Timing
Provides the FPP conguration timing waveforms.
AS Conguration Timing
Table 1-68: AS Timing Parameters for AS ×1 and ×4 Congurations in Arria V Devices
e minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device
conguration.
e tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS
Timing Parameters for Arria V Devices table. You can obtain the tCF2ST1 value if you do not delay conguration by externally holding nSTATUS low.
Symbol Parameter Minimum Maximum Unit
tCO DCLK falling edge to the AS_DATA0/ASDO output — 2 ns
tSU Data setup time before the falling edge on DCLK 1.5 — ns
tDH Data hold time aer the falling edge on DCLK 0 — ns
tCD2UM CONF_DONE high to user mode 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
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Related Information
•PS Conguration Timing on page 1-81
•AS Conguration Timing
Provides the AS conguration timing waveform.
DCLK Frequency Specication in the AS Conguration Scheme
Table 1-69: DCLK Frequency Specication in the AS Conguration Scheme
is table lists the internal clock frequency specication for the AS conguration scheme. e DCLK frequency specication applies when you use
the internal oscillator as the conguration clock source. e AS multi-device conguration scheme does not support DCLK frequency of 100 MHz.
Parameter Minimum Typical Maximum Unit
DCLK frequency in AS conguration scheme
5.3 7.9 12.5 MHz
10.6 15.7 25.0 MHz
21.3 31.4 50.0 MHz
42.6 62.9 100.0 MHz
PS Conguration Timing
Table 1-70: PS Timing Parameters for Arria V Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — µs
tSTATUS nSTATUS low pulse width 268 1506(103) µs
tCF2ST1 nCONFIG high to nSTATUS high — 1506(104) µs
(103) You can obtain this value if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(104) You can obtain this value if you do not delay conguration by externally holding nSTATUS low.
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Symbol Parameter Minimum Maximum Unit
tCF2CK(105) nCONFIG high to rst rising edge on DCLK 1506 — µs
tST2CK(105) nSTATUS high to rst rising edge of DCLK 2 — µs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency — 125 MHz
tCD2UM CONF_DONE high to user mode(106) 175 437 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR
period)
— —
Tinit Number of clock cycles required for device initialization 8,576 — Cycles
Related Information
PS Conguration Timing
Provides the PS conguration timing waveform.
(105) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(106) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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Initialization
Table 1-71: Initialization Clock Source Option and the Maximum Frequency for Arria V Devices
Initialization Clock Source Conguration Scheme Maximum Frequency (MHz) Minimum Number of Clock Cycles
Internal Oscillator AS, PS, and FPP 12.5
Tinit
CLKUSR(107) PS and FPP 125
AS 100
DCLK PS and FPP 125
Conguration Files
Table 1-72: Uncompressed .rbf Sizes for Arria V Devices
Use this table to estimate the le size before design compilation. Dierent conguration le formats, such as a hexadecimal le (.hex) or tabular
text le (.ttf) format, have dierent le sizes.
For the dierent types of conguration le and le sizes, refer to the Quartus Prime soware. However, for a specic version of the Quartus Prime
soware, any design targeted for the same device has the same uncompressed conguration le size.
e IOCSR raw binary le (.rbf) size is specically for the Conguration via Protocol (CvP) feature.
(107) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime
soware from the General panel of the Device and Pin Options dialog box.
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Variant Member Code Conguration .rbf Size (bits) IOCSR .rbf Size (bits)
Arria V GX
A1 71,015,712 439,960
A3 71,015,712 439,960
A5 101,740,800 446,360
A7 101,740,800 446,360
B1 137,785,088 457,368
B3 137,785,088 457,368
B5 185,915,808 463,128
B7 185,915,808 463,128
Arria V GT
C3 71,015,712 439,960
C7 101,740,800 446,360
D3 137,785,088 457,368
D7 185,915,808 463,128
Arria V SX B3 185,903,680 450,968
B5 185,903,680 450,968
Arria V ST D3 185,903,680 450,968
D5 185,903,680 450,968
Minimum Conguration Time Estimation
Table 1-73: Minimum Conguration Time Estimation for Arria V Devices
e estimated values are based on the conguration .rbf sizes in Uncompressed .rbf Sizes for Arria V Devices table.
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Variant Member Code
Active Serial(108) Fast Passive Parallel(109)
Width DCLK (MHz) Minimum Congura‐
tion Time (ms)
Width DCLK (MHz) Minimum Conguration Time
(ms)
Arria V GX
A1 4 100 178 16 125 36
A3 4 100 178 16 125 36
A5 4 100 255 16 125 51
A7 4 100 255 16 125 51
B1 4 100 344 16 125 69
B3 4 100 344 16 125 69
B5 4 100 465 16 125 93
B7 4 100 465 16 125 93
Arria V GT
C3 4 100 178 16 125 36
C7 4 100 255 16 125 51
D3 4 100 344 16 125 69
D7 4 100 465 16 125 93
Arria V SX B3 4 100 465 16 125 93
B5 4 100 465 16 125 93
Arria V ST D3 4 100 465 16 125 93
D5 4 100 465 16 125 93
Related Information
Conguration Files on page 1-83
(108) DCLK frequency of 100 MHz using external CLKUSR.
(109) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
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Remote System Upgrades
Table 1-74: Remote System Upgrade Circuitry Timing Specications for Arria V Devices
Parameter Minimum Unit
tRU_nCONFIG(110) 250 ns
tRU_nRSTIMER(111) 250 ns
Related Information
•Remote System Upgrade State Machine
Provides more information about conguration reset (RU_CONFIG) signal.
•User Watchdog Timer
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Oscillator Frequency Specications
Table 1-75: User Watchdog Internal Oscillator Frequency Specications for Arria V Devices
Parameter Minimum Typical Maximum Unit
User watchdog internal oscillator frequency 5.3 7.9 12.5 MHz
I/O Timing
Altera oers two ways to determine I/O timing—the Excel-based I/O timing and the Quartus Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. e data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
(110) is is equivalent to strobing the reconguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication.
(111) is is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication.
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e Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specics of the design aer you complete
place-and-route.
Related Information
Arria V I/O Timing Spreadsheet
Provides the Arria V Excel-based I/O timing spreadsheet.
Programmable IOE Delay
Table 1-76: I/O element (IOE) Programmable Delay for Arria V Devices
Parameter(112
)
Available
Settings
Minimum
Oset(113)
Fast Model Slow Model
Unit
Industrial Commercial –C4 –C5 –C6 –I3 –I5
D1 32 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns
D3 8 0 1.763 1.795 2.999 3.496 3.571 3.031 3.643 ns
D4 32 0 0.508 0.518 0.869 1.063 1.063 1.063 1.057 ns
D5 32 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns
Programmable Output Buer Delay
Table 1-77: Programmable Output Buer Delay for Arria V Devices
is table lists the delay chain settings that control the rising and falling edge delays of the output buer.
You can set the programmable output buer delay in the Quartus Prime soware by setting the Output Buer Delay Control assignment to either
positive, negative, or both edges, with the specic values stated here (in ps) for the Output Buer Delay assignment.
(112) You can set this value in the Quartus Prime soware by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
(113) Minimum oset does not include the intrinsic delay.
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Symbol Parameter Typical Unit
DOUTBUF Rising and/or falling edge delay
0 (default) ps
50 ps
100 ps
150 ps
Glossary
Table 1-78: Glossary
Term Denition
Dierential I/O standards Receiver Input Waveforms
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
VID
VID
p - n = 0 V
VCM
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Term Denition
Transmitter Output Waveforms
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
p - n = 0 V
VCM
fHSCLK Le/right PLL input clock frequency.
fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI), non-DPA.
fHSDRDPA High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDRDPA =1/TUI), DPA.
J High-speed I/O block—Deserialization factor (width of parallel data bus).
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Term Denition
PLL specications Diagram of PLL specications
Core Clock
External Feedback
Reconfigurable in User Mode
Legend
CLK
N
PFD
Switchover
Delta Sigma
Modulator
VCO
CP LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO fOUT
fOUT _EXT
Counters
C0..C17
4
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
RLReceiver dierential input discrete resistor (external to the Arria V device).
Sampling window (SW) Timing diagram—e period of time during which the data must be valid in order to capture it correctly.
e setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
0.5 x TCCS RSKM Sampling Window
(SW)
RSKM 0.5 x TCCS
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Term Denition
Single-ended voltage referenced I/O
standard e JEDEC standard for the SSTL and HSTL I/O denes both the AC and DC input signal values. e AC
values indicate the voltage levels at which the receiver must meet its timing specications. e DC values
indicate the voltage levels at which the nal logic state of the receiver is unambiguously dened. Aer the
receiver input has crossed the AC value, the receiver changes to the new logic state.
e new logic state is then maintained as long as the input stays beyond the DC threshold. is approach
is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
VIH(AC )
VIH(DC )
VREF VIL(DC )
VIL(AC )
VOH
VOL
VCCIO
VSS
tCHigh-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew) e timing dierence between the fastest and slowest output edges, including the tCO variation and clock
skew, across channels driven by the same PLL. e clock is included in the TCCS measurement (refer to
the Timing Diagram gure under SW in this table).
tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock.
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Term Denition
tFALL Signal high-to-low transition time (80–20%)
tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO Period jitter on the GPIO driven by a PLL
tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL
tRISE Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI) e timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/
(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
VCM(DC) DC common mode input voltage.
VICM Input common mode voltage—e common mode of the dierential signal at the receiver.
VID Input dierential voltage swing—e dierence in voltage between the positive and complementary
conductors of a dierential transmission at the receiver.
VDIF(AC) AC dierential input voltage—Minimum AC input dierential voltage required for switching.
VDIF(DC) DC dierential input voltage— Minimum DC input dierential voltage required for switching.
VIH Voltage input high—e minimum positive voltage applied to the input which is accepted by the device as
a logic high.
VIH(AC) High-level AC input voltage
VIH(DC) High-level DC input voltage
VIL Voltage input low—e maximum positive voltage applied to the input which is accepted by the device as
a logic low.
VIL(AC) Low-level AC input voltage
VIL(DC) Low-level DC input voltage
VOCM Output common mode voltage—e common mode of the dierential signal at the transmitter.
VOD Output dierential voltage swing—e dierence in voltage between the positive and complementary
conductors of a dierential transmission line at the transmitter.
VSWING Dierential input voltage
VXInput dierential cross point voltage
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Term Denition
VOX Output dierential cross point voltage
W High-speed I/O block—Clock boost factor
Document Revision History
Date Version Changes
December 2016 2016.12.09 • Updated VICM (AC coupled) specications in Receiver Specications for Arria V GX and SX Devices table.
• Added maximum specication for Td in Management Data Input/Output (MDIO) Timing Requirements for
Arria V Devices table.
• Updated Tinit specications in the following tables:
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices
• FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices
• AS Timing Parameters for AS ×1 and ×4 Congurations in Arria V Devices
• PS Timing Parameters for Arria V Devices
June 2016 2016.06.10 • Changed pin capacitance to maximum values.
• Updated SPI Master Timing Requirements for Arria V Devices table.
• Added Tsu and Th specications.
• Removed Tdinmax specications.
• Updated SPI Master Timing Diagram.
• Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Arria V Devices table.
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December 2015 2015.12.16 • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices table.
• Updated Fclk, Tdutycycle, and Tdssfrst specications.
• Added Tqspi_clk, Tdin_start, and Tdin_end specications.
• Removed Tdinmax specications.
• Updated the minimum specication for Tclk to 16.67 ns and removed the maximum specication in SPI
Master Timing Requirements for Arria V Devices table.
• Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices table.
• Updated T clk to Tsdmmc_clk_out symbol.
• Updated Tsdmmc_clk_out and Td specications.
• Added Tsdmmc_clk, Tsu, and Th specications.
• Removed Tdinmax specications.
• Updated the following diagrams:
• Quad SPI Flash Timing Diagram
• SD/MMC Timing Diagram
• Updated conguration .rbf sizes for Arria V devices.
• Changed instances of Quartus II to Quartus Prime.
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June 2015 2015.06.16 • Added the supported data rates for the following output standards using true LVDS output buer types in
the High-Speed I/O Specications for Arria V Devices table:
• True RSDS output standard: data rates of up to 360 Mbps
• True mini-LVDS output standard: data rates of up to 400 Mbps
• Added note in the condition for Transmitter—Emulated Dierential I/O Standards fHSDR data rate parameter
in the High-Speed I/O Specications for Arria V Devices table. Note: When using True LVDS RX channels
for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
• Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
• Updated Th location in I2C Timing Diagram.
• Updared Twp location in NAND Address Latch Timing Diagram.
• Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for
Arria V Devices table.
• Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Congu‐
rations in Arria V Devices table.
• Moved the following timing diagrams to the Conguration, Design Security, and Remote System Upgrades
in Arria V Devices chapter.
• FPP Conguration Timing Waveform When DCLK-to-DATA[] Ratio is 1
• FPP Conguration Timing Waveform When DCLK-to-DATA[] Ratio is >1
• AS Conguration Timing Waveform
• PS Conguration Timing Waveform
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January 2015 2015.01.30 • Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply” in the following tables:
• Absolute Maximum Ratings for Arria V Devices
• HPS Power Supply Operating Conditions for Arria V SX and ST Devices
• Added statement in I/O Standard Specications: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
• Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of
dierential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK
phase noise specication.
• Updated the description in Periphery Performance Specications to mention that proper timing closure is
required in design.
• Updated HPS Clock Performance main_base_clk specications from 525 MHz (for –I3 speed grade) and 462
MHz (for –C4 speed grade) to 400 MHz.
• Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C5, –I5, and –C6 speed grades), 1,850
MHz (for –C4 speed grade), and 2,100 MHz (for –I3 speed grade).
• Changed the symbol for HPS PLL input jitter divide value from NR to N.
• Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:
• SPI Master Timing Requirements for Arria V Devices
• SPI Slave Timing Requirements for Arria V Devices
• Added descriptions to USB Timing Characteristics section in HPS Specications: PHYs that support LPM
mode may not function properly with the USB controller due to a timing issue. It is recommended that
designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development
board.
• Added HPS JTAG timing specications.
• Updated FPGA JTAG timing specications note as follows: A 1-ns adder is required for each VCCIO voltage
step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals
1.8 V.
• Updated the value in the VICM (AC Coupled) row and in note 6 from 650 mV to 750 mV in the Transceiver
Specications for Arria V GT and ST Devices table.
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July 2014 3.8 • Added a note in Table 3, Table 4, and Table 5: e power supply value describes the budget for the DC
(static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN
tool for the additional budget for the dynamic tolerance requirements.
• Updated VCC_HPS specication in Table 5.
• Added a note in Table 19: Dierential inputs are powered by VCCPD which requires 2.5 V.
• Updated "Minimum dierential eye opening at the receiver serial input pins" specication in Table 20 and
Table 21.
• Updated description in “HPS PLL Specications” section.
• Updated VCO range maximum specication in Table 39.
• Updated Td and Th specications in Table 45.
• Added Th specication in Table 47 and Figure 13.
• Updated a note in Figure 20, Figure 21, and Figure 23 as follows: Do not leave DCLK oating aer congura‐
tion. DCLK is ignored aer conguration is complete. It can toggle high or low if required.
• Removed “Remote update only in AS mode” specication in Table 58.
• Added DCLK device initialization clock source specication in Table 60.
• Added description in “Conguration Files” section: e IOCSR .rbf size is specically for the Congura‐
tion via Protocol (CvP) feature.
• Removed fMAX_RU_CLK specication in Table 63.
February 2014 3.7 • Updated VCCRSTCLK_HPS maximum specication in Table 1.
• Added VCC_AUX_SHARED specication in Table 1.
December 2013 3.6 • Added “HPS PLL Specications”.
• Added Table 24, Table 39, and Table 40.
• Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41, Table 42, Table 43, Table
44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, Table 51, Table 55, Table 56, and Table 59.
• Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19.
• Removed table: GPIO Pulse Width for Arria V Devices.
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August 2013 3.5 • Removed “Pending silicon characterization” note in Table 29.
• Updated Table 25.
August 2013 3.4 • Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12,
Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, Table 23,
Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 30, Table 31, Table 35, Table 36, Table 51,
Table 53, Table 54, Table 55, Table 56, Table 57, Table 60, Table 62, and Table 64.
• Updated Table 1, Table 3, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, and Table 29.
June 2013 3.3 Updated Table 20, Table 21, Table 25, and Table 38.
May 2013 3.2 • Added Table 37.
• Updated Figure 8, Figure 9, Figure 20, Figure 22, and Figure 23.
• Updated Table 1, Table 5, Table 10, Table 13, Table 19, Table 20, Table 21, Table 23, Table 29, Table 39, Table
40, Table 46, Table 56, Table 57, Table 60, and Table 64.
• Updated industrial junction temperature range for –I3 speed grade in “PLL Specications” section.
March 2013 3.1 • Added HPS reset information in the “HPS Specications” section.
• Added Table 60.
• Updated Table 1, Table 3, Table 17, Table 20, Table 29, and Table 59.
• Updated Figure 21.
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November 2012 3.0 • Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21, Table 25, Table 29, Table
36, Table 56, Table 57, and Table 60.
• Removed table: Transceiver Block Jitter Specications for Arria V Devices.
• Added HPS information:
• Added “HPS Specications” section.
• Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47,
Table 48, Table 49, and Table 50.
• Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure
16, Figure 17, Figure 18, and Figure 19.
• Updated Table 3 and Table 5.
October 2012 2.4 • Updated Arria V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum values, and data
rate in Table 4.
• Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM (AC coupled) and
VOCM (DC coupled) values in Table 20 and Table 21.
August 2012 2.3 Updated the SERDES factor condition in Table 30.
July 2012 2.2 • Updated the maximum voltage for VI (DC input voltage) in Table 1.
• Updated Table 20 to include the Arria V GX -I3 speed grade.
• Updated the minimum value of the xedclk clock frequency in Table 20 and Table 21.
• Updated the SERDES factor condition in Table 30.
• Updated Table 50 to include the IOE programmable delay settings for the Arria V GX -I3 speed grade.
June 2012 2.1 Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4.
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Date Version Changes
June 2012 2.0 • Updated for the Quartus II soware v12.0 release:
• Restructured document.
• Updated “Supply Current and Power Consumption” section.
• Updated Table 20, Table 21, Table 24, Table 25, Table 26, Table 35, Table 39, Table 43, and Table 52.
• Added Table 22, Table 23, and Table 33.
• Added Figure 1–1 and Figure 1–2.
• Added “Initialization” and “Conguration Files” sections.
February 2012 1.3 • Updated Table 2–1.
• Updated Transceiver-FPGA Fabric Interface rows in Table 2–20.
• Updated VCCP description.
December 2011 1.2 Updated Table 2–1 and Table 2–3.
November 2011 1.1 • Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36.
• Added Table 2–5.
• Added Figure 2–4.
August 2011 1.0 Initial release.
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Arria V GZ Device Datasheet 2
2016.12.09
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is document covers the electrical and switching characteristics for Arria V GZ devices. Electrical characteristics include operating conditions and
power consumption. Switching characteristics include transceiver specications, core, and periphery performance. is document also describes
I/O timing, including programmable I/O element (IOE) delay and programmable output buer delay.
Related Information
Arria V Device Overview
For information regarding the densities and packages of devices in the Arria V GZ family.
Electrical Characteristics
Operating Conditions
When you use Arria V GZ devices, they are rated according to a set of dened parameters. To maintain the highest possible performance and
reliability of Arria V GZ devices, you must consider the operating requirements described in this datasheet.
Arria V GZ devices are oered in commercial and industrial temperature grades.
Commercial devices are oered in –3 (fastest) and –4 core speed grades. Industrial devices are oered in –3L and –4 core speed grades. Arria V GZ
devices are oered in –2 and –3 transceiver speed grades.
Table 2-1: Commercial and Industrial Speed Grade Oering for Arria V GZ Devices
C = Commercial temperature grade; I = Industrial temperature grade.
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other
countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for products
or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Lower number refers to faster speed grade.
L = Low power devices.
Transceiver Speed Grade
Core Speed Grade
C3 C4 I3L I4
2 Yes — Yes —
3 — Yes — Yes
Absolute Maximum Ratings
Absolute maximum ratings dene the maximum operating conditions for Arria V GZ devices. e values are based on experiments conducted with
the devices and theoretical modeling of breakdown and damage mechanisms. e functional operation of the device is not implied for these
conditions.
Caution: Conditions other than those listed in the following table may cause permanent damage to the device. Additionally, device operation at
the absolute maximum ratings for extended periods of time may have adverse eects on the device.
Table 2-2: Absolute Maximum Ratings for Arria V GZ Devices
Symbol Description Minimum Maximum Unit
VCC Power supply for core voltage and periphery circuitry –0.5 1.35 V
VCCPT Power supply for programmable power technology –0.5 1.8 V
VCCPGM Power supply for conguration pins –0.5 3.9 V
VCC_AUX Auxiliary supply for the programmable power technology –0.5 3.4 V
VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.9 V
VCCPD I/O pre-driver power supply –0.5 3.9 V
VCCIO I/O power supply –0.5 3.9 V
VCCD_FPLL PLL digital power supply –0.5 1.8 V
VCCA_FPLL PLL analog power supply –0.5 3.4 V
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Symbol Description Minimum Maximum Unit
VIDC input voltage –0.5 3.8 V
TJOperating junction temperature –55 125 °C
TSTG Storage temperature (No bias) –65 150 °C
IOUT DC output current per pin –25 40 mA
Table 2-3: Transceiver Power Supply Absolute Conditions for Arria V GZ Devices
Symbol Description Minimum Maximum Unit
VCCA_GXBL Transceiver channel PLL power supply (le side) –0.5 3.75 V
VCCA_GXBR Transceiver channel PLL power supply (right side) –0.5 3.75 V
VCCHIP_L Transceiver hard IP power supply (le side) –0.5 1.35 V
VCCHSSI_L Transceiver PCS power supply (le side) –0.5 1.35 V
VCCHSSI_R Transceiver PCS power supply (right side) –0.5 1.35 V
VCCR_GXBL Receiver analog power supply (le side) –0.5 1.35 V
VCCR_GXBR Receiver analog power supply (right side) –0.5 1.35 V
VCCT_GXBL Transmitter analog power supply (le side) –0.5 1.35 V
VCCT_GXBR Transmitter analog power supply (right side) –0.5 1.35 V
VCCH_GXBL Transmitter output buer power supply (le side) –0.5 1.8 V
VCCH_GXBR Transmitter output buer power supply (right side) –0.5 1.8 V
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in the following table. ey may also undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
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e maximum allowed overshoot duration is specied as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% of the duty cycle.
For example, a signal that overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for a device lifetime of 10 years, the
overshoot duration amounts to ~2 years.
Table 2-4: Maximum Allowed Overshoot During Transitions for Arria V GZ Devices
Symbol Description Condition (V) Overshoot Duration as % @ TJ = 100°C Unit
Vi (AC) AC input voltage
3.8 100 %
3.85 64 %
3.9 36 %
3.95 21 %
4 12 %
4.05 7 %
4.1 4 %
4.15 2 %
4.2 1 %
Recommended Operating Conditions
Table 2-5: Recommended Operating Conditions for Arria V GZ Devices
Power supply ramps must all be strictly monotonic, without plateaus.
Symbol Description Condition Minimum(114) Typical Maximum (114) Unit
VCC Core voltage and periphery circuitry power supply (115) — 0.82 0.85 0.88 V
(114) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(115) e VCC core supply must be set to 0.9 V if the Partial Reconguration (PR) feature is used.
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Symbol Description Condition Minimum(114) Typical Maximum (114) Unit
VCCPT Power supply for programmable power technology — 1.45 1.50 1.55 V
VCC_AUX Auxiliary supply for the programmable power
technology
— 2.375 2.5 2.625 V
VCCPD (116
)
I/O pre-driver (3.0 V) power supply — 2.85 3.0 3.15 V
I/O pre-driver (2.5 V) power supply — 2.375 2.5 2.625 V
VCCIO
I/O buers (3.0 V) power supply — 2.85 3.0 3.15 V
I/O buers (2.5 V) power supply — 2.375 2.5 2.625 V
I/O buers (1.8 V) power supply — 1.71 1.8 1.89 V
I/O buers (1.5 V) power supply — 1.425 1.5 1.575 V
I/O buers (1.35 V) power supply — 1.283 1.35 1.45 V
I/O buers (1.25 V) power supply — 1.19 1.25 1.31 V
I/O buers (1.2 V) power supply — 1.14 1.2 1.26 V
VCCPGM
Conguration pins (3.0 V) power supply — 2.85 3.0 3.15 V
Conguration pins (2.5 V) power supply — 2.375 2.5 2.625 V
Conguration pins (1.8 V) power supply — 1.71 1.8 1.89 V
VCCA_
FPLL
PLL analog voltage regulator power supply — 2.375 2.5 2.625 V
VCCD_
FPLL
PLL digital voltage regulator power supply — 1.45 1.5 1.55 V
VCCBAT (117) Battery back-up power supply (For design security
volatile key register)
— 1.2 — 3.0 V
(114) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(116) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(117) If you do not use the design security feature in Arria V GZ devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Arria V GZ power-on-reset
(POR) circuitry monitors VCCBAT. Arria V GZ devices do not exit POR if VCCBAT is not powered up.
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Symbol Description Condition Minimum(114) Typical Maximum (114) Unit
VIDC input voltage — –0.5 — 3.6 V
VOOutput voltage — 0 — VCCIO V
TJOperating junction temperature Commercial 0 — 85 °C
Industrial –40 — 100 °C
tRAMP Power supply ramp time Standard POR 200 µs — 100 ms —
Fast POR 200 µs — 4 ms —
Recommended Transceiver Power Supply Operating Conditions
Table 2-6: Recommended Transceiver Power Supply Operating Conditions for Arria V GZ Devices
Symbol Description Minimum (118) Typical Maximum(118) Unit
VCCA_GXBL
(119), (120) Transceiver channel PLL power supply (le side) 2.85 3.0 3.15 V
2.375 2.5 2.625
VCCA_
GXBR (119), (120) Transceiver channel PLL power supply (right side) 2.85 3.0 3.15 V
2.375 2.5 2.625
VCCHIP_L Transceiver hard IP power supply (le side) 0.82 0.85 0.88 V
VCCHSSI_L Transceiver PCS power supply (le side) 0.82 0.85 0.88 V
VCCHSSI_R Transceiver PCS power supply (right side) 0.82 0.85 0.88 V
(114) e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(118) is value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
(119) is supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are congured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps, you can
connect this supply to either 3.0 V or 2.5 V.
(120) When using ATX PLLs, the supply must be 3.0 V.
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Symbol Description Minimum (118) Typical Maximum(118) Unit
VCCR_GXBL (121) Receiver analog power supply (le side)
0.82 0.85 0.88
V0.97 1.0 1.03
1.03 1.05 1.07
VCCR_GXBR (121) Receiver analog power supply (right side)
0.82 0.85 0.88
V
0.97 1.0 1.03
1.03 1.05 1.07
VCCT_GXBL (121) Transmitter analog power supply (le side)
0.82 0.85 0.88
V
0.97 1.0 1.03
1.03 1.05 1.07
VCCT_GXBR (121) Transmitter analog power supply (right side)
0.82 0.85 0.88
V
0.97 1.0 1.03
1.03 1.05 1.07
VCCH_GXBL Transmitter output buer power supply (le side) 1.425 1.5 1.575 V
VCCH_GXBR Transmitter output buer power supply (right side) 1.425 1.5 1.575 V
(118) is value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
(121) is supply must be connected to 1.0 V if the transceiver is congured at a data rate > 6.5 Gbps, and to 1.05 V if congured at a data rate > 10.3 Gbps
when DFE is used. For data rate up to 6.5 Gbps, you can connect this supply to 0.85 V.
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Transceiver Power Supply Requirements
Table 2-7: Transceiver Power Supply Voltage Requirements for Arria V GZ Devices
Conditions VCCR_GXB and VCCT_GXB (122) VCCA_GXB VCCH_GXB Unit
If BOTH of the following conditions are true:
• Data rate > 10.3 Gbps.
• DFE is used.
1.05
3.0
1.5 V
If ANY of the following conditions are true (123) :
• ATX PLL is used.
• Data rate > 6.5Gbps.
• DFE (data rate ≤ 10.3 Gbps), AEQ, or EyeQ feature
is used.
1.0
If ALL of the following conditions are true:
• ATX PLL is not used.
• Data rate ≤ 6.5Gbps.
• DFE, AEQ, and EyeQ are not used.
0.85 2.5
DC Characteristics
Supply Current
Standby current is the current drawn from the respective power rails used for power budgeting.
Use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design because these currents vary greatly with the
resources you use.
(122) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and
VCCT_GXB are set to 0.85 V, they can be shared with the VCC core supply.
(123) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions.
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Related Information
•PowerPlay Early Power Estimator User Guide
For more information about the EPE tool.
•PowerPlay Power Analysis
For more information about PowerPlay power analysis.
Power Consumption
Altera oers two ways to estimate power consumption for a design—the Excel-based Early Power Estimator and the Quartus II PowerPlay Power
Analyzer feature.
Note: You typically use the interactive Excel-based Early Power Estimator before designing the FPGA to get a magnitude estimate of the device
power. e Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specics of the design aer you complete
place-and-route. e PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities
that, when combined with detailed circuit models, yields very accurate power estimates.
Related Information
•PowerPlay Early Power Estimator User Guide
For more information about the EPE tool.
•PowerPlay Power Analysis
For more information about PowerPlay power analysis.
I/O Pin Leakage Current
Table 2-8: I/O Pin Leakage Current for Arria V GZ Devices
If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected.
Symbol Description Conditions Min Typ Max Unit
IIInput pin VI = 0 V to VCCIOMAX –30 — 30 µA
IOZ Tri-stated I/O
pin
VO = 0 V to VCCIOMAX –30 — 30 µA
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Bus Hold Specications
Table 2-9: Bus Hold Parameters for Arria V GZ Devices
Parameter Symbol Conditions
VCCIO
Unit1.2 V 1.5 V 1.8 V 2.5 V 3.0 V
Min Max Min Max Min Max Min Max Min Max
Low
sustaining
current
ISUSL VIN > VIL
(maximum)
22.5 — 25.0 — 30.0 — 50.0 — 70.0 — µA
High
sustaining
current
ISUSH VIN < VIH
(minimum)
–22.5 — –25.0 — –30.0 — –50.0 — –70.0 — µA
Low
overdrive
current
IODL 0V < VIN <
VCCIO
— 120 — 160 — 200 — 300 — 500 µA
High
overdrive
current
IODH 0V < VIN <
VCCIO
— –120 — –160 — –200 — –300 — –500 µA
Bus-hold
trip point
VTRIP — 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V
On-Chip Termination (OCT) Specications
If you enable OCT calibration, calibration is automatically performed at power-up for I/Os connected to the calibration block.
Table 2-10: OCT Calibration Accuracy Specications for Arria V GZ Devices
OCT calibration accuracy is valid at the time of calibration only.
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Symbol Description Conditions
Calibration Accuracy
Unit
C3, I3L C4, I4
25-Ω RSInternal series termination with
calibration (25-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 %
50-Ω RSInternal series termination with
calibration (50-Ω setting)
VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 %
34-Ω and 40-Ω RSInternal series termination with
calibration (34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35, 1.25, 1.2 V ±15 ±15 %
48-Ω, 60-Ω, 80-Ω, and
240-Ω RS
Internal series termination with
calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω
setting)
VCCIO = 1.2 V ±15 ±15 %
50-Ω RTInternal parallel termination with
calibration (50-Ω setting)
VCCIO = 2.5, 1.8, 1.5, 1.2 V –10 to +40 –10 to
+40
%
20-Ω, 30-Ω, 40-Ω, 60-Ω,
and 120-Ω RT
Internal parallel termination with
calibration (20-Ω , 30-Ω, 40-Ω, 60-Ω, and
120-Ω setting)
VCCIO = 1.5, 1.35, 1.25 V –10 to +40 –10 to
+40
%
60-Ω and 120-Ω RTInternal parallel termination with
calibration (60-Ω and 120-Ω setting)
VCCIO = 1.2 –10 to +40 –10 to
+40
%
25-Ω RS_le_shi Internal le shi series termination with
calibration (25-Ω RS_le_shi setting)
VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 %
Table 2-11: OCT Without Calibration Resistance Tolerance Specications for Arria V GZ Devices
Symbol Description Conditions
Resistance Tolerance
Unit
C3, I3L C4, I4
25-Ω R, 50-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 3.0 and 2.5 V ±40 ±40 %
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2016.12.09 On-Chip Termination (OCT) Specications 2-11
Arria V GZ Device Datasheet Altera Corporation
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Symbol Description Conditions
Resistance Tolerance
Unit
C3, I3L C4, I4
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.8 and 1.5 V ±40 ±40 %
25-Ω RSInternal series termination without
calibration (25-Ω setting)
VCCIO = 1.2 V ±50 ±50 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.8 and 1.5 V ±40 ±40 %
50-Ω RSInternal series termination without
calibration (50-Ω setting)
VCCIO = 1.2 V ±50 ±50 %
100-Ω RDInternal dierential termination (100-Ω
setting)
VCCIO = 2.5 V ±25 ±25 %
Figure 2-1: OCT Variation Without Re-Calibration for Arria V GZ Devices
ROCT = RSCAL dR
dT T±dR
dV V
(
(
)
1 + x
( ) (x
Notes:
1. The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO.
2. RSCAL is the OCT resistance value at power-up.
3. ΔT is the variation of temperature with respect to the temperature at power-up.
4. ΔV is the variation of voltage with respect to the VCCIO at power-up.
5. dR/dT is the percentage change of RSCAL with temperature.
6. dR/dV is the percentage change of RSCAL with voltage.
Table 2-12: OCT Variation after Power-Up Calibration for Arria V GZ Devices
Valid for a VCCIO range of ±5% and a temperature range of 0° to 85°C.
2-12 On-Chip Termination (OCT) Specications AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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Symbol Description VCCIO (V) Typical Unit
dR/dV OCT variation with voltage without re-calibration
3.0 0.0297
%/mV
2.5 0.0344
1.8 0.0499
1.5 0.0744
1.2 0.1241
dR/dT OCT variation with temperature without re-calibration
3.0 0.189
%/°C
2.5 0.208
1.8 0.266
1.5 0.273
1.2 0.317
Pin Capacitance
Table 2-13: Pin Capacitance for Arria V GZ Devices
Symbol Description Maximum Unit
CIOTB Input capacitance on the top and bottom I/O pins 6 pF
CIOLR Input capacitance on the le and right I/O pins 6 pF
COUTFB Input capacitance on dual-purpose clock output and feedback pins 6 pF
AV-51002
2016.12.09 Pin Capacitance 2-13
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Hot Socketing
Table 2-14: Hot Socketing Specications for Arria V GZ Devices
Symbol Description Maximum
IIOPIN (DC) DC current per I/O pin 300 μA
IIOPIN (AC) AC current per I/O pin 8 mA (124)
IXCVR-TX (DC) DC current per transceiver transmitter pin 100 mA
IXCVR-RX (DC) DC current per transceiver receiver pin 50 mA
Internal Weak Pull-Up Resistor
Table 2-15: Internal Weak Pull-Up Resistor for Arria V GZ Devices
All I/O pins have an option to enable the weak pull-up resistor except the conguration, test, and JTAG pins. e internal weak pull-down feature is
only available for the JTAG TCK pin. e typical value for this internal weak pull-down resistor is approximately 25 kΩ .
Symbol Description VCCIO Conditions (V) (125) Value (126) Unit
RPU
Value of the I/O pin pull-up resistor
before and during conguration, as well as
user mode if you enable the
programmable pull-up resistor option.
3.0 ±5% 25 k Ω
2.5 ±5% 25 k Ω
1.8 ±5% 25 k Ω
1.5 ±5% 25 kΩ
1.35 ±5% 25 k Ω
1.25 ±5% 25 k Ω
1.2 ±5% 25 k Ω
(124) e I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate.
(125) e pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(126) ese specications are valid with a ±10% tolerance to cover changes over PVT.
2-14 Hot Socketing AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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I/O Standard Specications
e VOL and VOH values are valid at the corresponding IOH and IOL, respectively.
Table 2-16: Single-Ended I/O Standards for Arria V GZ Devices
I/O Standard
VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V)
IOL (mA) IOH (mA)
Min Typ Max Min Max Min Max Max Min
LVTTL 2.85 3 3.15 –0.3 0.8 1.7 3.6 0.4 2.4 2 –2
LVCMOS 2.85 3 3.15 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 0.1 –0.1
2.5 V 2.375 2.5 2.625 –0.3 0.7 1.7 3.6 0.4 2 1 –1
1.8 V 1.71 1.8 1.89 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
0.45 VCCIO – 0.45 2 –2
1.5 V 1.425 1.5 1.575 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
0.25 ×
VCCIO
0.75 × VCCIO 2 –2
1.2 V 1.14 1.2 1.26 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
0.25 ×
VCCIO
0.75 × VCCIO 2 –2
Table 2-17: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specications for Arria V GZ Devices
I/O Standard
VCCIO (V) VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2
Class I, II
2.375 2.5 2.625 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
VREF – 0.04 VREF VREF + 0.04
SSTL-18
Class I, II
1.71 1.8 1.89 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15
Class I, II
1.425 1.5 1.575 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 × VCCIO
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2016.12.09 I/O Standard Specications 2-15
Arria V GZ Device Datasheet Altera Corporation
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I/O Standard
VCCIO (V) VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-135
Class I, II
1.283 1.35 1.418 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 × VCCIO 0.51 × VCCIO
SSTL-125
Class I, II
1.19 1.25 1.26 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 × VCCIO
SSTL-12
Class I, II
1.14 1.20 1.26 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 × VCCIO
HSTL-18
Class I, II
1.71 1.8 1.89 0.85 0.9 0.95 — VCCIO/2 —
HSTL-15
Class I, II
1.425 1.5 1.575 0.68 0.75 0.9 — VCCIO/2 —
HSTL-12
Class I, II
1.14 1.2 1.26 0.47 × VCCIO 0.5 ×
VCCIO
0.53 ×
VCCIO
— VCCIO/2 —
HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 ×
VCCIO
0.51 ×
VCCIO
— — —
Table 2-18: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specications for Arria V GZ Devices
I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
Iol (mA) Ioh (mA)
Min Max Min Max Max Min Max Min
SSTL-2 Class
I
–0.3 VREF –
0.15
VREF + 0.15 VCCIO
+ 0.3
VREF – 0.31 VREF + 0.31 VTT –
0.608
VTT
+ 0.608
8.1 –8.1
SSTL-2 Class
II
–0.3 VREF –
0.15
VREF + 0.15 VCCIO
+ 0.3
VREF – 0.31 VREF + 0.31 VTT – 0.81 VTT + 0.81 16.2 –16.2
SSTL-18
Class I
–0.3 VREF –
0.125
VREF
+ 0.125
VCCIO
+ 0.3
VREF – 0.25 VREF + 0.25 VTT –
0.603
VTT
+ 0.603
6.7 –6.7
2-16 I/O Standard Specications AV-51002
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I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
Iol (mA) Ioh (mA)
Min Max Min Max Max Min Max Min
SSTL-18
Class II
–0.3 VREF –
0.125
VREF
+ 0.125
VCCIO
+ 0.3
VREF – 0.25 VREF + 0.25 0.28 VCCIO –
0.28
13.4 –13.4
SSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 ×
VCCIO
0.8 ×
VCCIO
8 –8
SSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 ×
VCCIO
0.8 ×
VCCIO
16 –16
SSTL-135
Class I, II
— VREF –
0.09
VREF + 0.09 — VREF – 0.16 VREF + 0.16 0.2 * VCCIO 0.8 * VCCIO — —
SSTL-125
Class I, II
— VREF –
0.85
VREF + 0.85 — VREF – 0.15 VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO — —
SSTL-12
Class I, II
— VREF – 0.1 VREF + 0.1 — VREF – 0.15 VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO — —
HSTL-18
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-18
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-15
Class I
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-15
Class II
— VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-12
Class I
–0.15 VREF –
0.08
VREF + 0.08 VCCIO
+ 0.15
VREF – 0.15 VREF + 0.15 0.25 ×
VCCIO
0.75 ×
VCCIO
8 –8
HSTL-12
Class II
–0.15 VREF –
0.08
VREF + 0.08 VCCIO
+ 0.15
VREF – 0.15 VREF + 0.15 0.25 ×
VCCIO
0.75 ×
VCCIO
16 –16
HSUL-12 — VREF –
0.13
VREF + 0.13 — VREF – 0.22 VREF + 0.22 0.1 ×
VCCIO
0.9 ×
VCCIO
— —
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2016.12.09 I/O Standard Specications 2-17
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Table 2-19: Dierential SSTL I/O Standards for Arria V GZ Devices
I/O Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max
SSTL-2 Class I,
II
2.375 2.5 2.625 0.3 VCCIO
+ 0.6
VCCIO/2
– 0.2
— VCCIO/2
+ 0.2
0.62 VCCIO + 0.6
SSTL-18 Class I,
II
1.71 1.8 1.89 0.25 VCCIO
+ 0.6
VCCIO/2
– 0.175
— VCCIO/2
+ 0.175
0.5 VCCIO + 0.6
SSTL-15 Class I,
II
1.425 1.5 1.575 0.2 (127) VCCIO/2
– 0.15
— VCCIO/2
+ 0.15
0.35 —
SSTL-135
Class I, II
1.283 1.35 1.45 0.2 (127) VCCIO/2
– 0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC)
- VREF)
2(VIL(AC) - VREF)
SSTL-125
Class I, II
1.19 1.25 1.31 0.18 (127) VCCIO/2
– 0.15
VCCIO/2 VCCIO/2
+ 0.15
2(VIH(AC)
- VREF)
—
SSTL-12
Class I, II
1.14 1.2 1.26 0.18 — VREF
–0.15
VCCIO/2 VREF
+ 0.15
–0.30 0.30
Table 2-20: Dierential HSTL and HSUL I/O Standards for Arria V GZ Devices
I/O Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Max
HSTL-18 Class
I, II
1.71 1.8 1.89 0.2 — 0.78 — 1.12 0.78 — 1.12 0.4 —
HSTL-15 Class
I, II
1.425 1.5 1.575 0.2 — 0.68 — 0.9 0.68 — 0.9 0.4 —
(127) e maximum value for VSWING(DC) is not dened. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
2-18 I/O Standard Specications AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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I/O Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Max
HSTL-12 Class
I, II
1.14 1.2 1.26 0.16 VCCIO
+ 0.3
— 0.5 × VCCIO — 0.4 ×
VCCIO
0.5
×
VCC
IO
0.6 ×
VCCIO
0.3 VCCIO
+ 0.48
HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 ×
VCCIO –
0.12
0.5 × VCCIO 0.5 ×
VCCIO
+ 0.12
0.4 ×
VCCIO
0.5
×
VCC
IO
0.6 ×
VCCIO
0.44 0.44
Table 2-21: Dierential I/O Standard Specications for Arria V GZ Devices
I/O Standard
VCCIO (V) (128) VID (mV) (129) VICM(DC) (V) VOD (V) (130) VOCM (V) (130)
Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max
PCML Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For transmitter,
receiver, and reference clock I/O pin specications, refer to the "Transceiver Performance Specications" section.
2.5 V
LVDS
(131)
2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 DMAX ≤
700 Mbps
1.8 0.247 — 0.6 1.125 1.25 1.375
— 1.05 DMAX >
700 Mbps
1.55 0.247 — 0.6 1.125 1.25 1.375
BLVDS
(132)
2.375 2.5 2.625 100 — — — — — — — — — — —
(128) Dierential inputs are powered by VCCPD which requires 2.5 V.
(129) e minimum VID value is applicable over the entire common mode range, VCM.
(130) RL range: 90 ≤ RL ≤ 110 Ω.
(131) For optimized LVDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.6 V for data rates above 700 Mbps, and 0 V
to 1.85 V for data rates below 700 Mbps.
(132) ere are no xed VICM, VOD, and VOCM specications for BLVDS. ey depend on the system topology.
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2016.12.09 I/O Standard Specications 2-19
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I/O Standard
VCCIO (V) (128) VID (mV) (129) VICM(DC) (V) VOD (V) (130) VOCM (V) (130)
Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max
RSDS
(HIO)
(133)
2.375 2.5 2.625 100 VCM =
1.25 V
— 0.3 — 1.4 0.1 0.2 0.6 0.5 1.2 1.4
Mini-
LVDS
(HIO)
(134)
2.375 2.5 2.625 200 — 600 0.4 — 1.325 0.25 — 0.6 1 1.2 1.4
LVPECL
(135), (136)
— — — 300 — — 0.6 DMAX ≤
700 Mbps
1.8 — — — — — —
— — — 300 — — 1 DMAX >
700 Mbps
1.6 — — — — — —
Related Information
Glossary on page 2-73
(128) Dierential inputs are powered by VCCPD which requires 2.5 V.
(129) e minimum VID value is applicable over the entire common mode range, VCM.
(130) RL range: 90 ≤ RL ≤ 110 Ω.
(133) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(134) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(135) LVPECL is only supported on dedicated clock input pins.
(136) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and
0.45 V to 1.95 V for data rate below 700 Mbps.
2-20 I/O Standard Specications AV-51002
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Switching Characteristics
Transceiver Performance Specications
Reference Clock
Table 2-22: Reference Clock Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Reference Clock
Supported I/O Standards
Dedicated reference clock
pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Dierential LVPECL, LVDS,
and HCSL
RX reference clock pin 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock
Frequency
(CMU PLL) (137)
— 40 — 710 40 — 710 MHz
Input Reference Clock
Frequency
(ATX PLL)(137)
— 100 — 710 100 — 710 MHz
(137) e input reference clock frequency options depend on the data rate and the device speed grade.
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Rise time Measure at ±60 mV of
dierential signal (138)
— — 400 — — 400
ps
Fall time Measure at ±60 mV of
dierential signal (138)
— — 400 — — 400
Duty cycle — 45 — 55 45 — 55 %
Spread-spectrum modulating
clock frequency
PCI Express ®(PCIe) 30 — 33 30 — 33 kHz
Spread-spectrum downspread PCIe — 0 to
–0.5
— — 0 to
–0.5
— %
On-chip termination resistors — — 100 — — 100 — Ω
Absolute VMAX
Dedicated reference clock
pin
— — 1.6 — — 1.6
V
RX reference clock pin — — 1.2 — — 1.2
Absolute VMIN — –0.4 — — –0.4 — — V
Peak-to-peak dierential input
voltage
— 200 — 1600 200 — 1600 mV
VICM (AC coupled)
Dedicated reference clock
pin
1000/900/850 (139) 1000/900/850 (139) mV
RX reference clock pin 1.0/0.9/0.85 (140) 1.0/0.9/0.85(140) mV
VICM (DC coupled) HCSL I/O standard for
PCIe reference clock
250 — 550 250 — 550 mV
(138) REFCLK performance requires to meet transmitter REFCLK phase noise specication.
(139) e reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(140) is supply follows VCCR_GXB
2-22 Reference Clock AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Transmitter REFCLK Phase
Noise (622 MHz) (141)
100 Hz — — -70 — — -70 dBc/Hz
1 kHz — — -90 — — -90 dBc/Hz
10 kHz — — -100 — — -100 dBc/Hz
100 kHz — — -110 — — -110 dBc/Hz
≥1 MHz — — -120 — — -120 dBc/Hz
Transmitter REFCLK Phase
Jitter (100 MHz) (142)
10 kHz to 1.5 MHz
(PCIe)
— — 3 — — 3 ps (rms)
RREF — — 1800 ±1% — — 1800 ±1% — Ω
Related Information
Arria V Device Overview
For more information about device ordering codes.
Transceiver Clocks
Table 2-23: Transceiver Clocks Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
(141) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz) =
REFCLK phase noise at 622 MHz + 20*log(f/622).
(142) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
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2016.12.09 Transceiver Clocks 2-23
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
fixedclk clock frequency PCIe
Receiver Detect
— 100 or
125
— — 100 or
125
— MHz
Reconguration clock (mgmt_clk_
clk) frequency
— 100 — 125 100 — 125 MHz
Related Information
Arria V Device Overview
For more information about device ordering codes.
Receiver
Table 2-24: Receiver Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Supported I/O Standards 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate (Standard PCS) (143), (144) — 600 — 9900 600 — 8800 Mbps
Data rate (10G PCS) (143), (144) — 600 — 12500 600 — 10312.5 Mbps
Absolute VMAX for a receiver pin (145) — — — 1.2 — — 1.2 V
Absolute VMIN for a receiver pin — –0.4 — — –0.4 — — V
(143) e line data rate may be limited by PCS-FPGA interface speed grade.
(144) To support data rates lower than the minimum specication through oversampling, use the CDR in LTR mode only.
(145) e device cannot tolerate prolonged operation at this absolute maximum.
2-24 Receiver AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Maximum peak-to-peak dierential
input voltage VID (di p-p) before
device conguration
— — — 1.6 — — 1.6 V
Maximum peak-to-peak dierential
input voltage VID (di p-p) aer
device conguration (146)
VCCR_GXB = 1.0 V
(VICM = 0.75 V)
— — 1.8 — — 1.8 V
VCCR_GXB = 0.85 V
(VICM = 0.6 V)
— — 2.4 — — 2.4 V
Minimum dierential eye opening at
receiver serial input pins (147)(148)
— 85 — — 85 — — mV
Dierential on-chip termination
resistors
85−Ω setting — 85 ± 30% — — 85
± 30%
— Ω
100−Ω setting — 100
± 30%
— — 100
± 30%
— Ω
120−Ω setting — 120
± 30%
— — 120
± 30%
— Ω
150−Ω setting — 150
± 30%
— — 150
± 30%
— Ω
(146) e maximum peak to peak dierential input voltage VID aer device conguration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(147) e dierential eye opening specication at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(148) Minimum eye opening of 85 mV is only for the unstressed input eye condition.
AV-51002
2016.12.09 Receiver 2-25
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
VICM (AC and DC coupled)
VCCR_GXB = 0.85 V
full bandwidth
— 600 — — 600 — mV
VCCR_GXB = 0.85 V
half bandwidth
— 600 — — 600 — mV
VCCR_GXB = 1.0 V
full bandwidth
— 700 — — 700 — mV
VCCR_GXB = 1.0 V
half bandwidth
— 700 — — 700 — mV
tLTR (149) — — — 10 — — 10 µs
tLTD (150) — 4 — — 4 — — µs
tLTD_manual (151) — 4 — — 4 — — µs
tLTR_LTD_manual (152) — 15 — — 15 — — µs
Programmable equalization
(AC Gain)
Full bandwidth (6.25 GHz)
Half bandwidth (3.125 GHz)
— — 16 — — 16 dB
(149) tLTR is the time required for the receive CDR to lock to the input reference clock frequency aer coming out of reset.
(150) tLTD is time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high.
(151) tLTD_manual is the time required for the receiver CDR to start recovering valid data aer the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(152) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode aer the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
2-26 Receiver AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Programmable DC gain
DC gain setting = 0 — 0 — — 0 — dB
DC gain setting = 1 — 2 — — 2 — dB
DC gain setting = 2 — 4 — — 4 — dB
DC gain setting = 3 — 6 — — 6 — dB
DC gain setting = 4 — 8 — — 8 — dB
Related Information
Arria V Device Overview
For more information about device ordering codes.
Transmitter
Table 2-25: Transmitter Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Supported I/O Standards 1.4-V and 1.5-V PCML
Data rate (Standard PCS) — 600 — 9900 600 — 8800 Mbps
Data rate (10G PCS) — 600 — 12500 600 — 10312.5 Mbps
AV-51002
2016.12.09 Transmitter 2-27
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Dierential on-chip termination
resistors
85-Ω setting — 85 ± 20% — — 85
± 20%
— Ω
100-Ω setting — 100
± 20%
— — 100
± 20%
— Ω
120-Ω setting — 120
± 20%
— — 120
± 20%
— Ω
150-Ω setting — 150
± 20%
— — 150
± 20%
— Ω
VOCM (AC coupled) 0.65-V setting — 650 — — 650 — mV
VOCM (DC coupled) — — 650 — — 650 — mV
Intra-dierential pair skew Tx VCM = 0.5 V and slew rate
of 15 ps
— — 15 — — 15 ps
Intra-transceiver block transmitter
channel-to-channel skew
x6 PMA bonded mode — — 120 — — 120 ps
Inter-transceiver block transmitter
channel-to-channel skew
xN PMA bonded mode — — 500 — — 500 ps
Related Information
Arria V Device Overview
For more information about device ordering codes.
2-28 Transmitter AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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CMU PLL
Table 2-26: CMU PLL Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Supported data range — 600 — 12500 600 — 10312.5 Mbps
tpll_powerdown (153) — 1 — — 1 — — µs
tpll_lock(154) — — 10 — — 10 µs
Related Information
Arria V Device Overview
For more information about device ordering codes.
ATX PLL
Table 2-27: ATX PLL Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
(153) tpll_powerdown is the PLL powerdown minimum pulse width.
(154) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency aer coming out of reset.
AV-51002
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Supported data rate range
VCO post-divider
L = 2
8000 — 12500 8000 — 10312.5 Mbps
L = 4 4000 — 6600 4000 — 6600 Mbps
L = 8 (155) 2000 — 3300 2000 — 3300 Mbps
tpll_powerdown (156) — 1 — — 1 — — µs
tpll_lock (157) — — — 10 — — 10 µs
Related Information
•Arria V Device Overview
For more information about device ordering codes.
•Transceiver Clocking in Arria V Devices
For more information about clocking ATX PLLs.
•Dynamic Reconguration in Arria V Devices
For more information about reconguring ATX PLLs.
Fractional PLL
Table 2-28: Fractional PLL Specications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specications in each speed grade combination oered. For more
information about device ordering codes, refer to the Arria V Device Overview.
(155) is clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more information
about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconguration in Arria V Devices chapter.
(156) tpll_powerdown is the PLL powerdown minimum pulse width.
(157) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency aer coming out of reset.
2-30 Fractional PLL AV-51002
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Altera Corporation Arria V GZ Device Datasheet
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Symbol/Description Conditions
Transceiver Speed Grade 2 Transceiver Speed Grade 3
Unit
Min Typ Max Min Typ Max
Supported data range — 600 — 3250/
3125(158)
600 — 3250/
3125 (158)
Mbps
tpll_powerdown(159) — 1 — — 1 — — µs
tpll_lock (160) — — — 10 — 10 µs
Related Information
Arria V Device Overview
For more information about device ordering codes.
Clock Network Data Rate
Table 2-29: Clock Network Maximum Data Rate Transmitter Specications
Valid data rates below the maximum specied in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
Clock Network
ATX PLL CMU PLL (161) fPLL
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
x1 (162) 12.5 — 6 12.5 — 6 3.125 — 3
x6 (162) — 12.5 6 — 12.5 6 — 3.125 6
x6 PLL Feedback (163) — 12.5 Side-wide — 12.5 Side-wide — — —
(158) When you use fPLL as a TXPLL of the transceiver.
(159) tpll_powerdown is the PLL powerdown minimum pulse width.
(160) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency aer coming out of reset.
(161) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(162) Channel span is within a transceiver bank.
(163) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
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2016.12.09 Clock Network Data Rate 2-31
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Clock Network
ATX PLL CMU PLL (161) fPLL
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
Non-bonded
Mode (Gbps)
Bonded
Mode (Gbps)
Channel
Span
xN (PCIe) — 8.0 8 — 5.0 8 — — —
xN (Native PHY IP)
8.0 8.0 Up to 13
channels
above and
below PLL
7.99 7.99
Up to 13
channels
above and
below PLL
3.125 3.125
Up to 13
channels
above
and
below
PLL
— 8.01 to
9.8304
Up to 7
channels
above
and
below
PLL
Standard PCS Data Rate
Table 2-30: Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices
e maximum data rate is also constrained by the transceiver speed grade. Refer to the “Commercial and Industrial Speed Grade Oering for Arria
V GZ Devices” table for the transceiver speed grade.
Mode (164) Transceiver
Speed Grade
PMA Width 20 20 16 16 10 10 8 8
PCS/Core Width 40 20 32 16 20 10 16 8
FIFO
2 C3, I3L
core speed grade
9.9 9 7.84 7.2 5.3 4.7 4.24 3.76
3 C4, I4
core speed grade
8.8 8.2 7.2 6.56 4.8 4.3 3.84 3.44
(161) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(164) e Phase Compensation FIFO can be congured in FIFO mode or register mode. In the FIFO mode, the pointers are not xed, and the latency can
vary. In the register mode the pointers are xed for low latency.
2-32 Standard PCS Data Rate AV-51002
2016.12.09
Altera Corporation Arria V GZ Device Datasheet
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Mode (164) Transceiver
Speed Grade
PMA Width 20 20 16 16 10 10 8 8
PCS/Core Width 40 20 32 16 20 10 16 8
Register
2 C3, I3L
core speed grade
9.9 9 7.92 7.2 4.9 4.,5 3.92 3.6
3 C4, I4
core speed grade
8.8 8.2 7.04 6.56 4.4 4.1 3.52 3.28
Related Information
Operating Conditions on page 2-1
10G PCS Data Rate
Table 2-31: 10G PCS Approximate Maximum Data Rate (Gbps) for Arria V GZ Devices
Mode (165) Transceiver Speed
Grade
PMA Width 64 40 40 40 32 32
PCS Width 64 66/67 50 40 64/66/67 32
FIFO
2 C3, I3L core speed
grade
12.5 12.5 10.69 12.5 10.88 10.88
3 C4, I4 core speed
grade
10.3125 10.3125 10.69 10.3125 9.92 9.92
Register
2 C3, I3L core speed
grade
12.5 12.5 10.69 12.5 10.88 10.88
3 C4, I4 core speed
grade
10.3125 10.3125 10.69 10.3125 9.92 9.92
(164) e Phase Compensation FIFO can be congured in FIFO mode or register mode. In the FIFO mode, the pointers are not xed, and the latency can
vary. In the register mode the pointers are xed for low latency.
(165) e Phase Compensation FIFO can be congured in FIFO mode or register mode. In the FIFO mode, the pointers are not xed, and the latency can
vary. In the register mode the pointers are xed for low latency.
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2016.12.09 10G PCS Data Rate 2-33
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Typical VOD Settings
Table 2-32: Typical VOD Setting for Arria V GZ Channel, TX Termination = 100 Ω
e tolerance is +/-20% for all VOD settings except for settings 2 and below.
Symbol VOD Setting VOD Value (mV) VOD Setting VOD Value (mV)
VOD dierential peak to peak typical
0 (166) 0 32 640
1(166) 20 33 660
2(166) 40 34 680
3(166) 60 35 700
4(166) 80 36 720
5(166) 100 37 740
6 120 38 760
7 140 39 780
8 160 40 800
9 180 41 820
10 200 42 840
11 220 43 860
12 240 44 880
13 260 45 900
14 280 46 920
(166) If TX termination resistance = 100 Ω,this VOD setting is illegal.
2-34 Typical VOD Settings AV-51002
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Symbol VOD Setting VOD Value (mV) VOD Setting VOD Value (mV)
VOD dierential peak to peak typical
15 300 47 940
16 320 48 960
17 340 49 980
18 360 50 1000
19 380 51 1020
20 400 52 1040
21 420 53 1060
22 440 54 1080
23 460 55 1100
24 480 56 1120
25 500 57 1140
26 520 58 1160
27 540 59 1180
28 560 60 1200
29 580 61 1220
30 600 62 1240
31 620 63 1260
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2016.12.09 Typical VOD Settings 2-35
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Core Performance Specications
Clock Tree Specications
Table 2-33: Clock Tree Performance for Arria V GZ Devices
Symbol
Performance
Unit
C3, I3L C4, I4
Global and Regional Clock 650 580 MHz
Periphery Clock 500 500 MHz
PLL Specications
Table 2-34: PLL Specications for Arria V GZ Devices
Symbol Parameter Min Typ Max Unit
fIN (167) Input clock frequency (C3, I3L speed grade) 5 — 800 MHz
Input clock frequency (C4, I4 speed grade) 5 — 650 MHz
fINPFD Input frequency to the PFD 5 — 325 MHz
fFINPFD Fractional Input clock frequency to the PFD 50 — 160 MHz
fVCO (168) PLL VCO operating range (C3, I3L speed grade) 600 — 1600 MHz
PLL VCO operating range (C4, I4 speed grade) 600 — 1300 MHz
tEINDUTY Input clock or external feedback clock input duty
cycle
40 — 60 %
(167) is specication is limited in the Quartus II soware by the I/O maximum frequency. e maximum I/O frequency is dierent for each I/O
standard.
(168) e VCO frequency reported by the Quartus II soware in the PLL Usage Summary section of the compilation report takes into consideration the
VCO post-scale counter K value. erefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specication.
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2016.12.09 Core Performance Specications 2-37
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Symbol Parameter Min Typ Max Unit
fOUT (169)
Output frequency for an internal global or regional
clock (C3, I3L speed grade)
— — 650 MHz
Output frequency for an internal global or regional
clock (C4, I4 speed grade)
— — 580 MHz
fOUT_EXT (169)
Output frequency for an external clock output (C3,
I3L speed grade)
— — 667 MHz
Output frequency for an external clock output (C4,
I4 speed grade)
— — 533 MHz
tOUTDUTY Duty cycle for a dedicated external clock output
(when set to 50%)
45 50 55 %
tFCOMP External feedback clock compensation time — — 10 ns
fDYCONFIGCLK Dynamic conguration clock for mgmt_clk and
scanclk
— — 100 MHz
tLOCK Time required to lock from the end-of-device
conguration or deassertion of areset
— — 1 ms
tDLOCK Time required to lock dynamically (aer switchover
or reconguring any non-post-scale counters/
delays)
— — 1 ms
fCLBW
PLL closed-loop low bandwidth — 0.3 — MHz
PLL closed-loop medium bandwidth — 1.5 — MHz
PLL closed-loop high bandwidth (170) — 4 — MHz
tPLL_PSERR Accuracy of PLL phase shi — — ±50 ps
tARESET Minimum pulse width on the areset signal 10 — — ns
(169) is specication is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(170) High bandwidth PLL settings are not supported in external feedback mode.
2-38 PLL Specications AV-51002
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Symbol Parameter Min Typ Max Unit
tINCCJ (171), (172) Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz) — — 0.15 UI (p-p)
Input clock cycle-to-cycle jitter (fREF < 100 MHz) -750 — +750 ps (p-p)
tOUTPJ_DC (173)
Period Jitter for dedicated clock output in integer
PLL (fOUT ≥ 100 MHz)
— — 175 ps (p-p)
Period Jitter for dedicated clock output in integer
PLL (fOUT < 100 Mhz)
— — 17.5 mUI (p-p)
tFOUTPJ_DC (173)
Period Jitter for dedicated clock output in fractional
PLL (fOUT ≥ 100 MHz)
— — 250(176),
175(174)
ps (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
— — 25(176),
17.5 (174)
mUI (p-p)
tOUTCCJ_DC (173)
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT ≥ 100 MHz)
— — 175 ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT < 100 MHz)
— — 17.5 mUI (p-p)
tFOUTCCJ_DC (173)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT ≥ 100 MHz)
— — 250(176),
175 (174)
ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)
— — 25(176),
17.5 (174)
mUI (p-p)
(171) A high input jitter directly aects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(172) e fREF is fIN/N specication applies when N = 1.
(173) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% condence level). e output jitter specication applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. e external memory interface clock output jitter specications use a dierent
measurement method and are available in the "Worst-Case DCD on Arria V GZ I/O Pins" table.
(174) is specication only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
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2016.12.09 PLL Specications 2-39
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Symbol Parameter Min Typ Max Unit
tOUTPJ_IO, (173), (175)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
— — 600 ps (p-p)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT < 100 MHz)
— — 60 mUI (p-p)
tFOUTPJ_IO (173), (175), (176)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT ≥ 100 MHz)
— — 600 ps (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
— — 60 mUI (p-p)
tOUTCCJ_IO (173), (175)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT ≥ 100 MHz)
— — 600 ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT < 100 MHz)
— — 60 mUI (p-p)
tFOUTCCJ_IO (173), (175), (176)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT ≥ 100 MHz)
— — 600 ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT < 100 MHz)
— — 60 mUI (p-p)
tCASC_OUTPJ_DC (173), (177)
Period Jitter for a dedicated clock output in
cascaded PLLs (fOUT ≥ 100 MHz)
— — 175 ps (p-p)
Period Jitter for a dedicated clock output in
cascaded PLLS (fOUT < 100 MHz)
— — 17.5 mUI (p-p)
dKBIT Bit number of Delta Sigma Modulator (DSM) 8 24 32 Bits
(175) e external memory interface clock output jitter specications use a dierent measurement method, which is available in the "Memory Output Clock
Jitter Specication for Arria V GZ Devices" table.
(176) is specication only covered fractional PLL for low bandwidth. e fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(177) e cascaded PLL specication is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
2-40 PLL Specications AV-51002
2016.12.09
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Symbol Parameter Min Typ Max Unit
kVALUE Numerator of Fraction 128 8388608 2147483648 —
fRES Resolution of VCO frequency (fINPFD = 100 MHz) 390625 5.96 0.023 Hz
Related Information
•Duty Cycle Distortion (DCD) Specications on page 2-56
•DLL Range Specications on page 2-53
DSP Block Specications
Table 2-35: DSP Block Performance Specications for Arria V GZ Devices
Mode
Performance
Unit
C3, I3L C4 I4
Modes using One DSP Block
ree 9 × 9 480 420 MHz
One 18 × 18 480 420 400 MHz
Two partial 18 × 18 (or 16 × 16) 480 420 400 MHz
One 27 × 27 400 350 MHz
One 36 × 18 400 350 MHz
One sum of two 18 × 18 (One sum of two 16 × 16) 400 350 MHz
One sum of square 400 350 MHz
One 18 × 18 plus 36 (a × b) + c 400 350 MHz
Modes using Two DSP Blocks
ree 18 × 18 400 350 MHz
One sum of four 18 × 18 380 300 MHz
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2016.12.09 DSP Block Specications 2-41
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Mode
Performance
Unit
C3, I3L C4 I4
One sum of two 27 × 27 380 300 290 MHz
One sum of two 36 × 18 380 300 MHz
One complex 18 × 18 400 350 MHz
One 36 × 36 380 300 MHz
Modes using ree DSP Blocks
One complex 18 × 25 340 275 265 MHz
Modes using Four DSP Blocks
One complex 27 × 27 350 310 MHz
Memory Block Specications
Table 2-36: Memory Block Performance Specications for Arria V GZ Devices
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set
to 50% output duty cycle. Use the Quartus II soware to report timing for this and other memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX.
Memory Mode
Resources Used Performance
Unit
ALUTs Memory C3 C4 I3L I4
MLAB
Single port, all supported widths 0 1 400 315 400 315 MHz
Simple dual-port, x32/x64 depth 0 1 400 315 400 315 MHz
Simple dual-port, x16 depth (178) 0 1 533 400 533 400 MHz
ROM, all supported widths 0 1 500 450 500 450 MHz
(178) e FMAX specication is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
2-42 Memory Block Specications AV-51002
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Memory Mode
Resources Used Performance
Unit
ALUTs Memory C3 C4 I3L I4
M20K
Block
Single-port, all supported widths 0 1 650 550 500 450 MHz
Simple dual-port, all supported widths 0 1 650 550 500 450 MHz
Simple dual-port with the read-during-write
option set to Old Data, all supported widths
0 1 455 400 455 400 MHz
Simple dual-port with ECC enabled, 512 × 32 0 1 400 350 400 350 MHz
Simple dual-port with ECC and optional
pipeline registers enabled, 512 × 32
0 1 500 450 500 450 MHz
True dual port, all supported widths 0 1 650 550 500 450 MHz
ROM, all supported widths 0 1 650 550 500 450 MHz
Temperature Sensing Diode Specications
Table 2-37: Internal Temperature Sensing Diode Specication
Temperature Range Accuracy Oset Calibrated
Option
Sampling Rate Conversion Time Resolution Minimum Resolution
with no Missing
Codes
–40°C to 100°C ±8°C No 1 MHz, 500 kHz < 100 ms 8 bits 8 bits
Table 2-38: External Temperature Sensing Diode Specications for Arria V GZ Devices
Description Min Typ Max Unit
Ibias, diode source current 8 — 200 μA
Vbias, voltage across diode 0.3 — 0.9 V
Series resistance — — < 1 Ω
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2016.12.09 Temperature Sensing Diode Specications 2-43
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Description Min Typ Max Unit
Diode ideality factor 1.006 1.008 1.010 —
Periphery Performance
I/O performance supports several system interfaces, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X
bus interface. General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are capable of a typical 167 MHz and 1.2-LVCMOS
at 100 MHz interfacing frequency with a 10 pF load.
Note: e actual achievable frequency depends on design- and system-specic factors. Ensure proper timing closure in your design and perform
HSPICE/IBIS simulations based on your specic design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specication
High-Speed Clock Specications
Table 2-39: High-Speed Clock Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
Arria V GZ devices support the following output standards using true LVDS output buer types on all I/O banks.
• True RSDS output standard with data rates of up to 230 Mbps
• True mini-LVDS output standard with data rates of up to 340 Mbps
2-44 Periphery Performance AV-51002
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Altera Corporation Arria V GZ Device Datasheet
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Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
fHSCLK_in (input clock
frequency) True Dierential
I/O Standards (179)
Clock boost factor
W = 1 to 40 (180)
5 — 625 5 — 525 MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (180)
5 — 625 5 — 525 MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (180)
5 — 420 5 — 420 MHz
fHSCLK_OUT (output clock
frequency)
— 5 — 625 (181) 5 — 525 (181) MHz
Transmitter High-Speed I/O Specications
Table 2-40: Transmitter High-Speed I/O Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
(179) is only applies to DPA and so-CDR modes.
(180) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(181) is is achieved by using the LVDS clock network.
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Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
True Dierential I/O
Standards - fHSDR (data rate)
SERDES factor J = 3 to 10
(182), (183)
(184) — 1250 (184) — 1050 Mbps
SERDES factor J ≥ 4
LVDS TX with DPA
(185), (186), (187), (188)
(184) — 1600 (184) — 1250 Mbps
SERDES factor J = 2,
uses DDR Registers
(184) —(189) (184) —(189) Mbps
SERDES factor J = 1,
uses SDR Register
(184) —(189) (184) —(189) Mbps
Emulated Dierential I/O
Standards with ree
External Output Resistor
Networks - fHSDR (data rate)
(190)
SERDES factor J = 4 to 10 (191) (184) — 840 (184) — 840 Mbps
(182) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(183) e FMAX specication is based on the fast clock used for serial data. e interface FMAX is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(184) e minimum specication depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. e I/O dierential buer and input register do not have a minimum toggle rate.
(185) Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
(186) Requires package skew compensation with PCB trace length.
(187) Do not mix single-ended I/O buer within LVDS I/O bank.
(188) Chip-to-chip communication only with a maximum load of 5 pF.
(189) e maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity simulation is clean.
(190) You must calculate the leover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leover timing margin.
(191) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
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Altera Corporation Arria V GZ Device Datasheet
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Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
tx Jitter - True Dierential I/O
Standards
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
— — 160 — — 160 ps
Total Jitter for Data Rate
< 600 Mbps
— — 0.1 — — 0.1 UI
tx Jitter - Emulated Dierential
I/O Standards with ree
External Output Resistor
Network
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
— — 300 — — 325 ps
Total Jitter for Data Rate
< 600 Mbps
— — 0.2 — — 0.25 UI
tDUTY Transmitter output clock duty
cycle for both True and Emulated
Dierential I/O Standards
45 50 55 45 50 55 %
tRISE & tFALL
True Dierential I/O Standards — — 200 — — 200 ps
Emulated Dierential I/O
Standards with three external
output resistor networks
— — 250 — — 300 ps
TCCS
True Dierential I/O Standards — — 150 — — 150 ps
Emulated Dierential I/O
Standards
— — 300 — — 300 ps
Receiver High-Speed I/O Specications
Table 2-41: Receiver High-Speed I/O Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
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2016.12.09 Receiver High-Speed I/O Specications 2-47
Arria V GZ Device Datasheet Altera Corporation
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Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
True Dierential I/O
Standards - fHSDRDPA
(data rate)
SERDES factor J = 3 to 10
(192), (193), (194), (195), (196), (197)
150 — 1250 150 — 1050 Mbps
SERDES factor J ≥ 4
LVDS RX with DPA
(193), (195), (196), (197)
150 — 1600 150 — 1250 Mbps
SERDES factor J = 2,
uses DDR Registers
(198) —(199) (198) —(199) Mbps
SERDES factor J = 1,
uses SDR Register
(198) —(199) (198) —(199) Mbps
fHSDR (data rate)
SERDES factor J = 3 to 10 (198) —(200) (198) —(200) Mbps
SERDES factor J = 2,
uses DDR Registers
(198) —(199) (198) —(199) Mbps
SERDES factor J = 1,
uses SDR Register
(198) —(199) (198) —(199) Mbps
(192) e FMAX specication is based on the fast clock used for serial data. e interface FMAX is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(193) Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
(194) Arria V GZ LVDS serialization and de-serialization factor needs to be x4 and above.
(195) Requires package skew compensation with PCB trace length.
(196) Do not mix single-ended I/O buer within LVDS I/O bank.
(197) Chip-to-chip communication only with a maximum load of 5 pF.
(198) e minimum specication depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. e I/O dierential buer and input register do not have a minimum toggle rate.
(199) e maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity simulation is clean.
(200) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
2-48 Receiver High-Speed I/O Specications AV-51002
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Altera Corporation Arria V GZ Device Datasheet
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DPA Mode High-Speed I/O Specications
Table 2-42: High-Speed I/O Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
DPA run length — — — 10000 — — 10000 UI
Figure 2-3: DPA Lock Time Specication with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 data
transitions 96 slow
clock cycles 256 data
transitions 256 data
transitions
96 slow
clock cycles
Table 2-43: DPA Lock Time Specications for Arria V GZ Devices
e DPA lock time is for one channel.
One data transition is dened as a 0-to-1 or 1-to-0 transition.
e DPA lock time stated in this table applies to both commercial and industrial grade.
Standard Training Pattern Number of Data Transitions
in One Repetition of the
Training Pattern
Number of Repetitions per
256 Data Transitions (201)
Maximum
SPI-4 00000000001111111111 2 128 640 data transitions
(201) is is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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Standard Training Pattern Number of Data Transitions
in One Repetition of the
Training Pattern
Number of Repetitions per
256 Data Transitions (201)
Maximum
Parallel Rapid I/O 00001111 2 128 640 data transitions
10010000 4 64 640 data transitions
Miscellaneous 10101010 8 32 640 data transitions
01010101 8 32 640 data transitions
Soft CDR Mode High-Speed I/O Specications
Table 2-44: High-Speed I/O Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
So-CDR ppm tolerance — — — 300 — — 300 ± ppm
(201) is is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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Figure 2-4: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specication for a Data Rate ≥ 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
F1 F2 F3 F4
Jitter Frequency (Hz)
Jitter Amphlitude (UI)
0.1
0.35
8.5
25
Table 2-45: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate ≥ 1.25 Gbps
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1 10,000 25.000
F2 17,565 25.000
F3 1,493,000 0.350
F4 50,000,000 0.350
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Figure 2-5: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specication for a Data Rate < 1.25 Gbps
0.1 UI P-P
baud/1667 20 MHz Frequency
Sinusoidal Jitter Amplitude
20db/dec
Non DPA Mode High-Speed I/O Specications
Table 2-46: High-Speed I/O Specications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
Symbol Conditions
C3, I3L C4, I4
Unit
Min Typ Max Min Typ Max
Sampling Window — — — 300 — — 300 ps
2-52 Non DPA Mode High-Speed I/O Specications AV-51002
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DLL Range Specications
Table 2-47: DLL Range Specications for Arria V GZ Devices
Arria V GZ devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Parameter C3, I3L C4, I4 Unit
DLL operating frequency range 300 – 890 300 – 890 MHz
DQS Logic Block Specications
Table 2-48: DQS Phase Oset Delay Per Setting for Arria V GZ Devices
e typical value equals the average of the minimum and maximum values.
e delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when using a –3 speed grade and applying
a 10-phase oset setting to a 90° phase shi at 400 MHz, the expected average cumulative delay is [625 ps + (10 × 11 ps) ± 20 ps] = 735 ps ± 20 ps.
Speed Grade Min Max Unit
C3, I3L 8 15 ps
C4, I4 8 16 ps
Table 2-49: DQS Phase Shift Error Specication for DLL-Delayed Clock (tDQS_PSERR) for Arria V GZ Devices
is error specication is the absolute maximum and minimum error. For example, skew on three DQS delay buers in a –3 speed grade is ±84 ps
or ±42 ps.
Number of DQS Delay Buers C3, I3L C4, I4 Unit
1 30 32 ps
2 60 64 ps
3 90 96 ps
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Number of DQS Delay Buers C3, I3L C4, I4 Unit
4 120 128 ps
Memory Output Clock Jitter Specications
Table 2-50: Memory Output Clock Jitter Specication for Arria V GZ Devices
e clock jitter specication applies to the memory output clock pins generated using dierential signal-splitter and DDIO circuits clocked by a
PLL output routed on a PHY, regional, or global clock network as specied. Altera recommends using PHY clock networks whenever possible.
e clock jitter specication applies to the memory output clock pins clocked by an integer PLL.
e memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14
sigma.
Clock Network Parameter Symbol
C3, I3L C4, I4
Unit
Min Max Min Max
Regional
Clock period jitter tJIT(per) –55 55 –55 55 ps
Cycle-to-cycle period jitter tJIT(cc) –110 110 –110 110 ps
Duty cycle jitter tJIT(duty) –82.5 82.5 –82.5 82.5 ps
Global
Clock period jitter tJIT(per) –82.5 82.5 –82.5 82.5 ps
Cycle-to-cycle period jitter tJIT(cc) –165 165 –165 165 ps
Duty cycle jitter tJIT(duty) –90 90 –90 90 ps
PHY Clock
Clock period jitter tJIT(per) –30 30 –35 35 ps
Cycle-to-cycle period jitter tJIT(cc) –60 60 –70 70 ps
Duty cycle jitter tJIT(duty) –45 45 –56 56 ps
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OCT Calibration Block Specications
Table 2-51: OCT Calibration Block Specications for Arria V GZ Devices
Symbol Description Min Typ Max Unit
OCTUSRCLK Clock required by the OCT calibration blocks — — 20 MHz
TOCTCAL Number of OCTUSRCLK clock cycles required for OCT RS/RT calibration — 1000 — Cycles
TOCTSHIFT Number of OCTUSRCLK clock cycles required for the OCT code to shi out — 32 — Cycles
TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a
bidirectional I/O buer to dynamically switch between OCT RS and RT (See
the gure below.)
— 2.5 — ns
Figure 2-6: Timing Diagram for oe and dyn_term_ctrl Signals
oe
Tristate
RX RXTX
dyn_term_ctrl
TRS_RT
Tristate
TRS_RT
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Duty Cycle Distortion (DCD) Specications
Table 2-52: Worst-Case DCD on Arria V GZ I/O Pins
e DCD numbers do not cover the core clock network.
Symbol
C3, I3L C4, I4
Unit
Min Max Min Max
Output Duty Cycle 45 55 45 55 %
Conguration Specication
POR Specications
Table 2-53: Fast and Standard POR Delay Specication for Arria V GZ Devices
Select the POR delay based on the MSEL setting as described in the “Conguration Schemes for Arria V Devices” table in the Conguration, Design
Security, and Remote System Upgrades in Arria V Devices chapter.
POR Delay Minimum (ms) Maximum (ms)
Fast 4 12 (202)
Standard 100 300
Related Information
Conguration, Design Security, and Remote System Upgrades in Arria V Devices
(202) e maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize aer the POR trip.
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JTAG Conguration Specications
Table 2-54: JTAG Timing Parameters and Values for Arria V GZ Devices
Symbol Description Min Max Unit
tJCP TCK clock period 30 — ns
tJCP TCK clock period 167 (203) — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 2 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 11 (204) ns
tJPZX JTAG port high impedance to valid output — 14 (204) ns
tJPXZ JTAG port valid output to high impedance — 14 (204) ns
Fast Passive Parallel (FPP) Conguration Timing
DCLK-to-DATA[] Ratio (r) for FPP Conguration
FPP conguration requires a dierent DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
(203) e minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile key programming.
(204) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO I/O bank = 2.5 V, or 13 ns if it
equals 1.8 V.
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Table 2-55: DCLK-to-DATA[] Ratio for Arria V GZ Devices
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the data rate in bytes per second (Bps), or words per
second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[] ratio is 2, the DCLK frequency must be 2 times the data rate in Wps. Arria V GZ
devices use the additional clock cycles to decrypt and decompress the conguration data.
Conguration Scheme Decompression Design Security DCLK-to-DATA[] Ratio
FPP ×8
Disabled Disabled 1
Disabled Enabled 1
Enabled Disabled 2
Enabled Enabled 2
FPP ×16
Disabled Disabled 1
Disabled Enabled 2
Enabled Disabled 4
Enabled Enabled 4
FPP ×32
Disabled Disabled 1
Disabled Enabled 4
Enabled Disabled 8
Enabled Enabled 8
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FPP Conguration Timing when DCLK to DATA[] = 1
Figure 2-7: FPP Conguration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
Timing waveform for FPP conguration when using a MAX® II or MAX V device as an external host.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[31..0]
User I/O
INIT_DONE
Word 0 Word 1 Word 2 Word 3
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z User Mode
(5)
(7)
(4)
User Mode
Word n-2 Word n-1
(6)
Notes:
1. The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is
pulled low, a reconfiguration cycle begins.
2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay.
3. After power-up, before and during configuration, CONF_DONE is low.
4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete.
It can toggle high or low if required.
5. For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0] are available as a user I/O
pin after configuration. The state of this pin depends on the dual-purpose pin settings.
6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device.
CONF_DONE is released high when the Arria V GZ device receives all the configuration data
successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE
goes low.
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Note: When you enable the decompression or design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the
respective DCLK-to-DATA[] ratio, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
Table 2-56: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1
Use these timing parameters when the decompression and design security features are disabled.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — μs
tSTATUS nSTATUS low pulse width 268 1,506 (205) μs
tCF2ST1 nCONFIG high to nSTATUS high — 1,506 (206) μs
tCF2CK
(207)
nCONFIG high to rst rising edge on DCLK 1,506 — μs
tST2CK (207)
nSTATUS high to rst rising edge of DCLK 2 — μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX
DCLK frequency (FPP ×8/×16) — 125 MHz
DCLK frequency (FPP ×32) — 100 MHz
tCD2UM CONF_DONE high to user mode (208) 175 437 μs
(205) is value is applicable if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(206) is value is applicable if you do not delay conguration by externally holding the nSTATUS low.
(207) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
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Symbol Parameter Minimum Maximum Unit
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum
DCLK period
— —
tCD2UM
C
CONF_DONE high to user mode with CLKUSR option on tCD2CU +
(17,408 × CLKUSR
period) (209)
— —
Related Information
•DCLK-to-DATA[] Ratio (r) for FPP Conguration on page 2-57
•Conguration, Design Security, and Remote System Upgrades in Arria V Devices
(208) e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(209) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specication on these pins, refer to the
“Initialization” section of the Conguration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
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FPP Conguration Timing when DCLK to DATA[] > 1
Figure 2-8: FPP Conguration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 ,
Timing when using a MAX II device, MAX V device, or microprocessor as an external host.
nCONFIG
nSTATUS (3)
CONF_DONE (4)
DCLK (6)
DATA[31..0] (8)
User I/O
INIT_DONE
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCF2CK
t
tCF2ST0
tST2CK
High-Z User Mode
1 2 r 1 2 r 1 2
Word 0 Word 1 Word 3
1
tDSU tDH
STATUS
tDH
tCH
tCL
tCLK
Word (n-1)
(7)
(8)
(9)
(5)
User Mode
r
Notes:
1. To find out the DCLK-to-DATA[] ratio for your system, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
2. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
3. After power-up, the Arria V GZ device holds nSTATUS low for the time as specified by the POR delay.
4. After power-up, before and during configuration, CONF_DONE is low.
5. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or
low if required.
6. “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design
security feature enable settings, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
7. If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0]
pins prior to sending the first DCLK rising edge.
8. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is
released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes
high, send two additional falling edges on DCLK to begin initialization and enter user mode.
9. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
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Table 2-57: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1
Use these timing parameters when you use the decompression and design security features.
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — μs
tSTATUS nSTATUS low pulse width 268 1,506 (210) μs
tCF2ST1 nCONFIG high to nSTATUS high — 1,506 (211) μs
tCF2CK (212) nCONFIG high to rst rising edge on DCLK 1,506 — μs
tST2CK(212) nSTATUS high to rst rising edge of DCLK 2 — μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK N–1/fDCLK (213) — s
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX
DCLK frequency (FPP ×8/×16) — 125 MHz
DCLK frequency (FPP ×32) — 100 MHz
tRInput rise time — 40 ns
tFInput fall time — 40 ns
tCD2UM CONF_DONE high to user mode (214) 175 437 μs
(210) You can obtain this value if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(211) You can obtain this value if you do not delay conguration by externally holding the nSTATUS low.
(212) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(213) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
(214) e minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
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Symbol Parameter Minimum Maximum Unit
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK
period
— —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU +
(17,408 × CLKUSR
period) (215)
— —
Related Information
•DCLK-to-DATA[] Ratio (r) for FPP Conguration on page 2-57
•Conguration, Design Security, and Remote System Upgrades in Arria V Devices
(215) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specication on these pins, refer to the
“Initialization” section of the Conguration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
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Active Serial Conguration Timing
Figure 2-9: AS Conguration Timing
Timing waveform for the active serial (AS) x1 mode and AS x4 mode conguration timing.
Read Address
bit 1
bit 0 bit (n - 2) bit (n - 1)
tCD2UM
nSTATUS
nCONFIG
CONF_DONE
nCSO
DCLK
AS_DATA0/ASDO
AS_DATA1 (1)
INIT_DONE (3)
User I/O User Mode
tCF2ST1
tDH
tSU
tCO
(2)
Notes:
1. If you are using AS ×4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
2. The initialization clock can be from internal oscillator or CLKUSR pin.
3. After the option bit to enable the INIT_DONE pin is configured into the d evice, the INIT_DONE goes low.
Table 2-58: AS Timing Parameters for AS x1 and AS x4 Congurations in Arria V GZ Devices
e minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in the "PS Timing Parameters
for Arria V GZ Devices" table.
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Symbol Parameter Minimum Maximum Unit
tCO DCLK falling edge to AS_DATA0/ASDO output — 4 ns
tSU Data setup time before falling edge on DCLK 1.5 — ns
tHData hold time aer falling edge on DCLK 0 — ns
tCD2UM CONF_DONE high to user mode (216) 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK
period
— —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 ×
CLKUSR period)
— —
Table 2-59: DCLK Frequency Specication in the AS Conguration Scheme
is applies to the DCLK frequency specication when using the internal oscillator as the conguration clock source.
e AS multi-device conguration scheme does not support DCLK frequency of 100 MHz.
Minimum Typical Maximum Unit
5.3 7.9 12.5 MHz
10.6 15.7 25.0 MHz
21.3 31.4 50.0 MHz
42.6 62.9 100.0 MHz
Related Information
•Passive Serial Conguration Timing on page 2-67
•Conguration, Design Security, and Remote System Upgrades in Arria V Devices
(216) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specication on this pin, refer to the
“Initialization” section of the Conguration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
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Passive Serial Conguration Timing
Figure 2-10: PS Conguration Timing Waveform
Timing waveform for a passive serial (PS) conguration when using a MAX II device, MAX V device, or microprocessor as an external host.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA0
User I/O
INIT_DONE (7)
Bit 0 Bit 1 Bit 2 Bit 3
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z User Mode
(5)
(4)
(6)
Bit (n-1)
Notes:
1. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS,
and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay.
3. After power-up, before and during configuration, CONF_DONE is low.
4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete.
It can toggle high or low if required.
5. DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the
dual-purpose pin settings in the Device and Pins Option.
6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device.
CONF_DONE is released high after the Arria V GZ device receives all the configuration data
successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
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Table 2-60: PS Timing Parameters for Arria V GZ Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low — 600 ns
tCF2ST0 nCONFIG low to nSTATUS low — 600 ns
tCFG nCONFIG low pulse width 2 — μs
tSTATUS nSTATUS low pulse width 268 1,506 (217) μs
tCF2ST1 nCONFIG high to nSTATUS high — 1,506 (218) μs
tCF2CK
(219)
nCONFIG high to rst rising edge on DCLK 1,506 — μs
tST2CK (219) nSTATUS high to rst rising edge of DCLK 2 — μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns
tDH DATA[] hold time aer rising edge on DCLK 0 — ns
tCH DCLK high time 0.45 × 1/fMAX — s
tCL DCLK low time 0.45 × 1/fMAX — s
tCLK DCLK period 1/fMAX — s
fMAX DCLK frequency — 125 MHz
tCD2UM CONF_DONE high to user mode (220) 175 437 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK
period
— —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 ×
CLKUSR period) (221)
— —
(217) is value is applicable if you do not delay conguration by extending the nCONFIG or nSTATUS low pulse width.
(218) is value is applicable if you do not delay conguration by externally holding the nSTATUS low.
(219) If nSTATUS is monitored, follow the tST2CK specication. If nSTATUS is not monitored, follow the tCF2CK specication.
(220) e minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
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Related Information
Conguration, Design Security, and Remote System Upgrades in Arria V Devices
Initialization
Table 2-61: Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices
Initialization Clock Source Conguration Schemes Maximum Frequency (MHz) Minimum Number of Clock Cycles
Internal Oscillator AS, PS, FPP 12.5
17,408CLKUSR (222) PS, FPP 125
AS 100
DCLK PS, FPP 125
Conguration Files
Use the following table to estimate the le size before design compilation. Dierent conguration le formats, such as a hexadecimal le (.hex) or
tabular text le (.ttf) format, have dierent le sizes.
For the dierent types of conguration le and le sizes, refer to the Quartus II soware. However, for a specic version of the Quartus II soware,
any design targeted for the same device has the same uncompressed conguration le size.
(221) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specication on these pins, refer to the
“Initialization” section of the Conguration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(222) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II soware
from the General panel of the Device and Pin Options dialog box.
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Table 2-62: Uncompressed .rbf Sizes for Arria V GZ Devices
Variant Member Code Conguration .rbf Size (bits) IOCSR .rbf Size (bits) (223)
Arria V GZ
E1 137,598,880 562,208
E3 137,598,880 562,208
E5 213,798,880 561,760
E7 213,798,880 561,760
Table 2-63: Minimum Conguration Time Estimation for Arria V GZ Devices
Variant Member Code
Active Serial (224) Fast Passive Parallel (225)
Width DCLK (MHz) Min Cong Time
(ms)
Width DCLK (MHz) Min Cong Time
(ms)
Arria V GZ
E1 4 100 344 32 100 43
E3 4 100 344 32 100 43
E5 4 100 534 32 100 67
E7 4 100 534 32 100 67
Remote System Upgrades Circuitry Timing Specication
Table 2-64: Remote System Upgrade Circuitry Timing Specications
Parameter Minimum Maximum Unit
tRU_nCONFIG (226) 250 — ns
tRU_nRSTIMER (227) 250 — ns
(223) e IOCSR .rbf size is specically for the Conguration via Protocol (CvP) feature.
(224) DCLK frequency of 100 MHz using external CLKUSR.
(225) Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
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Related Information
•Conguration, Design Security, and Remote System Upgrades in Arria V Devices
For more information about the reconguration input for the ALTREMOTE_UPDATE IP core, refer to the “User Watchdog Timer” section.
•Conguration, Design Security, and Remote System Upgrades in Arria V Devices
For more information about the reset_timer input for the ALTREMOTE_UPDATE IP core, refer to the “Remote System Upgrade State
Machine” section.
User Watchdog Internal Oscillator Frequency Specication
Table 2-65: User Watchdog Internal Oscillator Frequency Specications
Minimum Typical Maximum Unit
5.3 7.9 12.5 MHz
I/O Timing
Altera oers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. e data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
e Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specics of the design aer you complete place-
and-route.
Related Information
Arria V Devices Documentation page
For the Excel-based I/O Timing spreadsheet
(226) is is equivalent to strobing the reconguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication. For more
information, refer to the “Remote System Upgrade State Machine” section in the Conguration, Design Security, and Remote System Upgrades in
Arria V Devices chapter.
(227) is is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specication. For more
information, refer to the “User Watchdog Timer” section in the Conguration, Design Security, and Remote System Upgrades in Arria V Devices
chapter.
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Programmable IOE Delay
Table 2-66: IOE Programmable Delay for Arria V GZ Devices
Parameter (228) Available
Settings Min Oset (229) Fast Model Slow Model
Unit
Industrial Commercial C3 C4 I3L I4
D1 64 0 0.464 0.493 0.924 1.011 0.921 1.006 ns
D2 32 0 0.230 0.244 0.459 0.503 0.456 0.500 ns
D3 8 0 1.587 1.699 2.992 3.192 3.047 3.257 ns
D4 64 0 0.464 0.492 0.924 1.011 0.920 1.006 ns
D5 64 0 0.464 0.493 0.924 1.011 0.921 1.006 ns
D6 32 0 0.229 0.244 0.458 0.503 0.456 0.499 ns
Programmable Output Buer Delay
Table 2-67: Programmable Output Buer Delay for Arria V GZ Devices
You can set the programmable output buer delay in the Quartus II soware by setting the Output Buer Delay Control assignment to either
positive, negative, or both edges, with the specic values stated here (in ps) for the Output Buer Delay assignment.
Symbol Parameter Typical Unit
DOUTBUF Rising and/or falling edge delay
0 (default) ps
50 ps
100 ps
150 ps
(228) You can set this value in the Quartus II soware by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column of Assignment Editor.
(229) Minimum oset does not include the intrinsic delay.
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Glossary
Table 2-68: Glossary
Term Denition
Dierential I/O
Standards
Receiver Input Waveforms
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
VID
VID
p - n = 0 V
VCM
Transmitter Output Waveforms
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Term Denition
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
p - n = 0 V
VCM
fHSCLK Le and right PLL input clock frequency.
fHSDR High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J High-speed I/O block—Deserialization factor (width of parallel data bus).
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Term Denition
JTAG Timing Speci‐
cations
JTAG Timing Specications:
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
tJCL
tJCH
TDI
TMS
PLL Specications Diagram of PLL Specications
Core Clock
External Feedback
Reconfigurable in User Mode
Key
CLK
NPFD
Switchover
Delta Sigma
Modulator
VCO
CP LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO fOUT
fOUT_EXT
Counters
C0..C 17
4
Note:
1. Core Clock can only be fed by dedicated clock input pins or PLL outputs.
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Term Denition
RLReceiver dierential input discrete resistor (external to the Arria V GZ device).
SW (sampling
window)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. e setup and
hold times determine the ideal strobe position within the sampling window, as shown:
Bit Time
0.5 x TCCS RSKM Sampling Window
(SW)
RSKM 0.5 x TCCS
Single-ended voltage
referenced I/O
standard
e JEDEC standard for SSTL and HSTL I/O denes both the AC and DC input signal values. e AC values indicate the
voltage levels at which the receiver must meet its timing specications. e DC values indicate the voltage levels at which
the nal logic state of the receiver is unambiguously dened. Aer the receiver input has crossed the AC value, the receiver
changes to the new logic state.
e new logic state is then maintained as long as the input stays beyond the DC threshold. is approach is intended to
provide predictable receiver timing in the presence of input waveform ringing:
Single-Ended Voltage Referenced I/O Standard
VIH(AC )
VIH(DC )
VREF VIL(D C )
VIL(AC )
VOH
VOL
VCCIO
VSS
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Term Denition
tCHigh-speed receiver and transmitter input and output clock period.
TCCS (channel-to-
channel-skew)
e timing dierence between the fastest and slowest output edges, including tCO variation and clock skew, across channels
driven by the same PLL. e clock is included in the TCCS measurement (refer to the Timing Diagram gure under SW in
this table).
tDUTY High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
tFALL Signal high-to-low transition time (80-20%)
tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO Period jitter on the general purpose I/O driven by a PLL.
tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL.
tRISE Signal low-to-high transition time (20-80%)
Timing Unit Interval
(TUI)
e timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(receiver input clock frequency multiplication factor) = tC/w)
VCM(DC) DC common mode input voltage.
VICM Input common mode voltage—e common mode of the dierential signal at the receiver.
VID Input dierential voltage swing—e dierence in voltage between the positive and complementary conductors of a
dierential transmission at the receiver.
VDIF(AC) AC dierential input voltage—Minimum AC input dierential voltage required for switching.
VDIF(DC) DC dierential input voltage— Minimum DC input dierential voltage required for switching.
VIH Voltage input high—e minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC) High-level AC input voltage
VIH(DC) High-level DC input voltage
VIL Voltage input low—e maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL(AC) Low-level AC input voltage
VIL(DC) Low-level DC input voltage
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Term Denition
VOCM Output common mode voltage—e common mode of the dierential signal at the transmitter.
VOD Output dierential voltage swing—e dierence in voltage between the positive and complementary conductors of a
dierential transmission at the transmitter.
VSWING Dierential input voltage
VXInput dierential cross point voltage
VOX Output dierential cross point voltage
W High-speed I/O block—clock boost factor
Document Revision History
Date Version Changes
June 2016 2016.06.20 • Changed column heading from "Value" to "Maximum" in the "Pin Capacitance for Arria V GZ Devices"
table.
• Changed the minimum supported data rate range values from "1000" to "2000" in the "ATX PLL Specica‐
tions for Arria V GZ Devices" table.
• Added the supported data rates for the following output standards using true LVDS output buer types in
the "High-Speed Clock Specications for Arria V GZ Devices" table:
• True RSDS output standard: data rates of up to 230 Mbps
• True mini-LVDS output standard: data rates of up to 340 Mbps
December 2015 2015.12.16 • Removed the CDR ppm tolerance specication from the "Receiver Specications for Arria V GZ Devices"
table.
• Removed transmitter rise and fall time specications from the "Transmitter Specications for Arria V GZ
Devices" table.
• Changed the .rbf sizes in the "Uncompressed .rbf Sizes for Arria V GZ Devices" table.
• Added a footnote to the "Transmitter High-Speed I/O Specications for Arria V GZ Devices" table.
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Date Version Changes
June 2015 2015.06.16 • Changed the conditions for the reference clock rise and fall time and added a note to the condition in the
"Reference Clock Specications for Arria V GZ Devices" table.
• Added a note to the "Minimum dierential eye opening at receiver serial input pins" specication in the
"Receiver Specications for Arria V GZ Devices" table.
January 2015 2015.01.30 • Added 240-Ω to the "OCT Calibration Accuracy Specications for Arria V GZ Devices" table.
• Changed the CDR PPM tolerance spec in the "Receiver Specications for Arria V GZ Devices" table.
• Added additional max data rate for fPLL in the "Fractional PLL Specications for Arria V GZ Devices" table.
July 2014 3.8 • Updated Table 21.
• Updated Table 22 VOCM (DC Coupled) condition.
• Updated the DCLK note to Figure 6, Figure 7, and Figure 9.
• Added note to Table 5 and Table 6.
• Added the DCLK specication to Table 50.
• Added note to Table 51.
• Updated the list of parameters in Table 53.
February 2014 3.7 Updated Table 28.
December 2013 3.6 • Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37, Table 38, Table 45,
Table 46, Table 47, Table 56, Table 49.
• Updated “PLL Specications”.
August 2013 3.5 Updated Table 28.
August 2013 3.4 • Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28, Table 29, Table 31,
Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, and Table 54.
• Updated Table 2 and Table 28.
June 2013 3.3 Updated Table 23, Table 28, Table 51, and Table 55.
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Date Version Changes
May 2013 3.2 • Added Table 23.
• Updated Table 5, Table 22, Table 26, and Table 57.
• Updated Figure 6, Figure 7, Figure 8, and Figure 9.
March 2013 3.1 • Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52.
• Updated “Maximum Allowed Overshoot and Undershoot Voltage”.
December 2012 3.0 Initial release.
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