Arria V Device Datasheet TOC-2 Contents Arria V GX, GT, SX, and ST Device Datasheet..................................................................................................... 1-1 Electrical Characteristics.................................................................................................................................................................................................... 1-1 Operating Conditions............................................................................................................................................................................................. 1-1 Switching Characteristics..................................................................................................................................................................................................1-23 Transceiver Performance Specifications............................................................................................................................................................. 1-23 Core Performance Specifications.........................................................................................................................................................................1-43 Periphery Performance......................................................................................................................................................................................... 1-49 HPS Specifications................................................................................................................................................................................................. 1-58 Configuration Specifications............................................................................................................................................................................................ 1-75 POR Specifications.................................................................................................................................................................................................1-75 FPGA JTAG Configuration Timing.................................................................................................................................................................... 1-76 FPP Configuration Timing...................................................................................................................................................................................1-77 AS Configuration Timing..................................................................................................................................................................................... 1-80 DCLK Frequency Specification in the AS Configuration Scheme..................................................................................................................1-81 PS Configuration Timing......................................................................................................................................................................................1-81 Initialization........................................................................................................................................................................................................... 1-83 Configuration Files................................................................................................................................................................................................ 1-83 Minimum Configuration Time Estimation........................................................................................................................................................1-84 Remote System Upgrades..................................................................................................................................................................................... 1-86 User Watchdog Internal Oscillator Frequency Specifications......................................................................................................................... 1-86 I/O Timing..........................................................................................................................................................................................................................1-86 Programmable IOE Delay.....................................................................................................................................................................................1-87 Programmable Output Buffer Delay................................................................................................................................................................... 1-87 Glossary...............................................................................................................................................................................................................................1-88 Document Revision History.............................................................................................................................................................................................1-94 Arria V GZ Device Datasheet................................................................................................................................ 2-1 Electrical Characteristics.................................................................................................................................................................................................... 2-1 Altera Corporation Operating Conditions .............................................................................................................................................................................................2-1 Switching Characteristics .................................................................................................................................................................................................2-21 Transceiver Performance Specifications ............................................................................................................................................................ 2-21 Core Performance Specifications ........................................................................................................................................................................2-37 Periphery Performance ........................................................................................................................................................................................ 2-44 Configuration Specification .............................................................................................................................................................................................2-56 POR Specifications ................................................................................................................................................................................................2-56 JTAG Configuration Specifications .................................................................................................................................................................... 2-57 Fast Passive Parallel (FPP) Configuration Timing ........................................................................................................................................... 2-57 Active Serial Configuration Timing ................................................................................................................................................................... 2-65 Passive Serial Configuration Timing ..................................................................................................................................................................2-67 Initialization .......................................................................................................................................................................................................... 2-69 Configuration Files ............................................................................................................................................................................................... 2-69 Remote System Upgrades Circuitry Timing Specification ..............................................................................................................................2-70 User Watchdog Internal Oscillator Frequency Specification .......................................................................................................................... 2-71 I/O Timing .........................................................................................................................................................................................................................2-71 Programmable IOE Delay ....................................................................................................................................................................................2-72 Programmable Output Buffer Delay .................................................................................................................................................................. 2-72 Glossary ..............................................................................................................................................................................................................................2-73 Document Revision History ............................................................................................................................................................................................2-78 Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet 1 2016.12.09 AV-51002 Subscribe Send Feedback This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Arria(R) V devices. Arria V devices are offered in commercial and industrial grades. Commercial devices are offered in -C4 (fastest), -C5, and -C6 speed grades. Industrial grade devices are offered in the -I3 and -I5 speed grades. Related Information Arria V Device Overview Provides more information about the densities and packages of devices in the Arria V family. Electrical Characteristics The following sections describe the operating conditions and power consumption of Arria V devices. Operating Conditions Arria V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria V devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Arria V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. (c) 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 1-2 AV-51002 2016.12.09 Absolute Maximum Ratings Caution: Conditions outside the range listed in the following table may cause permanent damage tothe device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 1-1: Absolute Maximum Ratings for Arria V Devices Symbol Description Minimum Maximum Unit VCC Core voltage power supply -0.50 1.43 V VCCP Periphery circuitry, PCIe(R) hardIP block, and transceiver physical coding sublayer (PCS) power supply -0.50 1.43 V VCCPGM Configuration pins power supply -0.50 3.90 V VCC_AUX Auxiliary supply -0.50 3.25 V VCCBAT Battery back-up power supply for design security volatile key register -0.50 3.90 V VCCPD I/O pre-driver power supply -0.50 3.90 V VCCIO I/O power supply -0.50 3.90 V VCCD_FPLL Phase-locked loop (PLL) digital power supply -0.50 1.80 V VCCA_FPLL PLL analog power supply -0.50 3.25 V VCCA_GXB Transceiver high voltage power -0.50 3.25 V VCCH_GXB Transmitter output buffer power -0.50 1.80 V VCCR_GXB Receiver power -0.50 1.50 V VCCT_GXB Transmitter power -0.50 1.50 V VCCL_GXB Transceiver clock network power -0.50 1.50 V VI DC input voltage -0.50 3.80 V VCC_HPS HPS core voltage and periphery circuitry power supply -0.50 1.43 V VCCPD_HPS HPS I/O pre-driver power supply -0.50 3.90 V VCCIO_HPS HPS I/O power supply -0.50 3.90 V VCCRSTCLK_HPS HPS reset and clock input pins power supply -0.50 3.90 V Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Maximum Allowed Overshoot and Undershoot Voltage Symbol Description Minimum Maximum Unit VCCPLL_HPS HPS PLL analog power supply -0.50 3.25 V VCC_AUX_SHARED HPS auxiliary power supply -0.50 3.25 V IOUT DC output current per pin -25 40 mA TJ Operating junction temperature -55 125 C TSTG Storage temperature (no bias) -65 150 C 1-3 Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years. Table 1-2: Maximum Allowed Overshoot During Transitions for Arria V Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-4 AV-51002 2016.12.09 Recommended Operating Conditions Symbol Vi (AC) Description AC input voltage Condition (V) Overshoot Duration as % of High Time Unit 3.8 100 % 3.85 68 % 3.9 45 % 3.95 28 % 4 15 % 4.05 13 % 4.1 11 % 4.15 9 % 4.2 8 % 4.25 7 % 4.3 5.4 % 4.35 3.2 % 4.4 1.9 % 4.45 1.1 % 4.5 0.6 % 4.55 0.4 % 4.6 0.2 % Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Arria V devices. Recommended Operating Conditions Table 1-3: Recommended Operating Conditions for Arria V Devices This table lists the steady-state voltage values expected from Arria V devices. Power supply ramps must all be strictly monotonic, without plateaus. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Recommended Operating Conditions Symbol Description VCC Core voltage power supply VCCP Periphery circuitry, PCIe hard IP block, and transceiver PCS power supply VCCPGM Configuration pins power supply Condition Minimum(1) Typical Maximum(1) Unit -C4, -I5, -C5, -C6 1.07 1.1 1.13 V -I3 1.12 1.15 1.18 V -C4, -I5, -C5, -C6 1.07 1.1 1.13 V -I3 1.12 1.15 1.18 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V VCC_AUX Auxiliary supply -- 2.375 2.5 2.625 V VCCBAT Battery back-up power supply -- 1.2 -- 3.0 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V (2) 1-5 (For design security volatile key register) VCCPD(3) (1) (2) (3) I/O pre-driver power supply The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. If you do not use the design security feature in Arria V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Arria V power-on reset (POR) circuitry monitors VCCBAT. Arria V devices do not exit POR if VCCBAT is not powered up. VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is 3.3 V. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-6 Symbol VCCIO (1) (4) AV-51002 2016.12.09 Recommended Operating Conditions Description I/O buffers power supply Condition Minimum(1) Typical Maximum(1) Unit 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V 1.283 1.35 1.418 V 1.25 V 1.19 1.25 1.31 V 1.2 V 1.14 1.2 1.26 V VCCD_FPLL PLL digital voltage regulator power supply -- 1.425 1.5 1.575 V VCCA_FPLL PLL analog voltage regulator power supply -- 2.375 2.5 2.625 V VI DC input voltage -- -0.5 -- 3.6 V VO Output voltage -- 0 -- VCCIO V TJ Operating junction temperature Commercial 0 -- 85 C Industrial -40 -- 100 C tRAMP(4) Power supply ramp time Standard POR 200 s -- 100 ms -- Fast POR 200 s -- 4 ms -- The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Power Supply Operating Conditions 1-7 Transceiver Power Supply Operating Conditions Table 1-4: Transceiver Power Supply Operating Conditions for Arria V Devices Symbol (5) (6) Description VCCA_GXBL Transceiver high voltage power (left side) VCCA_GXBR Transceiver high voltage power (right side) VCCR_GXBL GX and SX speed grades--receiver power (left side) VCCR_GXBR GX and SX speed grades--receiver power (right side) VCCR_GXBL GT and ST speed grades--receiver power (left side) VCCR_GXBR GT and ST speed grades--receiver power (right side) VCCT_GXBL GX and SX speed grades--transmitter power (left side) VCCT_GXBR GX and SX speed grades--transmitter power (right side) VCCT_GXBL GT and ST speed grades--transmitter power (left side) VCCT_GXBR GT and ST speed grades--transmitter power (right side) VCCH_GXBL Transmitter output buffer power (left side) VCCH_GXBR Transmitter output buffer power (right side) Minimum(5) Typical Maximum(5) Unit 2.375 2.500 2.625 V 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V 1.425 1.500 1.575 V The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. For data rate <=3.2 Gbps, connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps, connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-8 AV-51002 2016.12.09 HPS Power Supply Operating Conditions Symbol Description VCCL_GXBL GX and SX speed grades--clock network power (left side) VCCL_GXBR GX and SX speed grades--clock network power (right side) VCCL_GXBL GT and ST speed grades--clock network power (left side) VCCL_GXBR GT and ST speed grades--clock network power (right side) Minimum(5) Typical Maximum(5) Unit 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V Related Information Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines Provides more information about the power supply connection for different data rates. HPS Power Supply Operating Conditions Table 1-5: HPS Power Supply Operating Conditions for Arria V SX and ST Devices This table lists the steady-state voltage and current values expected from Arria V system-on-a-chip (SoC) devices with ARM(R)-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria V Devices table for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices. Symbol VCC_HPS (5) (7) Description Condition Minimum(7) Typical Maximum(7) Unit HPS core voltage and periphery circuitry power supply -C4, -I5, -C5, -C6 1.07 1.1 1.13 V -I3 1.12 1.15 1.18 V The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 HPS Power Supply Operating Conditions Symbol VCCPD_HPS (8) VCCIO_HPS VCCRSTCLK_HPS VCCPLL_HPS (7) (8) (9) Description HPS I/O pre-driver power supply HPS I/O buffers power supply HPS reset and clock input pins power supply HPS PLL analog voltage regulator power supply Condition Minimum(7) Typical Maximum(7) Unit 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V (9) 1.283 1.35 1.418 V 1.2 V 1.14 1.2 1.26 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V -- 2.375 2.5 2.625 V 1-9 The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when VCCIO_HPS is 3.3 V. VCCIO_HPS 1.35 V is supported for HPS row I/O bank only. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-10 AV-51002 2016.12.09 DC Characteristics Symbol VCC_AUX_SHARED Description Condition Minimum(7) Typical Maximum(7) Unit -- 2.375 2.5 2.625 V HPS auxiliary power supply Related Information Recommended Operating Conditions on page 1-4 Provides the steady-state voltage values for the FPGA portion of the device. DC Characteristics Supply Current and Power Consumption Altera offers two ways to estimate power for your design--the Excel-based Early Power Estimator (EPE) and the Quartus(R) Prime PowerPlay Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use. The Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-androute. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information * PowerPlay Early Power Estimator User Guide Provides more information about power estimation tools. * PowerPlay Power Analysis chapter, Quartus Prime Handbook Provides more information about power estimation tools. (7) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 1-11 I/O Pin Leakage Current I/O Pin Leakage Current Table 1-6: I/O Pin Leakage Current for Arria V Devices Symbol Description Condition Min Typ Max Unit II Input pin VI = 0 V to VCCIOMAX -30 -- 30 A IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX -30 -- 30 A Bus Hold Specifications Table 1-7: Bus Hold Parameters for Arria V Devices The bus-hold trip points are based on calculated input voltages from the JEDEC standard. VCCIO (V) Parameter Symbol Condition 1.2 1.5 1.8 2.5 3.0 3.3 Unit Min Max Min Max Min Max Min Max Min Max Min Max 8 -- 12 -- 30 -- 50 -- 70 -- 70 -- A -8 -- -12 -- -30 -- -50 -- -70 -- -70 -- A Bus-hold, low, sustaining current ISUSL Bus-hold, high, sustaining current ISUSH Bus-hold, low, overdrive current IODL 0 V < VIN < VCCIO -- 125 -- 175 -- 200 -- 300 -- 500 -- 500 A Bus-hold, high, overdrive current IODH 0 V <VIN <VCCIO -- -125 -- -175 -- -200 -- -300 -- -500 -- -500 A VIN > VIL (max) VIN < VIH (min) Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-12 AV-51002 2016.12.09 OCT Calibration Accuracy Specifications VCCIO (V) Parameter Bus-hold trip point Symbol VTRIP Condition -- 1.2 1.5 1.8 2.5 3.0 3.3 Unit Min Max Min Max Min Max Min Max Min Max Min Max 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 1-8: OCT Calibration Accuracy Specifications for Arria V Devices Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Symbol Description Condition (V) Calibration Accuracy -I3, -C4 -I5, -C5 -C6 Unit 25- RS Internal series termination with VCCIO = 3.0, 2.5, 1.8, 1.5, calibration (25- setting) 1.2 15 15 15 % 50- RS Internal series termination with VCCIO = 3.0, 2.5, 1.8, 1.5, calibration (50- setting) 1.2 15 15 15 % 34- and 40- RS Internal series termination with VCCIO = 1.5, 1.35, 1.25, calibration (34- and 40- 1.2 setting) 15 15 15 % 48-, 60-, and 80 RS Internal series termination with VCCIO = 1.2 calibration (48-, 60-, and 80- setting) 15 15 15 % 50- RT Internal parallel termination with calibration (50- setting) -10 to +40 -10 to +40 -10 to +40 % -10 to +40 -10 to +40 -10 to +40 % VCCIO = 2.5, 1.8, 1.5, 1.2 20-, 30-, 40-,60- Internal parallel termination VCCIO = 1.5, 1.35, 1.25 , and 120- RT with calibration (20-, 30-, 40-, 60-, and 120- setting) Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 OCT Without Calibration Resistance Tolerance Specifications Symbol Description Condition (V) 60- and 120- RT Internal parallel termination VCCIO = 1.2 with calibration (60- and 120 setting) 25- RS_left_shift Internal left shift series termination with calibration (25- RS_left_shift setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 Calibration Accuracy 1-13 Unit -I3, -C4 -I5, -C5 -C6 -10 to +40 -10 to +40 -10 to +40 % 15 15 15 % OCT Without Calibration Resistance Tolerance Specifications Table 1-9: OCT Without Calibration Resistance Tolerance Specifications for Arria V Devices This table lists the Arria V OCT without calibration resistance tolerance to PVT changes. Symbol Description Condition (V) ResistanceTolerance -I3, -C4 -I5, -C5 -C6 Unit 25- RS Internal series termination without VCCIO = 3.0, 2.5 calibration (25- setting) 30 40 40 % 25- RS Internal series termination without VCCIO = 1.8, 1.5 calibration (25- setting) 30 40 40 % 25- RS Internal series termination without VCCIO = 1.2 calibration (25- setting) 35 50 50 % 50- RS Internal series termination without VCCIO = 3.0, 2.5 calibration (50- setting) 30 40 40 % 50- RS Internal series termination without VCCIO = 1.8, 1.5 calibration (50- setting) 30 40 40 % 50- RS Internal series termination without VCCIO = 1.2 calibration (50- setting) 35 50 50 % 100- RD Internal differential termination (100- setting) 25 40 40 % Arria V GX, GT, SX, and ST Device Datasheet Send Feedback VCCIO = 2.5 Altera Corporation 1-14 AV-51002 2016.12.09 OCT Variation after Power-Up Calibration Figure 1-1: Equation for OCT Variation Without Recalibration The definitions for the equation are as follows: * * * * * * The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO. RSCAL is the OCT resistance value at power-up. T is the variation of temperature with respect to the temperature at power up. V is the variation of voltage with respect to the VCCIO at power up. dR/dT is the percentage change of RSCAL with temperature. dR/dV is the percentage change of RSCAL with voltage. OCT Variation after Power-Up Calibration Table 1-10: OCT Variation after Power-Up Calibration for Arria V Devices This table lists OCT variation with temperature and voltage after power-up calibration. The OCT variation is valid for a VCCIO range of 5% and a temperature range of 0C to 85C. Symbol dR/dV Altera Corporation Description OCT variation with voltage without recalibration VCCIO (V) Value 3.0 0.100 2.5 0.100 1.8 0.100 1.5 0.100 1.35 0.150 1.25 0.150 1.2 0.150 Unit %/mV Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Pin Capacitance Symbol Description OCT variation with temperature without recalibration dR/dT VCCIO (V) Value 3.0 0.189 2.5 0.208 1.8 0.266 1.5 0.273 1.35 0.200 1.25 0.200 1.2 0.317 1-15 Unit %/C Pin Capacitance Table 1-11: Pin Capacitance for Arria V Devices Symbol Description Maximum Unit CIOTB Input capacitance on top/bottom I/O pins 6 pF CIOLR Input capacitance on left/right I/O pins 6 pF COUTFB Input capacitance on dual-purpose clock output/feedback pins 6 pF CIOVREF Input capacitance on VREF pins 48 pF Maximum Unit Hot Socketing Table 1-12: Hot Socketing Specifications for Arria V Devices Symbol Description IIOPIN (DC) DC current per I/O pin 300 A IIOPIN (AC) AC current per I/O pin 8(10) mA IXCVR-TX (DC) DC current per transceiver transmitter (TX) pin 100 mA Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-16 AV-51002 2016.12.09 Internal Weak Pull-Up Resistor Symbol IXCVR-RX (DC) Description DC current per transceiver receiver (RX) pin Maximum Unit 50 mA Internal Weak Pull-Up Resistor All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. Table 1-13: Internal Weak Pull-Up Resistor Values for Arria V Devices Symbol Description Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. RPU Condition (V)(11) Value(12) Unit VCCIO = 3.3 5% 25 k VCCIO = 3.0 5% 25 k VCCIO = 2.5 5% 25 k VCCIO = 1.8 5% 25 k VCCIO = 1.5 5% 25 k VCCIO = 1.35 5% 25 k VCCIO = 1.25 5% 25 k VCCIO = 1.2 5% 25 k Related Information Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. (10) (11) (12) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. Valid with 10% tolerances to cover changes over PVT. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 I/O Standard Specifications 1-17 I/O Standard Specifications Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Arria V devices. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Single-Ended I/O Standards Table 1-14: Single-Ended I/O Standards for Arria V Devices (13) VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) Min Typ Max Min Max Min Max Max Min IOL(13) (mA) 3.3-V LVTTL 3.135 3.3 3.465 -0.3 0.8 1.7 3.6 0.45 2.4 4 -4 3.3-V LVCMOS 3.135 3.3 3.465 -0.3 0.8 1.7 3.6 0.2 VCCIO - 0.2 2 -2 3.0-V LVTTL 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 2.4 2 -2 3.0-V LVCMOS 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.2 VCCIO - 0.2 0.1 -0.1 3.0-V PCI 2.85 3 3.15 -- 0.3 x VCCIO 0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5 3.0-V PCI-X 2.85 3 3.15 -- 0.35 x VCCIO 0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5 2.5 V 2.375 2.5 2.625 -0.3 0.7 1.7 3.6 0.4 2 1 -1 1.8 V 1.71 1.8 1.89 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2 -2 1.5 V 1.425 1.5 1.575 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 1.2 V 1.14 1.2 1.26 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 I/O Standard IOH(13) (mA) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-18 AV-51002 2016.12.09 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Table 1-15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V Devices I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO VREF - 0.04 VREF VREF + 0.04 SSTL-18 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF - 0.04 VREF VREF + 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-135 Class I, II 1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-125 Class I, II 1.19 1.25 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VCCIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VCCIO/2 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO -- VCCIO/2 -- HSUL-12 1.14 1.2 1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO -- -- -- Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1-19 Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Table 1-16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V Devices (14) VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) Min Max Min Max Max Min Max Min IOL(14) (mA) SSTL-2 Class I -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 VTT - 0.608 VTT + 0.608 8.1 -8.1 SSTL-2 Class II -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 VTT - 0.81 VTT + 0.81 16.2 -16.2 SSTL-18 Class I -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 VTT - 0.603 VTT + 0.603 6.7 -6.7 SSTL-18 Class II -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 VCCIO - 0.28 13.4 -13.4 SSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 8 -8 SSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 16 -16 SSTL-135 -- VREF - 0.09 VREF + 0.09 -- VREF - 0.16 VREF + 0.16 0.2 x VCCIO 0.8 x VCCIO -- -- SSTL-125 -- VREF - 0.85 VREF + 0.85 -- VREF - 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO -- -- HSTL-18 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 HSTL-18 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 I/O Standard IOH(14) (mA) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-20 AV-51002 2016.12.09 Differential SSTL I/O Standards VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) Min Max Min Max Max Min Max Min IOL(14) (mA) HSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-12 Class I -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 8 -8 HSTL-12 Class II -0.15 VREF - 0.08 VREF + 0.08 VCCIO+ 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 16 -16 HSUL-12 -- VREF - 0.13 VREF + 0.13 -- VREF - 0.22 VREF + 0.22 -- -- I/O Standard 0.1 x VCCIO 0.9 x VCCIO IOH(14) (mA) Differential SSTL I/O Standards Table 1-17: Differential SSTL I/O Standards for Arria V Devices I/O Standard (14) (15) VCCIO (V) VSWING(DC) (V) Min Typ Max Min SSTL-2 Class I, II 2.375 2.5 2.625 0.3 SSTL-18 Class I, II 1.71 1.8 1.89 SSTL-15 Class I, II 1.425 1.5 SSTL-135 1.283 1.35 Max VX(AC) (V) Min VSWING(AC) (V) Typ Max Min Max VCCIO + 0.6 VCCIO/2 - 0.2 -- VCCIO/2 + 0.2 0.62 VCCIO + 0.6 0.25 VCCIO + 0.6 VCCIO/2 - 0.175 -- VCCIO/2 + 0.175 0.5 VCCIO + 0.6 1.575 0.2 (15) VCCIO/2 - 0.15 -- VCCIO/2 + 0.15 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) 1.45 0.18 (15) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)). Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Differential HSTL and HSUL I/O Standards I/O Standard SSTL-125 VCCIO (V) VSWING(DC) (V) VX(AC) (V) 1-21 VSWING(AC) (V) Min Typ Max Min Max Min Typ Max Min Max 1.19 1.25 1.31 0.18 (15) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) Differential HSTL and HSUL I/O Standards Table 1-18: Differential HSTL and HSUL I/O Standards for Arria V Devices I/O Standard VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max 1.71 1.8 1.89 0.2 -- 0.78 -- 1.12 0.78 -- 1.12 0.4 -- HSTL-15 1.425 Class I, II 1.5 1.575 0.2 -- 0.68 -- 0.9 0.68 -- 0.9 0.4 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO + 0.3 -- 0.5 x VCCIO -- 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO 0.3 VCCIO + 0.48 HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 x VCCIO - 0.12 0.5 x VCCIO 0.5 x VCCIO + 0.12 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO 0.44 0.44 HSTL-18 Class I, II Differential I/O Standard Specifications Table 1-19: Differential I/O Standard Specifications for Arria V Devices Differential inputs are powered by VCCPD which requires 2.5 V. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-22 AV-51002 2016.12.09 Differential I/O Standard Specifications I/O Standard PCML 2.5 V LVDS(19) VID (mV)(16) VCCIO (V) Min Typ Max Min Condition Max Min Condition VCM = 1.25 V -- 0.05 DMAX 1.25 Gbps 1.80 -- 1.05 DMAX > 1.25 Gbps 1.55 2.5 2.625 100 2.375 2.5 2.625 100 VCM = 1.25 V -- 0.25 -- Mini-LVDS 2.375 (HIO)(21) 2.5 2.625 200 -- 600 0.300 LVPECL(22) Max Min Typ VOCM (V)(17)(18) Max Min Typ Max Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Transceiver Specifications for Arria V GX and SX Devices and Transceiver Specifications for Arria V GT and ST Devices tables. 2.375 RSDS (HIO)(20) VOD (V)(17) VICM(DC) (V) -- -- -- 300 -- -- 0.247 -- 0.6 1.125 1.25 1.375 1.45 0.1 0.2 0.6 0.5 1.2 1.4 -- 1.425 0.25 -- 0.6 1 1.2 1.4 0.60 DMAX 700 Mbps 1.80 1.00 DMAX > 700 Mbps 1.60 -- -- -- -- -- -- Related Information * Transceiver Specifications for Arria V GX and SX Devices on page 1-23 Provides the specifications for transmitter, receiver, and reference clock I/O pin. (16) (17) (18) (19) (20) (21) (22) The minimum VID value is applicable over the entire common mode range, VCM. RL range: 90 RL 110 . This applies to default pre-emphasis setting only. For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 1.25 Gbps and 0 V to 1.85 V for data rates below 1.25 Gbps. For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V. For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V. For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Switching Characteristics 1-23 * Transceiver Specifications for Arria V GT and ST Devices on page 1-29 Provides the specifications for transmitter, receiver, and reference clock I/O pin. Switching Characteristics This section provides performance characteristics of Arria V core and periphery blocks. Transceiver Performance Specifications Transceiver Specifications for Arria V GX and SX Devices Table 1-20: Reference Clock Specifications for Arria V GX and SX Devices Symbol/Description Condition Supported I/O standards Input frequency from (24) (25) Min Typ Transceiver Speed Grade 6 Max Min Typ Max Unit 1.2 V PCML, 1.4 V PCML,1.5 V PCML, 2.5 V PCML, Differential LVPECL(23), HCSL, and LVDS -- 27 -- 710 27 -- 710 MHz Rise time Measure at 60 mV of differential signal(24) -- -- 400 -- -- 400 ps Fall time Measure at 60 mV of differential signal(24) -- -- 400 -- -- 400 ps Duty cycle -- 45 -- 55 45 -- 55 % Peak-to-peak differential input voltage -- 200 -- 300 / 2000 200 -- 300 / 2000 mV REFCLK input pins (23) Transceiver Speed Grade 4 (25) (25) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. REFCLK performance requires to meet transmitter REFCLK phase noise specification. The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-24 Symbol/Description Transceiver Speed Grade 4 Transceiver Speed Grade 6 Min Typ Max Min Typ Max Unit PCI Express(R) (PCIe) 30 -- 33 30 -- 33 kHz Spread-spectrum downspread PCIe -- 0 to -0.5% -- -- 0 to -0.5% -- -- On-chip termination resistors -- -- 100 -- -- 100 -- VICM (AC coupled) -- -- 1.1/1.15(26) -- -- 1.1/1.15(26) -- V VICM (DC coupled) HCSL I/O standard for the PCIe reference clock 250 -- 550 250 -- 550 mV 10 Hz -- -- -50 -- -- -50 dBc/Hz 100 Hz -- -- -80 -- -- -80 dBc/Hz 1 KHz -- -- -110 -- -- -110 dBc/Hz 10 KHz -- -- -120 -- -- -120 dBc/Hz 100 KHz -- -- -120 -- -- -120 dBc/Hz 1 MHz -- -- -130 -- -- -130 dBc/Hz -- -- 2000 1% -- -- 2000 1% -- RREF (27) Condition Spread-spectrum modulating clock frequency Transmitter REFCLK phase noise(27) (26) AV-51002 2016.12.09 Transceiver Specifications for Arria V GX and SX Devices For data rate 3.2 Gbps, connect VCCR_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps, connect VCCR_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines. The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Specifications for Arria V GX and SX Devices 1-25 Table 1-21: Transceiver Clocks Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Transceiver Speed Grade 6 Min Typ Max Min Typ Max Unit fixedclk clock frequency PCIe Receiver Detect -- 125 -- -- 125 -- MHz Transceiver Reconfigura tion Controller IP (mgmt_ clk_clk) clock frequency -- 75 -- 125 75 -- 125 MHz Table 1-22: Receiver Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Min Supported I/O standards (28) (29) Typ Max Transceiver Speed Grade 6 Min Typ Max Unit 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS Data rate(28) -- 611 -- 6553.6 611 -- 3125 Mbps Absolute VMAX for a receiver pin(29) -- -- -- 1.2 -- -- 1.2 V Absolute VMIN for a receiver pin -- -0.4 -- -- -0.4 -- -- V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration -- -- -- 1.6 -- -- 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration -- -- -- 2.2 -- -- 2.2 V To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. The device cannot tolerate prolonged operation at this absolute maximum. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-26 Symbol/Description (32) (33) (34) (35) (36) Transceiver Speed Grade 4 Transceiver Speed Grade 6 Min Typ Max Min Typ Max Unit -- 100 -- -- 100 -- -- mV VICM (AC coupled) -- -- 0.7/0.75/ 0.8(31) -- -- 0.7/0.75/ 0.8 (31) -- mV VICM (DC coupled) 3.2Gbps(32) 670 700 730 670 700 730 mV 85- setting -- 85 -- -- 85 -- 100- setting -- 100 -- -- 100 -- 120- setting -- 120 -- -- 120 -- 150- setting -- 150 -- -- 150 -- tLTR(33) -- -- -- 10 -- -- 10 s tLTD -- 4 -- -- 4 -- -- s tLTD_manual(35) -- 4 -- -- 4 -- -- s tLTR_LTD_manual(36) -- 15 -- -- 15 -- -- s Programmable ppm detector(37) -- (34) (31) Condition Minimum differential eye opening at the receiver serial input pins(30) Differential on-chip termination resistors (30) AV-51002 2016.12.09 Transceiver Specifications for Arria V GX and SX Devices 62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. The AC coupled VICM = 700 mV for Arria V GX and SX in PCIe mode only. The AC coupled VICM = 750 mV for Arria V GT and ST in PCIe mode only. For standard protocol compliance, use AC coupling. tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Specifications for Arria V GX and SX Devices Symbol/Description Condition Run length -- Programmable equaliza tion AC and DC gain AC gain setting = 0 to 3(38) DC gain setting = 0 to 1 Transceiver Speed Grade 4 Transceiver Speed Grade 6 Min Typ Max Min Typ Max -- -- 200 -- -- 200 Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices diagrams. 1-27 Unit UI dB Table 1-23: Transmitter Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Min Typ Supported I/O standards -- Typ Max Unit 611 -- 6553.6 611 -- 3125 Mbps VOCM (AC coupled) -- -- 650 -- -- 650 -- mV 3.2Gbps 670 700 730 670 700 730 mV 85- setting -- 85 -- -- 85 -- 100- setting -- 100 -- -- 100 -- 120- setting -- 120 -- -- 120 -- 150- setting -- 150 -- -- 150 -- Intra-differential pair skew TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps -- -- 15 -- -- 15 ps Intra-transceiver block transmitter channel-tochannel skew x6 PMA bonded mode -- -- 180 -- -- 180 ps Differential on-chip termination resistors (37) Min 1.5 V PCML Data rate VOCM (DC coupled) (38) Max Transceiver Speed Grade 6 (32) The rate match FIFO supports only up to 300 parts per million (ppm). The Quartus Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-28 AV-51002 2016.12.09 Transceiver Specifications for Arria V GX and SX Devices Transceiver Speed Grade 4 Symbol/Description Condition Inter-transceiver block transmitter channel-tochannel skew(39) xN PMA bonded mode Transceiver Speed Grade 6 Min Typ Max Min Typ Max -- -- 500 -- -- 500 Unit ps Table 1-24: CMU PLL Specifications for Arria V GX and SX Devices Symbol/Description Transceiver Speed Grade 4 Transceiver Speed Grade 6 Unit Min Max Min Max Supported data range 611 6553.6 611 3125 Mbps fPLL supported data range 611 3125 611 3125 Mbps Table 1-25: Transceiver-FPGA Fabric Interface Specifications for Arria V GX and SX Devices Symbol/Description Transceiver Speed Grade 4 and 6 Unit Min Max Interface speed (single-width mode) 25 187.5 MHz Interface speed (double-width mode) 25 163.84 MHz Related Information * CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 1-35 * CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain on page 1-36 * Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines Provides more information about the power supply connection for different data rates. (39) This specification is only applicable to channels on one side of the device across two transceiver banks. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices 1-29 Transceiver Specifications for Arria V GT and ST Devices Table 1-26: Reference Clock Specifications for Arria V GT and ST Devices Symbol/Description Supported I/O standards Input frequency from REFCLK input pins (41) (42) Transceiver Speed Grade 3 Min Typ Max Unit 1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL(40), HCSL, and LVDS -- 27 -- 710 MHz Rise time Measure at 60 mV of differential signal(41) -- -- 400 ps Fall time Measure at 60 mV of differential signal(41) -- -- 400 ps Duty cycle -- 45 -- 55 % Peak-to-peak differential input voltage -- 200 -- 300(42)/2000 mV PCI Express (PCIe) 30 -- 33 kHz Spread-spectrum downspread PCIe -- 0 to -0.5% -- -- On-chip termination resistors -- -- 100 -- VICM (AC coupled) -- -- 1.2 -- V VICM (DC coupled) HCSL I/O standard for the PCIe reference clock 250 -- 550 mV Spread-spectrum modulating clock frequency (40) Condition Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. REFCLK performance requires to meet transmitter REFCLK phase noise specification. The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-30 AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices Symbol/Description Transmitter REFCLK phase noise(43) Transceiver Speed Grade 3 Condition Unit Min Typ Max 10 Hz -- -- -50 dBc/Hz 100 Hz -- -- -80 dBc/Hz 1 KHz -- -- -110 dBc/Hz 10 KHz -- -- -120 dBc/Hz 100 KHz -- -- -120 dBc/Hz 1 MHz -- -- -130 dBc/Hz -- -- 2000 1% -- RREF Table 1-27: Transceiver Clocks Specifications for Arria V GT and ST Devices Symbol/Description fixedclk clock frequency Condition Transceiver Speed Grade 3 Unit Min Typ Max PCIe Receiver Detect -- 125 -- MHz -- 75 -- 125 MHz Transceiver Reconfiguration Controller IP (mgmt_clk_clk) clock frequency Table 1-28: Receiver Specifications for Arria V GT and ST Devices Symbol/Description Condition Supported I/O Standards Data rate (6-Gbps transceiver)(44) (43) (44) Transceiver Speed Grade 3 Min Typ Max Unit 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS -- 611 -- 6553.6 Mbps The transmitter REFCLK phase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma. To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices Symbol/Description Condition Data rate (10-Gbps transceiver)(44) (46) (47) (48) (49) (50) Unit Min Typ Max -- 0.611 -- 10.3125 Gbps Absolute VMAX for a receiver pin(45) -- -- -- 1.2 V Absolute VMIN for a receiver pin -- -0.4 -- -- V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration -- -- -- 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration -- -- -- 2.2 V Minimum differential eye opening at the receiver serial input pins(46) -- 100 -- -- mV VICM (AC coupled) -- -- 750(47)/800 -- mV VICM (DC coupled) 3.2Gbps(48) 670 700 730 mV Differential on-chip termination resistors (45) Transceiver Speed Grade 3 1-31 85- setting 85 100- setting 100 120- setting 120 150- setting 150 tLTR(49) -- -- -- 10 s tLTD(50) -- 4 -- -- s The device cannot tolerate prolonged operation at this absolute maximum. The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. The AC coupled VICM is 750 mV for PCIe mode only. For standard protocol compliance, use AC coupling. tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-32 AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices Symbol/Description Condition Transceiver Speed Grade 3 Min Typ Max Unit tLTD_manual(51) -- 4 -- -- s tLTR_LTD_manual(52) -- 15 -- -- s Programmable ppm detector(53) -- Run length -- Programmable equalization AC and DC gain 62.5, 100, 125, 200, 250, 300, 500, and 1000 -- AC gain setting = 0 to 3(54) DC gain setting = 0 to 1 -- 200 ppm UI Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices diagrams. Table 1-29: Transmitter Specifications for Arria V GT and ST Devices Symbol/Description Condition Transceiver Speed Grade 3 Min Supported I/O standards (51) (52) (53) (54) Typ Max Unit 1.5 V PCML Data rate (6-Gbps transceiver) -- 611 -- 6553.6 Mbps Data rate (10-Gbps transceiver) -- 0.611 -- 10.3125 Gbps VOCM (AC coupled) -- -- 650 -- mV VOCM (DC coupled) 3.2 Gbps(48) 670 700 730 mV tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. The rate match FIFO supports only up to 300 ppm. The Quartus Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices Symbol/Description Transceiver Speed Grade 3 Condition Unit Min Typ Max 85- setting -- 85 -- 100- setting -- 100 -- 120- setting -- 120 -- 150- setting -- 150 -- TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps -- -- 15 ps Intra-transceiver block transmitter channel-to-channel skew x6 PMA bonded mode -- -- 180 ps Inter-transceiver block transmitter channel-to-channel skew(55) xN PMA bonded mode -- -- 500 ps Differential on-chip termination resistors Intra-differential pair skew 1-33 Table 1-30: CMU PLL Specifications for Arria V GT and ST Devices Symbol/Description Supported data range fPLL supported data range (55) Transceiver Speed Grade 3 Unit Min Max 0.611 10.3125 Gbps 611 3125 Mbps This specification is only applicable to channels on one side of the device across two transceiver banks. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-34 AV-51002 2016.12.09 Transceiver Specifications for Arria V GT and ST Devices Table 1-31: Transceiver-FPGA Fabric Interface Specifications for Arria V GT and ST Devices Symbol/Description Transceiver Speed Grade 3 Unit Min Max Interface speed (PMA direct mode) 50 153.6(56), 161(57) MHz Interface speed (single-width mode) 25 187.5 MHz Interface speed (double-width mode) 25 163.84 MHz Related Information * CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 1-35 * CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain on page 1-36 (56) (57) The maximum frequency when core transceiver local routing is selected. The maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1-35 CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain Figure 1-2: Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-36 AV-51002 2016.12.09 CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain Figure 1-3: CTLE Response at Data Rates 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 1-37 Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Table 1-32: Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Symbol VOD differential peak-to-peak typical (58) (59) VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV) 6(59) 120 34 680 7(59) 140 35 700 (59) 8 160 36 720 9 180 37 740 10 200 38 760 11 220 39 780 12 240 40 800 13 260 41 820 14 280 42 840 15 300 43 860 16 320 44 880 17 340 45 900 18 360 46 920 19 380 47 940 20 400 48 960 21 420 49 980 22 440 50 1000 23 460 51 1020 24 480 52 1040 Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. Only valid for data rates 5 Gbps. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-38 AV-51002 2016.12.09 Transmitter Pre-Emphasis Levels Symbol VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV) 25 500 53 1060 26 520 54 1080 27 540 55 1100 28 560 56 1120 29 580 57 1140 30 600 58 1160 31 620 59 1180 32 640 60 1200 33 660 Transmitter Pre-Emphasis Levels The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions: * Low-frequency data pattern--five 1s and five 0s * Data rate--2.5 Gbps The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre-emphasis levels may change with data pattern and data rate. Arria V devices only support 1st post tap pre-emphasis with the following conditions: * The 1st post tap pre-emphasis settings must satisfy |B| + |C| 60 where |B| = VOD setting with termination value, RTERM = 100 and |C| = 1st post tap pre-emphasis setting. * |B| - |C| > 5 for data rates < 5 Gbps and |B| - |C| > 8.25 for data rates > 5 Gbps. * (VMAX/VMIN - 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| - |C|. Exception for PCIe Gen2 design: VOD setting = 43 and pre-emphasis setting = 19 are allowed for PCIe Gen2 design with transmit de-emphasis - 6dB setting (pipe_txdeemp = 1'b0) using Altera PCIe Hard IP and PIPE IP cores. (58) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transmitter Pre-Emphasis Levels 1-39 For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid: * |B| + |C| 60 40 + 2 = 42 * |B| - |C| > 5 40 - 2 = 38 * (VMAX/VMIN - 1)% < 600% (42/38 - 1)% = 10.52% To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Arria V HSSI HSPICE models. Table 1-33: Transmitter Pre-Emphasis Levels for Arria V Devices Quartus Prime 1st Post Tap PreEmphasis Setting Quartus Prime VOD Setting 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 0 0 0 0 0 0 0 0 dB 1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 dB 2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 dB 3 5.35 2.48 1.49 1.2 1 0.83 0.69 dB 4 7.27 3.31 2 1.63 1.36 1.14 0.96 dB 5 -- 4.19 2.55 2.1 1.76 1.49 1.26 dB 6 -- 5.08 3.11 2.56 2.17 1.83 1.56 dB 7 -- 5.99 3.71 3.06 2.58 2.18 1.87 dB 8 -- 6.92 4.22 3.47 2.93 2.48 2.11 dB 9 -- 7.92 4.86 4 3.38 2.87 2.46 dB 10 -- 9.04 5.46 4.51 3.79 3.23 2.77 dB 11 -- 10.2 6.09 5.01 4.23 3.61 -- dB 12 -- 11.56 6.74 5.51 4.68 3.97 -- dB 13 -- 12.9 7.44 6.1 5.12 4.36 -- dB 14 -- 14.44 8.12 6.64 5.57 4.76 -- dB 15 -- -- 8.87 7.21 6.06 5.14 -- dB Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Unit Altera Corporation 1-40 AV-51002 2016.12.09 Transceiver Compliance Specification Quartus Prime 1st Post Tap PreEmphasis Setting Quartus Prime VOD Setting 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 16 -- -- 9.56 7.73 6.49 -- -- dB 17 -- -- 10.43 8.39 7.02 -- -- dB 18 -- -- 11.23 9.03 7.52 -- -- dB 19 -- -- 12.18 9.7 8.02 -- -- dB 20 -- -- 13.17 10.34 8.59 -- -- dB 21 -- -- 14.2 11.1 -- -- -- dB 22 -- -- 15.38 11.87 -- -- -- dB 23 -- -- -- 12.67 -- -- -- dB 24 -- -- -- 13.48 -- -- -- dB 25 -- -- -- 14.37 -- -- -- dB 26 -- -- -- -- -- -- -- dB 27 -- -- -- -- -- -- -- dB 28 -- -- -- -- -- -- -- dB 29 -- -- -- -- -- -- -- dB 30 -- -- -- -- -- -- -- dB 31 -- -- -- -- -- -- -- dB Unit Related Information SPICE Models for Altera Devices Provides the Arria V HSSI HSPICE models. Transceiver Compliance Specification The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Arria V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Altera Sales Representative. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Compliance Specification 1-41 Table 1-34: Transceiver Compliance Specification for All Supported Protocol for Arria V GX, GT, SX, and ST Devices Protocol PCIe XAUI Serial RapidIO(R) (SRIO) Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Sub-protocol Data Rate (Mbps) PCIe Gen1 2,500 PCIe Gen2 5,000 PCIe Cable 2,500 XAUI 2135 3,125 SRIO 1250 SR 1,250 SRIO 1250 LR 1,250 SRIO 2500 SR 2,500 SRIO 2500 LR 2,500 SRIO 3125 SR 3,125 SRIO 3125 LR 3,125 SRIO 5000 SR 5,000 SRIO 5000 MR 5,000 SRIO 5000 LR 5,000 SRIO_6250_SR 6,250 SRIO_6250_MR 6,250 SRIO_6250_LR 6,250 Altera Corporation 1-42 Protocol Common Public Radio Interface (CPRI) Gbps Ethernet (GbE) OBSAI Serial digital interface (SDI) (60) AV-51002 2016.12.09 Transceiver Compliance Specification Sub-protocol Data Rate (Mbps) CPRI E6LV 614.4 CPRI E6HV 614.4 CPRI E6LVII 614.4 CPRI E12LV 1,228.8 CPRI E12HV 1,228.8 CPRI E12LVII 1,228.8 CPRI E24LV 2,457.6 CPRI E24LVII 2,457.6 CPRI E30LV 3,072 CPRI E30LVII 3,072 CPRI E48LVII 4,915.2 CPRI E60LVII 6,144 CPRI E96LVIII(60) 9,830.4 GbE 1250 1,250 OBSAI 768 768 OBSAI 1536 1,536 OBSAI 3072 3,072 OBSAI 6144 6,144 SDI 270 SD 270 SDI 1485 HD 1,485 SDI 2970 3G 2,970 You can achieve compliance with TX channel restriction of one HSSI channel per six-channel transceiver bank. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Core Performance Specifications Protocol SONET Gigabit-capable passive optical network (GPON) QSGMII Sub-protocol Data Rate (Mbps) SONET 155 155.52 SONET 622 622.08 SONET 2488 2,488.32 GPON 155 155.52 GPON 622 622.08 GPON 1244 1,244.16 GPON 2488 2,488.32 QSGMII 5000 5,000 1-43 Core Performance Specifications Clock Tree Specifications Table 1-35: Clock Tree Specifications for Arria V Devices Parameter Performance Unit -I3, -C4 -I5, -C5 -C6 Global clock and Regional clock 625 625 525 MHz Peripheral clock 450 400 350 MHz PLL Specifications Table 1-36: PLL Specifications for Arria V Devices This table lists the Arria V PLL block specifications. Arria V PLL block does not include HPS PLL. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-44 Symbol fIN Min Typ Max Unit -3 speed grade 5 -- 800(61) MHz -4 speed grade 5 -- 800 (61) MHz -5 speed grade 5 -- 750(61) MHz -6 speed grade 5 -- 625(61) MHz -- 5 -- 325 MHz fFINPFD Fractional input clock frequency to the PFD -- 50 -- 160 MHz -3 speed grade 600 -- 1600 MHz -4 speed grade 600 -- 1600 MHz -5 speed grade 600 -- 1600 MHz -6 speed grade 600 -- 1300 MHz -- 40 -- 60 % -3 speed grade -- -- 500(63) MHz -4 speed grade -- -- 500(63) MHz -5 speed grade -- -- 500(63) MHz -6 speed grade -- -- 400 MHz fOUT (63) Input clock frequency Condition Integer input clock frequency to the phase frequency detector (PFD) tEINDUTY (62) Parameter fINPFD fVCO(62) (61) AV-51002 2016.12.09 PLL Specifications PLL voltage-controlled oscillator (VCO) operating range Input clock or external feedback clock input duty cycle Output frequency for internal global or regional clock (63) This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. The VCO frequency reported by the Quartus Prime software takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 PLL Specifications Symbol fOUT_EXT Parameter Output frequency for external clock output Condition Min Typ Max Unit -3 speed grade -- -- 670(63) MHz -4 speed grade -- -- 670 (63) MHz -5 speed grade -- -- 622(63) MHz -6 speed grade -- -- 500(63) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) -- 45 50 55 % tFCOMP External feedback clock compensation time -- -- -- 10 ns Dynamic configuration clock for mgmt_ -- -- -- 100 MHz Time required to lock from end-ofdevice configuration or deassertion of -- -- -- 1 ms -- -- -- 1 ms Low -- 0.3 -- MHz Medium -- 1.5 -- MHz High(64) -- 4 -- MHz tDYCONFIGCLK tLOCK clk and scanclk 1-45 areset tDLOCK fCLBW (64) (65) (66) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) PLL closed-loop bandwidth tPLL_PSERR Accuracy of PLL phase shift -- -- -- 50 ps tARESET Minimum pulse width on the areset signal -- 10 -- -- ns tINCCJ(65)(66) Input clock cycle-to-cycle jitter FREF 100 MHz -- -- 0.15 UI (p-p) FREF < 100 MHz -- -- 750 ps (p-p) High bandwidth PLL settings are not supported in external feedback mode. A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. FREF is fIN/N, specification applies when N = 1. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-46 Symbol (67) (68) (69) (70) AV-51002 2016.12.09 PLL Specifications Parameter Condition Min Typ Max Unit tOUTPJ_DC(67) Period jitter for dedicated clock output in integer PLL FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) tFOUTPJ_DC(67) Period jitter for dedicated clock output in fractional PLL FOUT 100 MHz -- -- 250(68), 175(69) ps (p-p) FOUT < 100 MHz -- -- 25(68), 17.5(69) mUI (p-p) tOUTCCJ_DC(67) Cycle-to-cycle jitter for dedicated clock output in integer PLL FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- tFOUTCCJ_DC(67) Cycle-to-cycle jitter for dedicated clock output in fractional PLL FOUT 100 MHz -- -- 250 FOUT < 100 MHz -- -- 25(68), 17.5(69) mUI (p-p) tOUTPJ_IO(67)(70) Period jitter for clock output on a regular I/O in integer PLL FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) tFOUTPJ_IO(67)(68)(70) Period jitter for clock output on a regular I/O in fractional PLL FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) tOUTCCJ_IO(67)(70) Cycle-to-cycle jitter for clock output on a regular I/O in integer PLL FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) tFOUTCCJ_IO(67)(68)(70) Cycle-to-cycle jitter for clock output on a regular I/O in fractional PLL FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) 17.5 , 175 (68) mUI (p-p) (69) ps (p-p) Peak-to-peak jitter with a probability level of 10-12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Arria V Devices table. This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be 1000 MHz. This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be 1200 MHz. External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Arria V Devices table. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 PLL Specifications Symbol Parameter Condition Min Typ Max Unit tCASC_OUTPJ_DC(67)(71) Period jitter for dedicated clock output in cascaded PLLs FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) tDRIFT Frequency drift after PFDENA is disabled for a duration of 100 s -- -- -- 10 % dKBIT Bit number of Delta Sigma Modulator (DSM) -- 8 24 32 bits kVALUE Numerator of fraction -- 128 8388608 2147483648 -- fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz 1-47 Related Information Memory Output Clock Jitter Specifications on page 1-57 Provides more information about the external memory interface clock output jitter specifications. (71) The cascaded PLL specification is only applicable with the following conditions: * Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz * Downstream PLL: Downstream PLL BW > 2 MHz Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-48 AV-51002 2016.12.09 DSP Block Performance Specifications DSP Block Performance Specifications Table 1-37: DSP Block Performance Specifications for Arria V Devices Mode Performance Unit -I3, -C4 -I5, -C5 -C6 Independent 9 x 9 multiplication 370 310 220 MHz Independent 18 x 19 multiplication 370 310 220 MHz Independent 18 x 25 multiplication 370 310 220 MHz Modes using One DSP Independent 20 x 24 multiplication Block Independent 27 x 27 multiplication 370 310 220 MHz 310 250 200 MHz Two 18 x 19 multiplier adder mode 370 310 220 MHz 18 x 18 multiplier added summed with 36bit input 370 310 220 MHz Complex 18 x 19 multiplication 370 310 220 MHz Modes using Two DSP Blocks Memory Block Performance Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Internal Temperature Sensing Diode Specifications 1-49 Table 1-38: Memory Block Performance Specifications for Arria V Devices Memory MLAB M10K Block Resources Used Mode Performance Unit ALUTs Memory -I3, -C4 -I5, -C5 -C6 Single port, all supported widths 0 1 500 450 400 MHz Simple dual-port, all supported widths 0 1 500 450 400 MHz Simple dual-port with read and write at the same address 0 1 400 350 300 MHz ROM, all supported width -- -- 500 450 400 MHz Single-port, all supported widths 0 1 400 350 285 MHz Simple dual-port, all supported widths 0 1 400 350 285 MHz Simple dual-port with the read-duringwrite option set to Old Data, all supported widths 0 1 315 275 240 MHz True dual port, all supported widths 0 1 400 350 285 MHz ROM, all supported widths 0 1 400 350 285 MHz Internal Temperature Sensing Diode Specifications Table 1-39: Internal Temperature Sensing Diode Specifications for Arria V Devices Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time Resolution Minimum Resolution with no Missing Codes -40 to 100C 8C No 1 MHz < 100 ms 8 bits 8 bits Periphery Performance This section describes the periphery performance, high-speed I/O, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-50 AV-51002 2016.12.09 High-Speed I/O Specifications High-Speed I/O Specifications Table 1-40: High-Speed I/O Specifications for Arria V Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. The Arria V devices support the following output standards using true LVDS output buffer types on all I/O banks. * True RSDS output standard with data rates of up to 360 Mbps * True mini-LVDS output standard with data rates of up to 400 Mbps Symbol (74) (75) (76) (77) -I5, -C5 -C6 Min Typ Max Min Typ Max Min Typ Max Unit Clock boost factor W = 1 to 40(72) 5 -- 800 5 -- 750 5 -- 625 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards(73) Clock boost factor W = 1 to 40(72) 5 -- 625 5 -- 625 5 -- 500 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards(74) Clock boost factor W = 1 to 40(72) 5 -- 420 5 -- 420 5 -- 420 MHz -- 5 -- 625(75) 5 -- 625(75) 5 -- 500(75) MHz SERDES factor J =3 to 10(76) (77) -- 1250 (77) -- 1250 (77) -- 1050 Mbps Transmitter (72) -I3, -C4 fHSCLK_in (input clock frequency) True Differential I/O Standards fHSCLK_OUT (output clock frequency) (73) Condition True Differential I/O Standards - fHSDR (data rate) Clock boost factor (W) is the ratio between the input data rate and the input clock rate. This applies to DPA and soft-CDR modes only. This applies to non-DPA mode only. This is achieved by using the LVDS clock network. The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Symbol Condition -I3, -C4 (80) (81) -C6 Unit Typ Max Min Typ Max Min Typ Max SERDES factor J 8 , LVDS TX with RX DPA (77) -- 1600 (77) -- 1500 (77) -- 1250 Mbps SERDES factor J = 1 to 2, Uses DDR Registers (77) -- (79) (77) -- (79) (77) -- (79) Mbps Emulated Differential I/ O Standards with Three External Output Resistor Network - fHSDR (data rate)(80) SERDES factor J = 4 to 10(81) (77) -- 945 (77) -- 945 (77) -- 945 Mbps Emulated Differential I/ O Standards with One External Output Resistor Network - fHSDR (data rate)(80) SERDES factor J = 4 to 10(81) (77) -- 200 (77) -- 200 (77) -- 200 Mbps Total Jitter for Data Rate 600 Mbps - 1.25 Gbps -- -- 160 -- -- 160 -- -- 160 ps Total Jitter for Data Rate < 600 Mbps -- -- 0.1 -- -- 0.1 -- -- 0.1 UI tx Jitter -True Differential I/O Standards (79) -I5, -C5 Min (76)(78) (78) 1-51 High-Speed I/O Specifications The VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface. The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT), provided you can close the design timing and the signal integrity simulation is clean. You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-52 AV-51002 2016.12.09 High-Speed I/O Specifications Symbol Condition tDUTY tRISE and tFALL (82) -I5, -C5 -C6 Unit Min Typ Max Min Typ Max Min Typ Max -- -- 260 -- -- 300 -- -- 350 ps -- -- 0.16 -- -- 0.18 -- -- 0.21 UI -- -- -- 0.15 -- -- 0.15 -- -- 0.15 UI TX output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 45 50 55 % True Differential I/O Standards(82) -- -- 160 -- -- 180 -- -- 200 ps Emulated Differential I/O Standards with Three External Output Resistor Network -- -- 250 -- -- 250 -- -- 300 ps Emulated Differential I/O Standards with One External Output Resistor Network -- -- 500 -- -- 500 -- -- 500 ps Total Jitter for Data tx Jitter -Emulated Rate 600 Mbps - 1.25 Differential I/O Gbps Standards with Three External Output Resistor Total Jitter for Data Network Rate < 600 Mbps tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network -I3, -C4 This applies to default pre-emphasis and VOD settings only. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Symbol Condition -I3, -C4 -I5, -C5 -C6 Unit Min Typ Max Min Typ Max Min Typ Max True Differential I/O Standards -- -- 150 -- -- 150 -- -- 150 ps Emulated Differential I/O Standards -- -- 300 -- -- 300 -- -- 300 ps SERDES factor J =3 to 10(76) 150 -- 1250 150 -- 1250 150 -- 1050 Mbps SERDES factor J 8 with DPA(76)(78) 150 -- 1600 150 -- 1500 150 -- 1250 Mbps SERDES factor J = 3 to 10 (77) -- (83) (77) -- (83) (77) -- (83) Mbps fHSDR (data rate) SERDES factor J = 1 to 2, uses DDR registers (77) -- (79) (77) -- (79) (77) -- (79) Mbps DPA Mode DPA run length -- -- -- 10000 -- -- 10000 -- -- 10000 UI Soft-CDR Mode Soft-CDR ppm tolerance -- -- -- 300 -- -- 300 -- -- 300 ppm Non-DPA Mode Sampling Window -- -- -- 300 -- -- 300 -- -- 300 ps TCCS True Differential I/O Standards - fHSDRDPA (data rate) Receiver (83) 1-53 High-Speed I/O Specifications You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-54 AV-51002 2016.12.09 DPA Lock Time Specifications DPA Lock Time Specifications Figure 1-4: Dynamic Phase Alignment (DPA) Lock Time Specifications with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 Data Transitions 96 Slow Clock Cycles 256 Data Transitions 96 Slow Clock Cycles 256 Data Transitions Table 1-41: DPA Lock Time Specifications for Arria V Devices The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. Standard SPI-4 Parallel Rapid I/O Miscellaneous (84) Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions(84) Maximum Data Transition 00000000001111111111 2 128 640 00001111 2 128 640 10010000 4 64 640 10101010 8 32 640 01010101 8 32 640 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1-55 LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Jitter Amphlitude (UI) Figure 1-5: LVDS Soft-Clock Data Recovery (CDR)/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps 25 8.5 0.35 0.1 F1 F2 F3 Jitter Frequency (Hz) F4 Table 1-42: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps Jitter Frequency (Hz) F1 10,000 25.000 F2 17,565 25.000 F3 1,493,000 0.350 F4 50,000,000 0.350 Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Sinusoidal Jitter (UI) Altera Corporation 1-56 AV-51002 2016.12.09 DLL Frequency Range Specifications Figure 1-6: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P baud/1667 20 MHz Frequency DLL Frequency Range Specifications Table 1-43: DLL Frequency Range Specifications for Arria V Devices Parameter DLL operating frequency range -I3, -C4 -I5, -C5 -C6 Unit 200 - 667 200 - 667 200 - 667 MHz DQS Logic Block Specifications Table 1-44: DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria V Devices This error specification is the absolute maximum and minimum error. Number of DQS Delay Buffer -I3, -C4 -I5, -C5 -C6 Unit 2 40 80 80 ps Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Memory Output Clock Jitter Specifications 1-57 Memory Output Clock Jitter Specifications Table 1-45: Memory Output Clock Jitter Specifications for Arria V Devices The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10-12, equivalent to 14 sigma. Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance. Parameter Clock Network Symbol Clock period jitter PHYCLK tJIT(per) Cycle-to-cycle period jitter PHYCLK tJIT(cc) -I3, -C4 -I5, -C5 -C6 Min Max Min Max Min Max -41 41 -50 50 -55 55 63 90 Unit ps 94 ps OCT Calibration Block Specifications Table 1-46: OCT Calibration Block Specifications for Arria V Devices Symbol Min Typ Max Unit Clock required by OCT calibration blocks -- -- 20 MHz TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT/RT OCT calibration -- 1000 -- Cycles TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out -- 32 -- Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT -- 2.5 -- ns OCTUSRCLK Description Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-58 AV-51002 2016.12.09 Duty Cycle Distortion (DCD) Specifications Figure 1-7: Timing Diagram for oe and dyn_term_ctrl Signals Tristate RX Tristate TX RX oe dyn_term_ctrl TRS_RT TRS_RT Duty Cycle Distortion (DCD) Specifications Table 1-47: Worst-Case DCD on Arria V I/O Pins The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD. Symbol Output Duty Cycle -I3, -C4 -C5, -I5 -C6 Min Max Min Max Min Max 45 55 45 55 45 55 Unit % HPS Specifications This section provides HPS specifications and timing for Arria V devices. For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 HPS Clock Performance 1-59 HPS Clock Performance Table 1-48: HPS Clock Performance for Arria V Devices Symbol/Description -I3 -C4 -C5, -I5 -C6 Unit mpu_base_clk (microprocessor unit clock) 1050 925 800 700 MHz main_base_clk (L3/L4 interconnect clock) 400 400 400 350 MHz h2f_user0_clk 100 100 100 100 MHz h2f_user1_clk 100 100 100 100 MHz h2f_user2_clk 200 200 200 160 MHz HPS PLL Specifications HPS PLL VCO Frequency Range Table 1-49: HPS PLL VCO Frequency Range for Arria V Devices Description VCO range Speed Grade Minimum Maximum Unit -C5, -I5, -C6 320 1,600 MHz -C4 320 1,850 MHz -I3 320 2,100 MHz HPS PLL Input Clock Range The HPS PLL input clock range is 10 - 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs. Related Information Clock Select, Booting and Configuration chapter Provides more information about the clock range for different values of clock select (CSEL). Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-60 AV-51002 2016.12.09 HPS PLL Input Jitter HPS PLL Input Jitter Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64. Maximum input jitter = Input clock period x Divide value (N) x 0.02 Table 1-50: Examples of Maximum Input Jitter Input Reference Clock Period Divide Value (N) Maximum Jitter Unit 40 ns 1 0.8 ns 40 ns 2 1.6 ns 40 ns 4 3.2 ns Quad SPI Flash Timing Characteristics Table 1-51: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit -- -- 108 MHz 2.32 -- -- ns Fclk SCLK_OUT clock frequency (External clock) Tqspi_clk QSPI_CLK clock period (Internal reference clock) Tdutycycle SCLK_OUT duty cycle 45 -- 55 % Tdssfrst Output delay QSPI_SS valid before first clock edge -- 1/2 cycle of SCLK_OUT -- ns Tdsslst Output delay QSPI_SS valid after last clock edge -1 -- 1 ns Tdio I/O data output delay -1 -- 1 ns Tdin_start Input data valid start -- -- (2 + Rdelay) x Tqspi_clk - 7.52 (85) ns Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 SPI Timing Characteristics Symbol Tdin_end Description Input data valid end Min Typ Max Unit (2 + Rdelay) x Tqspi_clk - 1.21 (85) -- -- ns 1-61 Figure 1-8: Quad SPI Flash Timing Diagram This timing diagram illustrates clock polarity mode 0 and clock phase mode 0. Tdsslst QSPI_SS Tdssfrst SCLK_OUT Tdio Data Out QSPI_DATA Tdin_start Data In Tdin_end Related Information Quad SPI Flash Controller Chapter, Arria V Hard Processor System Technical Reference Manual Provides more information about Rdelay. SPI Timing Characteristics Table 1-52: SPI Master Timing Requirements for Arria V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Symbol (85) Description Tclk CLK clock period Tsu SPI Master-in slave-out (MISO) setup time Min Max Unit 16.67 -- ns -- ns 8.35 (86) Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Altera provides automatic Quad SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Arria V Hard Processor System Technical Reference Manual. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-62 Symbol (86) AV-51002 2016.12.09 SPI Timing Characteristics Description Min Max Unit Th SPI MISO hold time 1 -- ns Tdutycycle SPI_CLK duty cycle 45 55 % Tdssfrst Output delay SPI_SS valid before first clock edge 8 -- ns Tdsslst Output delay SPI_SS valid after last clock edge 8 -- ns Tdio Master-out slave-in (MOSI) output delay -1 1 ns This value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it's SCLK_ OUT. These timings are based on rx_sample_dly of 1. This delay can be adjusted as needed to accommodate slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_ sample_dly value because each SPI slave device may have different output delay and each application board may have different path delay. For more information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 SPI Timing Characteristics 1-63 Figure 1-9: SPI Master Timing Diagram Tdsslst SPI_SS SPI_CLK (scpol = 0) Tdssfrst SPI_CLK (scpol = 1) Tdio SPI_MOSI (scph = 1) Tsu Th SPI_MISO (scph = 1) Tdio SPI_MOSI (scph = 0) Tsu Th SPI_MISO (scph = 0) Table 1-53: SPI Slave Timing Requirements for Arria V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Symbol Description Min Max Unit Tclk CLK clock period 20 -- ns Ts MOSI Setup time 5 -- ns Th MOSI Hold time 5 -- ns Tsuss Setup time SPI_SS valid before first clock edge 8 -- ns Thss Hold time SPI_SS valid after last clock edge 8 -- ns Td MISO output delay -- 6 ns Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-64 AV-51002 2016.12.09 SD/MMC Timing Characteristics Figure 1-10: SPI Slave Timing Diagram Thss SPI_SS Tsuss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) Td SPI_MISO (scph = 1) Ts Th SPI_MOSI (scph = 1) Td SPI_MISO (scph = 0) Ts Th SPI_MOSI (scph = 0) Related Information SPI Controller, Arria V Hard Processor System Technical Reference Manual Provides more information about rx_sample_delay. SD/MMC Timing Characteristics Table 1-54: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 SD/MMC Timing Characteristics 1-65 After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager. drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase to a maximum of 200 MHz and 50 MHz respectively. The SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS software update. Symbol Min Max Unit SDMMC_CLK clock period (Identification mode) 20 -- ns SDMMC_CLK clock period (Default speed mode) 5 -- ns SDMMC_CLK clock period (High speed mode) 5 -- ns SDMMC_CLK_OUT clock period (Identification mode) 2500 -- ns SDMMC_CLK_OUT clock period (Default speed mode) 40 -- ns SDMMC_CLK_OUT clock period (High speed mode) 20 -- ns Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 % Td SDMMC_CMD/SDMMC_D output delay (Tsdmmc_clk x drvsel)/2 - 1.23 (87) (Tsdmmc_clk x drvsel)/2 + 1.69 (87) ns Tsu Input setup time 1.05 - (Tsdmmc_clk x smplsel)/2 (88) -- ns Th Input hold time (Tsdmmc_clk x smplsel)/ 2 (88) -- ns Tsdmmc_clk (internal reference clock) Tsdmmc_clk_out (interface output clock) (87) (88) Description drvsel is the drive clock phase shift select value. smplsel is the sample clock phase shift select value. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-66 AV-51002 2016.12.09 USB Timing Characteristics Figure 1-11: SD/MMC Timing Diagram SDMMC_CLK_OUT Td SDMMC_CMD & SDMMC_D (Out) Command/Data Out Tsu Th SDMMC_CMD & SDMMC_D (In) Command/Data In Related Information Booting and Configuration Chapter, Arria V Hard Processor System Technical Reference Manual Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table. USB Timing Characteristics PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Table 1-55: USB Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit Tclk USB CLK clock period -- 16.67 -- ns Td CLK to USB_STP/USB_DATA[7:0] output delay 4.4 -- 11 ns Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 -- -- ns Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 -- -- ns Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Ethernet Media Access Controller (EMAC) Timing Characteristics 1-67 Figure 1-12: USB Timing Diagram USB_CLK USB_STP Td USB_DATA[7:0] From PHY To PHY Tsu Th USB_DIR & USB_NXT Ethernet Media Access Controller (EMAC) Timing Characteristics Table 1-56: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit Tclk (1000Base-T) TX_CLK clock period -- 8 -- ns Tclk (100Base-T) TX_CLK clock period -- 40 -- ns Tclk (10Base-T) TX_CLK clock period -- 400 -- ns Tdutycycle TX_CLK duty cycle 45 -- 55 % Td TX_CLK to TXD/TX_CTL output data delay -0.85 -- 0.15 ns Figure 1-13: RGMII TX Timing Diagram TX_CLK TX_D[3:0] Td TX_CTL Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-68 AV-51002 2016.12.09 Ethernet Media Access Controller (EMAC) Timing Characteristics Table 1-57: RGMII RX Timing Requirements for Arria V Devices Symbol Description Min Typ Unit Tclk (1000Base-T) RX_CLK clock period -- 8 ns Tclk (100Base-T) RX_CLK clock period -- 40 ns Tclk (10Base-T) RX_CLK clock period -- 400 ns Tsu RX_D/RX_CTL setup time 1 -- ns Th RX_D/RX_CTL hold time 1 -- ns Figure 1-14: RGMII RX Timing Diagram RX_CLK Tsu Th RX_D[3:0] RX_CTL Table 1-58: Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit Tclk MDC clock period -- 400 -- ns Td MDC to MDIO output data delay 10 -- 20 ns Ts Setup time for MDIO data 10 -- -- ns Th Hold time for MDIO data 0 -- -- ns Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 I2C Timing Characteristics 1-69 Figure 1-15: MDIO Timing Diagram MDC Td MDIO_OUT Tsu Th MDIO_IN I2C Timing Characteristics Table 1-59: I2C Timing Requirements for Arria V Devices Symbol Description Standard Mode Fast Mode Min Max Min Max Unit Tclk Serial clock (SCL) clock period 10 -- 2.5 -- s Tclkhigh SCL high time 4.7 -- 0.6 -- s Tclklow SCL low time 4 -- 1.3 -- s Ts Setup time for serial data line (SDA) data to SCL 0.25 -- 0.1 -- s Th Hold time for SCL to SDA data 0 3.45 0 0.9 s Td SCL to SDA output data delay -- 0.2 -- 0.2 s Tsu_start Setup time for a repeated start condition 4.7 -- 0.6 -- s Thd_start Hold time for a repeated start condition 4 -- 0.6 -- s Tsu_stop Setup time for a stop condition 4 -- 0.6 -- s Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-70 AV-51002 2016.12.09 NAND Timing Characteristics Figure 1-16: I2C Timing Diagram I2C_SCL Td Ts Tsu_start Thd_start Data Out I2C_SDA Tsu_stop Th Data In NAND Timing Characteristics Table 1-60: NAND ONFI 1.0 Timing Requirements for Arria V Devices The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. This table lists the requirements for ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL and timing registers provided in the NAND controller. Symbol Min Max Unit Twp(89) Write enable pulse width 10 -- ns Twh(89) Write enable hold time 7 -- ns Trp Read enable pulse width 10 -- ns Treh(89) Read enable hold time 7 -- ns Tclesu(89) Command latch enable to write enable setup time 10 -- ns Tcleh Command latch enable to write enable hold time 5 -- ns Tcesu(89) Chip enable to write enable setup time 15 -- ns Tceh(89) Chip enable to write enable hold time 5 -- ns Talesu Address latch enable to write enable setup time 10 -- ns Taleh(89) Address latch enable to write enable hold time 5 -- ns Tdsu Data to write enable setup time 10 -- ns (89) (89) (89) (89) (89) Description Timing of the NAND interface is controlled through the NAND configuration registers. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 NAND Timing Characteristics Symbol Description Min Max Unit Tdh(89) Data to write enable hold time 5 -- ns Tcea Chip enable to data access time -- 25 ns Trea Read enable to data access time -- 16 ns Trhz Read enable to data high impedance -- 100 ns Trr Ready to read enable low 20 -- ns 1-71 Figure 1-17: NAND Command Latch Timing Diagram NAND_CLE NAND_CE Tclesu Tcesu Tcleh Twp Tceh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Tdh Command Altera Corporation 1-72 AV-51002 2016.12.09 NAND Timing Characteristics Figure 1-18: NAND Address Latch Timing Diagram NAND_CLE NAND_CE Tcesu Tclesu Twp Twh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Altera Corporation Tdh Address Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 NAND Timing Characteristics 1-73 Figure 1-19: NAND Data Write Timing Diagram NAND_CLE NAND_CE Tcleh Twp Tceh NAND_WE Talesu NAND_ALE Tdsu Tdh NAND_DQ[7:0] Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Din Altera Corporation 1-74 AV-51002 2016.12.09 ARM Trace Timing Characteristics Figure 1-20: NAND Data Read Timing Diagram Tcea NAND_CE Trr Trp Treh NAND_RE Trhz NAND_RB Trea NAND_DQ[7:0] Dout ARM Trace Timing Characteristics Table 1-61: ARM Trace Timing Requirements for Arria V Devices Most debugging tools have a mechanism to adjust the capture point of trace data. Description Min Max Unit 12.5 -- ns CLK maximum duty cycle 45 55 % CLK to D0 -D7 output data delay -1 1 ns CLK clock period UART Interface The maximum UART baud rate is 6.25 megasymbols per second. GPIO Interface The minimum detectable general-purpose I/O (GPIO) pulse width is 2 s. The pulse width is based on a debounce clock frequency of 1 MHz. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 HPS JTAG Timing Specifications 1-75 HPS JTAG Timing Specifications Table 1-62: HPS JTAG Timing Parameters and Values for Arria V Devices Symbol Description Min Max Unit tJCP TCK clock period 30 -- ns tJCH TCK clock high time 14 -- ns tJCL TCK clock low time 14 -- ns tJPSU (TDI) TDI JTAG port setup time 2 -- ns tJPSU (TMS) TMS JTAG port setup time 3 -- ns tJPH JTAG port hold time 5 -- ns tJPCO JTAG port clock to output -- 12(90) ns tJPZX JTAG port high impedance to valid output -- 14 (90) ns tJPXZ JTAG port valid output to high impedance -- 14(90) ns Configuration Specifications This section provides configuration specifications and timing for Arria V devices. POR Specifications Table 1-63: Fast and Standard POR Delay Specification for Arria V Devices POR Delay Fast (90) (91) Minimum Maximum Unit 4 12(91) ms A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-76 AV-51002 2016.12.09 FPGA JTAG Configuration Timing POR Delay Standard Minimum Maximum Unit 100 300 ms Related Information MSEL Pin Settings Provides more information about POR delay based on MSEL pin settings for each configuration scheme. FPGA JTAG Configuration Timing Table 1-64: FPGA JTAG Timing Parameters and Values for Arria V Devices Symbol (92) (93) Description Min Max Unit 30, 167(92) -- ns tJCP TCK clock period tJCH TCK clock high time 14 -- ns tJCL TCK clock low time 14 -- ns tJPSU (TDI) TDI JTAG port setup time 2 -- ns tJPSU (TMS) TMS JTAG port setup time 3 -- ns tJPH JTAG port hold time 5 -- ns tJPCO JTAG port clock to output -- 12(93) ns tJPZX JTAG port high impedance to valid output -- 14(93) ns tJPXZ JTAG port valid output to high impedance -- 14(93) ns The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V - 1.5 V when you perform the volatile key programming. A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 FPP Configuration Timing 1-77 FPP Configuration Timing DCLK-to-DATA[] Ratio (r) for FPP Configuration Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. Table 1-65: DCLK-to-DATA[] Ratio for Arria V Devices Configuration Scheme Encryption Compression DCLK-to-DATA[] Ratio (r) Off Off 1 On Off 1 Off On 2 On On 2 Off Off 1 On Off 2 Off On 4 On On 4 FPP (8-bit wide) FPP (16-bit wide) FPP Configuration Timing when DCLK-to-DATA[] = 1 When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP x8 and FPP x16. For the respective DCLKto-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria V Devices table. Table 1-66: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-78 AV-51002 2016.12.09 FPP Configuration Timing when DCLK-to-DATA[] = 1 Symbol Parameter Minimum Maximum Unit 268 1506(94) s -- 1506 s tSTATUS nSTATUS low pulse width tCF2ST1 nCONFIG high to nSTATUS high tCF2CK(96) nCONFIG high to first rising edge on DCLK 1506 -- s tST2CK(96) nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/ x16) -- 125 MHz tCD2UM CONF_DONE high to user mode(97) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit x CLKUSR period) -- -- Tinit Number of clock cycles required for device initialization 8,576 -- Cycles (95) Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (94) (95) (96) (97) You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width. You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 FPP Configuration Timing when DCLK-to-DATA[] >1 1-79 FPP Configuration Timing when DCLK-to-DATA[] >1 Table 1-67: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices Use these timing parameters when you use the decompression and design security features. Symbol (98) (100) (101) (102) Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1506(98) s tCF2ST1 nCONFIG high to nSTATUS high -- 1506(99) s tCF2CK nCONFIG high to first rising edge on DCLK 1506 -- s tST2CK(100) nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK N - 1/fDCLK(101) -- s tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/ x16) -- 125 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode(102) 175 437 s (100) (99) Parameter This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. This value can be obtained if you do not delay configuration by externally holding nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system. The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-80 AV-51002 2016.12.09 AS Configuration Timing Symbol Parameter tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Tinit Number of clock cycles required for device initialization Minimum Maximum Unit 4 x maximum DCLK period -- -- tCD2CU + (Tinit x CLKUSR period) -- -- 8,576 -- Cycles Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. AS Configuration Timing Table 1-68: AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Arria V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low. Symbol Parameter Minimum Maximum Unit tCO DCLK falling edge to the AS_DATA0/ASDO output -- 2 ns tSU Data setup time before the falling edge on DCLK 1.5 -- ns tDH Data hold time after the falling edge on DCLK 0 -- ns tCD2UM CONF_DONE high to user mode 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit x CLKUSR period) -- -- Tinit Number of clock cycles required for device initialization 8,576 -- Cycles Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 DCLK Frequency Specification in the AS Configuration Scheme 1-81 Related Information * PS Configuration Timing on page 1-81 * AS Configuration Timing Provides the AS configuration timing waveform. DCLK Frequency Specification in the AS Configuration Scheme Table 1-69: DCLK Frequency Specification in the AS Configuration Scheme This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Parameter DCLK frequency in AS configuration scheme Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz PS Configuration Timing Table 1-70: PS Timing Parameters for Arria V Devices Symbol (103) (104) Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1506 (103) s tCF2ST1 nCONFIG high to nSTATUS high -- 1506(104) s You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. You can obtain this value if you do not delay configuration by externally holding nSTATUS low. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-82 AV-51002 2016.12.09 PS Configuration Timing Symbol Parameter Minimum Maximum Unit tCF2CK(105) nCONFIG high to first rising edge on DCLK 1506 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency -- 125 MHz tCD2UM CONF_DONE high to user mode(106) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit x CLKUSR period) -- -- Tinit Number of clock cycles required for device initialization 8,576 -- Cycles (105) Related Information PS Configuration Timing Provides the PS configuration timing waveform. (105) (106) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Initialization 1-83 Initialization Table 1-71: Initialization Clock Source Option and the Maximum Frequency for Arria V Devices Initialization Clock Source Internal Oscillator CLKUSR(107) DCLK Configuration Scheme Maximum Frequency (MHz) AS, PS, and FPP 12.5 PS and FPP 125 AS 100 PS and FPP 125 Minimum Number of Clock Cycles Tinit Configuration Files Table 1-72: Uncompressed .rbf Sizes for Arria V Devices Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Quartus Prime software. However, for a specific version of the Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature. (107) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime software from the General panel of the Device and Pin Options dialog box. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-84 AV-51002 2016.12.09 Minimum Configuration Time Estimation Variant Arria V GX Arria V GT Arria V SX Arria V ST Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) A1 71,015,712 439,960 A3 71,015,712 439,960 A5 101,740,800 446,360 A7 101,740,800 446,360 B1 137,785,088 457,368 B3 137,785,088 457,368 B5 185,915,808 463,128 B7 185,915,808 463,128 C3 71,015,712 439,960 C7 101,740,800 446,360 D3 137,785,088 457,368 D7 185,915,808 463,128 B3 185,903,680 450,968 B5 185,903,680 450,968 D3 185,903,680 450,968 D5 185,903,680 450,968 Minimum Configuration Time Estimation Table 1-73: Minimum Configuration Time Estimation for Arria V Devices The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Arria V Devices table. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Minimum Configuration Time Estimation Active Serial(108) Variant Arria V GX Arria V GT Arria V SX Arria V ST 1-85 Fast Passive Parallel(109) Member Code Width DCLK (MHz) Minimum Configura tion Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) A1 4 100 178 16 125 36 A3 4 100 178 16 125 36 A5 4 100 255 16 125 51 A7 4 100 255 16 125 51 B1 4 100 344 16 125 69 B3 4 100 344 16 125 69 B5 4 100 465 16 125 93 B7 4 100 465 16 125 93 C3 4 100 178 16 125 36 C7 4 100 255 16 125 51 D3 4 100 344 16 125 69 D7 4 100 465 16 125 93 B3 4 100 465 16 125 93 B5 4 100 465 16 125 93 D3 4 100 465 16 125 93 D5 4 100 465 16 125 93 Related Information Configuration Files on page 1-83 (108) (109) DCLK frequency of 100 MHz using external CLKUSR. Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-86 AV-51002 2016.12.09 Remote System Upgrades Remote System Upgrades Table 1-74: Remote System Upgrade Circuitry Timing Specifications for Arria V Devices Parameter Minimum Unit tRU_nCONFIG(110) 250 ns tRU_nRSTIMER 250 ns (111) Related Information * Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal. * User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Oscillator Frequency Specifications Table 1-75: User Watchdog Internal Oscillator Frequency Specifications for Arria V Devices Parameter User watchdog internal oscillator frequency Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz I/O Timing Altera offers two ways to determine I/O timing--the Excel-based I/O timing and the Quartus Prime Timing Analyzer. Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. (110) (111) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Programmable IOE Delay 1-87 The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information Arria V I/O Timing Spreadsheet Provides the Arria V Excel-based I/O timing spreadsheet. Programmable IOE Delay Table 1-76: I/O element (IOE) Programmable Delay for Arria V Devices Parameter(112 Fast Model Slow Model Available Settings Minimum Offset(113) Industrial Commercial -C4 -C5 -C6 D1 32 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns D3 8 0 1.763 1.795 2.999 3.496 3.571 3.031 3.643 ns D4 32 0 0.508 0.518 0.869 1.063 1.063 1.063 1.057 ns D5 32 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns ) -I3 Unit -I5 Programmable Output Buffer Delay Table 1-77: Programmable Output Buffer Delay for Arria V Devices This table lists the delay chain settings that control the rising and falling edge delays of the output buffer. You can set the programmable output buffer delay in the Quartus Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. (112) (113) You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor. Minimum offset does not include the intrinsic delay. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-88 AV-51002 2016.12.09 Glossary Symbol DOUTBUF Parameter Rising and/or falling edge delay Typical Unit 0 (default) ps 50 ps 100 ps 150 ps Glossary Table 1-78: Glossary Term Differential I/O standards Definition Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = V IH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Glossary Term 1-89 Definition Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = V OH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK Left/right PLL input clock frequency. fHSDR High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI), non-DPA. fHSDRDPA High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDRDPA =1/TUI), DPA. J High-speed I/O block--Deserialization factor (width of parallel data bus). Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-90 AV-51002 2016.12.09 Glossary Term JTAG timing specifications Definition JTAG Timing Specifications TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX tJPCO t JPXZ TDO Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 1-91 Glossary Term PLL specifications Definition Diagram of PLL specifications CLKOUT Pins Switchover CLK f OUT 4 f IN N _EXT f INPFD PFD CP LF VCO Core Clock fVCO Counters C0..C17 GCLK f OUT RCLK Delta Sigma Modulator Legend Reconfigurable in User Mode External Feedback Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. RL Receiver differential input discrete resistor (external to the Arria V device). Sampling window (SW) Timing diagram--The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS Arria V GX, GT, SX, and ST Device Datasheet Send Feedback RSKM Sampling Window (SW) RSKM 0.5 x TCCS Altera Corporation 1-92 AV-51002 2016.12.09 Glossary Term Single-ended voltage referenced I/O standard Definition The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block--Duty cycle on high-speed transmitter output clock. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Glossary Term Definition tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20-80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/ (Receiver Input Clock Frequency Multiplication Factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage--The common mode of the differential signal at the receiver. VID Input differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage--Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage-- Minimum DC input differential voltage required for switching. VIH Voltage input high--The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low--The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage--The common mode of the differential signal at the transmitter. VOD Output differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage Arria V GX, GT, SX, and ST Device Datasheet Send Feedback 1-93 Altera Corporation 1-94 AV-51002 2016.12.09 Document Revision History Term Definition VOX Output differential cross point voltage W High-speed I/O block--Clock boost factor Document Revision History Date Version December 2016 2016.12.09 Changes * Updated VICM (AC coupled) specifications in Receiver Specifications for Arria V GX and SX Devices table. * Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices table. * Updated Tinit specifications in the following tables: * * * * June 2016 2016.06.10 FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices PS Timing Parameters for Arria V Devices * Changed pin capacitance to maximum values. * Updated SPI Master Timing Requirements for Arria V Devices table. * Added Tsu and Th specifications. * Removed Tdinmax specifications. * Updated SPI Master Timing Diagram. * Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Arria V Devices table. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Document Revision History Date Version December 2015 2015.12.16 1-95 Changes * Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices table. * Updated Fclk, Tdutycycle, and Tdssfrst specifications. * Added Tqspi_clk, Tdin_start, and Tdin_end specifications. * Removed Tdinmax specifications. * Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Arria V Devices table. * Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices table. * Updated T clk to Tsdmmc_clk_out symbol. * Updated Tsdmmc_clk_out and Td specifications. * Added Tsdmmc_clk, Tsu, and Th specifications. * Removed Tdinmax specifications. * Updated the following diagrams: * Quad SPI Flash Timing Diagram * SD/MMC Timing Diagram * Updated configuration .rbf sizes for Arria V devices. * Changed instances of Quartus II to Quartus Prime. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback Altera Corporation 1-96 AV-51002 2016.12.09 Document Revision History Date June 2015 Version 2015.06.16 Changes * Added the supported data rates for the following output standards using true LVDS output buffer types in the High-Speed I/O Specifications for Arria V Devices table: * * * * * * * * True RSDS output standard: data rates of up to 360 Mbps * True mini-LVDS output standard: data rates of up to 400 Mbps Added note in the condition for Transmitter--Emulated Differential I/O Standards fHSDR data rate parameter in the High-Speed I/O Specifications for Arria V Devices table. Note: When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported. Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash. Updated Th location in I2C Timing Diagram. Updared Twp location in NAND Address Latch Timing Diagram. Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices table. Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS x1 and x4 Configu rations in Arria V Devices table. Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. * * * * Altera Corporation FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1 FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1 AS Configuration Timing Waveform PS Configuration Timing Waveform Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Document Revision History Date January 2015 Version 2015.01.30 Changes * Updated the description for VCC_AUX_SHARED to "HPS auxiliary power supply" in the following tables: * * * * * * * * * * * Arria V GX, GT, SX, and ST Device Datasheet Send Feedback 1-97 * Absolute Maximum Ratings for Arria V Devices * HPS Power Supply Operating Conditions for Arria V SX and ST Devices Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated the conditions for transceiver reference clock rise time and fall time: Measure at 60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. Updated HPS Clock Performance main_base_clk specifications from 525 MHz (for -I3 speed grade) and 462 MHz (for -C4 speed grade) to 400 MHz. Updated HPS PLL VCO maximum frequency to 1,600 MHz (for -C5, -I5, and -C6 speed grades), 1,850 MHz (for -C4 speed grade), and 2,100 MHz (for -I3 speed grade). Changed the symbol for HPS PLL input jitter divide value from NR to N. Removed "Slave select pulse width (Texas Instruments SSP mode)" parameter from the following tables: * SPI Master Timing Requirements for Arria V Devices * SPI Slave Timing Requirements for Arria V Devices Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Added HPS JTAG timing specifications. Updated FPGA JTAG timing specifications note as follows: A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Updated the value in the VICM (AC Coupled) row and in note 6 from 650 mV to 750 mV in the Transceiver Specifications for Arria V GT and ST Devices table. Altera Corporation 1-98 AV-51002 2016.12.09 Document Revision History Date Version Changes July 2014 3.8 * Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. * Updated VCC_HPS specification in Table 5. * Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V. * Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20 and Table 21. * Updated description in "HPS PLL Specifications" section. * Updated VCO range maximum specification in Table 39. * Updated Td and Th specifications in Table 45. * Added Th specification in Table 47 and Figure 13. * Updated a note in Figure 20, Figure 21, and Figure 23 as follows: Do not leave DCLK floating after configura tion. DCLK is ignored after configuration is complete. It can toggle high or low if required. * Removed "Remote update only in AS mode" specification in Table 58. * Added DCLK device initialization clock source specification in Table 60. * Added description in "Configuration Files" section: The IOCSR .rbf size is specifically for the Configura tion via Protocol (CvP) feature. * Removed fMAX_RU_CLK specification in Table 63. February 2014 3.7 * Updated VCCRSTCLK_HPS maximum specification in Table 1. * Added VCC_AUX_SHARED specification in Table 1. December 2013 3.6 * Added "HPS PLL Specifications". * Added Table 24, Table 39, and Table 40. * Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, Table 51, Table 55, Table 56, and Table 59. * Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19. * Removed table: GPIO Pulse Width for Arria V Devices. Altera Corporation Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Document Revision History Date Version Changes August 2013 3.5 * Removed "Pending silicon characterization" note in Table 29. * Updated Table 25. August 2013 3.4 * Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 30, Table 31, Table 35, Table 36, Table 51, Table 53, Table 54, Table 55, Table 56, Table 57, Table 60, Table 62, and Table 64. * Updated Table 1, Table 3, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, and Table 29. June 2013 3.3 Updated Table 20, Table 21, Table 25, and Table 38. May 2013 3.2 * Added Table 37. * Updated Figure 8, Figure 9, Figure 20, Figure 22, and Figure 23. * Updated Table 1, Table 5, Table 10, Table 13, Table 19, Table 20, Table 21, Table 23, Table 29, Table 39, Table 40, Table 46, Table 56, Table 57, Table 60, and Table 64. * Updated industrial junction temperature range for -I3 speed grade in "PLL Specifications" section. March 2013 3.1 * * * * Arria V GX, GT, SX, and ST Device Datasheet Send Feedback 1-99 Added HPS reset information in the "HPS Specifications" section. Added Table 60. Updated Table 1, Table 3, Table 17, Table 20, Table 29, and Table 59. Updated Figure 21. Altera Corporation 1-100 AV-51002 2016.12.09 Document Revision History Date Version November 2012 3.0 Changes * Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21, Table 25, Table 29, Table 36, Table 56, Table 57, and Table 60. * Removed table: Transceiver Block Jitter Specifications for Arria V Devices. * Added HPS information: * Added "HPS Specifications" section. * Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, and Table 50. * Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, and Figure 19. * Updated Table 3 and Table 5. October 2012 2.4 * Updated Arria V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum values, and data rate in Table 4. * Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM (AC coupled) and VOCM (DC coupled) values in Table 20 and Table 21. August 2012 2.3 Updated the SERDES factor condition in Table 30. July 2012 2.2 * * * * * June 2012 2.1 Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4. Altera Corporation Updated the maximum voltage for VI (DC input voltage) in Table 1. Updated Table 20 to include the Arria V GX -I3 speed grade. Updated the minimum value of the fixedclk clock frequency in Table 20 and Table 21. Updated the SERDES factor condition in Table 30. Updated Table 50 to include the IOE programmable delay settings for the Arria V GX -I3 speed grade. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback AV-51002 2016.12.09 Document Revision History Date Version Changes June 2012 2.0 * * * * * * * February 2012 1.3 * Updated Table 2-1. * Updated Transceiver-FPGA Fabric Interface rows in Table 2-20. * Updated VCCP description. December 2011 1.2 Updated Table 2-1 and Table 2-3. November 2011 1.1 * Updated Table 2-1, Table 2-19, Table 2-26, and Table 2-36. * Added Table 2-5. * Added Figure 2-4. August 2011 1.0 Initial release. Arria V GX, GT, SX, and ST Device Datasheet Send Feedback 1-101 Updated for the Quartus II software v12.0 release: Restructured document. Updated "Supply Current and Power Consumption" section. Updated Table 20, Table 21, Table 24, Table 25, Table 26, Table 35, Table 39, Table 43, and Table 52. Added Table 22, Table 23, and Table 33. Added Figure 1-1 and Figure 1-2. Added "Initialization" and "Configuration Files" sections. Altera Corporation Arria V GZ Device Datasheet 2 2016.12.09 AV-51002 Subscribe Send Feedback This document covers the electrical and switching characteristics for Arria V GZ devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This document also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. Related Information Arria V Device Overview For information regarding the densities and packages of devices in the Arria V GZ family. Electrical Characteristics Operating Conditions When you use Arria V GZ devices, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria V GZ devices, you must consider the operating requirements described in this datasheet. Arria V GZ devices are offered in commercial and industrial temperature grades. Commercial devices are offered in -3 (fastest) and -4 core speed grades. Industrial devices are offered in -3L and -4 core speed grades. Arria V GZ devices are offered in -2 and -3 transceiver speed grades. Table 2-1: Commercial and Industrial Speed Grade Offering for Arria V GZ Devices C = Commercial temperature grade; I = Industrial temperature grade. (c) 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2-2 AV-51002 2016.12.09 Absolute Maximum Ratings Lower number refers to faster speed grade. L = Low power devices. Core Speed Grade Transceiver Speed Grade C3 C4 I3L I4 2 Yes -- Yes -- 3 -- Yes -- Yes Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Arria V GZ devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions other than those listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 2-2: Absolute Maximum Ratings for Arria V GZ Devices Symbol Description Minimum Maximum Unit VCC Power supply for core voltage and periphery circuitry -0.5 1.35 V VCCPT Power supply for programmable power technology -0.5 1.8 V VCCPGM Power supply for configuration pins -0.5 3.9 V VCC_AUX Auxiliary supply for the programmable power technology -0.5 3.4 V VCCBAT Battery back-up power supply for design security volatile key register -0.5 3.9 V VCCPD I/O pre-driver power supply -0.5 3.9 V VCCIO I/O power supply -0.5 3.9 V VCCD_FPLL PLL digital power supply -0.5 1.8 V VCCA_FPLL PLL analog power supply -0.5 3.4 V Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Maximum Allowed Overshoot and Undershoot Voltage Symbol Description Minimum Maximum Unit VI DC input voltage -0.5 3.8 V TJ Operating junction temperature -55 125 C TSTG Storage temperature (No bias) -65 150 C IOUT DC output current per pin -25 40 mA 2-3 Table 2-3: Transceiver Power Supply Absolute Conditions for Arria V GZ Devices Symbol Description Minimum Maximum Unit VCCA_GXBL Transceiver channel PLL power supply (left side) -0.5 3.75 V VCCA_GXBR Transceiver channel PLL power supply (right side) -0.5 3.75 V VCCHIP_L Transceiver hard IP power supply (left side) -0.5 1.35 V VCCHSSI_L Transceiver PCS power supply (left side) -0.5 1.35 V VCCHSSI_R Transceiver PCS power supply (right side) -0.5 1.35 V VCCR_GXBL Receiver analog power supply (left side) -0.5 1.35 V VCCR_GXBR Receiver analog power supply (right side) -0.5 1.35 V VCCT_GXBL Transmitter analog power supply (left side) -0.5 1.35 V VCCT_GXBR Transmitter analog power supply (right side) -0.5 1.35 V VCCH_GXBL Transmitter output buffer power supply (left side) -0.5 1.8 V VCCH_GXBR Transmitter output buffer power supply (right side) -0.5 1.8 V Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in the following table. They may also undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-4 AV-51002 2016.12.09 Recommended Operating Conditions The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% of the duty cycle. For example, a signal that overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for a device lifetime of 10 years, the overshoot duration amounts to ~2 years. Table 2-4: Maximum Allowed Overshoot During Transitions for Arria V GZ Devices Symbol Vi (AC) Description AC input voltage Condition (V) Overshoot Duration as % @ TJ = 100C Unit 3.8 100 % 3.85 64 % 3.9 36 % 3.95 21 % 4 12 % 4.05 7 % 4.1 4 % 4.15 2 % 4.2 1 % Recommended Operating Conditions Table 2-5: Recommended Operating Conditions for Arria V GZ Devices Power supply ramps must all be strictly monotonic, without plateaus. Symbol VCC (114) (115) Description Condition Minimum(114) Typical Maximum (114) Unit Core voltage and periphery circuitry power supply (115) -- 0.82 0.85 0.88 V The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. The VCC core supply must be set to 0.9 V if the Partial Reconfiguration (PR) feature is used. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-5 Recommended Operating Conditions Symbol Description Condition Minimum(114) Typical Maximum (114) Unit VCCPT Power supply for programmable power technology -- 1.45 1.50 1.55 V VCC_AUX Auxiliary supply for the programmable power technology -- 2.375 2.5 2.625 V -- 2.85 3.0 3.15 V -- 2.375 2.5 2.625 V I/O buffers (3.0 V) power supply -- 2.85 3.0 3.15 V I/O buffers (2.5 V) power supply -- 2.375 2.5 2.625 V I/O buffers (1.8 V) power supply -- 1.71 1.8 1.89 V I/O buffers (1.5 V) power supply -- 1.425 1.5 1.575 V I/O buffers (1.35 V) power supply -- 1.283 1.35 1.45 V I/O buffers (1.25 V) power supply -- 1.19 1.25 1.31 V I/O buffers (1.2 V) power supply -- 1.14 1.2 1.26 V Configuration pins (3.0 V) power supply -- 2.85 3.0 3.15 V Configuration pins (2.5 V) power supply -- 2.375 2.5 2.625 V Configuration pins (1.8 V) power supply -- 1.71 1.8 1.89 V PLL analog voltage regulator power supply -- 2.375 2.5 2.625 V PLL digital voltage regulator power supply -- 1.45 1.5 1.55 V -- 1.2 -- 3.0 V VCCPD (116 I/O pre-driver (3.0 V) power supply ) I/O pre-driver (2.5 V) power supply VCCIO VCCPGM VCCA_ FPLL VCCD_ FPLL VCCBAT (117) Battery back-up power supply (For design security volatile key register) (114) (116) (117) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. If you do not use the design security feature in Arria V GZ devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Arria V GZ power-on-reset (POR) circuitry monitors VCCBAT. Arria V GZ devices do not exit POR if VCCBAT is not powered up. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-6 AV-51002 2016.12.09 Recommended Transceiver Power Supply Operating Conditions Symbol Description Condition Minimum(114) Typical Maximum (114) Unit VI DC input voltage -- -0.5 -- 3.6 V VO Output voltage -- 0 -- VCCIO V TJ Operating junction temperature Commercial 0 -- 85 C Industrial -40 -- 100 C tRAMP Power supply ramp time Standard POR 200 s -- 100 ms -- Fast POR 200 s -- 4 ms -- Minimum (118) Typical Maximum(118) Unit 2.85 3.0 3.15 2.375 2.5 2.625 2.85 3.0 3.15 2.375 2.5 2.625 Recommended Transceiver Power Supply Operating Conditions Table 2-6: Recommended Transceiver Power Supply Operating Conditions for Arria V GZ Devices Symbol VCCA_GXBL (119) (120) , VCCA_ GXBR (114) (118) (119) (120) , (119) (120) Description Transceiver channel PLL power supply (left side) Transceiver channel PLL power supply (right side) V V VCCHIP_L Transceiver hard IP power supply (left side) 0.82 0.85 0.88 V VCCHSSI_L Transceiver PCS power supply (left side) 0.82 0.85 0.88 V VCCHSSI_R Transceiver PCS power supply (right side) 0.82 0.85 0.88 V The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps, you can connect this supply to either 3.0 V or 2.5 V. When using ATX PLLs, the supply must be 3.0 V. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Symbol VCCR_GXBL (121) VCCR_GXBR (121) VCCT_GXBL (121) VCCT_GXBR (121) (118) (121) 2-7 Recommended Transceiver Power Supply Operating Conditions Description Receiver analog power supply (left side) Receiver analog power supply (right side) Transmitter analog power supply (left side) Transmitter analog power supply (right side) Minimum (118) Typical Maximum(118) 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 Unit V V V V VCCH_GXBL Transmitter output buffer power supply (left side) 1.425 1.5 1.575 V VCCH_GXBR Transmitter output buffer power supply (right side) 1.425 1.5 1.575 V This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate > 10.3 Gbps when DFE is used. For data rate up to 6.5 Gbps, you can connect this supply to 0.85 V. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-8 AV-51002 2016.12.09 Transceiver Power Supply Requirements Transceiver Power Supply Requirements Table 2-7: Transceiver Power Supply Voltage Requirements for Arria V GZ Devices Conditions If BOTH of the following conditions are true: VCCR_GXB and VCCT_GXB (122) VCCA_GXB VCCH_GXB Unit 1.5 V 1.05 * Data rate > 10.3 Gbps. * DFE is used. If ANY of the following conditions are true (123) : 1.0 3.0 * ATX PLL is used. * Data rate > 6.5Gbps. * DFE (data rate 10.3 Gbps), AEQ, or EyeQ feature is used. If ALL of the following conditions are true: 0.85 2.5 * ATX PLL is not used. * Data rate 6.5Gbps. * DFE, AEQ, and EyeQ are not used. DC Characteristics Supply Current Standby current is the current drawn from the respective power rails used for power budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design because these currents vary greatly with the resources you use. (122) (123) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and VCCT_GXB are set to 0.85 V, they can be shared with the VCC core supply. Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Power Consumption 2-9 Related Information * PowerPlay Early Power Estimator User Guide For more information about the EPE tool. * PowerPlay Power Analysis For more information about PowerPlay power analysis. Power Consumption Altera offers two ways to estimate power consumption for a design--the Excel-based Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature. Note: You typically use the interactive Excel-based Early Power Estimator before designing the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information * PowerPlay Early Power Estimator User Guide For more information about the EPE tool. * PowerPlay Power Analysis For more information about PowerPlay power analysis. I/O Pin Leakage Current Table 2-8: I/O Pin Leakage Current for Arria V GZ Devices If VO = VCCIO to VCCIOMax, 100 A of leakage current per I/O is expected. Symbol Description Conditions Min Typ Max Unit II Input pin VI = 0 V to VCCIOMAX -30 -- 30 A IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX -30 -- 30 A Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-10 AV-51002 2016.12.09 Bus Hold Specifications Bus Hold Specifications Table 2-9: Bus Hold Parameters for Arria V GZ Devices VCCIO Parameter Symbol Conditions VIN > VIL 1.2 V 1.5 V 1.8 V 2.5 V 3.0 V Unit Min Max Min Max Min Max Min Max Min Max 22.5 -- 25.0 -- 30.0 -- 50.0 -- 70.0 -- A -22.5 -- -25.0 -- -30.0 -- -50.0 -- -70.0 -- A Low sustaining current ISUSL High sustaining current ISUSH Low overdrive current IODL 0V < VIN < VCCIO -- 120 -- 160 -- 200 -- 300 -- 500 A High overdrive current IODH 0V < VIN < VCCIO -- -120 -- -160 -- -200 -- -300 -- -500 A Bus-hold trip point VTRIP -- 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V (maximum) VIN < VIH (minimum) On-Chip Termination (OCT) Specifications If you enable OCT calibration, calibration is automatically performed at power-up for I/Os connected to the calibration block. Table 2-10: OCT Calibration Accuracy Specifications for Arria V GZ Devices OCT calibration accuracy is valid at the time of calibration only. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-11 On-Chip Termination (OCT) Specifications Symbol Description Conditions Calibration Accuracy C3, I3L C4, I4 Unit 25- RS Internal series termination with calibration (25- setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V 15 15 % 50- RS Internal series termination with calibration (50- setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V 15 15 % 34- and 40- RS Internal series termination with calibration (34- and 40- setting) VCCIO = 1.5, 1.35, 1.25, 1.2 V 15 15 % 48-, 60-, 80-, and 240- RS Internal series termination with calibration (48-, 60-, 80-, and 240- setting) VCCIO = 1.2 V 15 15 % 50- RT Internal parallel termination with calibration (50- setting) VCCIO = 2.5, 1.8, 1.5, 1.2 V -10 to +40 -10 to +40 % 20-, 30-, 40-, 60-, and 120- RT Internal parallel termination with calibration (20- , 30-, 40-, 60-, and 120- setting) VCCIO = 1.5, 1.35, 1.25 V -10 to +40 -10 to +40 % 60- and 120- RT Internal parallel termination with calibration (60- and 120- setting) VCCIO = 1.2 -10 to +40 -10 to +40 % 25- RS_left_shift Internal left shift series termination with calibration (25- RS_left_shift setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V 15 15 % Table 2-11: OCT Without Calibration Resistance Tolerance Specifications for Arria V GZ Devices Symbol 25- R, 50- RS Arria V GZ Device Datasheet Send Feedback Description Internal series termination without calibration (25- setting) Conditions VCCIO = 3.0 and 2.5 V Resistance Tolerance C3, I3L C4, I4 40 40 Unit % Altera Corporation 2-12 AV-51002 2016.12.09 On-Chip Termination (OCT) Specifications Symbol Description Conditions Resistance Tolerance C3, I3L C4, I4 Unit 25- RS Internal series termination without calibration (25- setting) VCCIO = 1.8 and 1.5 V 40 40 % 25- RS Internal series termination without calibration (25- setting) VCCIO = 1.2 V 50 50 % 50- RS Internal series termination without calibration (50- setting) VCCIO = 1.8 and 1.5 V 40 40 % 50- RS Internal series termination without calibration (50- setting) VCCIO = 1.2 V 50 50 % 100- RD Internal differential termination (100- setting) VCCIO = 2.5 V 25 25 % Figure 2-1: OCT Variation Without Re-Calibration for Arria V GZ Devices ( ROCT = RSCAL 1 + ( dR x dT T ) ( dR x dV V) ( Notes: 1. The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO. 2. RSCAL is the OCT resistance value at power-up. 3. T is the variation of temperature with respect to the temperature at power-up. 4. V is the variation of voltage with respect to the VCCIO at power-up. 5. dR/dT is the percentage change of RSCAL with temperature. 6. dR/dV is the percentage change of RSCAL with voltage. Table 2-12: OCT Variation after Power-Up Calibration for Arria V GZ Devices Valid for a VCCIO range of 5% and a temperature range of 0 to 85C. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Pin Capacitance Symbol dR/dV Description OCT variation with voltage without re-calibration dR/dT OCT variation with temperature without re-calibration VCCIO (V) Typical 3.0 0.0297 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 3.0 0.189 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 2-13 Unit %/mV %/C Pin Capacitance Table 2-13: Pin Capacitance for Arria V GZ Devices Symbol Description Maximum Unit CIOTB Input capacitance on the top and bottom I/O pins 6 pF CIOLR Input capacitance on the left and right I/O pins 6 pF COUTFB Input capacitance on dual-purpose clock output and feedback pins 6 pF Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-14 AV-51002 2016.12.09 Hot Socketing Hot Socketing Table 2-14: Hot Socketing Specifications for Arria V GZ Devices Symbol Description Maximum IIOPIN (DC) DC current per I/O pin 300 A IIOPIN (AC) AC current per I/O pin 8 mA (124) IXCVR-TX (DC) DC current per transceiver transmitter pin 100 mA IXCVR-RX (DC) DC current per transceiver receiver pin 50 mA Internal Weak Pull-Up Resistor Table 2-15: Internal Weak Pull-Up Resistor for Arria V GZ Devices All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins. The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is approximately 25 k . Symbol RPU (124) (125) (126) Value (126) Unit 3.0 5% 25 k 2.5 5% 25 k Value of the I/O pin pull-up resistor 1.8 5% before and during configuration, as well as 1.5 5% user mode if you enable the 1.35 5% programmable pull-up resistor option. 25 k 25 k 25 k 1.25 5% 25 k 1.2 5% 25 k Description VCCIO Conditions (V) (125) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. These specifications are valid with a 10% tolerance to cover changes over PVT. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-15 I/O Standard Specifications I/O Standard Specifications The VOL and VOH values are valid at the corresponding IOH and IOL, respectively. Table 2-16: Single-Ended I/O Standards for Arria V GZ Devices VCCIO (V) I/O Standard VIL (V) VIH (V) VOL (V) VOH (V) IOL (mA) IOH (mA) 2.4 2 -2 0.2 VCCIO - 0.2 0.1 -0.1 3.6 0.4 2 1 -1 0.65 x VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2 -2 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 Min Typ Max Min Max Min Max Max Min LVTTL 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 LVCMOS 2.85 3 3.15 -0.3 0.8 1.7 3.6 2.5 V 2.375 2.5 2.625 -0.3 0.7 1.7 1.8 V 1.71 1.8 1.89 -0.3 0.35 x VCCIO 1.5 V 1.425 1.5 1.575 -0.3 1.2 V 1.14 1.2 1.26 -0.3 Table 2-17: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V GZ Devices I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO VREF - 0.04 VREF VREF + 0.04 SSTL-18 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF - 0.04 VREF VREF + 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-16 AV-51002 2016.12.09 I/O Standard Specifications I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-135 Class I, II 1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-125 Class I, II 1.19 1.25 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-12 Class I, II 1.14 1.20 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VCCIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VCCIO/2 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO -- VCCIO/2 -- HSUL-12 1.14 1.2 1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO -- -- -- Table 2-18: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V GZ Devices I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) Iol (mA) Ioh (mA) VTT + 0.608 8.1 -8.1 VTT - 0.81 VTT + 0.81 16.2 -16.2 VTT - 0.603 VTT + 0.603 6.7 -6.7 Min Max Min Max Max Min Max Min SSTL-2 Class I -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 VTT - 0.608 SSTL-2 Class II -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 SSTL-18 Class I -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-17 I/O Standard Specifications I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) Iol (mA) Ioh (mA) VCCIO - 0.28 13.4 -13.4 0.2 x VCCIO 0.8 x VCCIO 8 -8 0.2 x VCCIO 0.8 x VCCIO 16 -16 0.2 * VCCIO 0.8 * VCCIO -- -- VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO -- -- VREF - 0.15 VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO -- -- -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-12 Class I -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 8 -8 HSTL-12 Class II -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 16 -16 HSUL-12 -- VREF - 0.13 VREF + 0.13 -- VREF - 0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO -- -- Min Max Min Max Max Min Max Min SSTL-18 Class II -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 SSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 SSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 SSTL-135 Class I, II -- VREF - 0.09 VREF + 0.09 -- VREF - 0.16 VREF + 0.16 SSTL-125 Class I, II -- VREF - 0.85 VREF + 0.85 -- VREF - 0.15 SSTL-12 Class I, II -- VREF - 0.1 VREF + 0.1 -- HSTL-18 Class I -- VREF - 0.1 VREF + 0.1 HSTL-18 Class II -- VREF - 0.1 HSTL-15 Class I -- HSTL-15 Class II Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-18 AV-51002 2016.12.09 I/O Standard Specifications Table 2-19: Differential SSTL I/O Standards for Arria V GZ Devices I/O Standard VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V) Min Typ Max Min Max Min Typ Max Min Max SSTL-2 Class I, II 2.375 2.5 2.625 0.3 VCCIO + 0.6 VCCIO/2 - 0.2 -- VCCIO/2 + 0.2 0.62 VCCIO + 0.6 SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 VCCIO/2 - 0.175 -- VCCIO/2 + 0.175 0.5 VCCIO + 0.6 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 (127) VCCIO/2 - 0.15 -- VCCIO/2 + 0.15 0.35 -- SSTL-135 Class I, II 1.283 1.35 1.45 0.2 (127) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) SSTL-125 Class I, II 1.19 1.25 1.31 0.18 (127) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) - VREF) -- SSTL-12 Class I, II 1.14 1.2 1.26 0.18 -- VREF -0.15 VCCIO/2 VREF + 0.15 -0.30 0.30 Table 2-20: Differential HSTL and HSUL I/O Standards for Arria V GZ Devices I/O Standard (127) VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-18 Class I, II 1.71 1.8 1.89 0.2 -- 0.78 -- 1.12 0.78 -- 1.12 0.4 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- 0.68 -- 0.9 0.68 -- 0.9 0.4 -- The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)). Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-19 I/O Standard Specifications VCCIO (V) I/O Standard HSTL-12 Class I, II VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) Min Typ Max Min Max Min Typ Max Min Typ 1.14 1.2 1.26 0.16 VCCIO + 0.3 -- 0.5 x VCCIO -- 0.4 x VCCIO VDIF(AC) (V) Max 0.5 0.6 x x VCCIO VCC Min Max 0.3 VCCIO + 0.48 0.44 0.44 IO HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 x VCCIO - 0.12 0.5 x VCCIO 0.5 x VCCIO + 0.12 0.4 x VCCIO 0.5 0.6 x x VCCIO VCC IO Table 2-21: Differential I/O Standard Specifications for Arria V GZ Devices VCCIO (V) (128) I/O Standard PCML Min (130) (131) (132) Min 2.5 V LVDS 2.375 2.5 2.625 100 BLVDS 2.375 2.5 2.625 100 (132) (129) Max Condition VOD (V) (130) VICM(DC) (V) Max Min Condition Max Min Typ VOCM (V) (130) Max Min Typ Max Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to the "Transceiver Performance Specifications" section. (131) (128) Typ VID (mV) (129) -- 0.05 1.8 0.247 -- 0.6 1.125 1.25 1.375 VCM = 1.25 V DMAX 700 Mbps -- 1.05 DMAX > 700 Mbps 1.55 0.247 -- 0.6 1.125 1.25 1.375 -- -- -- -- -- -- -- -- -- -- -- Differential inputs are powered by VCCPD which requires 2.5 V. The minimum VID value is applicable over the entire common mode range, VCM. RL range: 90 RL 110 . For optimized LVDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85 V for data rates below 700 Mbps. There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-20 AV-51002 2016.12.09 I/O Standard Specifications I/O Standard VCCIO (V) (128) VID (mV) (129) VOD (V) (130) VICM(DC) (V) VOCM (V) (130) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max RSDS (HIO) 2.375 2.5 2.625 100 VCM = 1.25 V -- 0.3 -- 1.4 0.1 0.2 0.6 0.5 1.2 1.4 MiniLVDS (HIO) 2.375 2.5 2.625 200 -- 600 0.4 -- 1.325 0.25 -- 0.6 1 1.2 1.4 -- -- -- 300 -- -- 0.6 DMAX 700 Mbps 1.8 -- -- -- -- -- -- -- -- -- 300 -- -- 1 DMAX > 700 Mbps 1.6 -- -- -- -- -- -- (133) (134) LVPECL (135) (136) , Related Information Glossary on page 2-73 (128) (129) (130) (133) (134) (135) (136) Differential inputs are powered by VCCPD which requires 2.5 V. The minimum VID value is applicable over the entire common mode range, VCM. RL range: 90 RL 110 . For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V. For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V. LVPECL is only supported on dedicated clock input pins. For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Switching Characteristics 2-21 Switching Characteristics Transceiver Performance Specifications Reference Clock Table 2-22: Reference Clock Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions Transceiver Speed Grade 2 Min Typ Max Transceiver Speed Grade 3 Min Typ Max Unit Reference Clock Supported I/O Standards Dedicated reference clock 1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, pin and HCSL RX reference clock pin (137) 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Input Reference Clock Frequency (CMU PLL) (137) -- 40 -- 710 40 -- 710 MHz Input Reference Clock Frequency (ATX PLL)(137) -- 100 -- 710 100 -- 710 MHz The input reference clock frequency options depend on the data rate and the device speed grade. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-22 AV-51002 2016.12.09 Reference Clock Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Rise time Measure at 60 mV of differential signal (138) -- -- 400 -- -- 400 Fall time Measure at 60 mV of differential signal (138) -- -- 400 -- -- 400 Duty cycle -- 45 -- 55 45 -- 55 % Spread-spectrum modulating clock frequency PCI Express (R)(PCIe) 30 -- 33 30 -- 33 kHz Spread-spectrum downspread PCIe -- 0 to -- -- 0 to -- % -0.5 -- -- 100 -- -- 100 -- -- -- 1.6 -- -- 1.6 Absolute VMAX Dedicated reference clock pin RX reference clock pin -- -- 1.2 -- -- 1.2 V Absolute VMIN -- -0.4 -- -- -0.4 -- -- V Peak-to-peak differential input voltage -- 200 -- 1600 200 -- 1600 mV Dedicated reference clock pin RX reference clock pin VICM (DC coupled) (139) (140) ps -0.5 On-chip termination resistors VICM (AC coupled) (138) Unit HCSL I/O standard for PCIe reference clock 250 1000/900/850 (139) 1000/900/850 (139) mV 1.0/0.9/0.85 (140) 1.0/0.9/0.85(140) mV -- 550 250 -- 550 mV REFCLK performance requires to meet transmitter REFCLK phase noise specification. The reference clock common mode voltage is equal to the VCCR_GXB power supply level. This supply follows VCCR_GXB Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Transceiver Clocks Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max 100 Hz -- -- -70 -- -- -70 dBc/Hz 1 kHz -- -- -90 -- -- -90 dBc/Hz 10 kHz -- -- -100 -- -- -100 dBc/Hz 100 kHz -- -- -110 -- -- -110 dBc/Hz 1 MHz -- -- -120 -- -- -120 dBc/Hz Transmitter REFCLK Phase Jitter (100 MHz) (142) 10 kHz to 1.5 MHz (PCIe) -- -- 3 -- -- 3 ps (rms) RREF -- -- 1800 1% -- -- 1800 1% -- Transmitter REFCLK Phase Noise (622 MHz) (141) 2-23 Related Information Arria V Device Overview For more information about device ordering codes. Transceiver Clocks Table 2-23: Transceiver Clocks Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. (141) (142) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622). To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz x 100/f. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-24 AV-51002 2016.12.09 Receiver Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit fixedclk clock frequency PCIe Receiver Detect -- 100 or 125 -- -- 100 or 125 -- MHz Reconfiguration clock (mgmt_clk_ -- 100 -- 125 100 -- 125 MHz clk) frequency Related Information Arria V Device Overview For more information about device ordering codes. Receiver Table 2-24: Receiver Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Supported I/O Standards (143) (144) (145) Conditions Transceiver Speed Grade 2 Min Typ Max Transceiver Speed Grade 3 Min Typ Max Unit 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Data rate (Standard PCS) (143), (144) -- 600 -- 9900 600 -- 8800 Mbps Data rate (10G PCS) (143), (144) -- 600 -- 12500 600 -- 10312.5 Mbps Absolute VMAX for a receiver pin (145) -- -- -- 1.2 -- -- 1.2 V Absolute VMIN for a receiver pin -- -0.4 -- -- -0.4 -- -- V The line data rate may be limited by PCS-FPGA interface speed grade. To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. The device cannot tolerate prolonged operation at this absolute maximum. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Symbol/Description Conditions Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration (146) Minimum differential eye opening at receiver serial input pins (147)(148) Differential on-chip termination resistors (146) (147) (148) 2-25 Receiver Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max -- -- -- 1.6 -- -- 1.6 V VCCR_GXB = 1.0 V (VICM = 0.75 V) -- -- 1.8 -- -- 1.8 V VCCR_GXB = 0.85 V (VICM = 0.6 V) -- -- 2.4 -- -- 2.4 V -- 85 -- -- 85 -- -- mV 85- setting -- 85 30% -- -- 85 30% -- 100- setting -- 100 30% -- -- 100 30% -- 120- setting -- 120 30% -- -- 120 30% -- 150- setting -- 150 30% -- -- 150 30% -- The maximum peak to peak differential input voltage VID after device configuration is equal to 4 x (absolute VMAX for receiver pin - VICM). The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Minimum eye opening of 85 mV is only for the unstressed input eye condition. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-26 Symbol/Description (151) (152) Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Typ Max Min Typ Max VCCR_GXB = 0.85 V full bandwidth -- 600 -- -- 600 -- mV VCCR_GXB = 0.85 V half bandwidth -- 600 -- -- 600 -- mV VCCR_GXB = 1.0 V full bandwidth -- 700 -- -- 700 -- mV VCCR_GXB = 1.0 V half bandwidth -- 700 -- -- 700 -- mV tLTR (149) -- -- -- 10 -- -- 10 s tLTD (150) -- 4 -- -- 4 -- -- s tLTD_manual (151) -- 4 -- -- 4 -- -- s tLTR_LTD_manual (152) -- 15 -- -- 15 -- -- s Full bandwidth (6.25 GHz) -- -- 16 -- -- 16 dB Programmable equalization (AC Gain) (150) Conditions Min VICM (AC and DC coupled) (149) AV-51002 2016.12.09 Receiver Half bandwidth (3.125 GHz) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-27 Transmitter Symbol/Description Programmable DC gain Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max DC gain setting = 0 -- 0 -- -- 0 -- dB DC gain setting = 1 -- 2 -- -- 2 -- dB DC gain setting = 2 -- 4 -- -- 4 -- dB DC gain setting = 3 -- 6 -- -- 6 -- dB DC gain setting = 4 -- 8 -- -- 8 -- dB Related Information Arria V Device Overview For more information about device ordering codes. Transmitter Table 2-25: Transmitter Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Supported I/O Standards Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit 1.4-V and 1.5-V PCML Data rate (Standard PCS) -- 600 -- 9900 600 -- 8800 Mbps Data rate (10G PCS) -- 600 -- 12500 600 -- 10312.5 Mbps Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-28 AV-51002 2016.12.09 Transmitter Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max 85- setting -- 85 20% -- -- 85 20% -- 100- setting -- 100 20% -- -- 100 20% -- 120- setting -- 120 20% -- -- 120 20% -- 150- setting -- 150 20% -- -- 150 20% -- VOCM (AC coupled) 0.65-V setting -- 650 -- -- 650 -- mV VOCM (DC coupled) -- -- 650 -- -- 650 -- mV Tx VCM = 0.5 V and slew rate of 15 ps -- -- 15 -- -- 15 ps Intra-transceiver block transmitter channel-to-channel skew x6 PMA bonded mode -- -- 120 -- -- 120 ps Inter-transceiver block transmitter channel-to-channel skew xN PMA bonded mode -- -- 500 -- -- 500 ps Differential on-chip termination resistors Intra-differential pair skew Related Information Arria V Device Overview For more information about device ordering codes. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-29 CMU PLL CMU PLL Table 2-26: CMU PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit Supported data range -- 600 -- 12500 600 -- 10312.5 Mbps tpll_powerdown (153) -- 1 -- -- 1 -- -- s tpll_lock(154) -- -- 10 -- -- 10 s Related Information Arria V Device Overview For more information about device ordering codes. ATX PLL Table 2-27: ATX PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. (153) (154) tpll_powerdown is the PLL powerdown minimum pulse width. tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-30 AV-51002 2016.12.09 Fractional PLL Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max VCO post-divider L=2 8000 -- 12500 8000 -- 10312.5 Mbps L=4 4000 -- 6600 4000 -- 6600 Mbps L = 8 (155) 2000 -- 3300 2000 -- 3300 Mbps tpll_powerdown (156) -- 1 -- -- 1 -- -- s tpll_lock (157) -- -- -- 10 -- -- 10 s Supported data rate range Related Information * Arria V Device Overview For more information about device ordering codes. * Transceiver Clocking in Arria V Devices For more information about clocking ATX PLLs. * Dynamic Reconfiguration in Arria V Devices For more information about reconfiguring ATX PLLs. Fractional PLL Table 2-28: Fractional PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. (155) (156) (157) This clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more information about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconfiguration in Arria V Devices chapter. tpll_powerdown is the PLL powerdown minimum pulse width. tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-31 Clock Network Data Rate Symbol/Description Transceiver Speed Grade 2 Conditions Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit Supported data range -- 600 -- 3250/ 3125(158) 600 -- 3250/ 3125 (158) Mbps tpll_powerdown(159) -- 1 -- -- 1 -- -- s tpll_lock (160) -- -- -- 10 -- 10 s Related Information Arria V Device Overview For more information about device ordering codes. Clock Network Data Rate Table 2-29: Clock Network Maximum Data Rate Transmitter Specifications Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the MegaWizard message during the PHY IP instantiation. CMU PLL (161) ATX PLL Clock Network (158) (159) (160) (161) (162) (163) Non-bonded Bonded Mode (Gbps) Mode (Gbps) Channel Span fPLL Non-bonded Bonded Mode (Gbps) Mode (Gbps) Channel Span Non-bonded Bonded Mode (Gbps) Mode (Gbps) Channel Span x1 (162) 12.5 -- 6 12.5 -- 6 3.125 -- 3 x6 (162) -- 12.5 6 -- 12.5 6 -- 3.125 6 x6 PLL Feedback (163) -- 12.5 Side-wide -- 12.5 Side-wide -- -- -- When you use fPLL as a TXPLL of the transceiver. tpll_powerdown is the PLL powerdown minimum pulse width. tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance. Channel span is within a transceiver bank. Side-wide channel bonding is allowed up to the maximum supported by the PHY IP. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-32 AV-51002 2016.12.09 Standard PCS Data Rate CMU PLL (161) ATX PLL Clock Network Non-bonded Bonded Mode (Gbps) Mode (Gbps) xN (PCIe) -- 8.0 8 8.0 8.0 Up to 13 channels above and below PLL -- xN (Native PHY IP) Channel Span 8.01 to 9.8304 Non-bonded Bonded Mode (Gbps) Mode (Gbps) -- Up to 7 channels above and below PLL fPLL 7.99 Channel Span 5.0 8 7.99 Up to 13 channels above and below PLL Non-bonded Bonded Mode (Gbps) Mode (Gbps) -- 3.125 Channel Span -- -- 3.125 Up to 13 channels above and below PLL Standard PCS Data Rate Table 2-30: Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices The maximum data rate is also constrained by the transceiver speed grade. Refer to the "Commercial and Industrial Speed Grade Offering for Arria V GZ Devices" table for the transceiver speed grade. Mode (164) FIFO (161) (164) PMA Width 20 20 16 16 10 10 8 8 PCS/Core Width 40 20 32 16 20 10 16 8 2 C3, I3L core speed grade 9.9 9 7.84 7.2 5.3 4.7 4.24 3.76 3 C4, I4 core speed grade 8.8 8.2 7.2 6.56 4.8 4.3 3.84 3.44 Transceiver Speed Grade ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance. The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can vary. In the register mode the pointers are fixed for low latency. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-33 10G PCS Data Rate Mode (164) PMA Width 20 20 16 16 10 10 8 8 PCS/Core Width 40 20 32 16 20 10 16 8 2 C3, I3L core speed grade 9.9 9 7.92 7.2 4.9 4.,5 3.92 3.6 3 C4, I4 core speed grade 8.8 8.2 7.04 6.56 4.4 4.1 3.52 3.28 Transceiver Speed Grade Register Related Information Operating Conditions on page 2-1 10G PCS Data Rate Table 2-31: 10G PCS Approximate Maximum Data Rate (Gbps) for Arria V GZ Devices Mode (165) Transceiver Speed Grade PMA Width 64 40 40 40 32 32 PCS Width 64 66/67 50 40 64/66/67 32 2 C3, I3L core speed grade 12.5 12.5 10.69 12.5 10.88 10.88 3 C4, I4 core speed grade 10.3125 10.3125 10.69 10.3125 9.92 9.92 2 C3, I3L core speed grade 12.5 12.5 10.69 12.5 10.88 10.88 3 C4, I4 core speed grade 10.3125 10.3125 10.69 10.3125 9.92 9.92 FIFO Register (164) (165) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can vary. In the register mode the pointers are fixed for low latency. The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can vary. In the register mode the pointers are fixed for low latency. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-34 AV-51002 2016.12.09 Typical VOD Settings Typical VOD Settings Table 2-32: Typical VOD Setting for Arria V GZ Channel, TX Termination = 100 The tolerance is +/-20% for all VOD settings except for settings 2 and below. Symbol VOD Setting VOD Value (mV) VOD Setting VOD Value (mV) 0 (166) 0 32 640 1(166) 20 33 660 2(166) 40 34 680 3(166) 60 35 700 4(166) 80 36 720 5(166) 100 37 740 6 120 38 760 7 140 39 780 8 160 40 800 9 180 41 820 10 200 42 840 11 220 43 860 12 240 44 880 13 260 45 900 14 280 46 920 VOD differential peak to peak typical (166) If TX termination resistance = 100 ,this VOD setting is illegal. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Typical VOD Settings Symbol VOD differential peak to peak typical Arria V GZ Device Datasheet Send Feedback VOD Setting VOD Value (mV) VOD Setting VOD Value (mV) 15 300 47 940 16 320 48 960 17 340 49 980 18 360 50 1000 19 380 51 1020 20 400 52 1040 21 420 53 1060 22 440 54 1080 23 460 55 1100 24 480 56 1120 25 500 57 1140 26 520 58 1160 27 540 59 1180 28 560 60 1200 29 580 61 1220 30 600 62 1240 31 620 63 1260 2-35 Altera Corporation 2-36 Typical VOD Settings AV-51002 2016.12.09 Figure 2-2: AC Gain Curves for Arria V GZ Channels (full bandwidth) Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Core Performance Specifications 2-37 Core Performance Specifications Clock Tree Specifications Table 2-33: Clock Tree Performance for Arria V GZ Devices Performance Symbol Unit C3, I3L C4, I4 Global and Regional Clock 650 580 MHz Periphery Clock 500 500 MHz PLL Specifications Table 2-34: PLL Specifications for Arria V GZ Devices Symbol Min Typ Max Unit Input clock frequency (C3, I3L speed grade) 5 -- 800 MHz Input clock frequency (C4, I4 speed grade) 5 -- 650 MHz fINPFD Input frequency to the PFD 5 -- 325 MHz fFINPFD Fractional Input clock frequency to the PFD 50 -- 160 MHz PLL VCO operating range (C3, I3L speed grade) 600 -- 1600 MHz PLL VCO operating range (C4, I4 speed grade) 600 -- 1300 MHz Input clock or external feedback clock input duty cycle 40 -- 60 % fIN (167) fVCO (168) tEINDUTY (167) (168) Parameter This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-38 AV-51002 2016.12.09 PLL Specifications Symbol Min Typ Max Unit Output frequency for an internal global or regional clock (C3, I3L speed grade) -- -- 650 MHz Output frequency for an internal global or regional clock (C4, I4 speed grade) -- -- 580 MHz Output frequency for an external clock output (C3, I3L speed grade) -- -- 667 MHz Output frequency for an external clock output (C4, I4 speed grade) -- -- 533 MHz tOUTDUTY Duty cycle for a dedicated external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time -- -- 10 ns fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and -- -- 100 MHz fOUT (169) fOUT_EXT (169) Parameter scanclk tLOCK Time required to lock from the end-of-device configuration or deassertion of areset -- -- 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/ delays) -- -- 1 ms PLL closed-loop low bandwidth -- 0.3 -- MHz PLL closed-loop medium bandwidth -- 1.5 -- MHz PLL closed-loop high bandwidth (170) -- 4 -- MHz tPLL_PSERR Accuracy of PLL phase shift -- -- 50 ps tARESET Minimum pulse width on the areset signal 10 -- -- ns fCLBW (169) (170) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL. High bandwidth PLL settings are not supported in external feedback mode. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 PLL Specifications Symbol tINCCJ (171), (172) tOUTPJ_DC (173) tFOUTPJ_DC (173) tOUTCCJ_DC (173) tFOUTCCJ_DC (173) (171) (172) (173) (174) Parameter Min Typ Max Unit Input clock cycle-to-cycle jitter (fREF 100 MHz) -- -- 0.15 UI (p-p) Input clock cycle-to-cycle jitter (fREF < 100 MHz) -750 -- +750 ps (p-p) Period Jitter for dedicated clock output in integer PLL (fOUT 100 MHz) -- -- 175 ps (p-p) Period Jitter for dedicated clock output in integer PLL (fOUT < 100 Mhz) -- -- 17.5 mUI (p-p) Period Jitter for dedicated clock output in fractional PLL (fOUT 100 MHz) -- -- 250(176), 175(174) ps (p-p) Period Jitter for dedicated clock output in fractional PLL (fOUT < 100 MHz) -- -- 25(176), 17.5 (174) mUI (p-p) Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT 100 MHz) -- -- 175 ps (p-p) Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT < 100 MHz) -- -- 17.5 mUI (p-p) Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT 100 MHz) -- -- 250(176), 175 (174) ps (p-p) Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT < 100 MHz) -- -- 25(176), 17.5 (174) mUI (p-p) 2-39 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. The fREF is fIN/N specification applies when N = 1. Peak-to-peak jitter with a probability level of 10-12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in the "Worst-Case DCD on Arria V GZ I/O Pins" table. This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be 1200 MHz. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-40 Symbol tOUTPJ_IO, (173), (175) tFOUTPJ_IO (173), (175), (176) tOUTCCJ_IO (173), (175) tFOUTCCJ_IO (173), (175), (176) tCASC_OUTPJ_DC (173), (177) dKBIT (175) (176) (177) AV-51002 2016.12.09 PLL Specifications Parameter Min Typ Max Unit Period Jitter for a clock output on a regular I/O in integer PLL (fOUT 100 MHz) -- -- 600 ps (p-p) Period Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) -- -- 60 mUI (p-p) Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT 100 MHz) -- -- 600 ps (p-p) Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) -- -- 60 mUI (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT 100 MHz) -- -- 600 ps (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) -- -- 60 mUI (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT 100 MHz) -- -- 600 ps (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) -- -- 60 mUI (p-p) Period Jitter for a dedicated clock output in cascaded PLLs (fOUT 100 MHz) -- -- 175 ps (p-p) Period Jitter for a dedicated clock output in cascaded PLLS (fOUT < 100 MHz) -- -- 17.5 mUI (p-p) Bit number of Delta Sigma Modulator (DSM) 8 24 32 Bits The external memory interface clock output jitter specifications use a different measurement method, which is available in the "Memory Output Clock Jitter Specification for Arria V GZ Devices" table. This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be 1000 MHz. The cascaded PLL specification is only applicable with the following condition: a. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 DSP Block Specifications Symbol Parameter kVALUE Numerator of Fraction fRES Resolution of VCO frequency (fINPFD = 100 MHz) Min Typ Max Unit 128 8388608 2147483648 -- 390625 5.96 0.023 Hz 2-41 Related Information * Duty Cycle Distortion (DCD) Specifications on page 2-56 * DLL Range Specifications on page 2-53 DSP Block Specifications Table 2-35: DSP Block Performance Specifications for Arria V GZ Devices Mode Performance C3, I3L C4 I4 Unit Modes using One DSP Block Three 9 x 9 480 420 MHz One 18 x 18 480 420 400 MHz Two partial 18 x 18 (or 16 x 16) 480 420 400 MHz One 27 x 27 400 350 MHz One 36 x 18 400 350 MHz One sum of two 18 x 18 (One sum of two 16 x 16) 400 350 MHz One sum of square 400 350 MHz One 18 x 18 plus 36 (a x b) + c 400 350 MHz Three 18 x 18 400 350 MHz One sum of four 18 x 18 380 300 MHz Modes using Two DSP Blocks Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-42 AV-51002 2016.12.09 Memory Block Specifications Performance Mode Unit C3, I3L C4 I4 One sum of two 27 x 27 380 300 290 One sum of two 36 x 18 380 300 MHz One complex 18 x 18 400 350 MHz One 36 x 36 380 300 MHz MHz Modes using Three DSP Blocks One complex 18 x 25 340 275 265 MHz Modes using Four DSP Blocks One complex 27 x 27 350 310 MHz Memory Block Specifications Table 2-36: Memory Block Performance Specifications for Arria V GZ Devices To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX. Memory MLAB (178) Mode Resources Used Performance Unit ALUTs Memory C3 C4 I3L I4 Single port, all supported widths 0 1 400 315 400 315 MHz Simple dual-port, x32/x64 depth 0 1 400 315 400 315 MHz Simple dual-port, x16 depth (178) 0 1 533 400 533 400 MHz ROM, all supported widths 0 1 500 450 500 450 MHz The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-43 Temperature Sensing Diode Specifications Memory M20K Block Resources Used Mode Performance Unit ALUTs Memory C3 C4 I3L I4 Single-port, all supported widths 0 1 650 550 500 450 MHz Simple dual-port, all supported widths 0 1 650 550 500 450 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 455 400 455 400 MHz Simple dual-port with ECC enabled, 512 x 32 0 1 400 350 400 350 MHz Simple dual-port with ECC and optional pipeline registers enabled, 512 x 32 0 1 500 450 500 450 MHz True dual port, all supported widths 0 1 650 550 500 450 MHz ROM, all supported widths 0 1 650 550 500 450 MHz Temperature Sensing Diode Specifications Table 2-37: Internal Temperature Sensing Diode Specification Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time Resolution Minimum Resolution with no Missing Codes -40C to 100C 8C No 1 MHz, 500 kHz < 100 ms 8 bits 8 bits Table 2-38: External Temperature Sensing Diode Specifications for Arria V GZ Devices Description Min Typ Max Unit Ibias, diode source current 8 -- 200 A Vbias, voltage across diode 0.3 -- 0.9 V Series resistance -- -- <1 Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-44 AV-51002 2016.12.09 Periphery Performance Description Diode ideality factor Min Typ Max Unit 1.006 1.008 1.010 -- Periphery Performance I/O performance supports several system interfaces, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are capable of a typical 167 MHz and 1.2-LVCMOS at 100 MHz interfacing frequency with a 10 pF load. Note: The actual achievable frequency depends on design- and system-specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specification High-Speed Clock Specifications Table 2-39: High-Speed Clock Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. Arria V GZ devices support the following output standards using true LVDS output buffer types on all I/O banks. * True RSDS output standard with data rates of up to 230 Mbps * True mini-LVDS output standard with data rates of up to 340 Mbps Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Transmitter High-Speed I/O Specifications Symbol Conditions C3, I3L C4, I4 Min Typ Max Min Typ Max Unit fHSCLK_in (input clock frequency) True Differential I/O Standards (179) Clock boost factor W = 1 to 40 (180) 5 -- 625 5 -- 525 MHz fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor W = 1 to 40 (180) 5 -- 625 5 -- 525 MHz fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor W = 1 to 40 (180) 5 -- 420 5 -- 420 MHz -- 5 -- 625 (181) 5 -- 525 (181) MHz fHSCLK_OUT (output clock frequency) 2-45 Transmitter High-Speed I/O Specifications Table 2-40: Transmitter High-Speed I/O Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. (179) (180) (181) This only applies to DPA and soft-CDR modes. Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate. This is achieved by using the LVDS clock network. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-46 AV-51002 2016.12.09 Transmitter High-Speed I/O Specifications Symbol True Differential I/O Standards - fHSDR (data rate) Emulated Differential I/O Standards with Three External Output Resistor Networks - fHSDR (data rate) Conditions C3, I3L C4, I4 Unit Min Typ Max Min Typ Max SERDES factor J = 3 to 10 (182) (183) , (184) -- 1250 (184) -- 1050 Mbps SERDES factor J 4 (184) -- 1600 (184) -- 1250 Mbps SERDES factor J = 2, uses DDR Registers (184) -- (189) (184) -- (189) Mbps SERDES factor J = 1, uses SDR Register (184) -- (189) (184) -- (189) Mbps SERDES factor J = 4 to 10 (191) (184) -- 840 (184) -- 840 Mbps LVDS TX with DPA , , , (185) (186) (187) (188) (190) (182) (183) (184) (185) (186) (187) (188) (189) (190) (191) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps. The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is design dependent and requires timing analysis. The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA. Requires package skew compensation with PCB trace length. Do not mix single-ended I/O buffer within LVDS I/O bank. Chip-to-chip communication only with a maximum load of 5 pF. The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity simulation is clean. You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin. When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-47 Receiver High-Speed I/O Specifications Symbol tx Jitter - True Differential I/O Standards tx Jitter - Emulated Differential I/O Standards with Three External Output Resistor Network tDUTY tRISE & tFALL TCCS Conditions C3, I3L C4, I4 Unit Min Typ Max Min Typ Max Total Jitter for Data Rate 600 Mbps - 1.25 Gbps -- -- 160 -- -- 160 ps Total Jitter for Data Rate < 600 Mbps -- -- 0.1 -- -- 0.1 UI Total Jitter for Data Rate 600 Mbps - 1.25 Gbps -- -- 300 -- -- 325 ps Total Jitter for Data Rate < 600 Mbps -- -- 0.2 -- -- 0.25 UI Transmitter output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 % True Differential I/O Standards -- -- 200 -- -- 200 ps Emulated Differential I/O Standards with three external output resistor networks -- -- 250 -- -- 300 ps True Differential I/O Standards -- -- 150 -- -- 150 ps Emulated Differential I/O Standards -- -- 300 -- -- 300 ps Receiver High-Speed I/O Specifications Table 2-41: Receiver High-Speed I/O Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-48 Symbol True Differential I/O Standards - fHSDRDPA (data rate) fHSDR (data rate) (192) (193) (194) (195) (196) (197) (198) (199) (200) AV-51002 2016.12.09 Receiver High-Speed I/O Specifications Conditions C3, I3L C4, I4 Unit Min Typ Max Min Typ Max SERDES factor J = 3 to 10 (192) (193) (194) (195) (196) (197) , , , , , 150 -- 1250 150 -- 1050 Mbps SERDES factor J 4 150 -- 1600 150 -- 1250 Mbps SERDES factor J = 2, uses DDR Registers (198) -- (199) (198) -- (199) Mbps SERDES factor J = 1, uses SDR Register (198) -- (199) (198) -- (199) Mbps SERDES factor J = 3 to 10 (198) -- (200) (198) -- (200) Mbps SERDES factor J = 2, uses DDR Registers (198) -- (199) (198) -- (199) Mbps SERDES factor J = 1, uses SDR Register (198) -- (199) (198) -- (199) Mbps LVDS RX with DPA , , , (193) (195) (196) (197) The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is design dependent and requires timing analysis. Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA. Arria V GZ LVDS serialization and de-serialization factor needs to be x4 and above. Requires package skew compensation with PCB trace length. Do not mix single-ended I/O buffer within LVDS I/O bank. Chip-to-chip communication only with a maximum load of 5 pF. The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity simulation is clean. You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-49 DPA Mode High-Speed I/O Specifications DPA Mode High-Speed I/O Specifications Table 2-42: High-Speed I/O Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. Symbol C3, I3L Conditions DPA run length -- C4, I4 Min Typ Max Min Typ Max -- -- 10000 -- -- 10000 Unit UI Figure 2-3: DPA Lock Time Specification with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 data transitions 96 slow clock cycles 256 data transitions 96 slow clock cycles 256 data transitions Table 2-43: DPA Lock Time Specifications for Arria V GZ Devices The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. The DPA lock time stated in this table applies to both commercial and industrial grade. Standard SPI-4 (201) Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (201) Maximum 00000000001111111111 2 128 640 data transitions This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-50 AV-51002 2016.12.09 Soft CDR Mode High-Speed I/O Specifications Standard Parallel Rapid I/O Miscellaneous Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (201) Maximum 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions Soft CDR Mode High-Speed I/O Specifications Table 2-44: High-Speed I/O Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. Symbol Soft-CDR ppm tolerance (201) Conditions -- C3, I3L C4, I4 Min Typ Max Min Typ Max -- -- 300 -- -- 300 Unit ppm This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Soft CDR Mode High-Speed I/O Specifications 2-51 Figure 2-4: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate 1.25 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification Jitter Amphlitude (UI) 25 8.5 0.35 0.1 F1 F3 F2 F4 Jitter Frequency (Hz) Table 2-45: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate 1.25 Gbps Jitter Frequency (Hz) Arria V GZ Device Datasheet Send Feedback Sinusoidal Jitter (UI) F1 10,000 25.000 F2 17,565 25.000 F3 1,493,000 0.350 F4 50,000,000 0.350 Altera Corporation 2-52 AV-51002 2016.12.09 Non DPA Mode High-Speed I/O Specifications Figure 2-5: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate < 1.25 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P Frequency 20 MHz baud/1667 Non DPA Mode High-Speed I/O Specifications Table 2-46: High-Speed I/O Specifications for Arria V GZ Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. Symbol Sampling Window Altera Corporation Conditions -- C3, I3L C4, I4 Min Typ Max Min Typ Max -- -- 300 -- -- 300 Unit ps Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 DLL Range Specifications 2-53 DLL Range Specifications Table 2-47: DLL Range Specifications for Arria V GZ Devices Arria V GZ devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least 300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range of the DLL. Parameter DLL operating frequency range C3, I3L C4, I4 Unit 300 - 890 300 - 890 MHz DQS Logic Block Specifications Table 2-48: DQS Phase Offset Delay Per Setting for Arria V GZ Devices The typical value equals the average of the minimum and maximum values. The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when using a -3 speed grade and applying a 10-phase offset setting to a 90 phase shift at 400 MHz, the expected average cumulative delay is [625 ps + (10 x 11 ps) 20 ps] = 735 ps 20 ps. Speed Grade Min Max Unit C3, I3L 8 15 ps C4, I4 8 16 ps Table 2-49: DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V GZ Devices This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a -3 speed grade is 84 ps or 42 ps. Number of DQS Delay Buffers C3, I3L C4, I4 Unit 1 30 32 ps 2 60 64 ps 3 90 96 ps Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-54 AV-51002 2016.12.09 Memory Output Clock Jitter Specifications Number of DQS Delay Buffers C3, I3L C4, I4 Unit 120 128 ps 4 Memory Output Clock Jitter Specifications Table 2-50: Memory Output Clock Jitter Specification for Arria V GZ Devices The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible. The clock jitter specification applies to the memory output clock pins clocked by an integer PLL. The memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14 sigma. Clock Network Regional Global PHY Clock Parameter C3, I3L C4, I4 Min Max Min Max Unit Clock period jitter tJIT(per) -55 55 -55 55 ps Cycle-to-cycle period jitter tJIT(cc) -110 110 -110 110 ps Duty cycle jitter tJIT(duty) -82.5 82.5 -82.5 82.5 ps Clock period jitter tJIT(per) -82.5 82.5 -82.5 82.5 ps Cycle-to-cycle period jitter tJIT(cc) -165 165 -165 165 ps Duty cycle jitter tJIT(duty) -90 90 -90 90 ps Clock period jitter tJIT(per) -30 30 -35 35 ps Cycle-to-cycle period jitter tJIT(cc) -60 60 -70 70 ps tJIT(duty) -45 45 -56 56 ps Duty cycle jitter Altera Corporation Symbol Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-55 OCT Calibration Block Specifications OCT Calibration Block Specifications Table 2-51: OCT Calibration Block Specifications for Arria V GZ Devices Symbol Description Min Typ Max Unit OCTUSRCLK Clock required by the OCT calibration blocks -- -- 20 MHz TOCTCAL Number of OCTUSRCLK clock cycles required for OCT RS/RT calibration -- 1000 -- Cycles TOCTSHIFT Number of OCTUSRCLK clock cycles required for the OCT code to shift out -- 32 -- Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between OCT RS and RT (See the figure below.) -- 2.5 -- ns Figure 2-6: Timing Diagram for oe and dyn_term_ctrl Signals RX Tristate TX Tristate RX oe dyn_term_ctrl TRS_RT Arria V GZ Device Datasheet Send Feedback TRS_RT Altera Corporation 2-56 AV-51002 2016.12.09 Duty Cycle Distortion (DCD) Specifications Duty Cycle Distortion (DCD) Specifications Table 2-52: Worst-Case DCD on Arria V GZ I/O Pins The DCD numbers do not cover the core clock network. Symbol Output Duty Cycle C3, I3L C4, I4 Min Max Min Max 45 55 45 55 Unit % Configuration Specification POR Specifications Table 2-53: Fast and Standard POR Delay Specification for Arria V GZ Devices Select the POR delay based on the MSEL setting as described in the "Configuration Schemes for Arria V Devices" table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. POR Delay Fast Standard Minimum (ms) Maximum (ms) 4 12 (202) 100 300 Related Information Configuration, Design Security, and Remote System Upgrades in Arria V Devices (202) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 JTAG Configuration Specifications 2-57 JTAG Configuration Specifications Table 2-54: JTAG Timing Parameters and Values for Arria V GZ Devices Symbol Description Min Max Unit tJCP TCK clock period 30 -- ns tJCP TCK clock period 167 (203) -- ns tJCH TCK clock high time 14 -- ns tJCL TCK clock low time 14 -- ns tJPSU (TDI) TDI JTAG port setup time 2 -- ns tJPSU (TMS) TMS JTAG port setup time 3 -- ns tJPH JTAG port hold time 5 -- ns tJPCO JTAG port clock to output -- 11 (204) ns tJPZX JTAG port high impedance to valid output -- 14 (204) ns tJPXZ JTAG port valid output to high impedance -- 14 (204) ns Fast Passive Parallel (FPP) Configuration Timing DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. (203) (204) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile key programming. A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO I/O bank = 2.5 V, or 13 ns if it equals 1.8 V. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-58 AV-51002 2016.12.09 DCLK-to-DATA[] Ratio (r) for FPP Configuration Table 2-55: DCLK-to-DATA[] Ratio for Arria V GZ Devices Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the data rate in bytes per second (Bps), or words per second (Wps). For example, in FPP x16 when the DCLK-to-DATA[] ratio is 2, the DCLK frequency must be 2 times the data rate in Wps. Arria V GZ devices use the additional clock cycles to decrypt and decompress the configuration data. Configuration Scheme FPP x8 FPP x16 FPP x32 Altera Corporation Decompression Design Security DCLK-to-DATA[] Ratio Disabled Disabled 1 Disabled Enabled 1 Enabled Disabled 2 Enabled Enabled 2 Disabled Disabled 1 Disabled Enabled 2 Enabled Disabled 4 Enabled Enabled 4 Disabled Disabled 1 Disabled Enabled 4 Enabled Disabled 8 Enabled Enabled 8 Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 FPP Configuration Timing when DCLK to DATA[] = 1 2-59 FPP Configuration Timing when DCLK to DATA[] = 1 Figure 2-7: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1 Timing waveform for FPP configuration when using a MAX(R) II or MAX V device as an external host. tCFG nCONFIG nSTATUS (2) CONF_DONE (3) tCF2ST1 t CF2CK tCF2ST0 tSTATUS tCLK tCH tCL tCF2CD t ST2CK (4) DCLK DATA[31..0] (5) User I/O (6) tDH Word 0 Word 1 Word 2 Word 3 tDSU User Mode Word n-2 Word n-1 User Mode High-Z INIT_DONE (7) tCD2UM Notes: 1. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. 2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay. 3. After power-up, before and during configuration, CONF_DONE is low. 4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. 5. For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[31..0] are available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings. 6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is released high when the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. 7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-60 AV-51002 2016.12.09 FPP Configuration Timing when DCLK to DATA[] = 1 Note: When you enable the decompression or design security feature, the DCLK-to-DATA[] ratio varies for FPP x8, FPP x16, and FPP x32. For the respective DCLK-to-DATA[] ratio, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table. Table 2-56: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1 Use these timing parameters when the decompression and design security features are disabled. Symbol Minimum Maximum Unit -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (205) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (206) s 1,506 -- s 2 -- s 5.5 -- ns 0 -- ns tCF2CD tCF2CK (207) Parameter nCONFIG low to CONF_DONE low nCONFIG low pulse width nCONFIG high to first rising edge on DCLK tST2CK (207)nSTATUS high to first rising edge of DCLK tDSU DATA[] setup time before rising edge on DCLK tDH DATA[] hold time after rising edge on DCLK tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK 1/fMAX -- s fMAX period DCLK frequency (FPP x8/x16) -- 125 MHz DCLK frequency (FPP x32) -- 100 MHz 175 437 s tCD2UM CONF_DONE high to user mode (208) (205) (206) (207) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. This value is applicable if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 2-61 FPP Configuration Timing when DCLK to DATA[] = 1 Symbol Parameter tCD2CU CONF_DONE high to CLKUSR enabled Minimum Maximum Unit 4 x maximum -- -- -- -- DCLK period tCD2UM CONF_DONE high to user mode with CLKUSR option on C tCD2CU + (17,408 x CLKUSR period) (209) Related Information * DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 2-57 * Configuration, Design Security, and Remote System Upgrades in Arria V Devices (208) (209) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the "Initialization" section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-62 AV-51002 2016.12.09 FPP Configuration Timing when DCLK to DATA[] > 1 FPP Configuration Timing when DCLK to DATA[] > 1 Figure 2-8: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 , Timing when using a MAX II device, MAX V device, or microprocessor as an external host. tCFG nCONFIG nSTATUS (3) CONF_DONE (4) DCLK (6) tCF2ST1 tCF2CK tSTATUS tCF2ST0 tCL tCH tCF2CD tST2CK 1 DATA[31..0] (8) User I/O tDSU High-Z 2 r 1 (8) 2 tCLK Word 0 Word 1 tDH tDH r (7) 1 Word 3 r 1 (5) 2 User Mode Word (n-1) User Mode INIT_DONE (9) tCD2UM Notes: 1. To find out the DCLK-to-DATA[] ratio for your system, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table. 2. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. 3. After power-up, the Arria V GZ device holds nSTATUS low for the time as specified by the POR delay. 4. After power-up, before and during configuration, CONF_DONE is low. 5. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. 6. "r" denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable settings, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table. 7. If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending the first DCLK rising edge. 8. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. 9. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 FPP Configuration Timing when DCLK to DATA[] > 1 2-63 Table 2-57: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1 Use these timing parameters when you use the decompression and design security features. Symbol (210) (212) (213) (214) Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (210) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (211) s tCF2CK (212) nCONFIG high to first rising edge on DCLK 1,506 -- s tST2CK(212) nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK N-1/fDCLK (213) -- s tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX (211) Parameter DCLK frequency (FPP x8/x16) -- 125 MHz DCLK frequency (FPP x32) -- 100 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (214) 175 437 s You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating. The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-64 AV-51002 2016.12.09 FPP Configuration Timing when DCLK to DATA[] > 1 Symbol Parameter tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Minimum Maximum Unit 4 x maximum DCLK period -- -- tCD2CU + (17,408 x CLKUSR period) (215) -- -- Related Information * DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 2-57 * Configuration, Design Security, and Remote System Upgrades in Arria V Devices (215) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the "Initialization" section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Active Serial Configuration Timing 2-65 Active Serial Configuration Timing Figure 2-9: AS Configuration Timing Timing waveform for the active serial (AS) x1 mode and AS x4 mode configuration timing. tCF2ST1 nCONFIG nSTATUS CONF_DONE nCSO DCLK AS_DATA0/ASDO tCO Read Address tDH tSU AS_DATA1 (1) bit 0 bit 1 bit (n - 2) bit (n - 1) tCD2UM(2) INIT_DONE (3) User I/O User Mode Notes: 1. If you a re using AS x4 mode, this signal rep rese nts the AS_DATA[3..0] and EPCQ sends in 4-bits of d ata for each DCLKcycle. 2. The initialization clock can be from internal oscillator or CLKUSR pin . 3. After the option bit to enable the INIT_DONE pin isconfigu red into the d evice, the INIT_DONE oges low. Table 2-58: AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in the "PS Timing Parameters for Arria V GZ Devices" table. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-66 AV-51002 2016.12.09 Active Serial Configuration Timing Symbol Parameter Minimum Maximum Unit tCO DCLK falling edge to AS_DATA0/ASDO output -- 4 ns tSU Data setup time before falling edge on DCLK 1.5 -- ns tH Data hold time after falling edge on DCLK 0 -- ns tCD2UM CONF_DONE high to user mode (216) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 x CLKUSR period) -- -- Table 2-59: DCLK Frequency Specification in the AS Configuration Scheme This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz Related Information * Passive Serial Configuration Timing on page 2-67 * Configuration, Design Security, and Remote System Upgrades in Arria V Devices (216) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the "Initialization" section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Passive Serial Configuration Timing 2-67 Passive Serial Configuration Timing Figure 2-10: PS Configuration Timing Waveform Timing waveform for a passive serial (PS) configuration when using a MAX II device, MAX V device, or microprocessor as an external host. tCFG nCONFIG nSTATUS (2) CONF_DONE (3) tCF2ST1 tCF2CK tCF2ST0 tSTATUS tCLK tCH tCL tCF2CD t ST2CK (4) DCLK DATA0 User I/O (6) tDH Bit 0 Bit 1 Bit 2 tDSU Bit 3 (5) Bit (n-1) User Mode High-Z INIT_DONE (7) tCD2UM Notes: 1. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. 2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay. 3. After power-up, before and during configuration, CONF_DONE is low. 4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. 5. DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins Option. 6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. 7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-68 AV-51002 2016.12.09 Passive Serial Configuration Timing Table 2-60: PS Timing Parameters for Arria V GZ Devices Symbol Parameter (219) (220) Unit nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (217) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (218) s tCF2CK nCONFIG high to first rising edge on DCLK 1,506 -- s 2 -- s 5.5 -- ns 0 -- ns tST2CK (219) nSTATUS high to first rising edge of DCLK (218) Maximum tCF2CD (219) (217) Minimum tDSU DATA[] setup time before rising edge on DCLK tDH DATA[] hold time after rising edge on DCLK tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency -- 125 MHz tCD2UM CONF_DONE high to user mode (220) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 x -- -- CLKUSR period) (221) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. This value is applicable if you do not delay configuration by externally holding the nSTATUS low. If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Initialization 2-69 Related Information Configuration, Design Security, and Remote System Upgrades in Arria V Devices Initialization Table 2-61: Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices Initialization Clock Source Internal Oscillator CLKUSR (222) DCLK Configuration Schemes Maximum Frequency (MHz) AS, PS, FPP 12.5 PS, FPP 125 AS 100 PS, FPP 125 Minimum Number of Clock Cycles 17,408 Configuration Files Use the following table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Quartus II software. However, for a specific version of the Quartus II software, any design targeted for the same device has the same uncompressed configuration file size. (221) (222) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the "Initialization" section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software from the General panel of the Device and Pin Options dialog box. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-70 AV-51002 2016.12.09 Remote System Upgrades Circuitry Timing Specification Table 2-62: Uncompressed .rbf Sizes for Arria V GZ Devices Variant Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) (223) E1 137,598,880 562,208 E3 137,598,880 562,208 E5 213,798,880 561,760 E7 213,798,880 561,760 Arria V GZ Table 2-63: Minimum Configuration Time Estimation for Arria V GZ Devices Active Serial (224) Variant Fast Passive Parallel (225) Member Code Width DCLK (MHz) Min Config Time (ms) Width DCLK (MHz) Min Config Time (ms) E1 4 100 344 32 100 43 E3 4 100 344 32 100 43 E5 4 100 534 32 100 67 E7 4 100 534 32 100 67 Arria V GZ Remote System Upgrades Circuitry Timing Specification Table 2-64: Remote System Upgrade Circuitry Timing Specifications Parameter (223) (224) (225) Minimum Maximum Unit tRU_nCONFIG (226) 250 -- ns tRU_nRSTIMER (227) 250 -- ns The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature. DCLK frequency of 100 MHz using external CLKUSR. Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 User Watchdog Internal Oscillator Frequency Specification 2-71 Related Information * Configuration, Design Security, and Remote System Upgrades in Arria V Devices For more information about the reconfiguration input for the ALTREMOTE_UPDATE IP core, refer to the "User Watchdog Timer" section. * Configuration, Design Security, and Remote System Upgrades in Arria V Devices For more information about the reset_timer input for the ALTREMOTE_UPDATE IP core, refer to the "Remote System Upgrade State Machine" section. User Watchdog Internal Oscillator Frequency Specification Table 2-65: User Watchdog Internal Oscillator Frequency Specifications Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz I/O Timing Altera offers two ways to determine I/O timing--the Excel-based I/O Timing and the Quartus II Timing Analyzer. Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete placeand-route. Related Information Arria V Devices Documentation page For the Excel-based I/O Timing spreadsheet (226) (227) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. For more information, refer to the "Remote System Upgrade State Machine" section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. For more information, refer to the "User Watchdog Timer" section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-72 AV-51002 2016.12.09 Programmable IOE Delay Programmable IOE Delay Table 2-66: IOE Programmable Delay for Arria V GZ Devices Available Settings Min Offset (229) D1 64 D2 Parameter (228) Fast Model Slow Model Unit Industrial Commercial C3 C4 I3L I4 0 0.464 0.493 0.924 1.011 0.921 1.006 ns 32 0 0.230 0.244 0.459 0.503 0.456 0.500 ns D3 8 0 1.587 1.699 2.992 3.192 3.047 3.257 ns D4 64 0 0.464 0.492 0.924 1.011 0.920 1.006 ns D5 64 0 0.464 0.493 0.924 1.011 0.921 1.006 ns D6 32 0 0.229 0.244 0.458 0.503 0.456 0.499 ns Programmable Output Buffer Delay Table 2-67: Programmable Output Buffer Delay for Arria V GZ Devices You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Symbol DOUTBUF (228) (229) Parameter Rising and/or falling edge delay Typical Unit 0 (default) ps 50 ps 100 ps 150 ps You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column of Assignment Editor. Minimum offset does not include the intrinsic delay. Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Glossary 2-73 Glossary Table 2-68: Glossary Term Differential I/O Standards Definition Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-74 AV-51002 2016.12.09 Glossary Term Definition Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK Left and right PLL input clock frequency. fHSDR High-speed I/O block--Maximum and minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block--Maximum and minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. J High-speed I/O block--Deserialization factor (width of parallel data bus). Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Glossary Term 2-75 Definition JTAG Timing Specifi JTAG Timing Specifications: cations TMS TDI tJCH tJCP t JCL tJPH tJPSU TCK tJPZX tJPXZ tJPCO TDO PLL Specifications Diagram of PLL Specifications CLKOUT Pins Switchover CLK fOUT_EXT 4 fIN Core Clock N fINPFD PFD CP LF VCO fVCO Counters C 0..C 17 fOUT GCLK RCLK Delta Sigma Modulator Key Reconfigurable in User Mode External Feedback Note: 1. Core Clock can only be fed by dedicated clock input pins or PLL outputs. Arria V GZ Device Datasheet Send Feedback Altera Corporation 2-76 AV-51002 2016.12.09 Glossary Term Definition RL Receiver differential input discrete resistor (external to the Arria V GZ device). SW (sampling window) Timing Diagram--the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window, as shown: Bit Time 0.5 x TCCS Single-ended voltage referenced I/O standard RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS Altera Corporation Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Glossary Term Definition tC High-speed receiver and transmitter input and output clock period. TCCS (channel-tochannel-skew) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block--Duty cycle on the high-speed transmitter output clock. tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input. tOUTPJ_IO Period jitter on the general purpose I/O driven by a PLL. tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL. tRISE Signal low-to-high transition time (20-80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(receiver input clock frequency multiplication factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage--The common mode of the differential signal at the receiver. VID Input differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage--Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage-- Minimum DC input differential voltage required for switching. VIH Voltage input high--The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low--The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage Arria V GZ Device Datasheet Send Feedback 2-77 Altera Corporation 2-78 AV-51002 2016.12.09 Document Revision History Term Definition VOCM Output common mode voltage--The common mode of the differential signal at the transmitter. VOD Output differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block--clock boost factor Document Revision History Date June 2016 Version Changes 2016.06.20 * Changed column heading from "Value" to "Maximum" in the "Pin Capacitance for Arria V GZ Devices" table. * Changed the minimum supported data rate range values from "1000" to "2000" in the "ATX PLL Specifica tions for Arria V GZ Devices" table. * Added the supported data rates for the following output standards using true LVDS output buffer types in the "High-Speed Clock Specifications for Arria V GZ Devices" table: * True RSDS output standard: data rates of up to 230 Mbps * True mini-LVDS output standard: data rates of up to 340 Mbps December 2015 Altera Corporation 2015.12.16 * Removed the CDR ppm tolerance specification from the "Receiver Specifications for Arria V GZ Devices" table. * Removed transmitter rise and fall time specifications from the "Transmitter Specifications for Arria V GZ Devices" table. * Changed the .rbf sizes in the "Uncompressed .rbf Sizes for Arria V GZ Devices" table. * Added a footnote to the "Transmitter High-Speed I/O Specifications for Arria V GZ Devices" table. Arria V GZ Device Datasheet Send Feedback AV-51002 2016.12.09 Document Revision History Date Version Changes June 2015 2015.06.16 * Changed the conditions for the reference clock rise and fall time and added a note to the condition in the "Reference Clock Specifications for Arria V GZ Devices" table. * Added a note to the "Minimum differential eye opening at receiver serial input pins" specification in the "Receiver Specifications for Arria V GZ Devices" table. January 2015 2015.01.30 * Added 240- to the "OCT Calibration Accuracy Specifications for Arria V GZ Devices" table. * Changed the CDR PPM tolerance spec in the "Receiver Specifications for Arria V GZ Devices" table. * Added additional max data rate for fPLL in the "Fractional PLL Specifications for Arria V GZ Devices" table. July 2014 3.8 * * * * * * * February 2014 3.7 Updated Table 28. December 2013 3.6 * Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37, Table 38, Table 45, Table 46, Table 47, Table 56, Table 49. * Updated "PLL Specifications". August 2013 3.5 Updated Table 28. August 2013 3.4 * Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28, Table 29, Table 31, Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, and Table 54. * Updated Table 2 and Table 28. June 2013 3.3 Updated Table 23, Table 28, Table 51, and Table 55. Arria V GZ Device Datasheet Send Feedback 2-79 Updated Table 21. Updated Table 22 VOCM (DC Coupled) condition. Updated the DCLK note to Figure 6, Figure 7, and Figure 9. Added note to Table 5 and Table 6. Added the DCLK specification to Table 50. Added note to Table 51. Updated the list of parameters in Table 53. Altera Corporation 2-80 AV-51002 2016.12.09 Document Revision History Date Version Changes May 2013 3.2 * Added Table 23. * Updated Table 5, Table 22, Table 26, and Table 57. * Updated Figure 6, Figure 7, Figure 8, and Figure 9. March 2013 3.1 * Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52. * Updated "Maximum Allowed Overshoot and Undershoot Voltage". December 2012 3.0 Initial release. Altera Corporation Arria V GZ Device Datasheet Send Feedback Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Altera: 5ASXBB5D6F40C6N 5ASTFD5K3F40I3N 5ASXFB5H6F40C6N 5ASXBB5D4F35C4N 5ASXBB5D6F35C6N 5ASXBB3D4F40C4N 5ASXMB3G4F40C5N 5ASXFB3H4F40C5N 5ASXBB3D4F40C5N 5ASXBB5D4F35I5N 5ASTFD5G3F35I3N 5ASXMB3G4F40C4N 5ASXBB5D4F35C5N 5ASXFB5H4F40I5N 5ASXBB3D4F40I5N 5ASXFB3G4F35I3N 5ASTMD5E3F31I5N 5ASXBB5D6F31C6N 5ASXFB5G4F35C4N 5ASXMB5E4F31I5N 5ASTFD3G3F35I5N 5ASXFB3H4F40I3N 5ASXFB5G6F35C6N 5ASXBB5D4F31C4N 5ASXBB3D4F35C5N 5ASXMB3E4F31C5N 5ASTMD3E3F31I5N 5ASXBB5D4F31C5N 5ASXMB3G4F40I5N 5ASXMB5E6F31C6N 5ASXBB3D6F35C6N 5ASXMB3E4F31I5N 5ASTFD5G3F35I5N 5ASXFB3H4F40C4N 5ASXFB5G4F35I5N 5ASTFD3K3F40I5N 5ASXBB3D4F35C4N 5ASXFB3H6F40C6N 5ASXMB5E4F31C4N 5ASXBB5D4F31I5N 5ASXFB5G4F35C5N 5ASTMD3E3F31I3N 5ASXBB3D6F40C6N 5ASTFD3G3F35I3N 5AGXFB5K4F40I3 5ASXBB3D6F31C6N 5ASXFB3G4F35C4N 5AGXFA5H4F35I3 5ASXMB5G4F40I5N 5ASXFB3H4F40I5N 5ASTMD5E3F31I3N 5ASXBB5D4F40C4N 5ASXBB3D4F35I5N 5ASXFB3G6F35C6N 5ASTFD5K3F40I5N 5ASXBB3D4F31C4N 5ASXFB5H4F40C4N 5ASXMB5G4F40C5N 5AGXFB5K4F40I5 5ASTFD3K3F40I3N 5ASXBB3D4F31C5N 5ASXFB5H4F40C5N 5ASXMB3E6F31C6N 5ASXMB5G6F40C6N 5ASXFB5H4F40I3N 5AGXMA5G4F35I5 5ASXBB5D4F40C5N 5ASXBB5D4F40I5N 5ASXMB3E4F31C4N 5ASXMB5G4F40C4N 5AGXMA7G4F31I3 5ASXFB5G4F35I3N 5AGXBA1D4F27I5 5ASXFB3G4F35C5N 5ASXMB3G6F40C6N 5ASXBB3D4F31I5N 5ASXFB3G4F35I5N 5ASXMB5E4F31C5N