128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05086 Rev. ** Revised September 5, 2001
347
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registe red inputs and outputs for pipeli ned o per-
ation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
—3.5 ns (for 166- MHz d evic e)
—4.0 ns (for 133- MHz d evic e)
—5.5 ns (for 100- MHz d evic e)
• User-selectable burst counter supporting Intel Pen-
tium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial Temperature
ranges
Functional Description
The CY7C1347 is a 3.3V, 128K by 36 synchronous-pipelined
cache SRAM designed to support zero-wait-state secondary
cache w ith mi nim al glue log ic.
The CY7C1347 I/O pins can operate at either the 2.5V or the
3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.
All syn chrono us in puts p ass t hrough input regi sters contro lled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1347 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address adv an ce men t th rough the burs t se que nc e
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the four Byte Write
Select (BW [3:0]) inputs . A Gl obal W ri te Enab le (GW) overri des
all byte w rite inp uts an d w rit es data to a ll four byt es . All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch rono us O utp ut En abl e (O E) provide for easy bank se-
lection and outpu t three-state c ontrol. In order to provide prop-
er da ta d urin g d ept h expansio n, O E is masked d uri ng the first
clock of a rea d cy cl e w he n em erg ing from a des el ec ted s tate.
Pentium and Intel are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BW3
BW2
BW1
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
OUTPUT
REGISTERS INPUT
REGISTERS
128KX36
MEMORY
ARRAY
CLK CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
36 36
17
15
15
17
(A[1;0])2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
DP[3:0]
DQ[31:24], DP[3]
BYTEWRITE
REGISTERS
DQ
DQ[23:16], DP[2]
BYTEWRITE
REGISTERS
DQ
DQ
DQ[15:8], DP[1]
BYTEWRITE
REGISTERS
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
DQ
ENABLE CE
REGISTER
DQ
ENABLE DELAY
REGISTER
DQ
CY7C1347
Document #: 38-05086 Rev. ** Page 2 of 16
Pin Configuration
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
DP1
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE
1
CE
2
BW
3
BW
2
BW
1
BW
0
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE0
BYTE1
BYTE3
BYTE2
100-Pin TQFP
CY7C1347
Selection Guide
7C1347-166 7C1347-133 7C1347-100
Maximum Access Time (ns) 3.5 4.0 5.5
Maximum Operating Current (mA) Commercial 420 375 325
Maximum CMOS Standby Current (mA) Commercial 10 10 10
CY7C1347
Document #: 38-05086 Rev. ** Page 3 of 16
Pin Definitions
Pin Number Name I/O Description
50–44, 81,
82, 99, 100,
32–37
A[16:0] Input-
Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampl ed active. A[1:0] feed the 2-bit counter.
96–93 BW[3:0] Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byt e writ es
to the SRAM. Sampled on the rising edge of CLK.
88 GW Input-
Synchronous Global Write Enable Input, active LOW . When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[3:0] and BWE).
87 BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to
increme nt the burst c ounter when ADV is asserted LOW, during a burst operation.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
86 OE Input-
Asynchronous Output Ena ble, as ynchr onous i nput, ac tive L OW. Controls the dire ction o f the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first
clock of a read cycle when emerging from a deselected state.
83 ADV Input-
Synchronous Advance Input signa l, sam pled on the risi ng edg e of C LK. Wh en asse rted , it au to-
matically increments the address in a burst cycle.
84 ADSP Input-
Synchronous Address Stro be from Proce ssor , sampled o n the rising edge o f CLK. When assert-
ed LOW, A[16:0] is captured in the add ress registers. A[1:0] are als o loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deasserted HIGH.
85 ADSC Input-
Synchronous Addres s Strobe from Co ntroller, samp led on the risin g edge of C LK. When assert-
ed LOW, A[16:0] is captured in the add ress registers. A[1:0] are als o loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
64 ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
“sleep” conditi on wi th d ata integrity pre ser ved . Fo r no rmal operat io n, th is pi n ha s
to be LOW or left floating.
30–28,
25–22, 19,
18, 13, 12,
9–6, 3–1,
80–78,
75–72, 69,
68, 63, 62
59–56, 53–51
DQ[31:0]
DP[3:0] I/O-
Synchronous Bidirecti onal D ata I/O lin es. As i nputs, they fee d in to an on- chip da ta regis ter that
is trigg ered by the rising edge of CLK. As ou tputs, they de liver the dat a contained
in the memory location specified by A[16:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. Whe n OE is asserted
LOW , the pins beh ave as outp uts. Whe n HIGH, DQ[31:0] and DP[3:0] are placed in
a three-state co ndition.
15, 41, 65, 91 VDD Power Supply Power s upply inputs to the co re of the de vice. Shou ld be conn ected to 3 .3V power
supply.
17, 40, 67, 90 VSS Ground Ground for the core of the device. Should be connected to ground of the system.
4, 11, 20, 27,
54, 61, 70, 77 VDDQ I/O Power
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power
supply.
5, 10, 21, 26,
55, 60, 71, 76 VSSQ I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.
CY7C1347
Document #: 38-05086 Rev. ** Page 4 of 16
Introduction
Functional Overview
All syn chrono us in puts p ass through input regist ers co ntrolle d
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns
(166-MHz device).
The CY7C1347 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst o rder supp orts Pentium an d i 48 6 p roc es so rs. The linear
burst sequence is suited for processors that utilize a linear
burst s equ enc e. The bu rst order is user se lec tab le, and is d e-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byt e Write S elect (BW[3:0]) inputs. A Global Write
Enable (G W) overri des all byte write inp uts and wri tes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self- t imed w rite ci rcu itry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch ro nous Ou tp ut En able ( O E) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asse rted active, and (3) the writ e signals
(GW, B W E) are all deasserted HIGH. ADSP is ignor e d if CE1
is HIGH . The address presented to the address inputs (A[16:0])
is stored into the addre ss advancem ent logic and the Addres s
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the ris ing edge of th e nex t clo ck t he da ta
is allowed to propagate through the OutputRegister and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW . The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the f irs t cy cl e of t h e a cc ess, t h e ou t pu ts a r e co nt ro ll e d by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is in itiat ed whe n both of t he foll owing condi tions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asser ted active. The ad dress presente d
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[3:0]) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data pres ented to the DQ[31:0] and DP[3:0] i nputs is written into
the corres pon di ng address loc ati on i n the RAM co re. If G W is
HIGH, then the write operation is controlled by BWE and
BW[3:0] signals. Th e CY7 C134 7 prov id es by te w rite cap abi lity
that is described in the Write Cycle Description table. Assert-
ing the Byte Write Enable input (BWE) with the selected Byte
Write ( BW[3:0]) input will selectively write to only the desired
bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] and DP[3:0] inputs. Doin g so wil l three-s tate th e
output driv ers. As a safety preca ution, DQ[31:0] and DP[3:0] are
automat icall y t hree-sta ted whenev er a w rite c ycle is d etecte d,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into th e add res s re gis ter a nd th e ad dres s a d-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ[31:0] and DP[3:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] and DP[3:0] inputs. Doin g so wil l three-s tate th e
output driv ers. As a safety preca ution, DQ[31:0] and DP[3:0] are
automat icall y t hree-sta ted whenev er a w rite c ycle is d etecte d,
regardless of the state of OE.
31 MODE Input-
Static Selects burst order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left fl oating sele cts i nterlea ved b urst s equen ce. Th is is a str ap pin an d
should remain static during device operation.
14, 16, 38, 39,
42, 43, 66 NC No Connects.
Pin Definitions
Pin Number Name I/O Description
CY7C1347
Document #: 38-05086 Rev. ** Page 5 of 16
Burst Sequences
The CY7C13 47 provides a two-bi t wraparound co unter , fed by
A[1:0], that imple ments either an interle aved or l inear bu rst se-
quence. The interleaved burst sequence is designed specifi-
cally to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise wil l auto ma tic al ly incre me nt
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported. Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. T wo clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be d ese le cted prior to ent erin g t he “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must rema in inactive for the
duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mode standby
current ZZ > VDD − 0.2V 10 mA
tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
CY7C1347
Document #: 38-05086 Rev. ** Page 6 of 16
Cycle Descriptions[1, 2, 3]
Next Cycle Add. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write
Unselected None L X X 1 X 0 X X Hi-Z X
Unselected None L 1 X 0 0 X X X Hi-Z X
Unselected None L X 0 0 0 X X X Hi-Z X
Unselected None L 1 X 0 1 0 X X Hi-Z X
Unselected None L X 0 0 1 0 X X Hi-Z X
Begin ReadExternal L010 0 XXXHi-ZX
Begin ReadExternal L010 1 0XXHi-ZRead
Continue Read Next L X X X 1 1 0 1 Hi-Z Read
Continue Read Next L X X X 1 1 0 0 DQ Read
Continue Read Next L X X 1 X 1 0 1 Hi-Z Read
Continue Read Next L X X 1 X 1 0 0 DQ Read
Suspend Read Current L X X X 1 1 1 1 Hi-Z Read
Suspend Read Current L X X X 1 1 1 0 DQ Read
Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read
Suspend Read Current L X X 1 X 1 1 0 DQ Read
Begin Write Current L X X X 1 1 1 X Hi-Z Write
Begin Write Current L X X 1 X 1 1 X Hi-Z Write
Begin WriteExternal L010 1 0XXHi-ZWrite
Contin ue W ri te Next L X X X 1 1 0 X Hi-Z W rite
Contin ue W ri te Next L X X 1 X 1 0 X Hi-Z Write
Suspend Write Current L X X X 1 1 1 X Hi-Z Write
Suspend Write Current L X X 1 X 1 1 X Hi-Z Write
ZZ “Sleep” None HXXX X XXXHi-ZX
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, B W[3:0], and G W. See Write Cycle Descriptions Table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
CY7C1347
Document #: 38-05086 Rev. ** Page 7 of 16
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z Stat e[7] .......................................−0.5V to VDD + 0.5V
DC Input Vo ltage[7]....................................−0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ[31:0]; DP[3:0] = High-Z when OE
is inactive or when the device is deselected, and DQ[31:0]; DP[3:0] = data when OE is active
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
Wr ite Cycle Descriptions [4, 5, 6]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write B yte 0 - DQ[7:0] 101110
Write B yte 1 - DQ[15:8] 101101
Write Bytes 1, 0 101100
Write B yte 2 - DQ[23:16] 101011
Write Bytes 2, 0 101010
Write Bytes 2, 1 101001
Write Bytes 2, 1, 0 1 0 1 0 0 0
Write B yte 3 - DQ[31:24] 100111
Write Bytes 3, 0 100110
Write Bytes 3, 1 100101
Write Bytes 3, 1, 0 1 0 0 1 0 0
Write Bytes 3, 2 100011
Write Bytes 3, 2, 0 1 0 0 0 1 0
Write Bytes 3, 2, 1 1 0 0 0 0 1
Write All Bytes 1 0 0 0 0 0
Write All Bytes 0 X X X X X
Operating Range
Range Ambient
Temperature[8] VDD VDDQ
Com’l 0°C to +70°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
Ind’l–40°C to +85°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
CY7C1347
Document #: 38-05086 Rev. ** Page 8 of 16
Electrical Characteristics Ov er the Op erating Range
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.3V −5%/+10% 3.135 3.6 V
VDDQ I/O Supply Voltage 2.5V −5% to 3.3V +10% 2.375 3.6 V
VOH Output HIGH Voltage VDDQ = 3.3V , VDD = Min., IOH = –4.0 mA 2.4 V
VDDQ = 2.5V , VDD = Min., IOH = –2.0 mA 2.0 V
VOL Output LOW Voltage VDDQ = 3.3V , VDD = Min., IOL = 8.0 mA 0.4 V
VDDQ = 2.5V , VDD = Min., IOL = 2.0 mA 0.7 V
VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3V V
VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3V V
VIL Input LOW Voltage[7] VDDQ = 3.3V –0.3 0.8 V
VIL Input LOW Voltage[7] VDDQ = 2.5V –0.3 0.7 V
IXInput Load Current
except ZZ and MODE GND ≤ VI ≤ VDDQ −5 5 µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Output Leakage
Current GND ≤ VI ≤ VDDQ, Out put Disabled −5 5 µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 6- ns cy cl e, 166 MH z 420 mA
7.5-ns c ycle, 133 MHz 375 mA
10-ns cycle, 100 MHz 325 mA
ISB1 Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
6-ns cy cl e, 166 MH z 150 mA
7.5-ns c ycle, 133 MHz 125 mA
10-ns cycle, 100 MHz 115 mA
ISB2 Automatic CS
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
All speeds 10 mA
ISB3 Automatic CS
Power-Down
Current—CMOS Inputs
Max. VDD, Devi ce Des elected, o r
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
6-ns cy cl e, 166 MH z 120 mA
7.5-ns c ycle, 133 MHz 95 mA
10-ns cycle, 100 MHz 85 mA
ISB4 Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0 18 mA
Capacitance[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
6pF
CCLK Clock Input C apacitance 8pF
CI/O Input/Output Capacitance 8pF
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
CY7C1347
Document #: 38-05086 Rev. ** Page 9 of 16
AC Test Loads and Waveforms
OUTPUT
R=317Ω
R=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL=50Ω
Z0=50Ω
VL= 1.5V
3.3V ALL INPUT PULSES[10]
2.5V
GND
90%
10% 90%
10%
≤2.5 ns ≤2.5 ns
(c)
Switching Characteristics Over the Operating Range[11, 12, 13 ]
-166 -133 -100
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cyc l e Time 6.0 7.5 10 ns
tCH Clock HIGH 1.7 1.9 3.5 ns
tCL Clock LO W 1.7 1.9 3.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns
tCO Data Output Valid After CLK Rise 3.5 4.0 5.5 ns
tDOH Data Output Hold After CLK Rise 1.5 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns
tWES BWE, GW, BW [3:0] Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tWEH BWE, GW, BW [3:0] Hold After CLK Rise 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns
tDS Data Input Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns
tCES Chip Select Set-Up 2.0 2.5 2.5 ns
tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns
tCHZ Clock to High-Z [12] 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[12] 0 0 0 ns
tOEHZ OE HIGH to Output High-Z[12, 13] 3.5 3.5 5.5 ns
tOELZ OE LOW to Output Low-Z[12, 13] 0 0 0 ns
tOEV OE LOW to Output Valid[12] 3.5 4.0 5.5 ns
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
1 1. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ .
CY7C1347
Document #: 38-05086 Rev. ** Page 10 of 16
1
Switching Waveforms
Wr ite Cycle Ti ming[14, 15]
Notes:
14. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data
In
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVS
t
ADVH
WD1 WD2 WD3
t
AH
t
AS
t
WS
t
WH
t
WH
t
WS
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
2b 3a
1a
Single Write Burst Write Unselected
ADSP ignored with CE
1
inac tive
CE
1
masks ADS P
= DON’T CARE
= UNDEFINED
Pip e lined Write
2a 2c 2d
t
DH
t
DS
High-Z
High-Z
Unselected with CE
2
ADV Mu s t Be Inactive for ADSP Write
ADSC initiated write
CY7C1347
Document #: 38-05086 Rev. ** Page 11 of 16
Read Cycle Timing[14, 16]
Note:
16. RDx stands for Read Data from Address X.
Switching Waveforms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCO
tEOV
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Single Read Burst Read Unselected
ADSP igno red with CE1 inactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
ADSC initiated read
Unselected with CE2
CY7C1347
Document #: 38-05086 Rev. ** Page 12 of 16
Read/Write Cycle Ti min g[14, 15, 16, 17]
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Switching Waveforms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Data In/Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 WD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tEOLZ
tCO
tEOV
3a 3c 3d
1a
tEOHZ tDOH
tCHZ
Single Read Burst Read Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
Out 2a
In 3b
Out
Out Out Out
Single Write
tDS tDH
2a
Out
See Note 17
CY7C1347
Document #: 38-05086 Rev. ** Page 13 of 16
Notes:
18. De vice ori g inal ly dese l ecte d.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Switching Waveforms (continued)
tAS
= DO N’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In/Out
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCO
Pipeline Timing[18, 19]
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back to Back Reads
ADSP initiated Reads
ADSC initiated Reads
CY7C1347
Document #: 38-05086 Rev. ** Page 14 of 16
Switching Waveforms (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
IDD IDD(active)
Three-state
I/Os
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
ZZ Mode Timing [20, 21]
CE2
IDDZZ
HIGH
CY7C1347
Document #: 38-05086 Rev. ** Page 15 of 16
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
166 CY7C1347-166AC A101 100-Lead Thin Quad Flat Pack Commercial
133 CY7C1347-133AC
100 CY7C1347-100AC
CY7C1347-100AI A101 100-Lead Thin Quad Flat Pack Industrial
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
CY7C1347
Document #: 38-05086 Rev. ** Page 16 of 16
Document Title: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM
Document Number: 38-05086
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107346 09/15/01 SZV Change Spec number from: 38-00727 to 38-05086
