QP27C64 March 9, 2009 QP27C64 - 64 Kilobit (8K x 8) CMOS EPROM General Description The QP27C64 is an 8Kx8 (64-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The QP27C64 meets the same specification requirements and utilizes the same programming methodology as the AMD 27C64 that it replaces. Products are available in windowed and non-windowed (OTP) ceramic hermetic packages, as well as plastic one time programmable (OTP) packages. Data is typically accessed in less than 45 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable ( OE ) and Chip Enable ( CE ) pins, eliminating bus contention in a multiple bus system. Typical power consumption is only 80 mW in active mode, and 100 W in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device is programmed identically to the AMD27C64 device that it replaces, using the same programming algorithm (100 us pulses). The QP27C64 features: - Same programming algorithm as the AMD27C64, allowing it to be programmed using the same equipment, data and algorithm. When programming this device select AMD as the manufacturer and 27C64 as the devicetype. - Speed options as fast as 45ns - JEDEC Pinout - Single +5V power supply - CMOS and TTL input/output compatibility - Two line control functions The device/family is constructed using an advanced UV CMOS wafer fabrication process. Block Diagram 2945 Oakmead Village Ct, Santa Clara, CA 95051 * Phone: (408) 737-0992 * Fax: (408) 736--8708 * Internet: www.qpsemi.com QP27C64 Pin Name A0 - A12 CE ( E ) DQ0 - DQ7 Function Address Inputs Chip Enable Input OE ( G ) Data Input/Output Output Enable Input PGM ( P ) Program Enable Input VCC VPP NC VCC Supply Voltage Program Voltage Input No Internal Connection Connection Diagrams CERDIP / CERPACK / PDIP LCC / PLCC Device Type Functional Description Device Erasure In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp with a wavelength of 2537A and an intensity of 12,000 W/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000A, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming Upon delivery, or after each erasure, the device has all of its bits in the "ONE", or HIGH state. "ZEROs" are loaded into the device through the programming procedure. The device enters the programming mode when 12.75V 0.25V is applied to the VPP pin, and both QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 CE & PGM are at Page 2 of 8 QP27C64 VIL. For programming, the data to be programmed is applied 8 bits in parallel to the data pins. The programming algorithm uses a 100 s programming pulse and gives each address only as many pulses as needed to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done with VCC = 6.25 V to assure that each bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Program Inhibit Programming different data to multiple devices in parallel is easily accomplished. Except for devices may be common. A TTL low-level program pulse applied to one device's and PGM LOW will program that particular device. A high-level CE CE CE , all like inputs of the input with VPP = 12.75 V 0.25 V input inhibits the other devices from being programmed. Program Verify Verification should be performed on the programmed bits to determine that they were correctly programmed. Verify should be performed with OE and CE at VIL, PGM at VIH, and VPP between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and device identification through identifier codes on DQ0-DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. Read Mode To obtain data at the device outputs, Chip Enable ( CE ) and Output Enable ( power to the device and is typically used to select the device. OE OE ) must be driven low. CE controls the enables the device to output data, independent of device selection. Addresses must be stable for at least tACC-tOE. Standby Mode The device enters the CMOS standby mode when The device enters the TTL-standby mode when CE CE is at VCC 0.3 V. Maximum VCC current is reduced to 100 A. is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE input. Output OR Connection To accommodate multiple memory connections, a two-line control function provides: CE * Low memory power dissipation * Assurance that output bus contention will not occur. should be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. As a minimum, a 0.1F ceramic capacitor (high frequency, low inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 3 of 8 QP27C64 MODE Select Table Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code Device Code CE OE PGM A0 A9 VPP Outputs VIL X VIH VCC0.3V VIL VIL VIH VIL VIL VIL VIH X X X VIL X VIL VIL X X X X VIL VIH X X X X X X X X X X VIL VIH X X X X X X X VH VH X X X X VPP VPP VPP X X DOUT High Z High Z High Z DIN DOUT High Z 01h 15h Notes \1 \1 \1 \1 \1 \1 \1 \1 \2 \3 \4 \1 \2 \3 \4 Notes: \1 X = Either VIH or VIL \2 VH = 12.0V 0.5V \3 A1-A8 & A10-A12 = VIL \4 Device Manufacture Code and Device ID match original AMD device for programming compatibility Absolute Maximum Ratings Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability Condition Units Notes Power Supply (VCC) -0.6 to +7.0 Volts DC Voltage with Respect to VSS All pins except A9, VPP, VCC -0.6 to VCC+0.6 Volts A9 and VPP -0.6 to 14 Volts Storage Temperature Range -65 to +150 C Lead Temperature (soldering, 10 seconds) +300 C Junction Temperature (TJ) +150 C Maximum Operating Temperature Commercial Devices 0 to 70 C Industrial Devices -40 to 85 C Military Temperature Range -55 to 125 C Data Retention 10 Years, minimum Device must not be removed from or inserted into a socket when VCC or VPP is applied. Recommended Operating Conditions Condition Supply Voltage Range (VCC) Input or Output Voltage Range Minimum High-Level Input Voltage (VIH) Maximum Low-Level Input Voltage (VIL) Case Operating Range (Tc) Commercial Devices Industrial Devices Military Temperature Range Units 4.5 to 5.5 0.0 to VCC 2.0 0.8 Volts DC Volts DC Volts DC Volts DC 0 to 70 C -40 to 85 C -55 to 125 C \5 \9 \6 \9 \7 \7 \7 \8 \7 \8 \7 \8 Notes \5 \6 \7 \8 \7 \8 \7 \8 \5 - Minimum DC Input Voltage on input or I/O pins -0.5V. During voltage transitions, the input may overshoot VSS to - QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 4 of 8 QP27C64 2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC+0.5V. During transitions, input and I/O pins may overshoot to VCC +2.0V for periods up to 20ns. \6 - Minimum DC Input Voltage on A9 is -0.5V. During voltage transitions, A9 and VPP may overshoot VSS to -2.0V for periods of up to 20ns. A9 and VPP must not exceed +13.5V at any time. \7 - Do not exceed 125C TC or TJ for plastic package devices. \8 - Maximum PD, Maximum TJ Are Not to Be Exceeded. \9 - During transitions, the inputs may undershoot to -2.0 V dc for periods less than 20 ns. \10 - VPP may be connected directly to VCC except during programming. \11 - Qualification Only. \12 - If not tested, shall be guaranteed to the limits specified. TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Input Load Current Symbol ILI Output Leakage Current ILO Operating Current, TTL ICC TTL Operating Current, CMOS Standby Current, TTL ICC CMOS ISB TTL Conditions -55C TA+125C Unless Otherwise Specified Min Max Unit VIN = 5.5V or 0.0V -10.0 +10.0 A VOIT = 5.5V or 0.0V -10.0 +10.0 A All other inputs at either VCC or GND OE ( G ) = VIL 70ns 65 mA CE ( E ) = VIL 90ns 75 mA VPP = VCC 120ns 65 mA O0-O7 = 0 mA 150ns 60 mA f = 5 MHz 200ns 30 mA 250ns 30 mA 350ns 25 mA OE ( G ) = 0 Vdc 70ns 70 mA CE ( E ) = 0 Vdc 90ns 60 mA VPP = VCC 120ns 55 mA O0-O7 = 0 mA 150ns 50 mA f = 5 MHz 200ns 10 mA All other inputs 250ns 10 mA at VCC or GND 350ns 10 mA OE ( G ) = VIH 70ns 15 mA CE ( E ) = VIH 90ns 2 mA 120ns 2 mA O0-O7 = disabled 150ns 2 mA 200ns 1 mA 250ns 1 mA 350ns 1 mA f = 0 MHz QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 5 of 8 QP27C64 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test Standby Current, CMOS Symbol ISB CMOS Conditions -55C TA+125C Unless Otherwise Specified Min Max Unit OE ( G ) = VCC 70ns 500 A CE ( E ) = VCC 90ns 200 A 120ns 200 A O0-O7 = disabled 150ns 200 A 200ns 140 A 250ns 140 A 350ns 140 A f = 0 MHz VPP Read Current IPP VPP = VCC, CE ( E ) = VCC 0.2V 100 A Input Low Voltage VIL VPP = VCC 0.8 V Input High Voltage VIH VPP = VCC Output Low Voltage VOL VIL=0.8V,VIH=2.0V 2.0 IOL= 2.1mA Output High Voltage VOH VIL=0.8V,VIH=2.0V V All except 70ns 0.45 V 70ns only 0.40 V 2.4 V IOL= -400 A Output Short Circuit Current IOS VCC = 5.5V, VOUT = 0.0V 100 mA VCC V VIN = 0V 10 pF 12 pF Duration not to exceed 1 second, one output at a time VPP Read Voltage \10 VPP Input Capacitance \11 CIN VCC - 0.7 Output Capacitance \11 COUT VOUT = 0V Address to Output Delay tACC OE ( G ) = VIL 70ns 70 ns CE ( E ) = VIL 90ns 90 ns 120ns 120 ns 150ns 150 ns 200ns 200 ns 250ns 250 ns 350ns 350 ns VPP = VCC QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 6 of 8 QP27C64 TABLE I - ELECTRICAL PERFORMANCE CHARACTERISTICS Test CE Symbol TCE to Output Delay Conditions -55C TA+125C Unless Otherwise Specified OE ( G ) = VIL VPP = VCC OE TOE to Output Delay CE ( E ) = VIL VPP = VCC OE High to Output Float \12 TDF CE ( E ) = VIL VPP = VCC TOH Output hold from Addresses, OE or CE Whichever Occurred First \12 Min Max Unit 70ns 70 ns 90ns 90 ns 120ns 120 ns 150ns 150 ns 200ns 200 ns 250ns 250 ns 350ns 350 ns 70ns 30 ns 90ns 30 ns 120ns 35 ns 150ns 45 ns 200ns 75 ns 250ns 100 ns 350ns 120 ns 70ns 0 25 ns 90ns 0 25 ns 120ns 0 35 ns 150ns 0 40 ns 200ns 0 55 ns 250ns 0 55 ns 350ns 0 105 ns CE ( E ) = VIL 70ns 10 ns OE ( G ) = VIL 90ns 0 ns 120ns 0 ns 150ns 0 ns 200ns 0 ns 250ns 0 ns 350ns 0 ns VPP = VCC QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 7 of 8 QP27C64 Ordering Information Part Number 8510201YA 8510201ZA 8510202YA 8510202ZA 8510203YA 8510203ZA 8510204YA 8510204ZA 8510205YA 8510205ZA 8510206YA 8510206ZA 8510207YA 8510207ZA Package (Mil-Std-1835) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) GDIP1-T28 CDIP2-T28 (DIP) CQCC1-N32 (LCC) Generic QP27C64-25/YA QP27C64-25/ZA QP27C64-35/YA QP27C64-35/ZA QP27C64-20/YA QP27C64-20/ZA QP27C64-90/YA QP27C64-90/ZA QP27C64-12/YA QP27C64-12/ZA QP27C64-15/YA QP27C64-15/ZA QP27C64-70/YA QP27C64-70/ZA QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product family. Notes: Package outline information and specifications are defined by Mil-Std-1835 package dimension requirements. "-MIL" products manufactured by QP Semiconductor are compliant to the assembly, burn-in, test and quality conformance requirements of Test Methods 5004 & 5005 of Mil-Std-883 for Class B devices. This datasheet defines the electrical test requirements for the device(s). The listed drawings, Mil-PRF-38535, Mil-Std-883 and Mil-Std-1835 are available online at http://www.dscc.dla.mil/ Additional information is available at our website http://www.qpsemi.com QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 8 of 8