Version 14.1 Altera Product Catalog CONTENTS OVERVIEW Altera(R) Solutions Portfolio 1 DEVICES Generation 10 Device Portfolio 3 28 nm Device Portfolio 11 40 nm Device Portfolio 31 60 nm Device Portfolio 38 MAX CPLD Series 44 (R) Enpirion Power Portfolio Configuration Devices (R) 47 52 ORDERING CODES Ordering Codes 53 DESIGN TOOLS Quartus(R) II Software Altera SDK for OpenCLTM SoC Embedded Design Suite Nios(R) II Processor Embedded Design Suite 59 62 63 64 O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S SoC Operating System Support Nios II Processor Operating System Support Nios II Processor Altera's Customizable Processor Portfolio 65 66 67 69 INTELLECTUAL PROPERTY Altera and Partner Functions 70 PROTOCOLS Transceiver Protocols 74 DEVELOPMENT KITS Altera and Partner Development Kits SoC System on Modules 76 90 TRAINING Training Overview Instructor-Led, Virtual, and Online Classes Online Training 91 92 93 REFERENCES 2Altera Product Catalog * Glossary 2015 * www.altera.com 96 OVERVIEW Altera S olutions Por tfolio Altera delivers the broadest portfolio of programmable logic devices--FPGAs, SoCs, and CPLDs in combination with software tools, intellectual property (IP), embedded processors, customer support, and technical training. Altera's product leadership, excellent value, and superior quality of service give you a measurable advantage. Bring your great ideas to life faster, better, and more cost effectively. High-End FPGA and SoC Midrange FPGA and SoC Lowest Cost and Power FPGA and SoC FPGAs Altera FPGAs give you the flexibility to innovate, differentiate, and stay ahead in the market. We have three classes of FPGAs to meet your market needs, from the industry's highest density and performance to the most cost effective. High-End FPGAs Midrange FPGAs Lowest Cost and Power FPGAs Highest bandwidth, highest density Balanced cost, power, and performance Lowest system cost and power Integrated transceiver variants Integrated transceiver and processor variants Integrated transceiver and processor variants Design entire systems on a chip Comprehensive design protection Fastest time to market SoCs SoCs bring high integration and advanced system, power, and security management capabilities to your platform. Altera SoCs are supported by industry-standard ARM(R) tools and a broad ecosystem of operating systems and development tools. High-End SoCs Midrange SoCs Lowest Cost and Power SoCs 64 bit quad-core ARM Cortex(R)-A53 processor 32 bit dual-core ARM Cortex-A9 processor 32 bit dual-core ARM Cortex-A9 processor 1.5 GHz maximum CPU frequency 1.5 GHz maximum CPU frequency 925 MHz maximum CPU frequency Performance/power efficiency Hardened floating-point digital signal processing (DSP) Broad ecosystem support Virtualization support Ease of software migration ARM Development Studio 5 (DS-5TM) Altera Edition tools Altera Product Catalog * 2015 * www.altera.com1 OVERVIEW Non-Volatile FPGA For customers seeking a cost-effective, low-power, single-chip solution for control plane or datapath applications, MAX 10 FPGAs provide a highly integrated system solution. CPLDs For glue logic and any control functions, our non-volatile MAX series offers the market's lowest cost CPLDs--a single-chip solution, great for interface bridging, level shifting, I/O expansion, and management of analog I/Os. Power Solutions Power your FPGA with Enpirion power management products. Our integrated products provide an industry-leading combination of small footprint, low noise performance, and high efficiency to complete your design faster. Productivity-Enhancing Design Software, Embedded Processing, IP, Development Kits, and Training With Altera, you get a complete design environment and a wide choice of design tools--all built to work together easily so your designs are up and running fast. You can try one of our training classes to get a jump-start on your designs. Choose Altera and see how we enhance your productivity and make a difference to your bottom line. 2Altera Product Catalog * 2015 * www.altera.com D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O Ar r ia 10 GX FPGA Features www.altera.com/selector The following features, packages, and I/O matrices give you an overview of our devices. For more details about these devices or previous generation devices that are available, check out our online selector guide at www.altera.com/selector. Arria 10 GX FPGAs: Up to 96 full-duplex transceivers with data rates up to 17.4 Gbps, 16 Gbps backplane, and up to 1,150K equivalent logic elements (LEs). Maximum Resource Count for Arria 10 GX FPGAs1 10AX016 10AX022 10AX027 10AX032 10AX048 10AX057 10AX066 10AX090 10AX115 61,510 83,730 101,620 118,730 181,790 217,080 250,540 339,620 427,200 160 220 270 320 480 570 660 900 1,150 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160 1,358,480 1,708,800 M20K memory blocks 440 588 750 891 1,438 1,800 2,133 2,423 2,713 M20K memory (Mb) 9 11 15 17 28 35 42 47 53 MLAB memory (Mb) 1.0 1.8 2.4 2.8 4.3 5.0 5.7 9.2 12.7 Variable-precision DSP 156 192 800 985 1,368 1,612 1,855 1,518 1,518 18 x 19 multipliers 312 382 1,660 1,970 2,736 3,046 3,356 3,036 3,036 8 16 16 16 Adaptive logic modules (ALMs) Architectural Features Resources LEs (K) Registers Global clock networks Regional clock networks 32 8 8 8 Design security 8 8 Bitstream encryption with authentication I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.02 3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL I/O Features I/O standards supported LVDS channels, 1.6 Gbps (receive/transmit) 120 168 168 222 324 3 On-chip termination (OCT) Series, parallel, and differential PCI Express (PCIe ) hard IP blocks (Gen3) (R) (R) Memory devices supported 2 120 Embedded dynamic phase alignment (DPA) circuitry Transceiver count 1 All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-18 (I and II), SSTL-15 (I and II), SSTL-135, SSTL-125, SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-135, Differential SSTL-125, Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 324 384 384 12 12 24 24 36 48 48 96 96 1 1 2 2 2 2 2 4 4 DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.0 V compliant, requires a 3.0 V power supply. Altera Product Catalog * 2015 * www.altera.com3 D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O Ar r ia 10 GT FPGA Features Arria 10 GT FPGAs: Up to 96 full-duplex optimized transceivers with data rates up to 28.1 Gbps, and up to 1,150K equivalent LEs. Maximum Resource Count for Arria 10 GT FPGAs1 10AT090 10AT115 ALMs 339,620 427,200 LEs (K) 900 1,150 1,358,480 1,708,800 M20K memory blocks 2,423 2,713 M20K memory (Mb) 47 53 MLAB memory (Mb) 9.2 12.7 Variable-precision DSP blocks 1,518 1,518 18 x 19 multipliers 3,036 3,036 Architectural Features Resources Registers Global clock networks 32 Regional clock networks 16 Design security 16 Bitstream encryption with authentication I/O voltage levels supported (V) 1.2, 1.25, 1.35, 1.8, 2.5, 3.02 3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125, Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O Features I/O standards supported LVDS channels, 1.6 Gbps (receive/transmit) 312 Embedded DPA circuitry 3 OCT Series, parallel, and differential Transceiver count 96 96 PCIe hard IP blocks (Gen3) 4 4 Memory devices supported 1 2 312 DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.0 V compliant, requires a 3.0 V power supply. 4Altera Product Catalog * 2015 * www.altera.com D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O Ar r ia 10 SX S oC Features The 20 nm Arria 10 SoCs deliver all the features and benefits of Arria 10 FPGAs plus a second-generation hard processor system with 87 percent higher processor performance (1.5 GHz dual-core ARM Cortex-A9 MPCoreTM processor) and enhancements, such as Secure Boot, three Ethernet media access controller (EMAC) hard IP cores, and 64 bit DDR4 SDRAM support--all while maintaining full software compatibility with 28 nm SoCs. Maximum Resource Count for Arria 10 SX SoCs1 10AS016 10AS022 10AS027 10AS032 10AS048 10AS057 10AS066 ALMs 61,510 83,730 101,620 118,730 181,790 217,080 250,540 LEs (K) 160 220 270 320 480 570 660 246,040 334,920 406,480 474,920 727,160 868,320 1,002,160 M20K memory blocks 440 588 750 891 1,438 1,800 2,133 M20K memory (Mb) 9 11 15 17 28 35 42 MLAB memory (Mb) 1 1.8 2.4 2.8 4.3 5.0 5.7 DSP blocks 156 192 800 985 1,368 1,612 1,855 18 x 19 multipliers 312 382 1,660 1,970 2,736 3,046 3,356 8 8 16 Architectural Features Resources Registers Global clock networks Regional clock networks 32 8 8 8 I/O voltage levels supported (V) 8 1.2, 1.25, 1.35, 1.8, 2.5, 3.02 3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL I/O Features I/O standards supported LVDS channels, 1.6 Gbps (receive/transmit) All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-135, SSTL-125, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-135, Differential SSTL-125, Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-12, Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 120 120 168 Embedded DPA circuitry 270 270 Series, parallel, and differential Transceiver count 12 12 24 24 36 48 48 PCIe hard IP blocks (Gen3) 1 1 2 2 2 2 2 Memory devices supported 2 222 3 OCT 1 168 DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.0 V compliant, requires a 3.0 V power supply. Altera Product Catalog * 2015 * www.altera.com5 D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O Ar r ia 10 SX S oC Features Maximum Resource Count for Arria 10 SX SoCs1 10AS016 Central processing unit (CPU) core CPU cache and co-processors Scratch pad RAM Hard Processor System 10AS027 10AS032 10AS048 Direct memory access (DMA) controller EMAC 10AS066 Dual-core ARM Cortex-A9 MPCore processor L1 instruction cache (32 KB) L1 data cache (32 KB) Layer 2 cache (512 KB) shared Floating-point unit (FPU) single and double precision ARM NeonTM media engine ARM CoreSightTM debug and trace technology Snoop control unit (SCU) Acceleration coherency port (ACP) DDR4, DDR3, and LP DDR3 [Up to 64 bit with error correction code (ECC)] 8 channel 3 x 10/100/1000 EMAC with integrated DMA USB on-the-go (OTG) controller UART controller 2 x USB OTG with integrated DMA 2 x UART 16550 compatible Serial peripheral interface (SPI) controller 4 x SPI I2C controller 5 x I2C Quad SPI flash controller 1 x SIO, DIO, QIO SPI flash supported SD/SDIO/MMC controller 1 x eMMC 4.5 with DMA and CE-ATA support 1 x ONFI 1.0 or later 8 and 16 bit support NAND flash controller General-purpose timers 7X Software-programmable general-purpose I/Os (GPIOs) Maximum 54 GPIOs Direct shared I/Os 48 I/Os to connect HPS peripherals directly to I/O Watchdog timers 4X Security Secure boot, Advanced Encryption Standard (AES), and secure hash algorithm All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 6Altera Product Catalog 10AS057 256 KB Hard processor system (HPS) DDR memory 1 10AS022 * 2015 * www.altera.com D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O Ar r ia 10 FPGA S er ies Pack age and I/O M atr ices Arria 10 GX/GT FPGAs1 UBGA (U) FBGA (F) 484 pin (U19) 672 pin (F27) 780 pin (F29) 10AX016 192, 48, 72, 6 240, 48, 96, 12 288, 48, 120, 12 10AX022 192, 48, 72, 6 19 x 19 (mm) 0.8-mm pitch 27 x 27 (mm) 1.0-mm pitch 29 x 29 (mm) 1.0-mm pitch 1,152 pin (F34) 1,152 pin (F35) 35 x 35 (mm) 1.0-mm pitch 240, 48, 96, 12 288, 48, 120, 12 10AX027 240, 48, 96, 12 360, 48, 156, 12 384, 48, 168, 24 384, 48, 168, 24 10AX032 240, 48, 96, 12 360, 48, 156, 12 384, 48, 168, 24 384, 48, 168, 24 10AX048 360, 48, 156, 12 1,152 pin (F36) 35 x 35 (mm) 1.0-mm pitch 35 x 35 (mm) 1.0-mm pitch 492, 48, 222, 24 396, 48, 174, 36 10AX057 492, 48, 222, 24 396, 48, 174, 36 432, 48, 192, 36 10AX066 492, 48, 222, 24 396, 48, 174, 36 432, 48, 192, 36 10AX090 504, 0, 252, 24 432, 0, 216, 36 10AX115 504, 0, 252, 24 432, 0, 216, 36 Arria 10 GX/GT FPGAs1 FBGA (F) 1,517 pin (F40) 1,517 pin (F40) 10AX057 696, 96, 324, 36 588, 48, 270, 48 10AX066 696, 96, 324, 36 588, 48, 270, 48 40 x 40 (mm) 1.0-mm pitch 40 x 40 (mm) 1.0-mm pitch 1,517 pin (F40) 1,932 pin (F45) 1,932 pin (F45) 1,932 pin (F45) 40 x 40 (mm) 1.0-mm pitch 45 x 45 (mm) 1.0-mm pitch 45 x 45 (mm) 1.0-mm pitch 45 x 45 (mm) 1.0-mm pitch 10AX027 10AX032 10AX048 10AX090 600, 0, 300, 48 342, 0, 154, 66 768, 0, 384, 48 624, 0, 312, 72 480, 0, 240, 96 10AX115 600, 0, 300, 48 342, 0, 154, 66 768, 0, 384, 48 624, 0, 312, 72 480, 0, 240, 96 10AT090 600, 0, 300, 48 624, 0, 312, 72 480, 0, 240, 96 10AT115 600, 0, 300, 48 624, 0, 312, 72 480, 0, 240, 96 Arria 10 SX SoCs1 UBGA (U) 672 pin (F27) 780 pin (F29) 10AS016 192, 48, 72, 6 240, 48, 96, 12 288, 48, 120, 12 10AS022 192, 48, 72, 6 240, 48, 96, 12 288, 48, 120, 12 10AS027 240, 48, 96, 12 360, 48, 156, 12 10AS032 240, 48, 96, 12 19 x 19 (mm) 0.8-mm pitch 27 x 27 (mm) 1.0-mm pitch 29 x 29 (mm) 1.0-mm pitch 1,152 pin (F34) 1,152 pin (F35) 384, 48, 168, 24 384, 48, 168, 24 35 x 35 (mm) 1.0-mm pitch 35 x 35 (mm) 1.0-mm pitch 1,517 pin (F40) 1,517 pin (F40) 40 x 40 (mm) 1.0-mm pitch 40 x 40 (mm) 1.0-mm pitch 360, 48, 156, 12 384, 48, 168, 24 384, 48, 168, 24 360, 48, 156, 12 492, 48, 222, 24 396, 48, 174, 36 10AS057 492, 48, 222, 24 396, 48, 174, 36 696, 96, 324, 36 588, 48, 270, 48 10AS066 492, 48, 222, 24 396, 48, 174, 36 696, 96, 324, 36 588, 48, 270, 48 10AS048 1 FBGA (F) 484 pin (U19) All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 624, 48, 192, 48 Numbers indicate GPIO count, 3.0 V I/O count, LVDS count, and transceiver count. Vertical migration (same Vcc, GND, in-system programmability (ISP), and input pins). User I/Os may be less than labeled for vertical migration. Arria 10 series devices are offered in extended and industrial temperatures, and RoHS-compliant packages. Altera Product Catalog * 2015 * www.altera.com7 D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O MAX 10 FPGA Features Altera's new MAX 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, instant-on, small form factor programmable logic device. The MAX 10 FPGAs are built on TSMC's 55 nm flash technology, enabling instant-on configuration so you can quickly control the power-up or initialization of other components in the system. The devices also include full-featured FPGA capabilities, such as DSP, analog functionality, Nios II Gen2 embedded processor support, and memory controllers. With a robust set of FPGA capabilities, MAX 10 FPGAs are optimized for a wide range of high-volume, cost-sensitive applications, including: Automotive * * * Built on TSMC's 55 nm high-volume flash process tailored for the automotive industry's rigorous safety and quality requirements Integrated flash provides instant-on behavior for applications requiring fast boot times such as rear-view cameras in advanced driver assistance systems (ADAS) and infotainment displays FPGA-class signal processing acceleration for electric vehicle (EV) applications, such as motor control, battery management, and power conversion Industrial * * * Reduced footprint, increased design security and reliability, and lower system cost Accurate environmental condition sensing and efficient real-time controls for motor control, I/O modules, and Internet of Things (IoT) applications Single-chip support for multiple industrial Ethernet protocols and machine-to-machine (M2M) communication Communications * * 8Altera Product Catalog * 2015 * Analog functionality for sensing board environment allows integration of power-up sequencing and system-monitoring circuitry in a single device High I/O count and software-based system management using the Nios II soft processor enable board management integration in an advanced, reliable single-chip system controller www.altera.com D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O MAX 10 FPGAs Features Maximum Resource Count for MAX 10 FPGAs1 10M02 10M04 10M08 10M16 10M25 10M40 10M50 2,000 4,000 8,000 16,000 25,000 40,000 50,000 M9K memory (Kb) 108 189 378 549 675 1,260 1,638 User flash memory2 (KB) 12 156 172 296 400 736 736 18 x 18 multipliers 16 20 24 45 55 125 144 Single Dual Dual Dual Dual Dual Dual Analog-to-digital converter (ADC), temperature sensing diode (TSD)3 - 1,1 1,1 1,1 2,1 2,1 2,1 Phase-locked loop (PLL)4 2 2 2 4 4 4 4 160 246 250 320 380 500 500 Dedicated transmitter 10 15 15 22 26 30 30 Emulated transmitter 73 114 116 151 181 241 241 Dedicated receiver 73 114 116 151 181 241 241 SRAM only SRAM only SRAM only Architectural Features Resources ALMs Internal configuration LVDS I/O Features GPIO Memory devices supported SRAM, DDR3 SDRAM, DDR2 SDRAM, and LPDDR2 1 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 2 The availability of user flash memory depends on configuration options. 3 The availability of the ADC/TSD varies by package type. Smaller pin-count packages do not have access to the ADC hard IP. 4 The number of PLLs available is dependent on the package option. Altera Product Catalog * 2015 * www.altera.com9 D E V I C E S : G E N E R AT I O N 10 D E V I C E P O R T F O L I O MAX 10 FPGA S er ies Pack age and I/O M atr ices MAX 10 FPGAs--Single Power Supply Devices (3.3 V or 3.0 V)1 MBGA UBGA (U) EQFP (E) M153 153 pin U169 169 pin E144 144 pin 8 x 8 (mm) 0.5 mm pitch2 11 x 11 (mm) 0.8 mm pitch 22 x 22 (mm) 0.5 mm pitch 10M02 C, 112, 9/29 C, 130, 9/38 C, 101, 7/27 10M04 C/F/A, 112, 9/29 C/F/A, 130, 9/38 C/F/A, 101, 10/27 10M08 C/F/A, 112, 9/29 C/F/A, 130, 9/38 C/F/A, 101, 10/27 C/F/A, 130, 9/38 C/F/A, 101, 10/28 10M16 10M25 C/F/A, 101, 10/28 10M40 C/F/A, 101, 10/28 10M50 C/F/A, 101, 10/28 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. "Easy PCB" utilizes 0.8 mm PCB design rules. 1 2 C, 223, 9/29 Indicates feature set options, GPIO count, LVDS transceiver/receiver count. Feature set options: C = Compact (single image), F= Flash (dual image with RSU), A = Analog (analog features block). Each has added premiums. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. MAX 10 FPGAs--Dual Power Supply Devices (1.2 V or 2.5 V)1 WLCSP V36 36 pin V81 81 pin 3 x 3 (mm) 0.4 mm pitch 10M02 UBGA (U) 4 x 4 (mm) 0.4 mm pitch U324 324 pin 15 x 15 (mm) 0.8 mm pitch FBGA (F) F256 256 pin 17 x 17 (mm) 1.0 mm pitch F484 484 pin 23 x 23 (mm) 1.0 mm pitch F672 672 pin 27 x 27 (mm) 1.0 mm pitch C, 160, 9/47 C, 27, 3/7 C/F/A, 246, 15/81 C/F/A, 178, 13/54 C/F/A, 246, 15/81 C/F/A, 178, 13/54 C/F/A, 250, 15/83 C/F/A, 246, 15/81 C/F/A, 178, 13/54 C/F/A, 320, 22/116 10M25 C/F/A, 178, 13/54 C/F/A, 360, 24/136 C/F/A, 380, 26/146 10M40 C/F/A, 178, 13/54 C/F/A, 360, 24/136 C/F/A, 500, 30/192 10M50 C/F/A, 178, 13/54 C/F/A, 360, 24/136 C/F/A, 500, 30/192 10M04 C, 56, 7/17 10M08 10M16 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 1 C, 27, 3/7 Indicates feature set options, GPIO count, LVDS transceiver/receiver count. Feature set options: C = Compact (single image), F= Flash (dual image with RSU), A = Analog (analog features block). Each has added premiums. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. 10Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Stratix V GT FPGA Features Maximum Resource Count for Stratix V GT FPGAs (0.85 V)1 5SGTC5 5SGTC7 ALMs 160,400 234,720 LEs (K) 425 622 641,600 938,880 M20K memory blocks 2,304 2,560 M20K memory (Mb) 45 50 MLAB memory (Mb) 4.9 7.16 Variable-precision DSP blocks 256 256 18 x 18 multipliers 512 512 Architectural Features Resources Registers Global clock networks 16 Regional clock networks 92 Design security 3 I/O voltage levels supported (V) I/O Features I/O standards supported LVDS channels, 1.4 Gbps (receive/transmit) 150 Memory devices supported 150 3 OCT PCIe hard IP blocks (Gen3) 2 LVCMOS, PCITM, PCI-XTM, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 Embedded DPA circuitry Transceiver count (28.05 Gbps/14.1 Gbps) 1 1.2, 1.5, 1.8, 2.5, 3.32 Series, parallel, and differential 4/32 4/32 1 1 DDR3, DDR2, QDR II, QDR II+, RLDRAM II, RLDRAM 3 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.3 V compliant, requires a 3.0 V power supply. Altera Product Catalog * 2015 * www.altera.com11 DEVICES: 28 nm DEVICE PORTFOLIO Stratix V GX FPGA Features Maximum Resource Count for Stratix V GX FPGAs (0.85 V)1 5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9 5SGXBB ALMs 128,300 158,500 185,000 234,720 317,000 359,200 185,000 225,400 317,000 359,200 LEs (K) 340 420 490 622 840 952 490 597 840 952 513,200 634,000 740,000 938,880 740,000 901,600 1,268,000 1,436,800 M20K memory blocks 957 1,900 2,304 2,560 2,640 2,640 2,100 2,660 2,640 2,640 M20K memory (Mb) 19 37 45 50 52 52 41 52 52 52 MLAB memory (Mb) 3.92 4.84 5.65 7.16 9.67 10.96 5.65 6.88 9.67 10.96 Variable-precision DSP blocks 256 256 256 256 352 352 399 399 352 352 18 x 18 multipliers 512 512 512 512 704 704 798 798 704 704 Architectural Features Resources Registers Global clock networks 16 Regional clock networks 92 Design security 3 I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.32 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 ((I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O Features I/O standards supported LVDS channels, 1.4 Gbps (receive/transmit) 174 174 210 210 210 150 150 150 150 3 Series, parallel, and differential Transceiver count (14.1 Gbps) 36 36 48 48 48 48 66 66 66 66 PCIe hard IP blocks (Gen3) 2 2 4 4 4 4 4 4 4 4 Memory devices supported 2 210 Embedded DPA circuitry OCT 1 1,268,000 1,436,800 DDR3, DDR2, QDR II, QDR II+, RLDRAM II, RLDRAM 3 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.3 V compliant, requires a 3.0 V power supply. 12Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Stratix V GS FPGA Features Maximum Resource Count for Stratix V GS FPGAs (0.85 V)1 5SGSD3 5SGSD4 5SGSD5 5SGSD6 5SGSD8 ALMs 89,000 135,840 172,600 220,000 262,400 LEs (K) 236 360 457 583 695 356,000 543,360 690,400 880,000 1,049,600 M20K memory blocks 688 957 2,014 2,320 2,567 M20K memory (Mb) 13 19 39 45 50 MLAB memory (Mb) 2.72 4.15 5.27 6.71 8.01 Variable-precision DSP blocks 600 1,044 1,590 1,775 1,963 18 x 18 multipliers 1,200 2,088 3,180 3,550 3,926 Architectural Features Resources Registers Global clock networks 16 Regional clock networks 92 Design security 3 I/O voltage levels supported (V) I/O Features I/O standards supported LVDS channels, 1.4 Gbps (receive/transmit) 2 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 108 174 Embedded DPA circuitry 174 210 210 3 OCT Series, parallel, and differential Transceiver count (14.1 Gbps) 24 36 36 48 48 PCIe hard IP blocks (Gen3) 1 1 1 2 2 Memory devices supported 1 1.2, 1.5, 1.8, 2.5, 3.32 DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.3 V compliant, requires a 3.0 V power supply. Altera Product Catalog * 2015 * www.altera.com13 DEVICES: 28 nm DEVICE PORTFOLIO Stratix V E FPGA Features Maximum Resource Count for Stratix V E FPGAs (0.85 V)1 5SEE9 5SEEB ALMs 317,000 359,200 LEs (K) 840 952 1,268,000 1,436,800 M20K memory blocks 2,640 2,640 M20K memory (Mb) 52 52 MLAB memory (Mb) 9.67 10.96 Variable-precision DSP blocks 352 352 18 x 18 multipliers 704 704 Architectural Features Resources Registers Global clock networks 16 Regional clock networks 92 Design security 3 I/O voltage levels supported (V) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O Features I/O standards supported LVDS channels, 1.4 Gbps (receive/transmit) 210 Embedded DPA circuitry Series, parallel, and differential Memory devices supported 2 210 3 OCT 1 1.2, 1.5, 1.8, 2.5, 3.32 DDR3, DDR2, QDR II, QDR II+, RLDRAM II, RLDRAM 3 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 3.3 V compliant, requires a 3.0 V power supply. 14Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Stratix V FPGA S er ies Pack age and I/O M atr ices Stratix V GS, GX, GT, and E FPGAs (0.85 V)1 FBGA (F) 780 pin 1,152 pin 1,152 pin 1,517 pin 1,517 pin 29 x 29 (mm) 1.0-mm pitch 35 x 35 (mm) 1.0-mm pitch 5SGSD3 360, 90, 122 432, 108, 24 5SGSD4 360, 90, 12 432, 108, 24 696, 174, 36 552, 138, 24 696, 174, 36 2 5SGSD5 35 x 35 (mm) 1.0-mm pitch 5SGSD6 5SGSD8 5SGXA3 360, 90, 12 40 x 40 (mm) 1.0-mm pitch 40 x 40 (mm) 1.0-mm pitch 1,760 pin 42.5 x 42.5 (mm) 1.0-mm pitch 1,932 pin 45 x 45 (mm) 1.0-mm pitch 696, 174, 36 840, 210, 48 696, 174, 36 840, 210, 48 432, 108, 24 432, 108, 36 696, 174, 36 5SGXA4 552, 138, 24 432, 108, 36 696, 174, 36 5SGXA5 552, 138, 24 432, 108, 36 696, 174, 36 600, 150, 48 840, 210, 48 5SGXA7 552, 138, 24 432, 108, 36 696, 174, 36 600, 150, 48 840, 210, 48 2 5SGXA9 696, 174, 36 3 840, 210, 48 5SGXAB 696, 174, 363 840, 210, 48 5SGXB5 432, 108, 66 600, 150, 66 5SGXB6 432, 108, 66 600, 150, 66 5SGXB9 600, 150, 663 5SGXBB 600, 150, 663 5SGTC5 600, 150, 364 5SGTC7 600, 150, 364 5SEE9 696, 174, 03 840, 210, 0 5SEEB 696, 174, 03 840, 210, 0 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. Hybrid package (flip chip) FBGA: 33 x 33 (mm) 1.0-mm pitch. 3 Hybrid package (flip chip) FBGA: 45 x 45 (mm) 1.0-mm pitch. 4 GX-GT migration. Unused transceiver channels connected to power/ground. 1 2 264, 66, 24 Numbers indicate GPIO count, LVDS count, and transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). User I/Os may be less than labelled for vertical migration. Stratix series devices are offered for commercial and industrial temperatures and RoHS-compliant packages. Stratix IV GT devices are only offered for industrial temperatures (0C to 100C). Altera Product Catalog * 2015 * www.altera.com15 DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V GX FPGA Features Maximum Resource Count for Arria V GX FPGAs (1.1 V, 1.15 V)1 5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7 ALMs 28,302 58,900 71,698 91,680 113,208 136,880 158,491 190,240 LEs (K) 75 156 190 242 300 362 420 504 113,208 235,600 286,792 366,720 452,832 547,520 633,964 760,960 M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414 M10K memory (Kb) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140 MLAB memory (Kb) 463 961 1,173 1,448 1,852 2,098 2,532 2,906 Variable-precision DSP blocks 240 396 600 800 920 1,045 1,092 1,156 18 x 18 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,312 12 12 16 16 Architectural Features Resources Registers Global clock networks 16 10 PLLs2 10 12 Design security 3 I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O standards supported I/O Features 12 LVDS transmitter (TX) 70 70 120 120 160 160 160 160 LVDS receiver (RX) 80 80 136 136 176 176 176 176 Embedded DPA circuitry 3 OCT Series and differential External Memory Interfaces Programmable drive strength 3 Transceiver count (6.5536 Gbps) 9 9 24 24 24 24 36 36 PCIe hard IP blocks (Gen2 x4) 1 1 2 2 2 2 2 2 Hard memory controllers3 2 2 4 4 4 4 4 4 Memory devices supported DDR3, DDR2, DDR II+4, QDR II, QDR II+, RLDRAM II, LPDDR4, LPDDR24 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit error correction code (ECC) support. 4 These memory interfaces are not available as Altera IP. 1 2 16Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V GT FPGA Features Maximum Resource Count for Arria V GT FPGAs (1.1 V, 1.15 V)1 5AGTC3 5AGTC7 5AGTD3 5AGTD7 ALMs 58,900 91,680 136,880 190,240 LEs (K) 156 242 362 504 235,600 366,720 547,520 760,960 M10K memory blocks 1,051 1,366 1,726 2,414 M10K memory (Kb) 10,510 13,660 17,260 24,140 MLAB memory (Kb) 961 1,448 2,098 2,906 Variable-precision DSP blocks 396 800 1,045 1,156 18 x 18 multipliers 792 1,600 2,090 2,312 12 16 Architectural Features Resources Registers Global clock networks PLLs2 16 10 12 Design security 3 I/O voltage levels supported (V) I/O Features I/O standards supported 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 LVDS transmitter (TX) 70 120 160 160 LVDS receiver (RX) 80 136 176 176 Embedded DPA circuitry 3 OCT Series and differential External Memory Interfaces Programmable drive strength 3 Transceiver count (10.3125 Gbps/6.5536 Gbps)3 4/3 12/6 12/6 20/6 PCIe hard IP blocks (Gen2 x4) 1 2 2 2 Hard memory controllers4 2 4 4 4 Memory devices supported DDR3, DDR2, DDR II+5, QDR II, QDR II+, RLDRAM II, LPDDR5, LPDDR25 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 One pair of 10 Gbps transceiver channels can be configured as three 6 Gbps transceiver channels. 4 With 16 and 32 bit ECC support. 5 These memory interfaces are not available as Altera IP. 1 2 Altera Product Catalog * 2015 * www.altera.com17 DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V GZ FPGA Features Maximum Resource Count for Arria V GZ FPGAs (0.85 V)1 5AGZE1 5AGZE3 5AGZE5 5AGZE7 ALMs 83,020 135,840 150,960 169,800 LEs (K) 220 360 400 450 332,080 543,360 603,840 679,200 M20K memory blocks 585 957 1,440 1,700 M20K memory (Kb) 11,700 19,140 28,800 34,000 MLAB memory (Kb) 2,594 4,245 4,718 5,306 800 1,044 1,092 1,139 1,600 2,088 2,184 2,278 24 24 Resources Registers Variable-precision DSP blocks Architectural Features 18 x 18 multipliers Global clock networks 16 20 PLLs2 20 Design security 3 I/O voltage levels supported (V) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 ((I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O standards supported I/O Features 1.2, 1.5, 1.8, 2.5, 3.0, 3.33 LVDS transmitter (TX) 99 99 166 166 LVDS receiver (RX) 108 108 168 168 Embedded DPA circuitry 3 OCT Series and differential External Memory Interfaces Programmable drive strength 3 Transceiver count (12.5 Gbps) 24 24 36 36 PCIe hard IP blocks (Gen2 x8, Gen3) 1 1 1 1 Memory devices supported DDR3, DDR2, QDR II, QDR II+, RLDRAM II, RLDRAM 3 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 3.3 V compliant, requires a 3.0 V power supply. 1 2 18Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V SX S oC Features Maximum Resource Count for Arria V SX SoCs (1.1 V)1 5ASXB3 5ASXB5 ALMs 132,075 174,340 LEs (K) 350 462 528,300 697,360 M10K memory blocks 1,729 2,282 M10K memory (Kb) 17,290 17,290 MLAB memory (Kb) 2,014 2,658 809 1,090 18 x 18 multipliers 1,618 2,180 Processor cores (ARM Cortex-A9) Dual Dual Resources Registers Architectural Features Variable-precision DSP blocks Maximum CPU clock frequency 1.05 GHz Global clock networks PLLs2 (FPGA) 14 14 PLLs (HPS) 3 3 2 Design security 3 I/O voltage levels supported (V) I/O Features 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O standards supported LVDS transmitter (TX) 136 136 LVDS receiver (RX) 120 120 Embedded DPA circuitry 3 OCT Series and differential Programmable drive strength 3 Transceiver count (6.5536 Gbps) 30 30 PCIe hard IP blocks (Gen2 x4) 2 2 540 540 208 208 Hard memory controllers (FPGA) 3 3 Hard memory controllers (HPS) 1 1 GPIOs (FPGA) GPIOs (HPS) 3 3 External Memory Interfaces 1.05 GHz 16 Memory devices supported DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, LPDDR24, SDR All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit ECC support. 4 These memory interfaces are not available as Altera IP. 1 2 Altera Product Catalog * 2015 * www.altera.com19 DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V ST S oC Features Resources Maximum Resource Count for Arria V ST SoCs (1.1 V)1 5ASTD3 5ASTD5 ALMs 132,075 174,340 LEs (K) 350 462 528,300 697,360 M10K memory blocks 1,729 2,282 M10K memory (Kb) 17,290 17,290 MLAB memory (Kb) 2,014 2,658 809 1,090 18 x 18 multipliers 1,618 2,180 Processor cores (ARM Cortex-A9) Dual Dual 1.05 GHz 1.05 GHz Registers Architectural Features Variable-precision DSP blocks Maximum CPU clock frequency Global clock networks 16 PLLs (FPGA) 14 14 PLLs (HPS) 3 3 2 2 Design security 3 I/O voltage levels supported (V) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O Features I/O standards supported LVDS transmitter (TX) 136 136 LVDS receiver (RX) 120 120 Embedded DPA circuitry 3 OCT Series and differential Programmable drive strength 3 Transceiver count (10.3125 Gbps/6.5536 Gbps) 16/30 16/30 PCIe hard IP blocks (Gen2 x4) 2 2 GPIOs (FPGA) 540 540 GPIOs (HPS) 208 208 Hard memory controllers (FPGA) 3 3 Hard memory controllers (HPS) 1 1 3 3 External Memory Interfaces 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Memory devices supported DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, LPDDR24, SDR All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit ECC support. 4 These memory interfaces are not available as Altera IP. 1 2 20Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V FPGA S er ies Pack age and I/O M atr ices Arria V GX,GT, and GZ FPGAs (0.85 V)1 FBGA (F) 672 pin 27 x 27 (mm) 1.0-mm pitch 5AGXA1 5AGXA3 5AGXA5 5AGXA7 Hybrid FBGA (H) FBGA (F) 780 pin 896 pin 29 x 29 (mm) 1.0-mm pitch 1,152 pin 31 x 31 (mm) 1.0-mm pitch 416 320 9,0 9,0 9,0 336 416 320 9,0 9,0 9,0 336 384 320 9,0 18,0 9,0 24,0 336 384 320 544 9,0 18,0 9,0 24,0 384 320 544 704 18,0 9,0 24,0 24,0 384 320 544 704 18,0 9,0 24,0 24,0 544 704 24,0 36,0 544 704 24,0 36,0 5AGXB3 5AGXB5 5AGXB7 416 320 3,4 3,4 3,4 384 320 6,8 3,4 6,12 384 320 544 704 6,8 3,4 6,12 6,12 544 704 6,12 6,20 5AGTD3 5AGTD7 5AGZE3 5AGZE5 5AGZE7 1 544 336 5AGTC7 5AGZE1 40 x 40 (mm) 1.0-mm pitch 336 5AGXB1 5AGTC3 1,517 pin 35 x 35 (mm) 1.0-mm pitch 544 342 414 12 24 342 414 12 24 534 674 24 36 534 674 24 36 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 636 8,0 For Arria V GX and GT devices, values on top indicate available user I/O pins and values at the bottom indicate the 6.5536 Gbps and 10.3125 Gbps transceiver count. One pair of 10 Gbps transceiver channels can be configured as three 6 Gbps transceiver channels. For Arria V GZ devices, values on top indicate available user I/O pins and values at the bottom indicate the 12.5 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). I/O pins can be migrated across device variants indicated with vertical migration lines of the same color. For vertical migration, the number of user I/Os may be less than the number stated in the table. Vertical migration is possible only if you use up to 320 I/O pins, up to nine 6.5536 Gbps transceiver count (for Arria V GX devices), and up to four 10.3125 Gbps transceiver count (for Arria V GT devices). Altera Product Catalog * 2015 * www.altera.com21 DEVICES: 28 nm DEVICE PORTFOLIO Ar r ia V FPGA S er ies Pack age and I/O M atr ices Arria V SX and ST SoCs (1.1 V)1 FBGA (F) 896 pin 1 1,152 pin 1,517 pin 31 x 31 (mm) 1.0-mm pitch 35 x 35 (mm) 1.0-mm pitch 40 x 40 (mm) 1.0-mm pitch 5ASXB3 250, 208 385, 208 540, 208 5ASXB5 250, 208 385, 208 540, 208 5ASTD3 250, 208 385, 208 540, 208 5ASTD5 250, 208 385, 208 540, 208 12+0 12+0 12+6 12+6 18+0 18+0 18+8 18+8 30+0 30+0 30+16 30+16 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 636, 216 8+0 Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 6.5536 Gbps plus 10.3125 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. 22Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V E FPGA Features Maximum Resource Count for Cyclone(R) V E FPGAs (1.1 V)1 5CEA2 5CEA4 5CEA5 5CEA7 5CEA9 ALMs 9,434 18,480 29,080 56,480 113,560 LEs (K) 25 49 77 149.5 301 37,736 73,920 116,320 225,920 454,240 M10K memory blocks 176 308 446 686 1,220 M10K memory (Kb) 1,760 3,080 4,460 6,860 12,200 MLAB memory (Kb) 196 303 424 836 1,717 Variable-precision DSP blocks 25 66 150 156 342 18 x 18 multipliers 50 132 300 312 684 6 6 Architectural Features Resources Registers Global clock networks PLLs2 16 4 4 Design security 3 I/O voltage levels supported (V) I/O Features I/O standards supported LVDS channels, 875 Mbps receive, 840 Mbps transmit 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS 56 56 3 PCIe hard IP blocks - External Memory Interfaces Memory devices supported 120 120 2 2 Series and differential Programmable drive strength Hard memory controllers2 2 60 - Embedded DPA circuitry OCT 1 6 1 1 2 DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. With 16 and 32 bit ECC support. Altera Product Catalog * 2015 * www.altera.com23 DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V GX FPGA Features Maximum Resource Count for Cyclone V GX FPGAs (1.1 V)1 5CGXC3 5CGXC4 5CGXC5 5CGXC7 5CGXC9 ALMs 13,460 18,868 29,080 56,480 113,560 LEs (K) 35.5 50 77 149.5 301 53,840 75,472 116,320 225,920 454,240 M10K memory blocks 135 250 446 686 1,220 M10K memory (Kb) 1,350 2,500 4,460 6,860 12,200 MLAB memory (Kb) 291 295 424 836 1,717 57 70 150 156 342 114 140 300 312 684 7 8 Resources Registers Variable-precision DSP blocks Architectural Features 18 x 18 multipliers Global clock networks 16 PLLs2 4 6 Design security 3 I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS I/O Features I/O standards supported LVDS channels, 875 Mbps receive, 840 Mbps transmit 52 84 84 120 140 - Embedded DPA circuitry OCT Series and differential Programmable drive strength External Memory Interfaces 6 3 Transceiver count (3.125 Gbps) 3 6 6 9 12 PCIe hard IP blocks (Gen1 x4) 1 2 2 2 2 Hard memory controllers3 1 2 2 2 2 Memory devices supported DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit ECC support. 1 2 24Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V GT FPGA Features Maximum Resource Count for Cyclone V GT FPGAs (1.1 V)1 5CGTD5 5CGTD7 5CGTD9 ALMs 29,080 56,480 113,560 LEs (K) 77 149.5 301 116,320 225,920 454,240 M10K memory blocks 446 686 1,220 M10K memory (Kb) 4,460 6,860 12,200 MLAB memory (Kb) 424 836 1,717 Variable-precision DSP blocks 150 156 342 18 x 18 multipliers 300 312 684 Architectural Features Resources Registers Global clock networks PLLs2 16 6 Design security I/O Features LVDS channels, 875 Mbps receive, 840 Mbps transmit 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS 84 120 140 - Embedded DPA circuitry OCT Series and differential Programmable drive strength External Memory Interfaces 8 3 I/O voltage levels supported (V) I/O standards supported 7 3 Transceiver count (6.144 Gbps)3 6 9 12 PCIe hard IP blocks (Gen2 x1, x2, and x4, Gen1 x4) 2 2 2 Hard memory controllers4 2 2 2 Memory devices supported DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 Automotive grade Cyclone V GT FPGAs come with a 5 Gbps transceiver. 4 With 16 and 32 bit ECC support. 1 2 Altera Product Catalog * 2015 * www.altera.com25 DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V SE S oC Features Maximum Resource Count for Cyclone V GT FPGAs (1.1 V)1 5CSEA2 5CSEA4 5CSEA5 5CSEA6 ALMs 9,434 15,094 32,075 41,509 LEs (K) 25 40 85 110 37,736 60,376 128,300 166,036 M10K memory blocks 140 270 397 557 M10K memory (Kb) 1,400 2,700 3,970 5,570 MLAB memory (Kb) 138 231 480 621 Variable-precision DSP blocks 36 84 87 112 18 x 18 multipliers 72 168 174 224 Single or dual Single or dual Single or dual Single or dual 925 MHz 925 MHz 925 MHz 925 MHz Resources Registers Architectural Features Processor cores (ARM Cortex-A9) Maximum CPU clock frequency Global clock networks 16 PLLs2 (FPGA) 5 5 6 6 PLLs2 (HPS) 3 3 3 3 Design security 3 I/O voltage levels supported (V) 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS I/O standards supported External Memory Interfaces I/O Features LVDS channels, 875 Mbps receive, 840 Mbps transmit 37, 32 37, 32 72, 72 72, 72 - Embedded DPA circuitry OCT Series and differential Programmable drive strength 3 PCIe hard IP blocks - GPIOs (FPGA) 145 145 288 288 GPIOs (HPS) 181 181 181 181 Hard memory controllers3 (FPGA) 1 1 1 1 Hard memory controllers3 (HPS) 1 1 1 1 Memory devices supported DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit ECC support. 1 2 26Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V SX S oC Features Maximum Resource Count for Cyclone V SX SoCs (1.1 V)1 5CSXC2 5CSXC4 5CSXC5 5CSXC6 ALMs 9,434 15,094 32,075 41,509 LEs (K) 25 40 85 110 37,736 60,376 128,300 166,036 M10K memory blocks 140 270 397 557 M10K memory (Kb) 1,400 2,700 3,970 5,570 MLAB memory (Kb) 138 231 480 621 Variable-precision DSP blocks 36 84 87 112 18 x 18 multipliers 72 168 174 224 Dual Dual Dual Dual 925 MHz 925 MHz 925 MHz 925 MHz Resources Registers Architectural Features Processor cores (ARM Cortex-A9) Maximum CPU clock frequency Global clock networks 16 PLLs2 (FPGA) 5 5 6 6 PLLs2 (HPS) 3 3 3 3 Design security 3 I/O voltage levels supported (V) I/O standards supported LVDS channels, 875 Mbps receive, 840 Mbps transmit 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS 37, 32 37, 32 I/O Features 72, 72 - Embedded DPA circuitry External Memory Interfaces 72, 72 OCT Series and differential Programmable drive strength 3 Transceiver count (3.125 Gbps) 6 6 9 9 PCIe hard IP blocks (Gen1 x4) 2 2 23 23 GPIOs (FPGA) 145 145 288 288 GPIOs (HPS) 181 181 181 181 Hard memory controllers4 (FPGA) 1 1 1 1 Hard memory controllers4 (HPS) 1 1 1 1 Memory devices supported DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 One PCIe hard IP block in U672 package. 4 With 16 and 32 bit ECC support. 1 2 Altera Product Catalog * 2015 * www.altera.com27 DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V ST S oC Features Architectural Features Resources Maximum Resource Count for Cyclone V ST SoCs (1.1 V)1 5CSTD5 5CSTD6 ALMs 32,075 41,509 LEs (K) 85 110 128,300 166,036 Registers M10K memory blocks 397 557 M10K memory (Kb) 3,970 5,570 MLAB memory (Kb) 480 621 Variable-precision DSP blocks 87 112 18 x 18 multipliers 174 224 Processor cores (ARM Cortex-A9) Dual Dual 925 MHz 925 MHz Maximum CPU clock frequency Global clock networks 16 PLLs2 (FPGA) 6 6 PLLs2 (HPS) 3 3 Design security 3 I/O voltage levels supported (V) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 ((I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12, HiSpi, SLVS, Sub-LVDS I/O standards supported I/O Features LVDS channels, 875 Mbps receive, 840 Mbps transmit 72 72 - Embedded DPA circuitry OCT Series and differential Programmable drive strength 3 Transceiver count (6.144 Gbps) 9 9 PCIe hard IP blocks (Gen2 x1,x2, and x4, Gen1 x4) 2 2 288 288 181 181 Hard memory controllers (FPGA) 1 1 Hard memory controllers (HPS) 1 1 GPIOs (FPGA) GPIOs (HPS) 3 3 External Memory Interfaces 1.1, 1.2, 1.5, 1.8, 2.5, 3.3 Memory devices supported DDR3, DDR2, LPDDR2 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs. 3 With 16 and 32 bit ECC support. 1 2 28Altera Product Catalog * 2015 * www.altera.com DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V FPGA S er ies Pack age and I/O M atr ices Cyclone V E, GX, and GT FPGAs (1.1 V)1 MBGA (M) 301 pin 11 x 11 (mm) 0.5-mm pitch 383 pin 13 x 13 (mm) 0.5-mm pitch UBGA (U) 484 pin 15 x 15 (mm) 0.5-mm pitch 324 pin 484 pin 256 pin 484 pin 15 x 15 (mm) 0.8-mm pitch 19 x 19 (mm) 0.8-mm pitch 17 x 17 (mm) 1.0-mm pitch 23 x 23 (mm) 1.0-mm pitch 5CEA2 223 176 224 128 224 5CEA4 223 176 224 128 224 5CEA5 175 5CEA7 240 5CEA9 144 5CGXC3 3 672 pin 896 pin 27 x 27 (mm) 1.0-mm pitch 31 x 31 (mm) 1.0-mm pitch 224 240 240 240 336 480 240 224 336 480 208 208 3 129 175 224 240 336 5CGXC5 129 175 224 240 336 240 240 336 480 240 224 336 480 224 240 336 240 240 336 480 240 224 336 480 4 4 6 6 6 6 240 3 5CGXC9 5CGTD5 5CGTD7 6 5 129 4 175 6 6 240 3 5CGTD9 6 5 1,152 pin 35 x 35 (mm) 1.0-mm pitch 3 5CGXC4 5CGXC7 1 FBGA (F) 6 6 6 6 6 6 6 6 6 9 9 9 12 560 12 6 9 9 9 12 560 12 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 636 12 Values on top indicate available user I/O pins; values at the bottom indicate the 3.125 Gbps, 5 Gbps, or 6.144 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. This vertical migration can be achieved if you use only up to 175 GPIOs. Altera Product Catalog * 2015 * www.altera.com29 DEVICES: 28 nm DEVICE PORTFOLIO Cyclone V FPGA S er ies Pack age and I/O M atr ices Cyclone V SE, SX, and ST SoCs (1.1 V)1 UBGA (U) 484 pin 1 FBGA (F) 672 pin 896 pin 19 x 19 (mm) 0.8-mm pitch 23 x 23 (mm) 0.8-mm pitch 5CSEA2 66, 151 145, 181 5CSEA4 66, 151 145, 181 5CSEA5 66, 151 145, 181 288, 181 5CSEA6 66, 151 145, 181 288, 181 0 0 0 0 31 x 31 (mm) 1.0-mm pitch 0 0 0 0 0 0 5CSXC2 145, 181 5CSXC4 145, 181 5CSXC5 145, 181 288, 181 5CSXC6 145, 181 288, 181 6 6 9 9 9 9 5CSTD5 288, 181 5CSTD6 288, 181 9 9 All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com. 636, 161 Values on top indicate available FPGA user I/O pins and HPS I/O pins; values at the bottom indicate the 3.125 Gbps or 5 Gbps transceiver count. 12 Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. This vertical migration can be achieved if you use only up to 138 GPIOs. 30Altera Product Catalog * 2015 * www.altera.com DEVICES: 40 nm DEVICE PORTFOLIO Stratix IV GT FPGA Features Maximum Resource Count for Stratix IV GT FPGAs (0.95 V)1 EP4S40G2 EP4S40G5 EP4S100G2 EP4S100G3 EP4S100G4 EP4S100G5 ALMs 91,200 212,480 91,200 116,480 141,440 212,480 LEs (K) 228 531 228 291 354 531 182,400 424,960 182,400 232,960 282,880 424,960 1,235 1,280 1,235 936 1,248 1,280 22 64 22 36 48 64 MLAB memory (Kb) 2,850 6,640 2,850 3,640 4,420 6,640 Embedded memory (Kb) 14,283 20,736 14,283 13,608 18,144 20,736 18 x 18 multipliers 1,288 1,024 1,288 832 1,024 1,024 Architectural Features Resources Registers2 M9K memory blocks M144K memory blocks Global clock networks 16 Regional clock networks 64 88 64 88 88 88 Periphery clock networks 88 112 88 112 112 112 PLLs 8 8 8 12 12 12 Design security 3 Others Plug & Play Signal Integrity, Programmable Power Technology I/O voltage levels supported (V) I/O Features I/O standards supported Emulated LVDS channels, 1,100 Mbps 1.2, 1.5, 1.8, 2.5, 3.33 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 192 256 192 LVDS channels, 1,600 Mbps (receive/transmit) Memory devices supported 256 3 OCT PCIe hard IP blocks 256 46/46 Embedded DPA circuitry Transceiver count4 (11.3 Gbps/8.5 Gbps/6.5 Gbps) 256 Series, parallel, and differential 12/12/12 12/12/12 24/0/12 24/8/16 24/8/16 32/0/16 2 2 2 4 4 4 DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM 2, SDR Available in industrial temperatures only (0oC to 100oC). The base core logic register count is shown. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent. 3 3.3 V compliant, requires a 3.0 V power supply. 4 The total transceiver count is the sum of the 11.3, 8.5, and 6.5 Gbps transceivers. 1 2 Altera Product Catalog * 2015 * www.altera.com31 DEVICES: 40 nm DEVICE PORTFOLIO Stratix IV GX FPGA Features Maximum Resource Count for Stratix IV GX FPGAs (0.9 V) EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 ALMs 29,040 42,240 70,300 91,200 116,480 141,440 212,480 LEs (K) 73 106 176 228 291 354 531 58,080 84,480 140,600 182,400 232,960 282,880 424,960 M9K memory blocks 462 660 950 1,235 936 1,248 1,280 M144K memory blocks 16 16 20 22 36 48 64 MLAB memory (Kb) 908 1,320 2,197 2,850 3,640 4,420 6,640 6,462 8,244 11,430 14,283 13,608 18,144 20,736 384 512 920 1,288 832 1,040 1,024 Resources Registers1 Embedded memory (Kb) Architectural Features 18 x 18 multipliers Global clock networks 16 Regional clock networks 64 64 64 64 88 88 88 Periphery clock networks 56 56 88 88 88 88 112 PLLs 4 4 8 8 12 12 12 Design security 3 Others Plug & Play Signal Integrity, Programmable Power Technology I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.33 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 I/O standards supported I/O Features 2 Emulated LVDS channels, 1,100 Mbps LVDS channels, 1,600 Mbps (receive/transmit) 128 128 192 192 256 256 256 56/56 56/56 88/88 88/88 98/98 98/98 98/98 Embedded DPA circuitry OCT Series, parallel, and differential Transceiver count (8.5 Gbps/6.5 Gbps)4 PCIe hard IP blocks 16/8 16/8 24/12 24/12 32/16 32/16 32/16 2 2 2 2 4 4 4 Memory devices supported DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM 2, SDR The base core logic register count is shown. The ALM can support three registers when used in LUTREG mode, which increases the total register count by an additional 50 percent. The EP4SGX360N device has 1,024 18 x 18 multipliers. 3 3.3 V compliant, requires a 3.0 V power supply. 4 The total transceiver count is the sum of 8.5 and 6.5 Gbps transceivers. 1 2 32Altera Product Catalog * 2015 * www.altera.com DEVICES: 40 nm DEVICE PORTFOLIO Stratix IV E FPGA Features Maximum Resource Count for Stratix IV E FPGAs (0.9 V) EP4SE230 EP4SE360 EP4SE530 EP4SE820 ALMs 91,200 141,440 212,480 325,220 LEs (K) 228 354 531 813 182,400 282,880 424,960 650,440 1,235 1,248 1,280 1,610 22 48 64 60 MLAB memory (Kb) 2,850 4,420 6,640 10,163 Embedded memory (Kb) 14,283 18,144 20,736 23,130 18 x 18 multipliers 1,288 1,040 1,024 960 Architectural Features Resources Registers1 M9K memory blocks M144K memory blocks Global clock networks 16 Regional clock networks 64 88 88 88 Periphery clock networks 88 88 112 132 PLLs 4 12 12 12 Design security 3 Others Programmable Power Technology I/O voltage levels supported (V) I/O Features I/O standards supported Emulated LVDS channels, 1,100 Mbps LVDS channels, 1,600 Mbps (receive/transmit) Embedded DPA circuitry OCT Memory devices supported 1 2 1.2, 1.5, 1.8, 2.5, 3.32 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 128 256 256 288 56/56 88/88 112/112 132/132 3 Series, parallel, and differential DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM 2, SDR Base core logic register count is shown. The ALM can support three registers when used in LUTREG mode, which can increase the total register count by an additional 50 percent. 3.3 V compliant, requires a 3.0 V power supply. Altera Product Catalog * 2015 * www.altera.com33 DEVICES: 40 nm DEVICE PORTFOLIO Stratix IV FPGA S er ies Pack age and I/O M atr ices FBGA (F)1 780 pin 29 x 29 (mm) 1.0-mm pitch 1,152 pin 35 x 35 (mm) 1.0-mm pitch 1,152 pin 35 x 35 (mm) 1.0-mm pitch 1,760 pin 42.5 x 42.5 (mm) 1.0-mm pitch 12+12+12 6464 EP4S40G5 12+12+12 646 EP4S100G2 24+0+12 769 EP4S100G3 24+8+16 769 EP4S100G4 24+8+16 6464 EP4S100G5 Stratix IV GX FPGAs (0.9 V)2 769 24+0+12 EP4SGX70 368 EP4SGX110 368 EP4SGX180 368 EP4SGX230 368 EP4SGX290 2883 EP4SGX360 2883 8+0 8+0 8+0 16+0 16+0 32+0+16 480 8+0 16+8 368 16+0 560 16+0 560 16+0 560 16+0 560 16+0 480 16+8 560 16+8 560 16+8 560 16+8 560 16+8 5604 EP4SGX530 Stratix IV E FPGAs 1,932 pin 45 x 45 (mm) 1.0-mm pitch 646 EP4S40G2 Stratix IV GT FPGAs (0.95 V) 1,517 pin 40 x 40 (mm) 1.0-mm pitch 16+8 736 24+12 736 24+12 736 24+12 736 24+12 7364 864 24+12 864 24+12 864 24+12 24+12 EP4SE820 7364 9604 1,104 EP4SE530 7364 9604 960 EP4SE360 4802 EP4SE230 480 904 32+16 904 32+16 904 32+16 736 FineLine ball grid array. I/O count does not include dedicated clock inputs that can be used as data inputs. 3 Hybrid package (flip chip) FBGA: 35 x 35 (mm) 1.0-mm pitch. 4 Hybrid package (flip chip) FBGA: 42.5 x 42.5 (mm) 1.0-mm pitch. 1 2 636 Values on top indicate available user I/O pins; values on bottom indicate the sum of 11.3, 8.5, and 6.5 Gbps transceiver count. 636 8+0 Values on top indicate available user I/O pins; values at the bottom indicate the sum of 8.5 and 6.5 Gbps transceiver count. 288 Number indicates available user I/O pins. 12+12+12 Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. Stratix series devices are offered in commercial and industrial temperatures and RoHS-compliant packages. Stratix IV GT devices are only offered in industrial temperatures (0C to 100C). 34Altera Product Catalog * 2015 * www.altera.com DEVICES: 40 nm DEVICE PORTFOLIO Ar r ia II GZ FPGA Features Maximum Resource Count for Arria II GZ FPGAs (0.9 V) EP2AGZ225 EP2AGZ300 EP2AGZ350 ALMs 89,600 119,200 139,400 LEs (K) 224 298 349 179,200 238,400 278,800 1,235 1,248 1,248 0 24 36 MLAB memory (Kb) 2,850 4,420 4,420 Embedded memory (Kb) 11,115 14,688 16,416 800 920 1,040 Resources Registers1 M9K memory blocks M144K memory blocks Architectural Features 18 x 18 multipliers Global clock networks Regional clock networks 16 64 Periphery clock networks PLLs 8 I/O Features LVDS channels, 1,250 Mbps (receive/transmit) Embedded DPA circuitry OCT Transceiver count (6.375 Gbps) External Memory Interfaces PCIe hard IP blocks (Base specification, Rev 1.1, 2.0, etc.) 1 Memory devices supported 8 8 3 I/O voltage levels supported (V) Emulated LVDS channels, 1,152 Mbps 88 88 Design security I/O standards supported 88 1.2, 1.5, 1.8, 2.5, 3.0 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 ((I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 184 184 184 Up to 86 3 Series and differential Up to 24 1 DDR3, DDR2, DDR, QDR II, RLDRAM 2, SDR Base core logic register count is shown. The ALM can support three registers when used in LUTREG mode, which can increase the total register count by an additional 50 percent. Altera Product Catalog * 2015 * www.altera.com35 DEVICES: 40 nm DEVICE PORTFOLIO Ar r ia II GX FPGA Features Resources Maximum Resource Count for Arria II GX FPGAs (0.9 V) EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 ALMs 18,050 25,300 37,470 49,640 76,120 102,600 LEs (K) 43 60 89 118 118 244 36,100 50,600 74,940 99,280 152,240 205,200 M9K memory blocks 319 495 612 730 840 950 MLAB memory (Kb) 564 791 1,171 1,551 2,379 3,206 2,871 4,455 5,508 6,570 7,560 8,550 232 312 448 576 656 736 Registers1 Embedded memory (Kb) Architectural Features 18 x 18 multipliers Global clock networks 16 Regional clock networks 48 Periphery clock networks 50 50 59 59 84 84 PLLs 4 4 6 6 6 6 Design security 3 Others Plug & Play Signal Integrity I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 I/O Features I/O standards supported Emulated LVDS channels, 945 Mbps LVDS channels, 1,250 Mbps (receive/transmit) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 56 56 64 64 96 96 85/84 85/84 105/104 105/104 145/144 145/144 16 16 Embedded DPA circuitry 3 OCT Series and differential External Memory Interfaces Transceiver count (6.375 Gbps) 1 8 8 12 12 PCIe hard IP block (Gen1) 1 Memory devices supported DDR3, DDR2, DDR, QDR II This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent. 36Altera Product Catalog * 2015 * www.altera.com DEVICES: 40 nm DEVICE PORTFOLIO Ar r ia II GZ and GX FPGA S er ies Pack age and I/O M atr ices Arria II GX FPGAs (0.9 V) UBGA (U) FBGA (F) 1 358 pin 572 pin 780 pin 1,152 pin 17 x 17 (mm) 0.8-mm pitch 25 x 25 (mm) 1.0-mm pitch 29 x 29 (mm) 1.0-mm pitch EP2AGX45 156 252 364 EP2AGX65 156 252 364 EP2AGX95 260 372 452 EP2AGX125 260 372 452 EP2AGX190 372 612 EP2AGX260 372 612 4 4 8 35 x 35 (mm) 1.0-mm pitch 8 8 8 8 12 8 12 12 12 12 16 12 16 Ultra FineLine ball grid array. 1 726 24 Values on top indicate available user I/O pins; values at the bottom indicate the 6.375 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. Arria II GZ FPGAs (0.9 V) Hybrid FBGA (H) 780 pin 33 x 33 (mm) 1.0-mm pitch EP2AGZ225 FBGA (F) 1,152 pin 1,517 pin 35 x 35 (mm) 1.0-mm pitch 40 x 40 (mm) 1.0-mm pitch 554 734 16 24 EP2AGZ300 281 554 734 EP2AGZ350 281 554 734 636 12 16 16 16 16 24 24 Values on top indicate available user I/O pins; values at the bottom indicate the 6.375 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. Altera Product Catalog * 2015 * www.altera.com37 DEVICES: 60 nm DEVICE PORTFOLIO Cyclone IV GX FPGA Features Architectural Features Resources Maximum Resource Count for Cyclone IV GX FPGAs (1.2 V) EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150 LEs (K) 14 21 29 50 74 109 150 M9K memory blocks 60 84 120 278 462 666 720 Embedded memory (Kb) 540 756 1,080 2,502 4,158 5,490 6,480 18 x 18 multipliers 0 40 80 140 198 280 360 Global clock networks 20 20 20 30 30 30 30 PLLs 3 4 4 8 8 8 8 I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 External Memory Interfaces I/O Features I/O standards supported 1 2 Emulated LVDS channels 9 40 40 73 73 139 139 LVDS channels, 840 Mbps (receive/transmit) 7/7 14/14 14/14 49/49 49/49 59/59 59/59 Transceiver count1 (2.5 Gbps/3.125 Gbps) 2/0 2, 0 / 4, 0 4, 0 / 0, 42 0, 8 0, 8 0, 8 0, 8 PCIe hard IP blocks (Gen1) 1 Memory devices supported DDR2, DDR, SDR Transceiver performance varies by product line and package offering. EP4CGX30 supports 3.125 Gbps transceivers only in F484 package option. 38Altera Product Catalog * 2015 * www.altera.com DEVICES: 60 nm DEVICE PORTFOLIO Cyclone IV E FPGA Features I/O Features Architectural Features Resources Maximum Resource Count for Cyclone IV E FPGAs EP4CE6 EP4CE10 EP4CE15 LEs (K) 6 10 15 M9K memory blocks 30 46 Embedded memory (Kb) 270 18 x 18 multipliers EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115 22 29 40 56 75 114 56 66 66 126 260 305 432 414 504 594 594 1,134 2,340 2,745 3,888 15 23 56 66 66 116 154 200 266 Global clock networks 10 10 20 20 20 20 20 20 20 PLLs 2 2 4 4 4 4 4 4 4 I/O voltage levels supported (V) I/O standards supported LVDS channels External Memory Interfaces EP4CE22 Memory devices supported 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, SSTL-18 (1 and II), SSTL-15 (I and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), Differential SSTL-18 (I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 66 66 137 52 224 224 160 178 230 DDR2, DDR, SDR Altera Product Catalog * 2015 * www.altera.com39 DEVICES: 60 nm DEVICE PORTFOLIO Cyclone III FPGA Features Architectural Features Resources Maximum Resource Count for Cyclone III FPGAs (1.2 V) EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 LEs (K) 5 10 15 25 40 56 81 119 M9K memory blocks 46 46 56 66 126 260 305 432 Embedded memory (Kb) 414 414 504 594 1,134 2,340 2,745 3,888 18 x 18 multipliers 23 23 56 66 126 156 244 288 Global clock networks 10 10 20 20 20 20 20 20 PLLs 2 2 4 4 4 4 4 4 - Design security I/O Features I/O voltage levels supported (V) 1.2, 1.5, 1.8, 2.5, 3.3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, LVPECL, SSTL-18 (1 and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), Differential SSTL-18 (I and II), Differential SSTL-2 (I and II), Differential HSTL I/O standards supported Emulated LVDS channels, 840 Mbps 66 External Memory Interfaces OCT 136 79 223 Series and differential Memory devices supported 40Altera Product Catalog 66 * 2015 * www.altera.com DDR2, DDR, SDR 159 177 229 DEVICES: 60 nm DEVICE PORTFOLIO Cyclone III LS FPGA Features Resources Maximum Resource Count for Cyclone III LS FPGAs (1.2 V) EP3CLS70 EP3CLS100 EP3CLS150 EP3CLS200 LEs (K) 70 100 151 198 M9K memory blocks 333 483 666 891 2,997 4,347 5,994 8,019 200 276 320 396 Embedded memory (Kb) Architectural Features 18 x 18 multipliers Global clock networks 20 PLLs 4 Design security 3 I/O Features I/O voltage levels supported (V) I/O standards supported LVTTL, LVCMOS, PCI, PCI-X, LVDS, LVPECL, SSTL-18 (1 and II), SSTL-2 (I and II), HSTL-18 (I and II), HSTL-15 (I and II), Differential SSTL-18 (I and II), Differential SSTL-2 (I and II), Differential HSTL LVDS channels, 840 Mbps 169 OCT External Memory Interfaces 1.2, 1.5, 1.8, 2.5, 3.3 Memory devices supported Series and differential DDR2, DDR, SDR Altera Product Catalog * 2015 * www.altera.com41 DEVICES: 60 nm DEVICE PORTFOLIO Cyclone IV GX and E FPGA S er ies Pack age and I/O M atr ices Cyclone IV GX FPGAs (1.2 V) QFN (N)1 FBGA (F) 148 pin 14 x 14 (mm) 1.0-mm pitch 72 72 EP4CGX15 1 169 pin 11 x 11 (mm) 0.5-mm pitch 2 324 pin 19 x 19 (mm) 1.0-mm pitch 484 pin 672 pin 23 x 23 (mm) 1.0-mm pitch 896 pin 27 x 27 (mm) 1.0-mm pitch 31 x 31 (mm) 1.0-mm pitch 2 EP4CGX22 72 150 EP4CGX30 72 150 2 4 2 290 4 4 EP4CGX50 290 310 EP4CGX75 290 310 EP4CGX110 270 393 475 EP4CGX150 270 393 475 4 8 4 8 4 8 4 8 8 8 Quad flat pack, no lead. 636 12 Values on top indicate available user I/O pins; values at the bottom indicate the 2.5 Gbps or 3.125 Gbps transceiver count. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. Cyclone IV E FPGAs (1.0 V and 1.2 V) EQFP (E)1 FBGA (F) 256 pin 144 pin 324 pin 19 x 19 (mm) 1.0-mm pitch MBGA (M) 484 pin 23 x 23 (mm) 1.0-mm pitch 780 pin 29 x 29 (mm) 1.0-mm pitch 164 pin 256 pin 22 x 22 (mm) 0.5-mm pitch 17 x 17 (mm) 1.0-mm pitch EP4CE6 91 179 179 EP4CE10 91 179 179 EP4CE15 81 165 EP4CE22 79 153 343 8 x 8 (mm) 0.5-mm pitch UBGA (U) 74 14 x 14 (mm) 0.8-mm pitch 484 pin 19 x 19 (mm) 0.8-mm pitch 165 153 EP4CE30 193 328 532 EP4CE40 193 328 532 328 EP4CE55 324 374 324 EP4CE75 292 426 292 EP4CE115 280 528 1 Enhanced thin quad flat pack. 636 Number indicates available user I/O pins. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. 42Altera Product Catalog * 2015 * www.altera.com DEVICES: 60 nm DEVICE PORTFOLIO Cyclone III S er ies Pack age and I/O M atr ices Cyclone III FPGAs (1.2 V) EQFP (E) 144 pin MBGA (M)1 164 pin PQFP (Q)2 240 pin 256 pin 17 x 17 (mm) 1.0-mm pitch 324 pin 484 pin 256 pin EP3C5 94 106 182 182 EP3C10 94 106 182 182 EP3C16 84 92 EP3C25 82 168 148 156 128 23 x 23 (mm) 1.0-mm pitch 780 pin 8 x 8 (mm) 0.5-mm pitch 160 19 x 19 (mm) 1.0-mm pitch UBGA (U) 22 x 22 (mm) 0.5-mm pitch EP3C40 34.6 x 34.6 (mm) 0.5-mm pitch FBGA (F) 29 x 29 (mm) 1.0-mm pitch 14 x 14 (mm) 0.8-mm pitch 346 168 215 196 484 pin 19 x 19 (mm) 0.8-mm pitch 346 156 331 535 331 EP3C55 327 377 327 EP3C80 295 429 295 EP3C120 283 531 EP3CLS70 294 429 294 EP3CLS100 294 429 294 EP3CLS150 226 429 EP3CLS200 226 429 Micro FineLine BGA. Plastic quad flat pack. 1 2 636 Number indicates available user I/O pins. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. Altera Product Catalog * 2015 * www.altera.com43 MAX CPLD SERIES MAX V CPLD Features Architectural Features Density and Speed MAX V CPLDs (1.8 V) 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z LEs 40 80 160 240 570 1270 2210 Equivalent macrocells1 32 64 128 192 440 980 1700 Pin-to-pin delay (ns) 7.5 7.5 7.5 7.5 9.0 6.2 7.0 Yes Yes Yes User flash memory (Kb) 8 Total on-chip memory (bits)2 Yes Yes Yes Internal oscillator 3 Digital PLL3 3 Fast power-on reset 3 Boundary-scan JTAG 3 JTAG ISP 3 Fast input registers 3 Programmable register power-up 3 JTAG translator 3 Real-time ISP 3 MultiVolt I/Os (V) 1.2, 1.5, 1.8, 2.5, 3.3 1.2, 1.5, 1.8, 2.5, 3.3, 5.04 I/O power banks 2 2 2 2 2 4 4 Maximum output enables 54 54 79 114 159 271 271 LVTTL/LVCMOS I/O Features Yes 3 LVDS outputs 32 bit, 66 MHz PCI compliant Yes Yes Yes Yes Yes Yes Yes - - - - - 34 34 Schmitt triggers 3 Programmable slew rate 3 Programmable pull-up resistors 3 Programmable GND pins 3 Open-drain outputs 3 Bus hold 3 Typical equivalent macrocells. Unused LEs can be converted to memory. The total number of available LE RAM bits depends on the memory mode, depth, and width configurations of the instantiated memory. 3 Optional IP core. Contact your Altera sales representative for availability. 4 An external resistor must be used for 5.0 V tolerance. 1 2 44Altera Product Catalog * 2015 * www.altera.com MAX CPLD SERIES MAX II CPLD Features Architectural Features Density and Speed MAX II CPLDs (3.3 V, 2.5 V, 1.8 V) Equivalent macrocells1 Pin-to-pin delay (ns) EPM240/Z EPM570/Z EPM1270 EPM2210 192 440 980 1,700 4.7, 7.5 5.4, 9.0 6.2 7.0 User flash memory (Kb) 8 Boundary-scan JTAG 3 JTAG ISP 3 Fast input registers 3 Programmable register power-up 3 JTAG translator 3 Real-time ISP 3 MultiVolt I/Os (V) 1.5, 1.8, 2.5, 3.3 1.5, 1.8, 2.5, 3.3 1.5, 1.8, 2.5, 3.3, 5.02 1.5, 1.8, 2.5, 3.3, 5.02 I/O power banks 2 2 4 4 Maximum output enables 80 160 212 272 32 32 I/O Features LVTTL/LVCMOS 32 bit, 66 MHz PCI compliant 3 - - Schmitt triggers 3 Programmable slew rate 3 Programmable pull-up resistors 3 Programmable GND pins 3 Open-drain outputs 3 Bus hold 3 Typical equivalent macrocells. An external resistor must be used for 5 V tolerance. 1 2 Altera Product Catalog * 2015 * www.altera.com45 MAX CPLD SERIES MAX V and MAX II CPLD S er ies Pack age and I/O M atr ices MAX V CPLDs (1.8 V)1 EQFP (E)2 TQFP (T)3 64 pin 100 pin 7 x 7 (mm) 0.4-mm pitch 144 pin 14 x 14 (mm) 0.5-mm pitch 5M40Z 54 5M80Z 54 79 5M160Z 54 79 MBGA (M)4 20 x 20 (mm) 0.5-mm pitch 64 pin 68 pin 4.5 x 4.5 (mm) 0.5-mm pitch FBGA (F) 100 pin 5 x 5 (mm) 0.5-mm pitch 256 pin 6 x 6 (mm) 0.5-mm pitch 17 x 17 (mm) 1.0-mm pitch 324 pin 19 x 19 (mm) 1.0-mm pitch 30 30 5M240Z 79 114 5M570Z 74 114 5M1270Z 52 52 79 52 79 74 159 114 5M2210Z 211 271 203 271 MAX II CPLDs (3.3 V, 2.5 V, 1.8 V)1 TQFP (T) FBGA (F) 144 pin 100 pin 16 x 16 (mm) 0.5-mm pitch 22 x 22 (mm) 0.5-mm pitch 100 pin 11 x 11 (mm) 1.0-mm pitch 256 pin 17 x 17 (mm) 1.0-mm pitch MBGA (M) 324 pin 19 x 19 (mm) 1.0-mm pitch EPM240Z EPM570Z 68 pin 100 pin 5 x 5 (mm) 0.5-mm pitch 6 x 6 (mm) 0.5-mm pitch 54 80 144 pin 11 x 11 (mm) 0.5-mm pitch 116 160 76 EPM240 80 EPM570 76 80 116 EPM1270 116 EPM2210 76 80 160 76 212 204 272 For temperature grades of specific packages (commercial, industrial, or extended temperatures), refer to Altera's online selector guide. Enhanced quad flat pack. 3 Thin quad flat pack. 4 Micro FineLine BGA (0.5 mm). 2 636 Number indicates available user I/O pins. Vertical migration (same Vcc, GND, ISP, and input pins). For vertical migration, the number of user I/Os may be less than the number stated in the table. * 2015 * www.altera.com 160 212 1 46Altera Product Catalog 256 pin 7 x 7 (mm) 0.5-mm pitch ENPIRION POWER PORTFOLIO Enpir ion Power DC-DC Conver ters Altera develops FPGAs and CPLDs using advanced process technologies that provide fast performance and high logic density. To meet demanding power requirements, Altera's Enpirion products deliver the industry's first family of power system-on-chip (PowerSoC) DC-DC converters featuring integrated inductors. They provide an industry-leading combination of high efficiency, small footprint, and low-noise performance. Powering Your Innovation--PowerSoC Key Intellectual Property High-frequency power conversion Integrated Power Management Systems Inductor Controller Engineered Turnkey Solutions Fully simulated, characterized, and validated Magnetics engineering System-level qualified Power packaging and construction Eliminates inductor and capacitor selection 2 MOSFETs High-frequency filter capacitors Altera Product Catalog * 2015 * www.altera.com47 ENPIRION POWER PORTFOLIO Enpir ion Power DC-DC Conver ters Benefits of PowerSoC Addressing today's and tomorrow's system power design challenges: PowerSoC Comparison Highest Power Density and Smallest Footprint PowerSoC-- 25% to 50% smaller footprint than alternative solutions Greatly minimizes the amount of PCB space and height profile required for point-of-load regulation compared to alternative discrete switching regulators and modules. High Efficiency and Thermal Performance Optimized with up to 96 percent efficiency. High-efficiency devices are industrial graded, from -40 to 85C ambient temperature and most solutions operate without load de-rating. Competitor module Lowest Component Count and Higher Reliability PowerSoCs are specified, simulated, characterized, validated, and manufacturing-tested as a complete power system. Fewer components and tightly controlled IC manufacturing processes permit an unsurpassed 45,000-year mean time between failures (MTBF) reliability. Competitor discrete regulators Ease of Design and Fastest Time to Market PowerSoCs with integrated inductor and compensation enable turnkey designs. Development requires fewer design steps with significantly less exposure to design iteration versus discrete switching regulators. Fully Validated Power Solutions Fully validated PCB layout and design files enable customers nearly 100 percent first-pass success. FB 600 mA 400 mA 2 x 1.75 mm 2.5 x 2.25 mm 600 -1500 mA 3 x 3 mm 1.5-3 A 6 x 4 mm 3- 4 A 7 x 4 mm Smallest Solution Footprint 48Altera Product Catalog * 2015 * www.altera.com 4-9 A 11 x 8 mm 9-12 A 10 x 11 mm 15 A 13 x 12 mm (Shown actual package size) ENPIRION POWER PORTFOLIO Enpir ion Power DC-DC Conver ters Low Radiated Noise Enpirion Competitor Low Ripple Fast Dynamic Response Competitor Enpirion Competitor Enpirion Applications Market pressures are driving equipment manufacturers to add more features, more functionality, and higher bandwidth while moving to smaller form factors and targeting improved energy efficiency. The newest 28 nm and 20 nm FPGAs, processors, and other SoCs address these challenges, in part, by implementing more granular and precise levels of power management. The result is an escalating number of power rails, complex power-up sequencing requirements, and tighter noise tolerances. Enpirion power solutions from Altera meet these power design challenges and are broadly used in many applications. Enterprise Storage Computer Server motherboards Network interface card (NIC) and host bus adapter (HBA) cards RAID controllers Micro servers Networking and Telecommunications Radio basestations (macro, pico, femto) Backhauls (microwave, wireline) Media gateways (ATCA/AMC) Industrial and Embedded Security systems/digital video recorder (DVR) Industrial computing Industrial communication modules Solid State Drives (SSD): SATA, Serial Attached SCSI (SAS), mSATA, PCIe Storage systems Test and Measurement Network analyzers Automated test equipment (ATE) Data acquisition Scopes, analyzers, signal generators Optical Networking Optical modules: Small form factor pluggable (SFP), XFP, CXP, c form factor pluggable (CFP) Active optical cables Reprogrammable add/drop multiplexers Altera Product Catalog * 2015 * www.altera.com49 ENPIRION POWER PORTFOLIO Enpir ion Power DC-DC Conver ters 0.9 21 6 * 0.6 2.4 - 5.5 1.80-3.3 u QFN16 2.5 2.25 1.1 14 2 E P53 5 [ x ] L U I 2 0.6 2.4 - 5.5 0.60-Note 1 u QFN16 2.5 2.25 1.1 14 2 E P53 A [ x ] H Q I 2 1.0 2.4 - 5.5 1.80-3.3 Q FN16 3.0 3.0 1.1 21 3 2 1.0 2.4 - 5.5 0.60-Note 1 Q FN16 3.0 3.0 1.1 21 3 * EP5 3 F 8Q I 1.5 2.4 - 5.5 0.60-Note 1 Q FN16 3.0 3.0 1.1 40 8 * * EN53 19Q I 1.5 2.4 - 5.5 0.60-Note 1 Q FN24 4.0 6.0 1.1 55 6 * * EN53 29Q I 2.0 2.4 - 5.5 0.60-Note 1 Q FN24 4.0 6.0 1.1 55 6 * * EN53 39Q I 3.0 2.4 - 5.5 0.60-Note 1 Q FN24 4.0 6.0 1.1 55 7 * * EN53 64Q I 6.0 2.4 - 6.6 0.60-Note 1 Q FN68 8.0 11.0 1.85 160 6 * * * EN53 6 7Q I 6.0 2.5 - 5.5 0.60-Note 1 Q FN54 10.0 5.5 3.0 160 12 * * * E N5 3 94Q I 9.0 2.4 - 6.6 0.60-Note 1 Q FN68 8.0 11.0 1.85 190 7 * * * Light Load Mode 1.75 H Parallel Capability 2.0 W Output Sync. u QFN14 L Solution Size (mm2 ) Input Sync. 0.60-Note 1 Package (pins) Margining 2.5 - 5.5 Part Number VOUT Range (VDC)1 Power Good XFB V Adjust 0.4 2 VIN (VDC) IOUT (A) Package Size (mm) VID V Adjust Ext. Components Program Soft Start Featured PowerSoC Products 5300 5 V Step-Down Converters EP5 3 48U I EP5 35[ x ] H U I EP5 3 A [ x ] L Q I * 3-p in * 3-p in * 3-p in * 3-p in * * * * * * * * * * 6 3 0 0 Effi ci ency -O ptim ized Step-Down DC-DC Converters EN63 10Q I 1.0 2.7 - 5.5 0.60-3.3 QFN30 4.0 5.0 1.85 65 10 * * * E N6 337Q I 3.0 2.5 - 6.6 0.75-Note 1 QFN38 4.0 7.0 1.85 75 6 * * * * * EN63 47Q I 4.0 2.5 - 6.6 0.75-Note 1 QFN38 4.0 7.0 1.85 75 6 * * * * E N6 3 60Q I 8.0 2.5 - 6.6 0.60-Note 1 QFN68 8.0 11.0 3.0 190 10 * * * * * EN63 A 0 Q I 12.0 2.5 - 6.6 0.60-Note 1 Q FN76 10.0 11.0 3.0 225 11 * * * * * * 2300 12 V Step-Down Converters EN23 42Q I 4.0 4.5 - 14.0 0.75-5.0 Q FN68 8.0 11.0 3.0 200 15 * * * * * E N2 3 60Q I 6.0 4.5 - 14.0 0.75-5.0 QFN68 8.0 11.0 3.0 200 13 * * * * * E N2 392Q I 9.0 4.5 - 13.2 0.75-3.3 QFN76 10.0 11.0 3.0 235 17 * * * * * * EN23 F 2Q I 15.0 4.5 - 13.2 0.75-3.3 QFN92 13.0 12.0 3.0 325 19 * * * * * * E V13 00 Source/ Si nk DDR VTT Converters E V1 320Q I 2.0 1.0 - 1.8 0.50-0.9 Q F N16 3.0 3.0 0.55 40 6 * * * E V1 3 40Q I 5.0 1.0 - 1.8 0.50-0.9 QFN54 5.5 10.0 3.0 125 14 * * * * E V1 3 80Q I 8.0 1.16 - 1.8 0.60-0.9 QFN68 8.0 11.0 3.0 200 14 * * * * Notes 1. Maximum VOUT = VIN - VDROPOUT where VDROPOUT = RDROPOUT x Load Current. Reference device datasheet to calculate VDROPOUT. Typical VDROPOUT = 0.4V. 2. [x] = "8" for pulse-width modulator (PWM) only; "7" for light load mode Definitions Qualified to industrial (I) ambient temperature range: -40C to + 85C VID = output voltage programming using voltage ID code pins VDC = Volts direct current Margining = ability to force VOUT out of regulation by a selectable percentage (via 2 pins) Input/output sync. = ability to control frequency of the regulator(s) to reduce input/output voltage ripple Size estimate for single-sided PCB including all suggested external components For a complete list of Enpirion power products, please visit www.altera.com/devices/power/power-index.html. 50Altera Product Catalog * 2015 * www.altera.com ENPIRION POWER PORTFOLIO Power ing Your FPGA I nnovation Featured Products for FPGA Applications Altera offers a range of verified power solutions that cover FPGA power requirements. Max. lLOAD (A) Solution Description VOUT Range (V)1 VIN Range (V) Core Power2 Low Noise3 EC7401QI and ET4040QI 4 - ph a s e pu l s e - w i dth mod ulation (P W M) c ontroller a n d 4 0 A po w e r t r a i n 4.5 - 14 0.6 - 5.0 * 40 ED8101P0xQI and ET4040QI S i n gl e - ph a s e di gi t al c ontroller w ith P MB us and 40A po w e r t r a i n 4.5 - 14 0.6 - 5.0 * 40 E D 8 1 0 6 N 0 x QI a n d E T 4 0 4 0 Q I S i n gl e - ph a s e di gi t al c ontroller and 40A p ow ertrain 4.5 - 14 0.6 - 5.0 * 15 EN23F2QI 1 5 A Po w e r S o C , pa r allel c ap ab ility 4.5 - 13.2 0.75 - 3.3 * * 12 EN63A0QI H i gh - e f f i c i e n c y 1 2 A Pow erSoC , p arallel c ap ab ility 2.5 - 6.6 * * 9 EN2392QI 9 A Po w e r S o C , pa r a llel c ap ab ility 4.5 - 13.2 * * 8 EN6360QI H i gh - e f f i c i e n c y 8 A Pow erSoC , p arallel c ap ab ility 2.5 - 6.6 * * 6 EN2360QI 6 A Po w e r S o C , pi n - c omp atib le w ith EN2340QI 4.5 - 14 * * 6 EN5367QI 6 A Po w e r S o C 2.5 - 5.5 4 EN2342QI 4 A Po w e r S o C , pi n - c omp atib le w ith EN2362QI 4.5 - 14 0.75 - 5.0 * * 4 EN6347QI H i gh - e f f i c i e n c y 4 A Pow erSoC 2.5 - 6.6 0.75 - V IN - V DR OP OUT * * 3 EN6337QI H i gh - e f f i c i e n c y 3 A Pow erSoC 2.5 - 6.6 0.75 - V IN - V DR OP OUT * * 3 EN5339QI 3 A Po w e r S o C ; pi n - c omp atib le w ith EN5329/19QI 2.4 - 5.5 0.6 - V IN - V DR OP OUT 2 ER2120QI 2 A s w i t c h i n g r e gu l ator w ith integ rated MOSFETs 5.0 - 14 0.6 - 12 2 EN5329QI 2 A Po w e r S o C ; pi n - c omp atib le w ith EN5339/19QI 2.4 - 5.5 0.6 - V IN - V DR OP OUT * 1. 5 EN5319QI 1 . 5 A Po w e r S o C ; pi n -c omp atib le w ith EN5339/29QI 2.4 - 5.5 0.6 - V IN - V DR OP OUT * 1 ER3110DI 1 A s w i t c h i n g r e gu l ator w ith integ rated MOSFETs 3.0 - 36 0.6 - 12 * 1 EN6310QI H i gh - e f f i c i e n c y 1 A Pow erSoC 2.7 - 5.5 0.6 - 3.3 * 1 EP53A8xQI U l t r a s m a l l 1 A Po werSoC 2.4 - 5.5 0.6 - V IN - V DR OP OUT 1 EY1501DI 1 A l i n e a r r e gu l a t o r 2.2 - 6 0.8 - 5 0. 6 EP5358xQI U l t r a s m a l l 0 . 6 A Po w erSoC 2.4 - 5.5 0.6 - V IN - V DR OP OUT 0. 5 ER3105QI 0 . 5 A s w i t c h i n g r e gulator w ith integ rated MOSFETs 3.0 - 36 0.6 - 34 * 0.1 5 EY1603TI 1 5 0 m A l o w I Q l i n e a r reg ulator 6.0 - 40 2.5 - 12 * * 0.0 5 EY1602SI 5 0 m A l o w I Q l i n e a r reg ulator 6.0 - 40 2.5 - 12 * * 16 0 0.6 - V IN - V DR OP OUT 0.75 - 3.3 0.6 - V IN - V DR OP OUT 0.75 - 5.0 0.6 - V IN - V DR OP OUT * * * * * * * * S p e ci al F uncti on Produc ts P rod uc t De s c ri pt i on E S1 010Q I 1 2 V p o w e r d is t r i bu t i o n h o t s wa p c o n t r o l l e r E S1 022Q I S e q u e n ce r w it h 4 de l a y a dj u s t a bl e s e qu e n c e d o u t p uts w ith inp ut voltag e monitoring E S1 020Q I S e q u e n ce r w it h 4 de l a y a dj u s t a bl e s e qu e n c e d o u t p uts w ith inp ut voltag e monitoring ; sup p lies g ate d rive for external FETs E S1 021Q I S e q u e n ce r w it h 4 de l a y a dj u s t a bl e s e qu e n c e d o u t p uts w ith inp ut voltag e monitoring ; sup p lies g ate d rive for external FETs; g ro u ps 4 c h a n n e l s i n t o 2 gr o u ps e a c h w i t h t h e i r o w n e n a bl e Notes 1. Reference device datasheet for VDROPOUT value. 2. Meets accuracy, ripple, and transient requirements for FPGA core rails. 3. Low-output voltage ripple and meets CISPR 22 Class B emissions standard. Altera Product Catalog * 2015 * www.altera.com51 CO N F I G U R AT I O N D E V I C E S Configuration D e vices www.altera.com/devices/common/serialcfg/scg-index.html The following is an overview of our configuration devices. To determine the right configuration device for your FPGA, refer to our Configuration Handbook or the configuration chapter in the handbook of your selected FPGA. Altera's serial configuration devices store the configuration file for our SRAM-based FPGAs. We designed our serial configuration devices to minimize board space while providing a dedicated FPGA configuration solution. Serial configuration devices are recommended for new designs. For information on additional configuration devices supporting older products, see our Configuration Handbook. EPCQ-L Serial Configuration Devices for Arria 10 FPGAs (1.8 V) FBGA 24 pin 6 x 8 (mm) 1.0-mm pitch EPCQL256 256 EPCQL512 512 EPCQL1024 512 1,024 Number indicates memory size in megabits (Mb). Vertical migration (same Vcc, GND, ISP, and input pins). EPCQ Serial Configuration Devices for 28 nm and Prior FPGAs (3.0 V-3.3 V) SOIC 8 pin 4.9 x 6.0 (mm) EPCQ16 16 EPCQ32 32 16 pin 10.3 x 10.3 (mm) EPCQ64 64 EPCQ128 128 EPCQ256 256 EPCQ512 512 512 Number indicates memory size in megabits (Mb). Vertical migration (same Vcc, GND, ISP, and input pins). 52Altera Product Catalog * 2015 * www.altera.com ORDERING CODES Ordering Information for Arria 10 (GX, GT) Devices Package Type Transceiver Count E: H: K: N: R: S: U: Family Signature F: FineLine BGA U: Ultra Fineline BGA 12 24 36 48 66 72 96 10A Operating Temperature E: Extended (0 to 100C) I: Industrial (-40 to 100C) X 024 K 2 F 40 E 2 Optional Suffix (1) SNE 10A : Arria 10 Character 15: Power profile S: Standard L: Low M: Multi-voltage Package Code Family Variant 19: 27: 29: 35: 40: 45: X: 17.4 Gbps transceivers T: 28.1 Gbps transceivers Device Type 484 pins 672 pins 780 pins 1,152 pins 1,517 pins 1,932 pins Character 16: Package material P: Leaded G: RoHS 6 FPGA Fabric Speed Grade Transceiver Speed Grade 10AX: 016, 022, 032, 048, 057, 066, 090, 115 10AT: 090, 115 Fast 1 2 3 4 Devices Slow 5 Arria 10 GX Arria 10 GT Character 17 and 18 engineering sample (ES) Slow Fast 1 2 3 Ordering Information for Arria 10 (SX) SoCs Package Type Transceiver Count E: H: K: N: F: FineLine BGA U: Ultra Fineline BGA 12 24 36 48 Operating Temperature E: Extended (0 to 100C) I: Industrial (-40 to 100C) Family Signature 10A S 027 H 2 F 35 E 2 Optional Suffix (1) SNE 10A: Arria 10 Package Code Family Variant 19: 27: 29: 35: 40: 45: S: SoC with 17.4 Gbps transceivers Device Type 10AS: 016, 022, 027, 032, 048, 066 Character 15: Power profile S: Standard L: Low M: Multi-voltage 484 pins 672 pins 780 pins 1,152 pins 1,517 pins 1,932 pins Transceiver Speed Grade Fast 1 2 3 Slow 4 5 Character 16: Package material P: Leaded G: RoHS 6 Character 17 and 18 ES FPGA Fabric Speed Grade Devices Slow Fast 1 2 3 Arria 10 SX Altera Product Catalog * 2015 * www.altera.com53 ORDERING CODES Ordering Information for MAX 10 Devices Package Type Feature Options SC: SF: SA: DC: DF: DA: V: E: M: U: F: Single supply, compact features Single supply, flash features Single supply, analog features Dual supply, compact features Dual supply, flash features Dual supply, analog features Family Signature 10M 16 Wafer-level chip scale (WLCSP) Plastic-enhanced quad flat pack (EQFP) Micro FineLine BGA (MBGA) Ultra FineLine BGA (UBGA) FineLine BGA (FBGA) Operating Temperature DA U 484 I 7 C: Commercial (TJ = 0C to 85C) I: Industrial (TJ = -40C to 100C) A: Automotive (TJ = -40C to 125C) G 10A: MAX 10 Optional Suffix FPGA Fabric Speed Grade Member Code 02: 04: 08: 16: 25: 40: 50: 2K logic elements 4K logic elements 8K logic elements 16K logic elements 25K logic elements 40K logic elements 50K logic elements Indicates specific device options or shipment method G: RoHS6 ES: Engineering sample 6 (fastest) 7 8 Package Code WLCSP Package Type 36: 36 pins, 3 x 3 mm 81: 81 pins, 4 x 4 mm UBGA Package Type 169: 169 pins, 11 x 11 mm 324: 324 pins, 15 x 15 mm EQFP Package Type 144: 144 pins, 22 x 22 mm FBGA Package Type 256: 256 pins, 17 x 17 mm 484: 484 pins, 23 x 23 mm 672: 672 pins, 27 x 27 mm MBGA Package Type 153: 153 pins, 8 x 8 mm Ordering Information for Stratix V (GT, GX, GS, E) Devices Transceiver Count E: H: K: N: R: Embedded Hard IP Blocks 5SE: 5SGS: 5SGT: 5SGX: - M, E M M, E Package Type 12 24 36 48 66 F: FineLine BGA H: Hybrid FineLine BGA Operating Temperature C: Commercial (0 to 85C) I: Industrial (-40 to 100C) Family Signature 5S GX M A5 K 3 F 35 C 2 LNES 5S: Stratix V L: Low-power device N: Lead-free packaging ES: Engineering sample Family Variant GX: GT: GS: E: 14.1 Gbps transceivers 28.05 Gbps transceivers DSP-Oriented Highest logic density, no transceivers 54Altera Product Catalog * 2015 Package Code Member Code * Optional Suffix (1) GX GT GS E A3 A4 A5 A7 A9 AB B5 B6 B9 BB C5 C7 D3 D4 D5 D6 D8 E9 EB www.altera.com Transceiver Speed Grade For Stratix V GX/GS FPGAs only 1: 14.1 Gbps 2: 12.5 Gbps 3: 8.5 Gbps For Stratix V GX/GS FPGAs only 2: 28.05 Gbps 3: 25.78 Gbps 29: 780 pins 35: 1,152 pins 40: 1,517 pins 43: 1,760 pins 45: 1,932 pins FPGA Fabric Speed Grade Devices Stratix V GT Stratix V GX Stratix V GS Stratix V E Fast 1 2 3 4 5 6 Slow 7 8 ORDERING CODES Ordering Information for Arria V (GT, GX, GZ) Devices Transceiver Count D: E: G: H: K: 9 (Arria V GX and GT devices only) 12 (Arria V GZ devices only) 18 (Arria V GX and GT devices only) 24 36 Package Type F : FineLine BGA H: Hybrid FineLine BGA Embedded Hard IP Blocks Operating Temperature C: Commercial (0 to 85C) I: Industrial (-40 to 100C for I5) (-40 to 100C for I3) 5AGX: B, M, F 5AGT: M, F 5AGZ: M Family Signature 5A GX B A7 D 4 F 27 C 4 NES 5A : Arria V Family Variant L: Low-power device N: Lead-free packaging ES: Engineering sample silicon Package Code GX: 6-Gbps transceivers GT: 10-Gbps transceivers GZ: 12.5-Gbps tranceivers Member Code GX GT GZ A1 A3 A5 A7 B1 B3 B5 B7 C3 C7 D3 D7 E1 E3 E5 E7 Transceiver Speed Grade For Arria V GX FPGAs only 4: 6.5536 Gbps 6: 3.125 Gbps For Arria V GT and GZ FPGAs only 3: 10.3125 Gbps Optional Suffix 27: 672 pins 29: 780 pins (Arria V GZ FPGAs only) FPGA Fabric Speed Grade 31: 896 pins 35: 1,152 pins Slow Fast 40: 1,517 pins Devices 1 2 3 4 5 6 7 8 Arria V GX Arria V GT Arria V GZ For Arria V GZ FPGAs only 2: 12.5 Gbps Ordering Information for Arria V (SX, ST) SoCs Transceiver Count D: E: G: H: K: Package Type 9 12 18 30 (Arria V SX devices only) 30 (Arria V ST devices only) F: FineLine BGA Operating Temperature Embedded Hard IP Blocks 5ASX: B, M, F 5AST: F C: Commercial (0 to 85C) I: Industrial (-40 to 100C) Family Signature 5S ST F D5 K 4 F 40 I 5 5A : Arria V N: Lead-free packaging ES: Engineering sample Family Variant SX: 6 Gbps transceivers ST: 10 Gbps transceivers Optional Suffix NES Package Code Member Code SX ST B3 B5 D3 D5 Transceiver Speed Grade For Arria V SX FPGAs only 6: 3.125 Gbps 31: 896 pins 35 : 1,152 pins 40 : 1,517 pins FPGA Fabric Speed Grade Devices Fast 1 2 Arria V SX Arria V ST Slow 3 4 5 6 7 8 For Arria V SX FPGAs only 4: 6.375 Gbps For Arria V ST FPGAs only 3: 10.3125 Gbps Altera Product Catalog * 2015 * www.altera.com55 ORDERING CODES Ordering Information for Cyclone V (E, GX, GT) Devices Package Type Transceiver Count B: F: A: C: D: E: Embedded Hard IP Blocks 5CE: B, F 5CGX : B, F 5CGT : F Family Signature 5C GX B F: FineLine BGA H: Hybrid FineLine BGA M: Micro FineLine BGA 3 4 5 6 9 12 C3 Operating Temperature A: Automotive (-40 to 125C) C: Commercial (0 to 85C) I: Industrial (-40 to 100C) B 6 F 23 C 7 Optional Suffix NES 5C: Cyclone V N: Lead-free packaging ES: Engineering sample Family Variant E: Enhanced logic/memory GX: 3 Gbps transceivers GT: 6 Gbps tranceivers Package Code Member Code E GX GT A2 A4 A5 A7 A9 C3 C4 C5 C7 C9 D5 D7 D9 FPGA Fabric Speed Grade 11: 13: 15 (M): 15 (U): 17: 19: 23: 27: 31: 35: Transceiver Speed Grade For Cyclone V GX FPGAs only 6: 3.125 Gbps 7: 2.5 Gbps For Cyclone V GT 5: 6.144 Gbps 301 pins 383 pins 484 pins 324 pins 256 pins 484 pins 484 pins 672 pins 896 pins 1,152 pins Fast 1 2 Devices 3 4 Slow 7 8 5 6 Cyclone V GT Cyclone V GX Cyclone V E Ordering Information for Cyclone V (SE, SX, ST) SoCs Package Type Transceiver Count F: FineLine BGA U: Ultra FineLine BGA C: 6 D: 9 Operating Temperature Embedded Hard IP Blocks A: Automotive (-40 to 125C) C: Commercial (0 to 85C) I: Industrial (-40 to 100C) 5CSE: B, M 5CSX: F 5CST: F Family Signature 5C ST F D6 D 4 F 31 C 6 S NES 5C: Cyclone V N: Lead-free packaging ES: Engineering sample Family Variant SE: SoCs with enhanced logic/memory SX: SoCs with 3 Gbps transceivers ST: SoCs with 6 Gbps transceivers Package Code 19: 484 pins 23: 672 pins 31: 896 pins Member Code 56Altera Product Catalog * SE SX ST A2 A4 A5 A6 C2 C4 C5 C6 D5 D6 2015 * www.altera.com Optional Suffix Transceiver Speed Grade For Cyclone V SX/ST FPGAs only 5: 6.144 Gbps 6: 3.125 Gbps Optional Single Core S: Single core (available in hard IP block "B" variants only) FPGA Fabric Speed Grade Devices Cyclone V SE Cyclone V SX Cyclone V ST Fast 1 2 3 4 5 6 Slow 7 8 ORDERING CODES Ordering Information for Stratix IV (E, GX, GT), Cyclone IV (E,GX), Cyclone III, MAX V, and MAX II Package Type Transceiver Count For transceiver-based (GX/GZ/GT) FPGAs only C: D: E: F: 4 8 12 16 G: H: K: N: 20 24 36 48 B: E: F: H: Product-Line Suffix For MAX II devices only Indicates device core voltage G: 1.8 V VCCINT device Blank: 2.5 V or 3.3 V VCCINT device Z: Zero power device Ball-grid array (BGA) Enhanced thin quad flat pack FineLine BGA Hybrid FineLine BGA M: Q: T: U: Micro BGA Plastic quad flat pack Thin quad flat pack Ultra FineLine BGA Operating Temperature A: Automotive (-40 to 125C) C: Commercial (0 to 85C) I: Industrial (-40 to 100C) M: Military (-55 to 125C) Optional Suffix (1) Family Signature EP4SE: EP4SGX: EP4S: EP4CE: EP4CGX: EP3CLS: EP3C: EP2AGZ: EP2AGX: 5M: EPM: Stratix IV E Stratix IV GX Stratix IV GT Cyclone IV E Cyclone IV GX Cyclone III LS Cyclone III Arria II GZ Arria II GX MAX V MAX II EP4SGX 230 K F 40 C 2 NES L: Low-power device N: Lead-free packaging ES: Engineering sample Device Type EP4SE: EP4SGX: EP4S: EP4CE: EP4CGX: EP3CLS: EP3C: EP2AGZ: EP2AGX: 5M: EPM: 110, 230, 290, 360, 530, 820 70, 110, 230, 290, 360, 530 40G, 100G 6,10, 15, 30, 40, 55, 75, 115 15, 22, 30, 50, 75, 110, 150 70, 100, 150, 200 5, 10, 16, 25, 40, 55, 80, 120 225, 300, 350 20, 30, 45, 65, 95, 125, 190, 260 40, 80, 160, 240, 570, 1270, 2210 240, 570, 1270, 2210 Package Code 29: 35: 40: 43: 45: 780 pins 1,152 pins 1,517 pins 1,760 pins 1,932 pins FPGA Fabric Speed Grade Devices Stratix IV E Stratix IV GX Stratix IV GT Cyclone IV E Cyclone IV GX Cyclone III LS Cyclone III Fast 1 2 Arria II GZ Arria II GX MAX V MAX II Altera Product Catalog 3 4 5 6 Slow 7 8 * 2015 * www.altera.com57 ORDERING CODES Ordering Information for Serial Configuration Devices Density in Megabits Operating Temperature 256: 256 Mb 512: 512 Mb 1024: 1,024 Mb Family Signature EPCQL I: Industrial (-40 to +85C) 1024 F 24 I Optional Suffix N N: Lead-free packaging EPCQL: For Arria 10 devices (1.8 V) Package Type F: Fineline BGA Package Code 24: 24 pins Density in Megabits 16: 32: 64: 128: 256: 512: Family Signature 16 Mb 32 Mb 64 Mb 128 Mb 256 Mb 512 Mb EPCQ Package Code 8: 8 pins 16: 16 pins 512 S I 16 Package Type Operating Temperature I: Industrial (-40 to +85C) 58Altera Product Catalog * 2015 * www.altera.com Optional Suffix N: Lead-free packaging EPCQ: For 28 nm and prior FPGAs (3.0-3.3 V) S: Small outline N DESIGN TOOLS Quar tus II D esign S of t ware www.altera.com/products/software Quartus II software is number one in performance and productivity for CPLD, FPGA, and SoC designs, providing the fastest path to convert your concept into reality. Quartus II software also supports many third-party tools for synthesis, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. Quartus II Software Design Flow Availability Quartus II Software Key Features Design Entry Subscription Edition Web Edition (Free) Cyclone FPGA and MAX device support 3 3 Arria and Stratix device support 3 31 Cyclone and Arria SoC support 3 3 Multiprocessor support (faster compile time support) 3 32 IP Base Suite (includes licenses for 15 popular IP cores) 3 Available for purchase Qsys (next-generation system-integration tool) 3 3 Rapid Recompile (faster compile for small design changes) 3 Incremental compile (performance preservation and team-based design) 3 ModelSim(R)-Altera Starter Edition software 3 3 ModelSim-Altera Edition software 33 33 Quartus II Integrated Synthesis (synthesis tool) 3 3 Fitter (placement and routing tool) 3 3 TimeQuest tool (static timing analysis) 3 3 PowerPlay tool and optimization (power analysis) 3 3 SignalTapTM II Logic Analyzer (embedded logic analyzer)2 3 32 Transceiver toolkit (transceiver interface and verification tool) 3 JNEye link analysis tool 3 Transceiver Configuration Console (dynamically programmed transceiver settings) 3 Functional Simulation Synthesis Placement and Routing Timing and Power Verification In-System Debug Availability Operating System (OS) Support Subscription Edition Web Edition (Free) 3 3 Windows/Linux 64 bit support The only Arria II FPGA supported is the EP2AGX45 device. Available with TalkBack feature enabled. 3 Requires an additional license. 1 2 Altera Product Catalog * 2015 * www.altera.com59 DESIGN TOOLS Quar tus II D esign S of t ware Third-Party Support Verification Performance and Timing Closure Methodology Design Flow Methodology Quartus II Design Software Features Summary 1 2 Incremental compilation1 Improves design timing closure and reduces design compilation times up to 70 percent. Supports team-based design. Pin planner Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs. Qsys (replaces SOPC Builder) Automates system development by integrating IP functions and subsystems (collection of IP functions) using a hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture. Off-the-shelf IP cores Lets you construct your system-level design using IP cores from Altera and from Altera's third-party IP partners. Parallel development in ASICs1 Allows for FPGA prototypes to be designed in parallel using the same design software and IP. Scripting support Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design. Rapid Recompile1 Maximizes your productivity by reducing your compilation time by 50 percent on average (for a small design change after a full compile). Improves design timing preservation. Physical synthesis Uses post placement and routing delay knowledge of a design to improve performance. Design space explorer (DSE) Increases performance by automatically iterating through combinations of Quartus II software settings to find optimal results. Extensive cross-probing Provides support for cross-probing between verification tools and design source files. Optimization advisors Provides design-specific advice to improve performance, resource usage, and power consumption. Chip planner Reduces verification time while maintaining timing closure by enabling small, post placement and routing design changes to be implemented in minutes. TimeQuest timing analyzer Provides native Synopsys(R) Design Constraint (SDC) support and allows you to create, manage, and analyze complex timing constraints and quickly perform advanced timing verification. SignalTap II embedded logic analyzer2 Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering capabilities available in an embedded logic analyzer. System Console Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to quickly create a GUI to help monitor and send data into your FPGA. PowerPlay technology Enables you to accurately analyze and optimize both dynamic and static power consumption. EDA partners Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit www.altera.com/products/software/partners/eda_partners/eda-index.html. Included in Subscription Edition only. Available with Talkback feature enabled in Web Edition. Getting Started Steps Step 1: Download free Web Edition www.altera.com/download Step 2: Get oriented with Quartus II software interactive tutorial After installation, open the interactive tutorial on the welcome screen. Step 3: Sign up for training www.altera.com/training 60Altera Product Catalog * 2015 * www.altera.com DESIGN TOOLS Quar tus II D esign S of t ware Purchase Quartus II software and increase your productivity today. Pricing $2,995 (SW-QUARTUS-SE-FIX) Renewal $2,495 (SWR-QUARTUS-SE-FIX) Description Fixed-node license: subscription for one year--Windows only. $3,995 (SW-QUARTUS-SE-FLT) Renewal $2,495 (SWR-QUARTUS-SE-FLT) Floating-node license: subscription for one year--Windows/Linux. Add seat $3,995 (SW-QUARTUS-SE-ADD) ModelSim-Altera Edition Software $945 (SW-MODELSIM-AE) Renewal $945 (SWR-MODELSIM-AE) ModelSim-Altera Edition software is available as a $945 option for both Quartus II Subscription Edition and Web Edition software. It is 33 percent faster than Starter Edition with no line limitation. ModelSim-Altera Starter Edition Software Free Free for both Quartus II Subscription Edition and Web Edition software with a 10,000 executable line limitation. ModelSim-Altera Starter Edition software is recommended for simulating small FPGA designs. Altera Product Catalog * 2015 * www.altera.com61 DESIGN TOOLS Altera SDK for OpenCL www.altera.com/opencl The Altera SDK for OpenCL1 allows the easy implementation of applications onto FPGAs by abstracting away the complexities of FPGA design, allowing software programmers to write hardware-accelerated kernel functions in OpenCL C, an ANSI C-based language with additional OpenCL constructs to extract parallelism. Using the FPGA, as an accelerator provides significant advantages over using a CPU or GPU by using customized small scalar or large vector processing units or a deep hardware pipeline to create a completely custom accelerator at the lowest possible power. Altera SDK for OpenCL Software Features Summary Altera Offline Compiler (AOC) * GCC-based model compiler of OpenCL kernel code * Diagnostics for board installation Altera OpenCL Utility (AOCL) * Flash or program FPGA image * Install board drivers (typically PCIe) * Purchase a one-year perpetual license ($995) Altera SDK for OpenCL Licensing * Fixed-node and floating-node licenses available * 60-day evaluation license available on request * Requires licensed Quartus II Subscription Edition or Development Kit Edition software * Microsoft 64 bit Windows 7 Operating System * Red Hat Enterprise 64 bit Linux (RHEL) 6.x Memory Requirements * Computer equipped with at least 16 GB RAM OpenCLTM and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance. 1 62Altera Product Catalog * 2015 * www.altera.com DESIGN TOOLS S oC Embedded D esign Suite The Altera SoC Embedded Design Suite (EDS) is a comprehensive tool suite for embedded software development on Altera SoCs. It comprises development tools, utility programs, run-time software, and design examples to jump-start firmware and application software development. The SoC EDS includes an exclusive offering of the ARM Development Studio 5 (DS-5) Altera Edition Toolkit. SoC Embedded Design Suite Availability SoC EDS Key Features Hardware/Software Handoff Tools Compiler Tools Run-time Libraries DS-5 Altera Edition Features Getting Started Examples Others Subscription Edition Web Edition (Free) Preloader Generator 3 3 Device Tree Generator 3 3 Linaro Compiler 3 3 Sourcery EABI GNU Compiler 3 3 SoC Linux 3 U-Boot 3 SoC Abstraction Layer (SoCAL) 3 3 Hardware Manager 3 3 Linux application debugging over Ethernet 3 3 Debugging over USB-BlasterTM II cable - Board bring-up - Device driver development - Operating system (OS) porting - Bare-metal programming 3 FPGA-adaptive debugging - Auto peripheral register discovery - Cross-triggering between CPU and FPGA domains - ARM CoreSight trace support - Access to System Trace Module (STM) events 3 Streamline Performance Analyzer support 3 Limited Golden system reference designs for SoC development kits 3 3 Other design examples: - Device-wide asymmetric multiprocessing - Triple Speed Ethernet (TSE) with Modular Scatter-Gather Direct Memory Access (mSG-DMA) - PCIe Root Port with Message Signal Interrupts (MSI) 3 3 Quartus II Programmer 3 3 SignalTap II Logic Analyzer 3 3 Altera Boot Disk Utility 3 3 Availability OS Support Subscription Edition Web Edition (Free) Windows/Linux 32 bit support 3 3 Windows/Linux 64 bit support Compatible Compatible SoC Embedded Design Suite Pricing Subscription Edition (ESW-SOCEDS-DS5-FIX) $995 Web Edition Free Altera Product Catalog * 2015 * www.altera.com63 DESIGN TOOLS N ios II Processor Embedded D esign Suite Altera's Nios II processor, the world's most versatile processor according to Gartner Research, is the most widely used soft processor in the FPGA industry. This soft processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and applications processing needs. All Altera FPGA families support the Nios II processor. Nios II EDS: What You Get for Free! The Nios II Embedded Design Suite (EDS) provides all the tools and software you need to develop code for the Nios II processor and Nios II Gen2 processors. With the Nios II EDS you can: Nios II EDS Contents Nios II Software Build Tools for Eclipse (Nios II SBT for Eclipse), for software development * Based on Eclipse IDE * New project wizards * Software templates * Source navigator and editor * Compiler for C and C++ (GNU) Software Debugger/Profiler Flash Programmer Embedded Software * Hardware Abstration Layer (HAL) * MicroC/OS-II RTOS * NicheStack TCP/IP Network Stack--Nios II Edition * Newlib ANSI-C standard library * Simple file system Other Altera Command-Line Tools and Utilities Design Examples Hardware Development Tools * Quartus II design software * Develop software with Nios II SBT for Eclipse: Based on industry-standard Eclipse, the Nios II SBT is an integrated development environment for editing, compiling, debugging software code, and flash programming. * Manage board support packages (BSPs): The Nios II EDS makes managing your BSP easier than ever. Nios II EDS will automatically add device drivers for Altera-provided IP to your BSP. The BSP Editor provides full control over your build options. * Get free network stack software: The Nios II EDS includes NicheStack TCP/IP Network Stack - Nios II Edition--a commercial-grade network stack software--for free. * Evaluate a RTOS: The Nios II EDS contains an evaluation version of the popular Micrium MicroC/OS-II RTOS. Product licenses are sold separately by Micrium. * Qsys system integration tool * SignalTap II embedded logic analyzer plug-in for Nios II processor * System Console for low-level debugging of Qsys systems Join the Nios II Community! Licensing Be part of thousands of Nios II developers by Getting started with the Nios II processor is now easier than ever. Not only is the Nios II EDS free, but the Nios II economy core IP is also free. visiting Altera Wiki, Altera Forum, and the Licenses for the Nios II standard and fast core IP are available for stand-alone IP (IP-NIOS) or as part of the Embedded IP Suite (IPS-EMBEDDED). These royalty-free licenses never expire and allow you to target your processor design to any Altera FPGA. The Embedded IP Suite is a value bundle that contains licenses of the Nios II processor IP core, DDR1/2/3 Memory Controller IP cores, Triple-Speed Ethernet MAC IP core, 16550 - compatible UART, and NicheStack TCP/IP Network Stack-Nios II Edition software. examples and design tips from Nios II developers all Rocketboards.org website have hundreds of design over the world. Join ongoing discussions on the Nios II section of Altera Forum to know more about Nios II Linux, hardware, and software development. Visit the following websites: www.alterawiki.com Development Kits Go to page 76 for information about embedded development kits. 64Altera Product Catalog Rocketboards.org website. Altera Wiki and the * 2015 * www.altera.com www.alteraforum.com www.rocketboards.org O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S S oC Operating System Suppor t Altera and our ecosystem partners offer comprehensive operating system support for Altera SoC development boards. Vendor OS/RTOS Development Tools Availability Open Source Linux 3.11 Linaro compiler Now through www.rocketboards.org VxWorks 6.9.3 Workbench 3.3.3 Now through Wind River C/OS-II, C/OS-III GNU compiler Now through Micrim OSE 5.5.3 Optima 2.6 Now through ENEA Express Logic ThreadX G5.5.5.0 GNU compiler Now through Express Logic Wind River Systems Wind River Linux 5 Workbench/GNU Now through Wind River QNX QNX/Neutrino 6.5.3 Momentics Now through QNX Android GNU compiler Now though Fujisoft INTEGRITY Multi/Green Hills Now through Green Hills Windows Embedded 7 Microsoft/Studio Now through iWave Code Time Technologies Abassi ARMCC/GCC Now through Code Time Mentor Graphics Nucleus GCC Now through Mentor Graphics ECOSPRO (eCos) GCC Now through eCosCentric Wind River Systems Micrim Enea Fujisoft Green Hills Software Microsoft eCosCentric More Information For the latest on OS support for Altera SoCs visit www.altera.com/devices/processor/dev-tools/support/os-support.html Altera Product Catalog * 2015 * www.altera.com65 O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S N ios II Processor Operating System Suppor t Altera and our ecosystem partners offer comprehensive operating system support for the Nios II processor. OS Availability eCos Now through eCosCentric eCos (Zylin) Now through Zylin embOS Now through Segger EUROS Now through Euros Linux Now through Wind River Linux Now through SLS Linux Now through www.rocketboards.org oSCAN Now through Vector ThreadX Now through Express Logic CLinux Now through the Linux community Toppers Now through Open Source C/OS-II, C/OS-III Now through Micrim Getting Started Learn more about Altera's portfolio of customizable processors and how you can get started by visiting www.altera.com/embedded. 66Altera Product Catalog * 2015 * www.altera.com O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S N ios II Processor The Nios II processor in any one of Altera's FPGAs offers a custom system solution that has the flexibility of software and the performance of hardware. Through its innovative design, the Nios II processor leverages the logic resources of the device to provide unprecedented hard and soft real-time capabilities. The Nios II processor may also be used in Altera SoCs in conjunction with the SoC ARM processor by implementing it in the FPGA logic. You can: * Lower overall system cost and complexity by integrating external processors into the FPGA * Scale performance with multiple processors, custom instructions (hardware acceleration of a processor instruction) or co-processor modules (hardware accelerator next to the soft processor) * Target any Stratix, Arria, Cyclone, or MAX 10 FPGA or the FPGA portion of the Arria V or Cyclone V SoCs * Eliminate the risk of processor and ASSP device obsolescence * Take advantage of the free Nios II economy core, the free Nios II Embedded Design Suite (EDS), and the free NicheStack TCP/IP Network Stack - Nios II Edition software to get started today Nios II Processor Development Flow Qsys Hardware Quartus II Software Software Define System RTL Generate FPGA Configuration Synthesize Place and Route Compile Download Processors Peripherals Memory Interfaces System Description System Testbench Targets RTL Simulation FPGA Configuration Nios II EDS Instruction Set Simulator Target Hardware Automatic BSP Generation System Library Header File Application Template Software Development Edit Compile Debug JTAG Debugger Altera Product Catalog * 2015 * www.altera.com67 O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S Summary of Nios II Soft Processors Category Processor Vendor Power- and cost-optimized processing Nios II economy core Altera Real-time processing Nios II standard and fast core Altera Applications processing Nios II fast core Altera A simple configuration option enables the Nios II fast core to use a memory management unit to run embedded Linux. Both open-source and commercially supported versions of Linux for Nios II processors are available. Safety-critical processing Nios II SC HCELL Certify your design for DO-254 compliance by using the Nios II Safety Critical core along with the DO-254 compliance design services offered by HCELL. 68Altera Product Catalog * 2015 * www.altera.com Description With unique, real-time hardware features such as custom instructions (ability to use FPGA hardware to accelerate a function), vectored interrupt controller, and tightly coupled memory, as well as support for industry-leading RTOS, the Nios II processor meets both your hard and soft real-time requirements, and offers a versatile solution for real-time processing. O P E R AT I N G S Y S T E M S U P P O R T A N D P R O C E S S O R S Altera's Customizable Processor Por tfolio Performance and Feature Set Summary of Key Processors Supported on Altera Devices Category Cost- and Power-Sensitive Processors Features Nios II Economy Real-Time Processor Nios II Standard Applications Processors Nios II Fast 28 nm1 Dual-Core ARM Cortex-A9 20 nm2 Dual-Core ARM Cortex-A9 1.5 GHz 410 (Stratix V) 280 (Stratix V) 360 925 MHz (Cyclone V SoC) 1.05 GHz (Arria V SoC) Maximum performance (MIPS4 at MHz) Stratix series 62 (at 340 MHz) 179 (at 300 MHz) 407 (at 310 MHz) - - Maximum performance (MIPS4 at MHz) Arria series 45 (at 300 MHz) 108 (at 170 MHz) 192 (at 170 MHz) 2,625 MIPS per core at 1.05 GHz 3,750 MIPS per core at 1.5 GHz Maximum performance (MIPS4 at MHz) Cyclone series 30 (at 200 MHz) 89 (at 145 MHz) 180 (at 160 MHz) 2,313 MIPS per core at 925 MHz - 0.15 0.64 1.13 2.5 2.5 16/32bit instruction set support 32 32 32 16 and 32 16 and 32 Level 1 instruction cache - Configurable Configurable 32 KB 32 KB Level 1 data cache - - Configurable 32 KB 32 KB Level 2 cache - - - 512 KB 512 KB Memory management unit - - Configurable Floating-point unit - FPCI5 FPCI5 Dual precision Dual precision Vectored interrupt controller - - - Tightly coupled memory - Configurable Configurable - - Up to 256 Up to 256 Up to 256 - - 600 1,200 1,800 - 3,200 HPS HPS Maximum frequency (MHz)3 Maximum performance efficiency (MIPS4 per MHz) Custom instruction interface Equivalent LEs Altera 28 nm SoCs comprise Cyclone V SoCs and Arria V SoCs. Altera 20 nm SoCs comprise Arria 10 SoCs. 3 Maximum performance measurements measured on Stratix V FPGAs. 4 Dhrystone 2.1 benchmark. 5 Floating-point custom instructions. 1 2 Altera Product Catalog * 2015 * www.altera.com69 INTELLECTUAL PROPERTY Altera and Par tner Func tions www.altera.com/selector The following is a partial list of IP functions from Altera and its partners. For more details, see our online selector guide. Product Name Vendor Name Product Name Error Detection/Correction Video and Image Processing (Continued) Reed-Solomon Encoder/Decoder II1 Altera JPEG CODEC CAST, Inc. Viterbi Compiler, High-Speed Parallel Decoder Altera JPEG Encoders and Decoders CAST, Inc. Viterbi Compiler, Low-Speed/ Hybrid Serial Decoder CAST, Inc. Altera Lossless JPEG Encoder and Decoder JPEG 2000 Encoder CAST, Inc. Turbo Convolutiona Decoder TurboConcept JPEG Extended Encoder CAST, Inc. WiMAX CTC Decoder TurboConcept H.264 AVC High Profile and Main Profile Video Encoders CAST, Inc. 3GPP/LTE CTC Decoder TurboConcept H.264 Encoders Jointwave Group LLC Turbo Product Code Decoder TurboConcept H.264 Baseline Profile Video Encoder CAST, Inc. Video Processor and Deinterlacer with Line-Doubled Output Crucial IP, Inc. Video Rotation Function Crucial IP, Inc. Video Scaler with Shrink and Zoom Support Crucial IP, Inc. Fast Fourier Transform (FFT)/ Inverse FFT (IFFT) Altera Cascaded Integrator Comb (CIC) Compiler Altera Finite Impulse Response (FIR) Compiler II Altera Modulation/Demodulation DSP (Continued) Filters and Transforms DSP Vendor Name Video Scaler with Up Converstion Crucial IP, Inc. to 4K Arithmetic Floating Point Megafunctions Altera Altera Digital Core Design ATSC and Multi-Channel ATSC 8-VSB Modulators Floating Point Arithmetic Co-Processor Commsonic Floating Point Mathematics Unit Digital Core Design DVB-T Modulator Commsonic Floating Point Pipelined Multiplier Unit Digital Core Design DVB-S2 Modulator Commsonic Multi-Channel Cable (QAM) Modulator Commsonic Numerically Controlled Oscillator Compiler Video and Image Processing Video and Image Processing Suite1 Altera JPEG Decoder and Encoder Barco Silex JPEG 2000 Sub-Frame Latency Encoder and Decoder Barco Silex Multi-Channel JPEG 2000 Encoder and Decoder Cores Barco Silex Qsys-compliant licensed core. 1 70Altera Product Catalog * 2015 * www.altera.com Additional Functions Multi-Purpose Advanced Encryption Standard (AES) Crypto Engine Barco Silex DES/3DES Encoder/Decoder Barco Silex Hashing IP Core Barco Silex Public Key Crypto Engine Barco Silex SHA-1 CAST, Inc. SHA-256 CAST, Inc. AES CODECs CAST, Inc. INTELLECTUAL PROPERTY Altera and Par tner Func tions Product Name Vendor Name Product Name Ethernet (Continued) 100G Ethernet MAC and PHY with 1588 Altera 10GBASE-KR PHY Altera 1G/10Gb Ethernet PHY Altera Carrier Ethernet CodeChips Arrive Technologies Pseudowire CodeChips Arrive Technologies CAST, Inc. Gigabit Ethernet MAC1 IFI Freescale High-Performance Gigabit Ethernet MAC1 IFI R8051XC2 Microcontroller CAST, Inc. 10G RTP Video over IP Macnica Americas DP8051 Pipelined HighPerformance 8 bit Microcontroller Digital Core Design 10G MAC Lite Macnica Americas DP8051XP Pipelined, HighPerformance 8 bit Microcontroller Digital Core Design 10/100/1000 Ethernet MAC with SGMII MorethanIP DF6811E 8 bit Fast Microcontroller Digital Core Design 10 Gigabit Ethernet MAC and Physical Coding Sub-Layer (PCS) MAC and PCS MorethanIP DFPIC1655X 8 bit RISC Microcontroller Digital Core Design 10 Gigabit Reduced XAUI PCS Core MorethanIP SPAUI MAC Core MorethanIP 20 Gigabit DXAUI PCS Core MorethanIP QSGMII PCS Core MorethanIP 2.5 Gbps Ethernet MAC MorethanIP Nios II (Classic/Gen2) Embedded Processors1 Altera ARM Cortex-A9 MPCore Processor Altera ARM Cortex-M11 ARM BA22 32 bit Deeply Embedded Processor CAST, Inc. BA22 32 bit Embedded Processor V1 ColdFire 1 8 bit Communication Optical Transport Network (OTN) Framers/Deframers Altera SFI-5.1 Altera SONET/Synchronous Digital Hierarchy (SDH) Framer/Deframer Aliathon SONET/SDH Mapper/Demapper Aliathon SDN CodeChips Arrive Technologies SONET/SDH CodeChips Arrive Technologies High Speed Ethernet 10 Gbps Ethernet Media Access Controller (MAC)1 with 1588 Altera Triple-Speed Ethernet (10/100/1000 Mbps) MAC and PHY1 with 1588 Altera 10GBASE-R PHY Altera 10G Base-X (XAUI) PHY Altera 40G Ethernet MAC and PHY with 1588 Interface and Protocols (Continued) Embedded Processors 32 bit/16 bit Interface and Protocols Vendor Name Altera RapidIO(R)1 Altera Common Public Radio Interface (CPRI) Altera Interlaken Altera Interlaken Look-Aside Altera SerialLite II/III Altera SATA 1.0/SATA 2.0 Intelliprop, Inc. QuickPath Interconnect (QPI) Intel Corporation RapidIO Controller Mobiveil, Inc. RapidIO to AXI Bridge Controller Mobiveil, Inc. Infiniband Link Layer and Target Channel Adapter Cores Polybus HyperTransportTM 3.0 University of Heidelberg Qsys-compliant licensed core. 1 Altera Product Catalog * 2015 * www.altera.com71 INTELLECTUAL PROPERTY Altera and Par tner Func tions Product Name Vendor Name Product Name Serial (Continued) PCIe Gen1 x11, x41, x8 Controller (Soft IP) Altera PCIe Gen1, Gen2, Gen3 Core x1, x2, x4, and x8 (Hardened IP) JTAG/Avalon Master Bridge2 Altera C_CAN1 Bosch Altera CAN 2.0/FD 1 CAST, Inc. PCIe Endpoint Controller x1, x4 CAST, Inc. Local Interconnect Network (LIN) Controller CAST, Inc. PCIe x8 Endpoint Controller CAST, Inc. SPI Master/Slave CAST, Inc. PCI 32/64 bit PCI Master Target 33/66 MHz Controllers CAST, Inc. H16450S UART CAST, Inc. PCI Multifunction Master/ Target Interface H16550S UART CAST, Inc. CAST, Inc. H16750S UART CAST, Inc. PCIe Express Cores Northwest Logic, Inc. MD5 Message-Digest CAST, Inc. PCI Express Multiport Transparent Switch Mobiveil, Inc. Smart Card Reader CAST, Inc. DI2CM I2C Bus Interface-Master Digital Core Design PCI Express Hybrid Controller Mobiveil, Inc. DI2CSB I2C Bus Interface-Slave Digital Core Design PCI Express to AXI Bridge Controller Mobiveil, Inc. D16550 UART with 16-Byte FIFO Digital Core Design PCI-X Core Northwest Logic, Inc. DSPI Serial Peripheral Interface Master/Slave Digital Core Design PCI Core Northwest Logic, Inc. Secure Digital (SD)/MMC SPI El Camino GmbH XpressRICH3 PCIe, Gen1, Gen2, and Gen3 PLDA Secure Digital I/O (SDIO)/SD Memory/Slave Controller Eureka Technology, Inc. PCI and PCI-X Master/ Target Cores 32/64 bit PLDA UART Eureka Technology, Inc. SDIO/SD Memory/ MMC Host Controller Eureka Technology, Inc. Nios II Advanced CAN1 IFI MediaLB Device Interface1 IFI I2C Master/Slave/PIO Controller Microtronix, Inc. Serial Serial Peripheral Interface (SPI)/ Avalon(R) Master Bridge2 Altera UART2 Altera JTAG UART2 Altera Qsys-compliant licensed core. Qsys component (no license required). 1 2 72Altera Product Catalog * 2015 * www.altera.com Interface and Protocols (Continued) Interface and Protocols (Continued) PCI Vendor Name INTELLECTUAL PROPERTY Altera and Par tner Func tions Vendor Name I C Master and Slave SLS PS2 Interface SLS USB High-Speed Function Controller1 SLS USB Full-/Low-Speed Function Controller1 SLS SD Host Controller SLS USB 3.0 SuperSpeed Device Controller SLS Interface and Protocols (Continued) 2 1 Audio and Video Character LCD2 Altera Pixel Converter (BGR0 -> BGR)2 Altera Video Sync Generator2 Altera SD/HD/3G-HD Serial Digital Interface (SDI) Altera DisplayPort Altera DisplayPort Bitec V-by-One HS Bitec Video LVDS Serializer/Deserializer (SERDES) Transmitter/Receiver Microtronic, Inc I2S Audio CODEC1 SLS Memories and Memory Controllers DMA Scatter-Gather DMA Controller2 Altera DMA Controller2 Altera Product Name Vendor Name SDRAM Memories and Memory Controllers (Continued) Product Name DDR/DDR2 and DDR3/DDR4 SDRAM Controllers1 Altera LPDDR2 SDRAM Controller Altera RLDRAM 2 Controller Altera Streaming Multi-Port SDRAM Memory Controller Microtronix, Inc. HyperDrive Multi-Port DDR2 Memory Controller Microtronix, Inc. Avalon Multi-Port SDRAM Memory Controller1 Microtronix, Inc. DDR and DDR2 SDRAM Controllers Northwest Logic, Inc. RLDRAM II and III Controllers Northwest Logic, Inc. Mobile DDR SDRAM Controller Northwest Logic, Inc. Mobile SDR SDRAM Controller Northwest Logic, Inc. SDR SDRAM Controller Northwest Logic, Inc. LPDDR2/3 Controllers Northwest Logic, Inc. SRAM 2 Altera QDR II/II+/II+Xtreme/IV SRAM Controller Altera SSRAM (Cypress CY7C1380C) Flash CompactFlash (True IDE)2 Altera EPCS Serial Flash Controller2 Altera Flash Memory2 Altera NAND Flash Controller Eureka Technology, Inc. ISA/PC Card/PCMCIA/ CompactFlash Host Adapter Eureka Technology, Inc. Universal NVM Express Controller (UNEX) Mobiveil, Inc. ONFI Controller SLS CompactFlash Interface1 SLS Qsys-compliant licensed core. Qsys component (no license required). 1 2 Altera Product Catalog * 2015 * www.altera.com73 PROTOCOLS Transceiver Protocols www.altera.com/datarates Altera device transceivers support the protocols listed in the following table. For details about the data rates, please visit www.altera.com/datarates. Supported Devices Protocols/ Interface Standards Stratix Series FPGAs Arria Series FPGAs Cyclone Series FPGAs V GX/GS V GT IV GX IV GT II GX 10 GX 10 GT V GX V GT/ST V GZ II GX II GZ V GX/SX V GT/ST IV GX Basic (proprietary) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CEI-6G-SR/LR 3 3 3 3 3 3 3 3 3 3 - - - - - CEI-11G-SR 3 3 - 3 - 3 3 - - - - - - - - CEI-28G-VSR - 3 - - - - 3 - - - - - - - - SFP+/SFF-8431 3 3 - 3 - 3 3 - - 3 - - - - - XFI 3 3 - 3 - 3 3 - 3 - - - - - - XFP 3 3 - - - 3 3 - - 3 - - - - - 1000BASE-X (GbE) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 10GBASE-R 3 3 - 3 - 3 3 - 3 3 - - - - - 10GBASE-KR 3 3 - - - 3 3 - - 3 - - - - - ASI 3 3 3 3 3 3 3 3 3 - 3 3 - - - CPRI 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CAUI/XLAUI 3 3 - 3 - 3 3 - - 3 - - - - - CAUI-4 - 3 - - - - 3 - - - - - - - - DisplayPort 3 3 3 3 3 3 3 3 3 3 - - 3 3 3 Fibre Channel 3 3 3 3 3 3 3 - 3 3 - - - - - GPON 3 3 3 3 - 3 3 3 3 3 3 3 - - - G.709 OTU-2 3 3 - 3 - 3 3 3 3 - - - 3 3 3 OTN with FEC 3 3 - 3 - 3 3 - - - - - - - - HiGig 3 3 3 3 3 3 3 3 3 3 3 3 - - - High-Definition Multimedia Interface (HDMI) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 74Altera Product Catalog * 2015 * www.altera.com PROTOCOLS Transceiver Protocols Supported Devices Stratix Series FPGAs Protocols Arria Series FPGAs Cyclone Series FPGAs V GX/GS V GT IV GX IV GT II GX 10 GX 10 GT V GX V GT/ST V GZ II GX II GZ V GX/SX V GT/ST IV GX JESD204 A/B 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 HMC1 - - - - - 3 3 - - - - - - - - HyperTransport 3 3 3 3 - 3 3 3 3 3 - - - - - InfiniBand 3 3 - - - 3 3 - - 3 - - - - - Interlaken 3 3 3 3 - 3 3 3 3 3 - - - - - Interlaken Look-Aside 3 3 - - - 3 3 3 3 3 - - - - - MoSys 3 - - - - 3 3 - - - - - - - - OBSAI 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PCI Express 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RXAUI/DXAUI 3 3 3 3 3 3 3 3 3 3 - - - - - SGMII/QSGMII 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 QPI 3 3 - - - 3 3 - - 3 - - - - - SAS/SATA 3 3 3 3 - 3 3 3 3 3 3 3 3 3 3 SerialLite II 3 3 3 3 - 3 3 3 3 - 3 3 - - - SerialLite III 3 3 - - - 3 3 - - 3 - - - - - SDI 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SFI-5.1 3 3 3 3 3 3 3 3 3 3 - - - - - SFI-S/SFI-5.2 3 3 - 3 - 3 3 - - 3 - - - - - RapidIO 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SPAUI 3 3 3 3 3 3 3 - - 3 - - - - - SONET/SDH 3 3 3 3 3 3 3 3 3 3 3 3 - - - XAUI (10GBASE-X) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 V-by-One 3 3 3 3 3 3 3 3 3 - - - - - 3 Contact Altera for more details on HMC support. 1 Altera Product Catalog * 2015 * www.altera.com75 DEVELOPMENT KITS Altera and Par tner D e velopment K its www.altera.com/selector Altera and partner development kits are listed below. For more details about these development kits or other older development kits that are available, check out our online selector guide at www.altera.com/selector. Product and Vendor Name Device The DSP Development Kit, Stratix V Edition provides a complete design environment that includes all the hardware and software you need to immediately begin developing DSP-intensive FPGA designs. The development kit is RoHScompliant. You can use this development kit to develop and test PCIe designs at data rates up Stratix V 5SGSMD5K2F40C2N to Gen3, develop and test memory subsystems for DDR3 SDRAM or QDR II SRAM memories, and use the high-speed mezzanine card (HSMC) connectors to interface to one of over 35 different HSMCs provided by Altera partners, supporting protocols such as Serial RapidIO, 10 Gbps Ethernet, SONET, CPRI, OBSAI, and others. DSP Development Kit, Stratix V Edition Altera Audio Video Development Kit, Stratix IV GX Edition Altera DSP Development Kit, Cyclone III Edition1 Altera Stratix IV GX EP4SGX230 This kit provides a complete video and image processing development environment for design engineers. It features the Stratix IV GX FPGA development board along with an SDI HSMC and associated reference designs. Cyclone III EP3C120N This kit is for general DSP or wireless design engineers, regardless of whether you need pre-processing, DSP plus FPGA coprocessing, or post-processsing. This kit includes complete 16 bit high-speed analog-to-digital (A/D) and digital-to-analog (D/A) converters (operating at up to 200 MSPS), as well as interfaces to TI DSP processors (DM642 and DaVinci). Altera's DSP Builder GUI simplifies the information flow between the FPGA toolset and MATLAB/Simulink (30-day evaluation copy included). Stratix V Stratix IV DSP ProcHILs GiDEL Cyclone III Video and Image Processing Development Kit1 Bitec Software Programmable Reconfiguration (SPR) Development System BittWare 1 Description Cyclone III EP3C120N Cyclone III FPGA This development kit provides a state-of-the-art Hardware in the Loop acceleration tool for running Simulink designs on Altera FPGAs. ProcHILs can automatically translate Simulink designs built using Altera's DSP Builder into FPGA code and run this code under Simulink. The generated code is compatible with the Proc board installed on the target PC and has the synchronization code needed to communicate with Simulink via PCIe. This kit is designed to help you start developing complex video applications. It supports various video I/O interfaces, allowing you to get your video data in and out of the Cyclone III FPGA. Different video interfaces are supported using the different daughtercards included in this kit: cards supporting asynchronous serial interface (ASI) or SDI, composite, component, and digital video interfaces (DVIs). This development system provides a system platform to explore software reconfiguration of waveform functionality for high-end signal processing applications such as software-defined radio. The platform provides a flexible, portable, low-cost environment for software-defined radio development in an Advanced Mezzanine Card (AdvancedMC) and Micro Telecommunications Computing Architecture (MicroTCA) SC DVI Output Module Bitec Daughtercard This module supports all Altera development kits with Altera DVI expansion slots. THDB-ADA Terasic Technologies, Inc. Daughtercard This card provides dual A/D channels with 14 bit resolution and data rates up to 65 MSPS and dual D/A channels with 14 bit resolution and data rates up to 125 MSPS. It supports both Altera HSMC and Terasic DE-style connectors. HSMC Dual-Link DVI Board Bitec Daughtercard This daughtercard is a two-channel, dual-link DVI output board for Altera FPGA development kits with HSMC expansion port. SC DVI Output Module Bitec Daughtercard This module supports all Altera development kits with Altera DVI expansion slots. RoHS compliant. 76Altera Product Catalog * 2015 * www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Stratix V GX FPGA Development Kit Altera I/O Interconnect Transceiver Signal Integrity Kit, Stratix V GX Edition Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition Altera 100G Development Kit, Stratix V GX Edition Altera Arria V GX FPGA Development Altera Arria V GX Starter Kit Altera Device Description Stratix V GX 5SGXEA7K2F40C2N This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to a Stratix V GX FPGA. This kit includes the PCIe x8 form factor, two HSMC connectors for expandability, and Ethernet, USB, and SDI interfaces. Memory includes one x72 DDR3 SDRAM, one x18 QDR II+ SRAM, and flash. This kit also includes two SMA connectors for a differential transceiver output. Several programmable oscillators are available and other user interfaces include three user push buttons, eight dual in-line package (DIP) switches, eight bi-color user LEDs, an LCD display, and power and temperature measurement circuitry. Stratix V GX 5SGXEA7N2F40C2N This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features include seven full-duplex transceiver channels with SMA connectors, two 14G backplane connectors (from Amphenol and Molex), four programmable clock oscillators, four user push buttons, eight DIP switches, eight user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, and Ethernet, an embedded USB Blaster download cable, and JTAG interfaces. Stratix V GT 5SGTMC7K3F40C2N The Altera Stratix V GT Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. This development kit can be used for evaluation of transceiver link performance up to 28 Gbps, generation and checking pseudo-random binary sequence (PRBS) patterns via an easy-to-use GUI that does not require the Quartus II software, access advanced equalization to fine-tune link settings for optimal bit error ratio (BER), jitter analysis, and verifying physical media attachment (PMA) interoperability with Stratix V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCIe Gen 3.0, 10GBASE-KR, 10 Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO, HD-SDI, and others. You can use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER. Stratix V GX 5SGXEA7N2F45C2N This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical modules, and applications requiring external memory interfaces through four x18 QDR II and four x32 DDR3 memory banks. With this kit, you can evaluate transceiver performance up to 11.3 Gbps, and verify PMA compliance to standards such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCIe (Gen1, Gen2, and Gen3), and other major standards. This kit can also validate interoperability between optical modules, such as SFP, SFP+, quad small form factor pluggable (QSFP), and CFP. Arria V GX 5AGXFB3H6F40C6N This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to an Arria V GX FPGA. This kit includes two Arria V 5AGXFB3H6F40C6N FPGAs, the PCIe x8 form factor, two HSMC connectors, one FPGA mezzanine card (FMC) connector, 1,152 MB 72 bit DDR3 SDRAM, 4 MB 36 bit QDR II+ SRAM, flash memory, and two additional 32 bit DDR3 SDRAM devices. This kit also includes SMA connectors and a bull's-eye connector for differential transceiver I/Os. Arria V GX 5AGXFB3H4F35C4 This kit provides a low-cost platform for developing transceiver I/O-based Arria V GX FPGA designs. This kit includes the PCIe x8 form factor, one HSMC connector, a 32 bit DDR3 SDRAM device, one-channel high-speed transceiver input and output connected to SMAs, HDMI output, SDI input and output, 16x2 LCD display, and flash memory. Altera Product Catalog * 2015 * www.altera.com77 DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Description Cyclone V E 5CEFA7F31C7N The Cyclone V E Development Kit offers a comprehensive general-purpose development platform for many markets and applications, including industrial, networking, military, and medical applications. The kit features an Altera Cyclone V device and a multitude of onboard resources including multiple banks of DDR3 and LPDDR2 memory, LCD character display, LEDs, user switches, USB, and RJ-45 connectors. The Cyclone V E FPGA Development Kit gives industrial equipment designers greater flexibility in implementing real-time Ethernet communications with industrial Ethernet IP cores. Cyclone V GT 5CGTFD9E5F35C7N This kit can be used to prototype Cyclone V GT FPGA or Cyclone V GX FPGA applications. It offers a quick and simple way to develop low-cost and low-power system-level designs and achieve rapid results. This kit supports a myriad of functionalities, such as FPGA prototyping, FPGA power measurement, transceiver I/O performance up to 5 Gbps, PCIe Gen2 x4 (at 5 Gbps per lane), endpoint or rootport support. Stratix IV GX EP4SGX230F1517 This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to a Stratix IV GX FPGA. This kit includes the PCIe x8 form factor, two HSMC connectors for expandability, and Ethernet, USB, SDI, and HDMI interfaces. Memory includes one x64 DDR3 SDRAM, one x16 DDR3 SDRAM, two x18 QDR II+ SRAM, flash, and SSRAM. This kit also includes two SMA connectors for a differential transceiver output. Several oscillators are available at 156.25 MHz,155.52 MHz, 125 MHz, 100 MHz, and 50 MHz. Other user interfaces include six user push buttons, eight DIP switches, eight user LEDs, 7-segment LCD display, and power and temperature measurement circuitry. Stratix IV GX EP4SGX530F1517 This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to a Stratix IV GX FPGA. This kit includes the PCIe x8 form factor, two HSMC connectors for expandability, and Ethernet, USB, SDI, and HDMI interfaces. Memory includes one x64 DDR3 SDRAM, one x16 DDR3 SDRAM, two x18 QDR II+ SRAM, flash, and SSRAM. This kit also includes two SMA connectors for a differential transceiver output. Several oscillators are available at 156.25 MHz,155.52 MHz, 125 MHz, 100 MHz, and 50 MHz. Other user interfaces include six user push buttons, eight DIP switches, eight user LEDs, 7-segment LCD display, and power and temperature measurement circuitry. 100G Development Kit, Stratix IV GT Edition Altera Stratix IV GT EP4S100G5F45I1N This kit enables a thorough evaluation of 100G designs. It supports 10G/40G line interfaces through optical modules, and applications requiring external memory interfaces through four x18 QDR II and four x32 DDR3 memory banks. With this kit, you can evaluate transceiver performance up to 11.3 Gbps, verify PMA compliance to standards, such as 10G/40G/100G Ethernet, Interlaken, CEI-6G/11G, Serial RapidIO, PCIe (Gen1, Gen2, and Gen3), and other major standards. This kit can also validate interoperability between optical modules, such as SFP, SFP+, QSFP, and CFP. Transceiver Signal Integrity Kit, Stratix IV GX Edition Altera Stratix IV GX EP4SGX230F1517 This kit features eight full-duplex transceiver channels with SMA connectors, 156.25 MHz, 155.52 MHz, 125 MHz, 100 MHz, and 50 MHz clock oscillators, six user push buttons, eight DIP switches, eight user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, and Ethernet, USB, and JTAG ports. Stratix IV EP4S100G2F40I1N This kit enables a thorough evaluation of transceiver interoperability and SERDES signal integrity by allowing you to evaluate transceiver performance up to 11.3 Gbps. You can generate and check PRBS patterns via a simple-to-use GUI, change differential output voltage (VOD), pre-emphasis, and equalization settings to optimize transceiver performance for your channel, perform jitter analysis, verify PMA compliance to 40G/100G Ethernet, Interlaken, CEI-6G/11G, PCIe -(Gen1, Gen2, and Gen3), Serial RapidIO, and other major standards, and validate interoperability between optical modules. Cyclone V E FPGA Development Kit Altera Cyclone V GT FPGA Development Kit Altera Stratix IV GX FPGA Development Kit Altera I/O Interconnect (Continued) Device Stratix IV GX FPGA Development Kit, 530 Edition Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Altera 78Altera Product Catalog * 2015 * www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Cyclone IV GX FPGA Development Kit Altera Cyclone IV GX Transceiver Starter Kit Altera I/O Interconnect (Continued) S5-6U-VPX (S56X) BittWare S5-PCIe-HQ (S5PH-Q) BittWare S5-PCIe (S5PE) BittWare PROCe V GiDEL Device Description Cyclone IV GX EP4CGX150DF31C7N This kit provides a comprehensive design environment that allows you to quickly develop low-cost and low-power FPGA system-level designs. This kit includes the PCIe short card form factor, two HSMC connectors, and a 10/100/1000 Mbps Ethernet interface. Onboard memory includes 128MB DDR2 SDRAM, 64 MB flash, and 4 MB SSRAM. This kit also includes SMA connectors, and 50 MHz, 100 MHz, and 125 MHz clock oscillators, as well as user interfaces including push buttons, LEDs, and a 7-segment LCD display. Cyclone IV GX EP4CGX15 This kit provides a low-cost platform for developing transceiver I/O-based FPGA designs. It includes the complete hardware and software you need to develop your FPGA design for cost-sensitive applications. You can measure the FPGA's power consumption, test the signal quality of the FPGA transceiver I/Os (up to 2.5 Gbps), and develop and test PCIe Gen1 designs. Stratix V GX/GS This rugged 6U VPX card is based on Altera's Stratix V GX or GS FPGAs. When combined with BittWare's Anemone FPGA coprocessor, the ARM Cortex-A8 control processor, and the ATLANTiS FrameWork FPGA development kit, it creates a flexible and efficient solution for high-performance signal processing and data acquisition. The board provides a configurable 48-port multi-gigabit transceiver interface supporting a variety of protocols, including Serial RapidIO, PCIe, and 10GbE. Additional I/O interfaces include Ethernet, RS-232, JTAG, and LVDS. The board features up to 8 GB of DDR3 SDRAM as well as flash memory for booting the FPGAs. Two VITA 57-compliant FMC sites provide additional flexibility for enhancing the board's I/O and processing capabilities. Stratix V GX/GS This half-length PCIe x8 card is based on Altera's Stratix V GX or GS FPGA and is a versatile and efficient solution for high-performance network processing, signal processing, and data acquisition. Combining it with BittWare's Anemone coprocessor and ATLANTiS FrameWork enhances productivity and portability, and allows even greater processing efficiency. Over 16 GB of onboard memory includes DDR3 SDRAM and QDR II/II+ SRAM. Two front-panel QSFP+ cages provide additional flexibility for serial I/O, allowing two 40GbE interfaces (or eight 10GbE), direct to the FPGA for reduced latency, making it ideal for high-frequency trading and networking applications. Stratix V GX/GS This PCIe x8 card is based on Altera's Stratix V GX or GS FPGA and is designed for high-performance network processing, signal processing, and data acquisition. Combining it with BittWare's Anemone coprocessor and ATLANTiS FrameWork enhances productivity and portability and allows even greater processing efficiency. The board provides up to 32 GB of DDR3 SDRAM with optional ECC. An optional VITA 57 FMC site provides additional flexibility for enhancing the board's I/O and processing capabilities, making it ideal for analog I/O and processing. The board also has the option of two front-panel QSFP+ cages for serial I/O, which support 10G per lane direct to the FPGA for reduced latency, making it ideal for high-frequency trading and networking applications. It is also available with A/D and D/A conversion options. Stratix V GX/GS (Gen3 x8) 5SGXMA3K2F40C3N 5SGXMA7K2F40C2N 5SGSMD8K2F40C2N This half-length PCIe x8 card is based on Altera's Stratix V GX or GS FPGA and is a versatile and efficient solution for high-performance network processing, signal processing, and data acquisition. Combining it with GiDEL's PROCWizard software and data management IP cores enhances productivity and portability, and allows even greater processing efficiency. The platform features 16+ GB of onboard memory that includes DDR3 SDRAM and SRAM. Typical sustainable throughput is 8,000 GBps for internal memories and 25+ GBps for onboard memory. Networking capabilities include one CXP connector cage suitable for 100GbE Ethernet (100GBASE-CR10, 100GBASE-SR10), 3x40 GbE, or single Infiniband 12xQDR link, two SFP+ cage suitable for 10 GbE, and Optical Transport Network. Additional I/O interfaces, 2x high-speed inter-board connectors (up to 12x14.1Gbps full duplex GPIO) for board-to-board and proprietary daughterboards connectivity. Altera Product Catalog * 2015 * www.altera.com79 DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name ProcFG GiDEL I/O Interconnect (Continued) S4-3U-VPX (S43X) BittWare SP/D4-AMC (D4AM) BittWare SP/S4-AMC (S4AM) BittWare 4S-XMC (4SXM) BittWare 80Altera Product Catalog * 2015 * Device Description Stratix V GX Stratix IV E This kit is based on Altera's Stratix FPGA. It is used for development of vision algorithms, machine vision, and medical imaging applications. ProcFG combines high-speed acquisition and powerful FPGA processing with selective on-the-fly region of interest (ROI) offloading for convenient processing on standard PCs. The ProcFG captures all incoming image data or dynamically targets and extracts ROIs based on real-time FPGA analysis of the incoming data, and supports acquisition from both line and area scan cameras. Stratix IV GX This commercial or rugged 3U VPX card is based on Altera's Stratix IV GX FPGA that is designed specifically for serial I/O-based applications, creating a completely flexible, reconfigurable VPX board. BittWare's ATLANTiS FrameWork and the FINe Host/Control Bridge greatly simplify application development and integration of this powerful board. The board provides a configurable 25-port SERDES interface supporting a variety of protocols, including Serial RapidIO, PCIe, and 10GbE. The board also features 10/100/1000 Ethernet, and up to 4 GB of DDR3 SDRAM. The VITA 57-compliant FMC site provides enhanced flexibility, which supports 10 SERDES, 60 LVDS pairs, and 6 clocks. Stratix IV This board features the I/O processing power of two Altera Stratix IV FPGAs and is a mid- or full-size, single-width AdvancedMC that can be attached to AdvancedTCA carriers or other cards equipped with AMC bays, and used in MicroTCA systems. An Altera Stratix IV GX FPGA paired with a Stratix IV E FPGA makes the D4AM an extremely high-density, flexible board. The FPGAs are connected by two full-duplex 2 GBps lanes of parallel I/O for data sharing. Each FPGA supports BittWare's ATLANTiS FrameWork to greatly simplify application development and integration. A VITA 57-compliant FMC site provides enhanced flexibility, which connects directly to the Stratix IV E FPGA for LVDS and to the Stratix IV GX FPGA for SERDES. The board also provides an IPMI system management interface and a configurable 18-port AMC SERDES interface supporting a variety of protocols. Onboard memory includes up to 1 GB of DDR3 SDRAM and 128 MB of flash memory, and Ethernet is available via the AMC front and rear panels. It is also available with A/D and D/A conversion options. Stratix IV GX This board is based on Altera's Stratix IV FPGA and is a mid- or full-size, single-width AdvancedMC that can be attached to AdvancedTCA carriers or other cards equipped with AMC bays, and used in MicroTCA systems. The S4AM features a high-density, low-power Altera Stratix IV GX FPGA designed specifically for serial I/O-based applications, creating a completely flexible, reconfigurable AMC. Providing enhanced flexibility is the VITA 57-compliant FMC site, which features 8 SERDES, 80 LVDS pairs, and 6 clocks directly to the FPGA. BittWare's ATLANTiS FrameWork, in conjunction with the FINe III Host/Control Bridge, greatly simplifies application development and integration of this powerful board. The board also provides an IPMI system management interface, a configurable 15-port AMC SERDES interface supporting a variety of protocols, and a front panel 4x SERDES interface supporting CPRI and OBSAI. Additionally, the board features 10/100 Ethernet, GbE, two banks of DDR3 SDRAM, two banks of QDR II+ SRAM, and flash memory for booting the FPGAs and FINe. It is also available with A/D and D/A conversion options. Stratix IV GX This is a single-width switched mezzanine card (XMC), designed to provide powerful FPGA processing and high-speed serial I/O capabilities to VME, VXS, VPX, cPCI, AdvancedTCA, or PCIe carrier boards. The 4SXM features a high-density, low-power Altera Stratix IV GX FPGA, which was designed specifically for serial I/O-based applications and is PCI-SIG(R) compliant for PCIe Gen1 and Gen2. Four SFP compact optical transceivers are available on the front panel. There are 8 multigigabit serial lanes supporting PCIe, Serial RapidIO, and 10GbE available via the board's rear panel, as well as 44 general-purpose digital I/O signals. The 4SXM also provides QDR II+ SRAM and flash memory. www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Description S4GX-AMC BittWare Stratix IV GX EP4SGX230F1517 This board is based on Altera's Stratix IV GX FPGA and is a mid-size, single-width AdvancedMC that can be attached to AdvancedTCA carriers or other cards equipped with AdvancedMC bays, and used in MicroTCA systems. This board has two banks of DDR3 SDRAM (up to 1 GB each), and two banks of QDR II SRAM (up to 9 MB). Includes IP support for Serial RapidIO, PCIe, GbE, 10G Ethernet (XAUI), CPRI, and OBSAI interfaces. ProcE GiDEL EP4S820E EP3S340L EP2S60F1020C4N This Altera-based PCIe x4 platform is ideal for high-speed data acquisition, algorithmic acceleration, IP validation, and verification of small SoCs. This board has five levels of memory structure (8.5 GB+) with maximum sustainable throughput of 4,693 GBps for internal memories and 12 GBps for DRAM. Stratix IV EP4S100G5 EP4SGX530 This board integrates the most fundamental electrical and optical interfaces for building 200G subsystems. It implements CAUI and Interlaken high-speed serial interfaces, industry-leading, high-speed DDR3 SDRAM and QDR II+ SRAM interfaces, and high-speed parallel interconnect for NetLogic knowledge-based processors (KBPs). The modular design enables expansion to support legacy and emerging optical modules. Stratix IV GX EP4SGX230KF40C2N This kit provides a complete hardware and software environment for Altera Stratix IV GX FPGAs. It is built around a PCI form factor card compliant with PCI-SIG and targets the development of designs using PCIe Gen1 or Gen2. Cyclone III EP3C16 This kit aids the development and testing of algorithms and signal processing applications including digital radio, modulator/demodulator development, software-defined radio, high-speed data acquisition and signal processing, and audio data acquisition and signal processing. The acquired signals are sampled and then digitally processed by a Cyclone III FPGA. The FPGA card comes with a JTAG programming connector and a configuration PROM to retain the FPGA settings. The PCI card provides interfaces for the FPGA card to a computer PCI bus, RS232 interface, and user push buttons and includes a digital radio reference design example and full documentation. Cyclone III FPGA/ PCI Development Board CEPD Cyclone III EP3C16F484C8N This board provides a platform for fast and easy prototyping and design verification with the Cyclone III EP3C16F484C8N FPGA. It can be accessed either through the PCI bus or powered as a stand-alone system and accessed through an RS232 port. It comes with an onboard configuration PROM to retain the FPGA settings, an RS232 level shifter, voltage monitor, oscillator, buttons, and LEDs. There is a prototyping area on the board for user circuits and all FPGA pins are accessible through connectors and clearly labeled test points. The connectors are designed to mate with other CEPD daughterboards. SuperUSBC3-55 PLDA Cyclone III EP3C55U484C6N This kit provides a low-cost hardware and software environment for prototyping and deploying SuperSpeed USB applications. It targets the Altera Cyclone III FPGA (EP3C55F484C6N) and includes everything you need to implement a complete USB 3.0 subsystem. Cyclone III FPGA This board provides a hardware platform for developing and prototyping low-power, high-performance, logic-intensive PCI-based designs on an Altera Cyclone III FPGA. External memory is provided to facilitate the development of designs that need extra storage capacity or higher bandwidth memory. It also includes an LVDS interface using high-speed Terasic connectors (HSTCs) for high-speed interface applications. Cyclone II EP2C20F256C7 This kit includes one QuickUSB module and one QuickUSB Cyclone II Evaluation Board. The evaluation board has a QuickUSB module site on headers that provide access to the signals. The EP2C20F256C7 FPGA connects to nearly every pin of the QuickUSB module, and extra I/O pins go to the headers so you can wire in your circuitry. The kit gets its power from the USB bus, but if you need more power, there is a power connector and a 5V 2A power supply included in the kit. Stratix IV GX/GT 40G/ 100G Interlaken HiTech Global Xpress GX4 Kit PLDA I/O Interconnect (Continued) Device C3 Digital Radio Kit CEPD PCI-X Development Board Terasic Technologies, Inc. QuickUSB Starter Kit Bitwise Systems Altera Product Catalog * 2015 * www.altera.com81 DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Description Daughtercard This daughtercard is designed for evaluating the Averlogic AL460A HD-FIFO. It has two embedded AL460A-7-PBF (or AL460A-13-PBF) devices operating in parallel, expanding the bus width to 32 bits. Control signals and data bus signals are available on two 50-pin connectors. A separate adaptor board (HSMC interface) is available for connecting the module directly to a Cyclone III FPGA Starter Kit. Daughtercard This card is designed for professional video equipment developers. The dual ASI/ SD-SDI interfaces allow access to industry-standard video transport signals. Based on the latest adaptive cable equalizers and drivers, the ASI/SDI interfaces provide excellent noise immunity up to cable lengths of 350 meters. A voltage-controlled crystal oscillator (VCXO) allows precise synchronization to incoming ASI signals. A DVB-T reference design using the Bitec broadcast video card daughtercard and a Cyclone III FPGA Development Kit is available. Daughtercard This board is based on the Texas Instruments TVP5154 quad video decoder. The analog video inputs include composite video and S-video. Video output is based on the Chrontel CH7010B device, enabling single-link DVI, component analog, and composite analog outputs. The device accepts digital, parallel video data, and clocking from the host FPGA via the HSMC connector, which configures and monitors the device over an I2C link. A DVI output connector and mini-DIN output connector are provided. Daughtercard This daughtercard interfaces a HDMI receiver and transmitter to your Altera FPGA development kit using the HSMC expansion connector. The receiver also supports an analog component video (YCbCr) interface. The card uses the Analog Devices AD9889 HDMI Transmitter and AD9880 HDMI Receiver to support HDTV formats up to 1080p at 60 Hz. The receiver offers the flexibility of both an analog interface and an HDMI receiver integrated on a single chip. Quad Link LVDS Interface Microtronix Daughtercard This daughtercard supports receive and transmit LVDS links, each consisting of five data channels and one clock for a total of 48 LVDS channels. The standard configuration of 20 TX + 4 clk and 20 RX + 2 clk is capable of supporting LCD display panels up to 1080p at 100/120 Hz. Onboard LVDS termination resistors can be removed to convert receiver channels into transmitters as required to support 12 bit or 14 bit color applications. It is used for capturing LVDS video data, connecting to a camera link interface, or connecting to LCD panels using LVDS, mini-LVDS, RSDS, and PPDS low-voltage panel interface signaling. Ethernet USB Expansion Kit Microtronix Inc. Daughtercard This kit includes a wireless 802.11b CompactFlash card and a Microtronix CompactFlash board. I2C Design Kit Microtronix Inc. Daughtercard This kit provides an easy way to design, develop, and test the Microtronix I2C IP core. 10/100/1000 Ethernet PHY Daughter Board with Marvell PHY MorethanIP Daughtercard This kit provides the ability to implement high-speed Ethernet PHY solutions for prototyping and evaluation and embedded software development. 10/100/1000 Ethernet PHY Daughter Board with Texas Instruments PHY MorethanIP Daughtercard This kit provides the ability to implement fast Ethernet solutions for prototyping and evaluation and embedded software development. CX4 to HSMC Adapter MorethanIP Daughtercard This passive daughtercard for 10GbE CX-4 copper interconnect prototyping features a four-lane differential 3.125 Gbps connector (CX-4) for 10GbE IEEE 802.3ak, a 160-pin HSMC to the main board, and compatibility with Stratix II GX mother boards that use HSMC connectors. SFP HSMC Terasic Technologies, Inc. Daughtercard This SFP HSMC is for the development of SGMII Ethernet, Fibre Channel, CPRI/ OBSAI, and SONET designs based on transceiver-based host boards with HSMC connectors. HD FIFO Modules Averlogic Broadcast Video Card Bitec Quad Video Board Bitec I/O Interconnect (Continued) Device HDMI Receiver/Transmitter Microtronix 82Altera Product Catalog * 2015 * www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Arria V SoC Development Kit and SoC Embedded Design Suite Altera Cyclone V SoC Development Kit Altera Embedded Cyclone V GT FPGA Development Kit Altera Cyclone V E FPGA Development Kit Altera Nios II Embedded Evaluation Kit, Cyclone III Edition1 Altera Cyclone III FPGA Development Kit Altera Nios II Development Kit, Cyclone III Edition1 Altera 1 Device Arria V SoC 5ASTFD5K3F40I3NES Description The Altera Arria V SoC Development Kit offers a quick and simple approach to develop custom ARM processor-based SoC designs. Altera's midrange, transceiver-based Arria V FPGA fabric provides the highest bandwidth with the lowest total power for midrange applications such as remote radio units, 10G/40G line cards, medical imaging, broadcast studio equipment, and the acceleration of image- and video-processing applications. This development kit includes the SoC Embedded Design Suite software development tools. The development board has PCIe Gen2 x4 lanes (endpoint or rootport), two FMC expansion headers, dual Ethernet PHYs, and various DRAM and flash memories. The Altera Cyclone V SoC Development Kit offers a quick and simple approach to develop custom ARM processor-based SoC designs accompanied by Altera's Cyclone V SoC low-power, low-cost Cyclone V FPGA fabric. This kit supports a wide range of 5CSXFC6D6F31C8NES functions, such as processor and FPGA prototyping and power measurement, industrial networking protocols, motor control applications, acceleration of image- and video-processing applications, PCIe x4 lane with ~1,000 MBps transfer rate (endpoint or rootport). Cyclone V GT 5CGTFD9E5F35C7N Cyclone V E 5CEFA7F31C7N This kit can be used to prototype Cyclone V GT FPGA or Cyclone V GX FPGA applications. It offers a quick and simple way to develop low-cost and low-power system-level designs and achieve rapid results. This kit supports a myriad of functionality, such as FPGA prototyping, FPGA power measurement, transceiver I/O performance up to 5.0 Gbps, PCIe Gen2 x4 (at 5.0 Gbps per lane), endpoint or rootport support. The Cyclone V E Development Kit offers a comprehensive general-purpose development platform for many markets and applications, including industrial, networking, military, and medical applications. The kit features an Altera Cyclone V device and a multitude of onboard resources, including multiple banks of DDR3 and LPDDR2 memory, LCD character display, LEDs, user switches, USB, and RJ-45 connectors. The Cyclone V E Development Kit gives industrial equipment designers greater flexibility in implementing real-time Ethernet communications with industrial Ethernet IP cores. Cyclone III EP3C25N This kit includes a complete hardware and software design environment for a 32 bit microcontroller plus FPGA evaluation. Beginners can check out the pre-built, eye-catching demos displayed on the LCD touch screen or do some lightweight development. Advanced microcontroller designers can learn about the latest techniques, multiprocessor systems, or about designing a complete system in 30 minutes. Cyclone III EP3C120N This kit contains 8 MB SSRAM, 256 MB DDR2 SDRAM, 64 MB flash, configuration via USB, 10/100/1000 Ethernet and USB ports, onboard oscillators and SMAs, graphics LCD and character LC displays, two HSMC expansion connectors, three HSMC debug cards, and onboard power measurement circuitry. Complete documentation including reference designs is also included: Create Your First FPGA Design in an Hour and Measure Cyclone III FPGA Power. This kit also includes Quartus II Web Edition design software, an evaluation edition of the Nios II processor plus related design suite, and the Altera IP library. Cyclone III EP3C120N The unique combination of high-performance embedded processor power and easy-to-use integrated design software has been updated to take advantage of Cyclone III devices, the industry's lowest cost, first-to-market 65 nm FPGA family. This development kit provides an ideal environment for developing and prototyping a wide range of price-sensitive, high-performance embedded applications. RoHS compliant. Altera Product Catalog * 2015 * www.altera.com83 DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Stratix IV E Stratix III L Stratix III E PROC104 GiDEL Stratix IV EP4SE530H35C2N (1-4 FPGAs) PROCStar IV GiDEL Embedded (Contniued) Device BeMicro SDK Arrow Industrial Networking Kit Terasic Technologies, Inc. Description This is a PCIe/104 standard Altera-based platform incorporating compact, self-stacking, and rugged industrial-standard connectors. This powerful platform is ideal for high-performance FPGA development and deployment across a range of size, weight, and power-constrained (SWaP-constrained) application areas, including signal intelligence, image processing, software-defined radio, and autonomous modules, or vehicles. The PROC104 can be hosted via 4-lane PCIe and is stackable. The board's high-speed performance coupled with memory and add-on daughterboards' flexible architecture enable the system to meet almost any computational needs. In addition to 512 MB onboard memory, two SODIMM sockets provide up to 8 GB of memory. This full-length PCIe x8 card is based on Altera's Stratix IV E FPGAs. It provides a high-capacity, high-speed FPGA-based platform fortified with high throughput and massive memory resulting in a powerful and highly flexible system. The performance, memory, and add-on daughterboards' flexible architecture enable the system to meet almost any computation needs. In addition to 2 GB onboard memory, 8 SODIMM sockets provide up to 32 GB of memory or additional connectivity and logic. The largest FPGA-based supercomputer at the National Science Foundation Center for High-Performance Reconfigurable Computing (NSF CHREC) center houses 100 of these cards (400 Altera FPGAs) and is used for Bio-RC, HFT, data mining, and seismic analysis applications. Cyclone IV E EP4CE22F17C7N This Arrow BeMicro SDK enables a quick and easy evaluation of soft core processors for both embedded software developers and hardware engineers. The kit builds on the success of the original BeMicro evaluation kit by adding features, such as Mobile DDR memory, Ethernet, and even the option of using a file system by slotting in a micro-SD card. The BeMicro SDK connects to a PC via a USB connection, which is used for power, programming, and debugging. Arrow has a number of reference designs and pre-built software templates that can be downloaded for this kit that highlight the benefits of building embedded systems in FPGAs. Cyclone IV E EP4CE115 The Industrial Networking Kit (INK) offers a comprehensive development platform for industrial automation and applications. The kit consists of the DE2-115 board featuring the Altera Cyclone IV device and dual 10/100/1000-Mbps Ethernet, 128 MB SDRAM, 8 MB flash memory, 2 MB SRAM, HSMC and GPIO connectors, USB 2.0, an SD card slot, switches and buttons, LEDs, 16x2 display, audio and video, and VGA-out. The kit also includes an Industrial Communications Board (ICB-HSMC) that supports RS-485, RS-232, CAN, and additional I/O expansion. Cyclone III EP3C25 MAX IIG EPM240T100 This platform uses the low-power Altera Cyclone III FPGAs and MAX IIG CPLDs. It demonstrates how to minimize power consumption in portable and battery-powered embedded systems and gives you the flexibility to create application-specific low-power solutions. Cyclone III EP3C25 This module allows you to implement general logic functions and Nios II processor operations in a compact form factor module. The module uses the Cyclone III EP3C25 FPGA, 512K x8 SRAM, EP1S16 FPGA serial loader (FPGA and Nios II processor boot), and a USB 2.0 peripheral port (low- and full-speed operation). This module also supports the Cardstac specification (master or slave standard card, 128 pins), and can interface with other modules designed to that specification. Lancelot VGA IP Design Kit Microtronix Inc. Daughtercard This kit includes a small hardware board with a 24 bit RAMDAC, VGA connector, stereo audio connector, and two PS/2 connectors. Compact Flash Expansion Kit Microtronix Inc. Daughtercard This inexpensive module allows the addition of compact flash cards to the Microtronix Product Starter Kit development board system. Low-Power Reference Platform Arrow CMCS002M Controller FPGA Module Dallas Logic 84Altera Product Catalog * 2015 * www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name Stratix IV E FPGA Development Kit Altera Stratix III FPGA Development Kit Altera ASIC Prototyping ProcSoC3-4S System GiDEL ProcE GiDEL Single-FPGA (Tile) Prototyping Solution Polaris Design Systems Multi-FPGA (Logic) Prototyping Solution Polaris Design Systems DN7002k10MEG The Dini Group DN7406k10PCIe-8T The Dini Group Device Description Stratix IV E EP4SE530 This kit allows rapid and early development of designs for high-performance Stratix IV FPGAs. The development board provides general I/Os that connect to onboard switches and indicators, and to the included two-line LCD and 128 x 64 graphics display. The board also has non-volatile and volatile memories (64 MB flash, 4 MB pseudo-SRAM, 36 Mb QDR II SRAM, 128 MB DDR2 DIMM, and 16 MB DDR2 device), HSMC, and 10/100/1000 Ethernet interfaces. The kit is delivered with Quartus II software and all of the cabling required to start using the board straight out of the box. Stratix III EP3SL150 This kit allows rapid and early development of designs for high-performance Stratix III FPGAs. The development board provides general I/Os that connect to onboard switches and indicators, and to the included two-line LCD and 128 x 64 graphics display. The board also has non-volatile and volatile memories (64 MB flash, 4 MB pseudo-SRAM, 36 Mb QDR II SRAM, 128 MB DDR2 DIMM, and 16 MB DDR2 device), HSMC, and 10/100/1000 Ethernet interfaces. The kit is delivered with Quartus II software and all of the cabling required to start using the board straight out of the box. Stratix IV EP4SE820F43C3 PROC_SoC Verification System provides scalability of multiple interconnected FPGA modules, enabling verification of SoC designs from 6 million to 360 million equivalent ASIC gates. Each ProcSoC module itself is a modular and scalable SoC verification system. Fast GbE connection combined with GiDEL's development tools enable it to run the target software or regression suites via remote servers connected to the SoC/ASIC design. The remote operation is performed at near actual system speed allowing for hardware-software integration and co-verification. Two chassis configurations are available, ProcSoC3 and ProcSoC10, capable of supporting up to 3 or 10 PROC12M boards, respectively. Each ProcSoC system can prototype a single SoC or be partitioned to prototype multiple designs in parallel. The ProcSoC's unique interconnectivity topology enables any FPGA to connect directly to any other FPGA in the system even in large systems. Stratix IV, III EP4S820E EP3S340L This Altera-based PCIe x4 platform is ideal for high-speed data acquisition, algorithmic acceleration, IP validation, and verification of small SoCs. This board has five levels of memory structure (8.5 GB+) with maximum sustainable throughput of 4,693 GBps for internal memories and 12 GBps for DRAM. Stratix IV This single-FPGA prototyping board can accommodate up to 15 million gate designs. It has a single Stratix IV FPGA and 18 Mb of SRAM. The board can be used either in a rack-mountable system or as a stand-alone unit. Stratix IV This multi-FPGA prototyping board can accommodate up to 30 million gate designs. The board has three Stratix IV FPGAs, SRAM, and 2 GB of DDR3 SDRAM (expandable to 8 GB). The board can be used either in a rack-mountable system or as a stand-alone unit. Stratix IV EP4SE820F43CxN EP4SE530F43CxN This complete logic emulation system allows you to prototype SoC logic and memory designs. It can operate as a stand-alone system, or be hosted via a USB interface. A single system, configured with two Stratix IV EP4SE820 FPGAs, can emulate up to 13 million gates. All FPGA resources are available for the target application. Each FPGA position can use any available speed grade. Stratix IV EP4SE820F43CxN EP4SE530F43CxN This complete logic prototyping system allows you to prototype logic and memory designs. The DN7406k10PCIe-8T is hosted in an eight-lane PCIe Gen1 bus, but can be used as a stand-alone system configured via USB or CompactFlash. A single board configured with six Altera Stratix IV EP4SE820 FPGAs can emulate up to 31 million gates. All of the FPGA resources are available for your application, and any combination of speed grades can be used. DN7020k10 The Dini Group Stratix IV This complete logic prototyping system gives ASIC and IP designers a vehicle to prototype logic and memory designs using up to 20 Stratix III or Stratix IV devices. DN7006K10PCIe-8T The Dini Group Stratix IV This complete logic prototyping system with a dedicated PCIe interface gives ASIC and IP designers a vehicle to prototype logic and memory designs using up to six Stratix III or Stratix IV devices. Altera Product Catalog * 2015 * www.altera.com85 DEVELOPMENT KITS Altera and Par tner D e velopm ent K its Product and Vendor Name Device Arria 10 FPGA Development Kit Altera Arria 10 Arria 10 MAX 10 This kit offer a comprehensive general-purpose development platform for many markets and applications, such as industrial and automotive. This fully featured development kit includes a 10M50DAF484C6G device, DDR3 memory, 2X 1 GbE, HSMC connector, quad serial peripheral interface, 16 bit digital-to-analog converter (DAC) flash, and 2X PMOD headers. MAX 10 The 10M08 evaluation board will enable a cost-effective entry point to MAX 10 FPGA design. The card comes complete with an Arduino header socket, which will enable a wide variety of daughtercards to be connected. Other features include a MAX 10 10M08SAE144C8G device, Arduino shield expansion, access to 80 I/O through-holes, and prototype area. Stratix V 2x 5SGXEA7N2F45C2N This kit is a complete systems design environment that includes both the hardware and software needed to begin architecture development and system design using Stratix V FPGAs. The PCIe-based form-factor utilizes a x16 edge connector, and includes high memory bandwidth to DDR3, QDR II+, and serial memory. Multiple high-speed protocols are accessible through FMC and HSMC connections. Cyclone V GT 5CGTFD9E5F35C7N This kit can be used to prototype Cyclone V GT FPGA or Cyclone V GX FPGA applications. It offers a quick and simple way to develop low-cost and low-power system-level designs and achieve rapid results. This kit supports a myriad of functionality, such as FPGA prototyping, FPGA power measurement, transceiver I/O performance up to 5 Gbps, and PCIe Gen2 x4 (at 5 Gbps per lane), endpoint or rootport support. General Purpose MAX 10 FPGA Development Kit Altera MAX 10 FPGA Evaluation Kit Altera Cyclone V GT FPGA Development Kit Altera Cyclone V E FPGA Development Kit Altera 86Altera Product Catalog Cyclone V E 5CEFA7F31C7N * 2015 * This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to an Arria 10 GX FPGA. This kit includes the PCIe x8 form factor, two FMC connectors for expandability, Ethernet, USB, and SDIs. The board includes one connector for plugging in DRAM and SRAM daughtercards. Supported daughtercard formats include DDR4 x72 SDRAM, DDR3 x72 SDRAM, RLDRAM 3 x36, and QDR IV x36 SRAM. This board also includes SMA connectors for transceiver output, clock output, and clock input. Several programmable oscillators are available and other user interfaces include user push buttons, DIP switches, bi-color user LEDs, an LCD display, power, and temperature measurement circuitry. This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features include five full-duplex 28 Gbps transceiver channels with edge launch connectors, one 14 Gbps backplane connector (from Amphenol), and ten full-duplex 12.5 Gbps transceiver channel with Samtec Bullseye connector. This board also includes several programmable clock oscillators, user push buttons, DIP switches, user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, Ethernet, an embedded USB-Blaster II, and JTAG interfaces. Arria 10 FPGA Signal Integrity Kit Altera Stratix V Advanced Systems Development Kit Altera Description www.altera.com The Cyclone V E FPGA Development Kit offers a comprehensive general-purpose development platform for many markets and applications, including industrial, networking, military, and medical applications. The kit features an Altera Cyclone V device and a multitude of onboard resources including multiple banks of DDR3 and LPDDR2 memory, LCD character display, LEDs, user switches, USB, and RJ-45 connectors. The Cyclone V E Development Kit gives industrial equipment designers greater flexibility in implementing real-time Ethernet communications with Industrial Ethernet IP cores. DEVELOPMENT KITS Altera and Par tner D e velopment K its Product and Vendor Name MAX V CPLD Development Kit Altera Cyclone III FPGA Starter Kit1 Altera Cyclone III LS FPGA Development Kit Altera General Purpose (Continued) BeMicro MAX 10 FPGA Evaluation Kit Arrow Mpression Odyssey MAX 10 FPGA IoT Evaluation Kit Macnica DE2-115 Development and Education Board Terasic Technologies, Inc. Video Development Kit Bitec ViClaro III HD Video Enhancement Development Platform Microtronix DE0 Development Board Terasic Technologies, Inc. CoreCommander Development Kit System Level Solutions 1 Device Description MAX V 5M570Z This low-cost platform will help you quickly begin developing low-cost, low-power CPLD designs. Use this kit as a stand-alone board or combined with a wide variety of daughtercards that are available from third parties. Cyclone III EP3C25N This kit contains 1 MB SSRAM, 16 MB DDR SDRAM, 16 MB parallel flash, configuration via USB, four user push buttons, four user LEDs, and power measurement circuitry. Complete documentation including reference designs is provided: Create Your First FPGA Design in a Hour, Measure Cyclone III FPGA Power, and Create Your First Nios II Design. This kit also includes Quartus II Web Edition design software, the evaluation edition of the Nios II processor plus related design suite, and the Altera IP library. Cyclone III LS EP3CLS200F780C7N This kit combines a high-density, low-power Cyclone III LS FPGA with a complete suite of security features implemented at the silicon, software, and IP levels. These security features provide passive and active protection of your IP from tampering, reverse engineering, and counterfeiting. It uses the EP3CLS200 FPGA--200K LEs at less than 0.25 W static power. MAX 10 MAX 10 The BeMicro MAX 10 FPGA evaluation kit is an entry-level kit from Arrow that includes the 10M08DAF484C8G device, 8 MB SDRAM, 2X PMOD headers, and 2X 40-pin prototype headers. The Macnica MAX 10 FPGA evaluation kit connects and controls your FPGA design via Bluetooth using the Mpression Odyssey Smartphone application. This kit also includes a 10M08U169C8G device, SDRAM, Arduino shield expansion capability, and Bluetooth SMART connectivity module. Cyclone IV E EP4CE115 This board is part of the DE2 educational development board series and features the Cyclone IV E EP4CE115 FPGA. The DE2-115 offers an optimal balance of low cost, low power, and a rich supply of logic, memory and DSP capabilities, as well as interfaces to support mainstream protocols including GbE. A HSMC connector is provided to support additional functionality and connectivity via HSMC daughtercards and cables. Cyclone III FPGA This kit contains the Cyclone III FPGA Development Kit and two HSMC video interface cards together with a collection of IP cores and reference designs. The kit provides a variety of video interface standards including both digital and analog up to HD resolutions. Cyclone III FPGA This video enhancement development platform supports 100/120-Hz HDTV that is 1080p bandwidth-capable and features 32 bit DDR2 SDRAM memory, a HDMI transmitter, an analog/HDMI receiver, and dual LVDS links. Cyclone III EP3C16F484C6N This board provides all the essential tools for you to learn about digital logic and FPGAs. It is equipped with an Altera Cyclone III EP3C16 FPGA, which offers 15,408 LEs. The board provides 346 user I/O pins and is loaded with a rich set of features. It is suitable for advanced university and college courses as well as the development of sophisticated digital systems, and includes software, reference designs, and accessories. Cyclone III EP3C25F256C8 This kit features the Altera Cyclone III FPGA that provides more than enough room for almost any embedded design. This flexible board comes with a suite of SLS IP Cores, drivers, and application software. Delivered as a complete package, this kit ensures quick and easy implementation of industry-leading cores with reduced risk, at a very low cost. RoHS compliant. Altera Product Catalog * 2015 * www.altera.com87 DEVELOPMENT KITS Altera and Par tner D e velopment K its General Purpose (Continued) Product and Vendor Name Device Description ProcPAK II GiDEL Cyclone II EP2C35 ProcPAK II development kit is based on Altera's Stratix II FPGA platform. The development kit greatly improves time to market. There is no need to design the board, the PCI driver, or the application driver layer, define board constraints, design memory controller, and write environment FPGA code. This kit enables designers to focus on their proprietary value-added design instead of spending their valuable effort to recreate standard design components. With ProcMultiPort innovative memory controller, the generated HDL code enables high-speed, easy-to-use parallel access to large memories. DE1 Development Board Terasic Technologies, Inc. Cyclone II EP2C20 This board is a smaller version of the DE2 board. It is useful for learning about digital logic and FPGAs. Featuring an Altera Cyclone II EP2C20 FPGA, it is designed for university and college laboratory use, and is suitable for a wide range of exercises in courses on digital logic and computer organization. DE2 Development Board Terasic Technologies, Inc. Cyclone II EP2C35 This board was designed by professors, for professors. It is an ideal vehicle for learning about digital logic and FPGAs. Featuring an Altera Cyclone II EP2C35 FPGA, the DE2 board is designed for university and college laboratory use. It is suitable for a wide range of exercises in courses on digital logic and computer organization. DE2-70 Digital Camera and Multimedia Development Platform Terasic Technologies, Inc. Cyclone II EP2C70F896C6N This board is a modified version of the Altera DE2 board with a larger FPGA and more memory. It is an excellent vehicle for learning about digital logic and FPGAs. Featuring an Altera Cyclone II EP2C70 FPGA, the DE2 board is designed for university and college laboratory use. MAX II EPM240 EPM240Z This board provides a hardware platform for designing and developing simple and low-end systems based on Altera MAX II or MAX IIZ devices. The board features a MAX II/MAX IIZ EPM240T100Cx/EPM240ZM100Cx device with 240 LEs and 8,192 bits of user flash memory (UFM). The board also supports vertical migration into EPM570T100Cx devices with 570 LEs and 8,192 bits of UFM. MAX II/MAX IIZ Development Kit System Level Solutions MAX II CPLD EPM2210F324C3 MAX II Micro Terasic Technologies, Inc. This kit, equipped with the largest Altera MAX II CPLD and an onboard USB-Blaster cable, functions as a development and education board for CPLD designs. This kit also includes reference designs with source code. HSMC Prototyping Board Bitec Daughtercard This board provides a solution for prototyping circuits and testing them together with the latest Altera FPGA development kits. This board provides access to the complete set of HSMC signals via a footprint of standard 0.1" pitch headers. The HSMC power pins are accessed via fuses for added security. The main prototype matrix comprises a 0.1" grid interleaved with +3.3 V and GND access points. Footprints for commonly used 25-way and 9-way D-type connectors are included on the board. HSMC DVI Input/Output Module Bitec Daughtercard This DVI transmitter/receiver module for the HSMC interface enables you to interface FPGA projects to real-world DVI signals. SC DVI Input Module Bitec Daughtercard This DVI module for the Santa Cruz interface enables you to interface FPGA projects to real-world DVI signals. 88Altera Product Catalog * 2015 * www.altera.com DEVELOPMENT KITS Altera and Par tner D e velopment K its General Purpose (Continued) Product and Vendor Name Device Description SC DVI Output Module Bitec Daughtercard This DVI module for the Santa Cruz interface enables you to drive high-resolution displays with digital clarity. SC Camera Bitec Daughtercard This board features a 5.2-megapixel camera daughtercard with selectable frame rates and resolutions. SC Proto Bitec Daughtercard This prototyping board for the Santa Cruz interface has convenient access points to power and ground with connector break-out. TRDB_DC2 1.3 Megapixel Camera Module Terasic Technologies, Inc. Daughtercard This module consists of complete digital camera reference designs with source code in Verilog HDL and a user manual with live demo examples. It supports exposure, light control, and motion capture. TRDB_LCM Digital Panel Daughtercard Terasic Technologies, Inc. Daughtercard This 3.6" digital panel development kit consists of reference designs (TV player and color pattern generator) with source code in Verilog HDL. Altera Product Catalog * 2015 * www.altera.com89 DEVELOPMENT KITS S oC System on M odules System on modules (SOMs) provide a compact, pre-configured memory and software solution perfect for prototyping, proof-of-concept and initial system production. SOMs enable you to focus on your IP, algorithms, and human/mechanical interfaces rather than fundamentals of the SoC and electrical system and software bring-up. In some cases, SOMs can also make sense for full system production. The following Altera SoC-based SOMs are available now from Altera Design Services Network (DSN) partners: Partner SOM Altera SoC Main Memory* MitySOM-5CSX Cyclone V SoC Up to 2 GB DDR3 with ECC MCV Cyclone V SoC 1 GB DDR3 SDRAM uS02 microSOMTM Cyclone V SoC 1 GB DDR3 SDRAM Qseven Module Cyclone V SoC 512 MB DDR3 SDRAM with ECC NovTech NOVSOM CV Cyclone V SoC Up to 2 GB DDR3 SDRAM with ECC Shiratech Spark-100 Cyclone V SoC 1 GB to 4 GB with ECC Critical Link DENX Computer Systems EXOR International iWave Systems Module Image * Processor main memory only. Additional FPGA, flash memory, eMMC, microSD, SD/MMC, and EEPROM memory may be provided but is not shown on this table. Consult SOM vendor specifications for complete memory details. For more information about Altera SoC system on modules, visit www.altera.com/soms. 90Altera Product Catalog * 2015 * www.altera.com TRAINING Training O ver vie w We offer an extensive curriculum of classes to deepen your expertise. Our classes are beneficial whether you're new to FPGA and CPLD design, or are an advanced user wanting an update on the latest tools, tips, and tricks. Our training paths are delivered in three ways: * Instructor-led training, typically lasting one to two days, involves in-person instruction with hands-on exercises from an Altera or Altera partner subject matter expert. Fees vary. www.altera.com/training Learn more about our training program or sign up for classes at www.altera.com/training. Start sharpening your competitive edge today! * Virtual classrooms, involving live instructor-taught training over the Web, allow you to benefit from the interactivity with an instructor from the comfort of your home or office. Classes are taught in 4.5-hour sessions across consecutive days. * Online training, typically one to two hours long, features pre-recorded presentations and demonstrations. Online classes are free and can be taken at any time. To help you decide which courses might be most useful to you, we've grouped classes into specific curricula. Curricula paths include Altera Fundamentals, I/O Interfaces, Software Developer, Embedded Hardware, DSP Designer, and more. Altera Product Catalog * 2015 * www.altera.com91 TRAINING I nstruc tor-Led, Vir tual, and Online Classes www.altera.com/training Altera Instructor-Led and Virtual Classroom Courses Virtual Classroom Courses Denoted with a * (All Courses Are One Day in Length Unless Otherwise Noted) Course Category General Description Course Titles * Introduction to VHDL* Design languages Attain the skills needed to design with Verilog HDL and VHDL for programmable logic * Advanced VHDL Design Techniques* * Introduction to Verilog HDL* * Advanced Verilog HDL Design Techniques* * The Quartus II Software Design Series: Foundation* * The Quartus II Software Debug and Analysis Tools Quartus II software * The Quartus II Software Design Series: Timing Analysis* Acquire design entry, compilation, programming, verification, * Timing Closure with the Quartus II Software* and optimization skills by learning how to use both basic * Advanced Timing Analysis with TimeQuest* and advanced features of Quartus II software * Design Optimization Using Quartus II Incremental Compilation* * Partial Reconfiguration with Altera FPGAs Software development Accelerate algorithm performance with Open Computing Language (OpenCL) by offloading to an FPGA System integration Build hierarchical systems by integrating IP and custom logic * Parallel Computing with OpenCL Workshop* * Optimizing OpenCL for Altera FPGAs* * Introduction to the Qsys System Integration Tool * Advanced Qsys System Integration Tool Methodologies * Designing with the Nios II Processor Embedded system design Learn to design an ARM-based or Nios II processor system in an Altera FPGA * Developing Software for the Nios II Processor (2-day course) * Designing with an ARM-based SoC * Developing Software for an ARM-based SoC Memory interfaces Implement interfaces to external memory System design Solve DSP and video system design challenges using Altera technology Connectivity design Build high-speed, gigabit interfaces using embedded transceivers found in leading-edge FPGA families 92Altera Product Catalog * 2015 * www.altera.com * Implementing, Simulating, and Debugging External Memory Interfaces* * Designing with DSP Builder Advanced Blockset* * Video Design Framework Workshop * Building Gigabit Interfaces in Generation 10 Devices * Building Gigabit Interfaces in 28 nm Devices * Creating PCI Express Links Using FPGAs TRAINING Online Training Altera Free Online Training Courses (Courses Are Approximately One Hour in Length) Course Category Getting started Course Titles Languages Read Me First! English, Chinese, and Japanese Basics of Programmable Logic English, Chinese, and Japanese How to Begin a Simple FPGA Design English, Chinese, and Japanese VHDL Basics English, Chinese, and Japanese Verilog HDL Basics English, Chinese, and Japanese SystemVerilog with the Quartus II Software English, Chinese, and Japanese Best HDL Design Practices for Timing Closure English, Chinese, and Japanese Using the Quartus II Software: An Introduction English, Chinese, and Japanese The Quartus II Software Interactive Tutorial English only The Quartus II Software Design Series: Foundation (note: this training is similar to the instructor-led course of the same name) English, Chinese, and Japanese What's New in the Quartus II Software English and Japanese Setting Up Floating Licenses English only Synplify Pro Tips and Tricks English only Synplify Synthesis Techniques with the Quartus II Software English only Using Quartus II Software: Schematic Design English and Chinese Introduction to Incremental Compilation English, Chinese, and Japanese I/O System Design English, Chinese, and Japanese Advanced I/O System Design English and Chinese Managing Metastability with the Quartus II Software English only Partial Reconfiguration English only Overview of Mentor Graphics ModelSim Software English and Japanese SignalTap II Embedded Logic Analyzer: Getting Started English, Chinese, and Japanese Using Quartus II Software: Chip Planner English only Debugging and Communicating with an FPGA Using the Virtual JTAG Megafunction English only System Console English and Chinese Debugging JTAG Chain Integrity English only Power Analysis and Optimization English and Chinese Resource Optimization English and Chinese Design languages Software overview and design entry Verification and debugging Altera Product Catalog * 2015 * www.altera.com93 TRAINING On line Training Altera Free Online Training Courses (Courses Are Approximately One Hour in Length) Course Category Timing analysis and closure Memory interfaces Connectivity design System design 94Altera Product Catalog * Course Titles Languages TimeQuest Timing Analyzer English, Chinese, and Japanese Timing Closure Using Quartus II Advisors and Design Space Explorer English and Chinese Timing Closure Using Quartus II Physical Synthesis Optimizations English and Chinese Timing Closure Using TimeQuest Custom Reporting English only Design Evaluation for Timing Closure English and Chinese Good High-Speed Design Practices English only Constraining Source Synchronous Interfaces English and Chinese Constraining Double Data Rate Source Synchronous Interfaces English and Chinese Using High-Performance Memory Interfaces in Altera FPGAs English and Chinese Integrating Memory Interfaces IP in Generation 10 Devices English only Introduction to Memory Interfaces IP in Generation 10 Devices English only On-Chip Debugging of Memory Interfaces IP in Generation 10 Devices English only Verifying Memory Interfaces IP in Generation 10 Devices English only Transceiver Basics English, Chinese, and Japanese Transceiver Toolkit English only Transceiver Reconfiguration in Altera 28 nm Devices English only Decision Feedback Equalization and Adaptive Equalization in Stratix IV GX/GT Devices English only Advanced Signal Conditioning for Stratix IV and Stratix V Receivers English only Getting Started with Altera's 28 nm PCI Express Solutions English only Getting Started with Altera's 40 nm PCI Express Solutions English and Japanese Custom Protocol Design in Altera 28 nm Devices English and Chinese Introduction to Altera's 10/100/1000 Mb Ethernet Solutions English and Chinese Introduction to Altera's 10 Gb Ethernet Solutions English only High-Speed Serial Protocol Design with Altera Transceiver Devices English and Chinese Dynamic Reconfiguration in Altera Transceiver Devices English and Chinese Transceiver Toolkit English and Chinese Introduction to Qsys English and Japanese Advanced System Design Using Qsys English only Custom IP Development Using Avalon and AXI Interfaces English, Chinese, and Japanese Designing with DSP Builder Advanced Blockset: An Overview English and Chinese DSP Builder Standard Blockset: An Overview English only Variable-Precision DSP Blocks in Altera 28 nm FPGAs English only Viterbi Decoder English only High-Performance Floating-Point Processing with FPGAs English only Building Video Systems English and Chinese 2015 * www.altera.com TRAINING On line Training Altera Free Online Training Courses (Courses Are Approximately One Hour in Length) Course Category System design (continued) OpenCL Embedded system design Device-specific training Scripting Course Titles Languages Implementing Video Systems English only Creating Reusable Design Blocks English only Using Cascaded-Integrator-Comb Filter in Multirate Digital Systems English only FIR Compiler II English only Avalon Verification Suite English and Chinese Introduction to Parallel Computing with OpenCL English, Japanese, and Chinese Writing OpenCL Programs for Altera FPGAs English, Japanese, and Chinese Running OpenCL on Altera FPGAs English, Japanese, and Chinese OpenCL: Single-threaded vs. Multi-threaded Kernels English only Building Custom Platforms for Altera SDK for OpenCL English only Designing with the Nios II Processor and Qsys - Day 1 Japanese only Developing Software for the Nios II Processor: Tools Overview English and Chinese Developing Software for the Nios II Processor: Design Flow English and Chinese SoC Hardware Overview - (Part 1) English, Japanese, and Chinese SoC Hardware Overview - (Part 2) English, Japanese, and Chinese Hardware Design Flow for an ARM-Based SoC English, Chinese, and Japanese Software Design Flow for an ARM-Based SoC English, Chinese, and Japanese Using the Nios II Processor English, Chinese, and Japanese Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse English and Japanese Nios II Software Build Tools for Eclipse and BSP Editor (Quartus II Software 10.0 Update) English only Developing Software for the Nios II Processor: HAL Primer English, Chinese, and Japanese Nios II Floating-Point Custom Instructions English and Chinese Developing Software for the Nios II Processor: MMU and MPU English and Chinese Lauterbach Debug Tools English only Introduction to Graphics English only Power Distribution Network Design for Stratix III and Stratix IV FPGAs English and Chinese Power Distribution Network Design Using Altera PDN Design Tools English only Configuring Altera FPGAs English and Chinese Command-Line Scripting English only Introduction to Tcl English and Chinese Quartus II Software Tcl Scripting English, Chinese, and Japanese Altera Product Catalog * 2015 * www.altera.com95 REFERENCES Glossar y Below is a glossary of helpful terms to bring you up to speed on Altera devices. Term Definition Adaptive logic module (ALM) Logic building block, used by some Altera devices, which provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two combinational adaptive LUTs (ALUTs). Configuration via Protocol (CvP) CvP is a configuration method that enables you to configure the FPGA using industry-standard protocols. Currently CvP supports the PCIe protocol. Embedded hard IP blocks These metal-programmable hard IP blocks deliver up to 14M ASIC gates or up to 700K additional LEs to harden standard or logic-intensive applications. Equivalent LE Device density represented as a comparable amount of LEs, which uses the 4-input LUT as a basis. Fractional phase-locked loops (Fractional PLLs) A phase-locked loop (PLL) in the core fabric, fractional PLLs provide increased flexibility as an additional clocking source for the transceiver, replacing external VCXOs. Global clock networks Global clocks can drive throughout the entire device, serving as low-skew clock sources for functional blocks such as ALMs, DSP blocks, TriMatrix memory blocks, and PLLs. See regional clocks and periphery clocks for more clock network information. Hard processor system (HPS) This processor system is a hardened component within the SoC, that comprises a dual-core ARM Cortex-A9 MPCore processor, a rich set of peripherals, and multiport memory controllers. Logic element (LE) This logic building block, used by some Altera devices, includes a 4-input LUT, a programmable register, and a carry chain connection. See device handbooks for more information. Macrocells Similar to LEs, this is the measure of density in MAX-series CPLDs. Memory logic array blocks (MLABs) MLABs are dual-purpose blocks, configurable as regular logic array blocks or as memory blocks. On-chip termination (OCT) Support for driver impedance matching and series termination, which eliminates the need for external resistors, improves signal integrity, and simplifies board design. On-chip series, parallel, and differential termination resistors are configurable via Quartus II software. Periphery clocks (PCLKs) PCLKs are a collection of individual clock networks driven from the periphery of the device. PCLKs can be used instead of general-purpose routing to drive signals into and out of the device. Plug & Play Signal Integrity This capability, consisting of Altera's adaptive dispersion engine and hot socketing, lets you change the position of backplane cards on the fly, without having to manually configure your backplane equalization settings. Programmable Power Technology This feature automatically optimizes logic, DSP, and memory blocks for the lowest power at the required performance. Only the blocks with critical-path logic need to be in high-performance mode; all others are in low-power mode. Real-time in-system programming (ISP) This capability allows you to program a MAX II device while the device is still in operation. The new design only replaces the existing design when there is a power cycle to the device, so can perform in-field updates to the MAX II device at any time without affecting the operation of the whole system. Regional clocks Regional clocks are device quadrant-oriented and provide the lowest clock delay and skew for logic contained within a single device quadrant. System on a chip (SoC) An SoC is an embedded system that consists of a processor, peripherals, and custom hardware integrated on a single device. Variable-precision blocks These integrated blocks provide native support for signal processing of varying precisions--for example, 9x9, 27x27, and 18x36--in a sum or independent mode. 96Altera Product Catalog * 2015 * www.altera.com M A I N C O R P O R AT E O F F I C E S Altera Corporation 101 Innovation Drive San Jose, CA 95134 USA Telephone: (408) 544 7000 www.altera.com Altera European Headquarters Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom Telephone: (44) 1 494 602 000 Altera Japan Ltd. Shinjuku i-Land Tower 32F 6-5-1, Nishi Shinjuku Shinjuku-ku, Tokyo 163-1332 Japan Telephone: (81) 3 3340 9480 www.altera.co.jp Altera International Ltd. Unit 11- 18, 9/F Millennium City 1, Tower 1 388 Kwun Tong Road Kwun Tong Kowloon, Hong Kong Telephone: (852) 2945 7000 www.altera.com.cn Altera Corporation Technology Center Plot 6, Bayan Lepas Technoplex Medan Bayan Lepas 11900 Bayan Lepas Penang, Malaysia Telephone: 604 636 6100 Altera European Trading Company Ltd. Building 2100 Cork Airport Business Park, Cork, Republic of Ireland Telephone: +353 21 454 7500 www.altera.com/twitter FSC logo www.altera.com/facebook www.alteraforum.com www.youtube.com/alteracorp www.linkedin.com/company/altera plus.google.com/+altera (c)2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal. January 2015 SG-PRDCT-14.1 Altera Product Catalog * 2015 * www.altera.com97 Providing what you need for successful designs. Reference Designs Design IP Design Tools Silicon