Altera Product CatalogVersion 14.1

■ Altera® Solutions Portfolio

■ Generation 10 Device Portfolio

■ 28 nm Device Portfolio

■ 40 nm Device Portfolio

■ 60 nm Device Portfolio

■ MAX® CPLD Series

■ Altera’s Customizable Processor Portfolio

■ Altera SDK for OpenCL™

■ Nios II Processor Operating System Support

■ Altera and Partner Functions

■ Transceiver Protocols

■ Altera and Partner Development Kits

■ SoC System on Modules

■ Enpirion® Power Portfolio

■ Training Overview

■ Instructor-Led, Virtual, and Online Classes

For Arria V GX and GT devices, values on top indicate available user I/O pins and values at the bottom indicate the 6.5536 Gbps and 10.3125 Gbps transceiver count. One pair

of 10 Gbps transceiver channels can be congured as three 6 Gbps transceiver channels. For Arria V GZ devices, values on top indicate available user I/O pins and values at the

bottom indicate the 12.5 Gbps transceiver count.

migration, the number of user I/Os may be less than the number stated in the table.

Vertical migration is possible only if you use up to 320 I/O pins, up to nine 6.5536 Gbps transceiver count (for Arria V GX devices), and up to four 10.3125 Gbps transceiver count

(for Arria V GT devices).