®
Altera Corporation 511
Understanding
FLASHlogic Timing
June 1996, ver. 1 Application Note 79
A-AN-079-01
Introduction
Altera devices provide device performance that is consistent from
simulation to application. Before programming or configuring a device,
you can determine the worst-case timing delays for any design. You can
calculate propagation delays with the timing models given in this
application note and the timing parameters listed in the
FLASHlogic
Programmable Logic Device Family Data Sheet
in this data book.
This application note defines internal and external timing parameters,
and illustrates the timing model for the FLASHlogic device family.
Familiarity with FLASHlogic device architecture and characteristics is
assumed. Refer to the
FLASHlogic Programmable Logic Device Family Data
Sheet
for a complete description of the FLASHlogic device architecture,
and for specific values of the timing parameters listed in this application
note.
Internal
Timing
Parameters
The timing delays contributed by individual FLASHlogic architectural
elements are called internal timing parameters, which cannot be
measured explicitly. All internal timing parameters are shown in italic
type. Each FLASHlogic logic array block (LAB) has two modes of
operation: logic (24V10) mode and SRAM mode, and the internal timing
parameters for each mode are provided in this section.
Logic (24V10) Mode
The following list defines the internal timing parameters for FLASHlogic
devices in logic (24V10) mode.
t
IN
Input pad and buffer delay. The time required for a dedicated
input and clock pin to drive the input signal into the
programmable interconnect array (PIA) and the global clock
delay.
t
IO
I/O input pad and buffer delay. The delay from the I/O pin to
the PIA when the I/O pin is used as an input.
t
PIA
Programmable interconnect array (PIA) delay. The delay
incurred by signals that are routed through the PIA.
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t
GLOB
Global clock delay. The delay from the dedicated clock pin to a
register’s clock input.
t
DGLOB
Delayed global clock delay. The delay from the dedicated clock
pin to a register’s clock input through the delayed global clock
path.
t
LAC
Logic array control delay. The
AND
array delay for register
control functions such as preset, clear, and output enable.
t
SOE
SRAM output enable control delay. The delay that activates the
output enable control when the LAB is used as SRAM.
t
ICOMP
Identity comparator delay. The delay for a signal that
propagates through the identity comparator in an LAB.
t
IC
Array clock delay. The delay through a macrocell’s clock
product term to the register’s clock input.
t
CLR
Register clear time. The delay from the assertion of the register’s
array clear input to the time the register output stabilizes at
logical low.
t
PRE
Register preset time. The delay from the assertion of the
register’s array preset input to the time the register output
stabilizes at logical high.
t
LAD
Logic array delay. The time required for a logic signal to
propagate through a macrocell’s
AND-OR-XOR
structure.
t
RD
Register delay. The delay from the rising edge of the register’s
clock to the time the data appears at the register output.
t
ISU
Register setup time. The time required for a signal to stabilize at
the register input before the clock’s rising edge to ensure that
the register correctly stores the input data.
t
IH
Register hold time. The time required for a signal to remain
stable at the register input after the clock’s rising edge to ensure
that the register correctly stores the input data.
t
IASU
Internal array setup time. The time required for a signal to
stabilize at the register input before the clock’s rising edge to
ensure that the register correctly stores the input data.
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t
IAH
Internal array hold time. The time required for a signal to
remain stable at the register input after the clock’s rising edge to
ensure that the register correctly stores the input data.
t
COMB
Combinatorial buffer delay. The delay from the time a
combinatorial logic signal bypasses the programmable register
to the time it becomes available at the macrocell output.
t
FD
Feedback delay. The delay of the macrocell output fed back into
the PIA input.
t
OD
Output buffer and pad delay. In FLASHlogic devices, the value
of V
CCIO
for 5.0-V or 3.3-V devices are the same.
t
XZ
Output buffer disable delay. The delay required for high
impedance to appear at the output pins after the output buffer’s
enable control is disabled.
t
ZX
Output buffer enable delay. The delay required for the output
signal to appear at the output pins after the tri-state buffer’s
enable control is enabled.
SRAM Mode
The following list defines the internal timing parameters for FLASHlogic
devices in SRAM mode.
t
IDD
Internal data-in to data-out delay. The data delay at the SRAM
output when the SRAM is in read cycle after a write cycle, i.e.,
the delay from the time data is written into the SRAM to the
time it appears at the SRAM output.
t
AA
SRAM address access delay. The delay from an address change
at the SRAM input to the time data appears at the SRAM
output.
t
WASU
Write address setup. The time required for the address signal to
stabilize at the SRAM input before the beginning of the write
pulse.
t
WAH
Write address hold. The time between the end of the write pulse
to when the address lines are allowed to change.
t
WDSU
Write data setup. The time required for the data signals to
stabilize at the SRAM input before the end of the write pulse.
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t
WDH
Write data hold. The time between the end of the write pulse to
when the data lines are allowed to change.
t
SISU
SRAM internal register setup. The time required for the SRAM
output to stabilize at the register input before the register clock’s
rising edge to ensure that the register correctly stores the input
data.
t
SIH
SRAM internal register hold. The time required for the SRAM
output to remain stable at the register input after the register
clock’s rising edge to ensure that the register correctly stores the
input data.
t
WP
SRAM write pulse width. The time during which both the block
enable (
BE
) signal and the write enable (
WE
) signal are asserted.
External
Timing
Parameters
External timing parameters represent actual pin-to-pin timing
characteristics. Each external timing parameter consists of a combination
of internal timing parameters. The
FLASHlogic Programmable Logic Device
Family Data Sheet
gives the values of the external timing parameters. These
external timing parameters are worst-case values, derived from extensive
performance measurements and ensured by device testing. All external
timing parameters are shown in bold type.
Logic (24V10) Mode
The following list defines the external timing parameters for a
FLASHlogic LAB in logic (24V10) mode.
t
PD1
Dedicated input pin to non-registered output delay. The time
required for a signal on any dedicated input pin to propagate
through the combinatorial logic in a macrocell and appear at an
external device output pin.
t
PD2
I/O pin input to non-registered output delay. The time required
for a signal on any I/O pin input to propagate through the
combinatorial logic in a macrocell and appear at an external
device output pin.
t
COMP
Dedicated input pin or I/O pin input to non-registered output
delay. The time required for a signal on any dedicated input pin
or I/O pin input to propagate through the identity comparator
in an LAB and appear at an external device output pin.
t
PZX
Tri-state to active output delay. The time required for an input
transition to change an external output from a tri-state (high-
impedance) logic level to a valid high or low logic level.
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t
PXZ
Active output to tri-state delay. The time required for an input
transition to change an external output from a valid high or low
logic level to a tri-state (high-impedance) logic level.
t
CLR
Time to clear register delay. The time required for a low signal to
appear at the external output, measured from the input
transition.
t
SU
Global clock setup time. The time data must be present at the
input pin before the global clock signal is asserted at the clock
pin.
t
H
Global clock hold time. The time the data must be present at the
input pin after the global clock signal is asserted at the clock pin.
t
DSU
Delayed global setup time. The time data must be present at the
input pin before the delayed global clock signal is asserted at
the clock pin.
t
DH
Delayed global hold time. The time the data must be present at
the input pin after the delayed global clock signal is asserted at
the clock pin.
t
CO1
Global clock to output delay. The time required to obtain a valid
output after the global clock is asserted at the clock pin.
t
DCO1
Delayed global clock to output delay. The time required to
obtain a valid output after the global clock is asserted at the
clock pin.
t
CNT
Minimum global clock period. The minimum period
maintained by a globally clocked counter.
t
ASU
Array clock setup time. The time when data must be present at
the input pin before an array clock signal is asserted at an input
pin.
t
AH
Array clock hold time. The time when data must be present at
the input pin after an array clock signal is asserted at an input
pin.
t
ACO1
Array clock to output delay. The time required to obtain a valid
output after an array clock signal is asserted at an input pin.
t
ACNT
Minimum array clock period. The minimum period maintained
by a counter that is clocked by a signal from the array.
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SRAM Mode
The following list defines the external timing parameters for the read and
write cycles of a FLASHlogic LAB in SRAM mode.
SRAM Read Cycle Timing Parameters
t
RC
Read cycle time. The time required for the address lines to
remain stable during a read operation.
t
DD
Data-in to data-out delay. The time required for the written data
to appear at the output pins.
t
AA
Address access time. The delay from an address change at the
input pins to the time data appears at the external device output
pins. This parameter is valid only when the block enable (
BE
)
and output enable (
OE
) signals are asserted.
t
ABE
Block enable access time. The delay from the time
BE
is asserted
to the time data appears at the output pins. This parameter is
valid only when
OE
is asserted.
t
OE
Output enable to output valid. The time required for an input
transition to change an external output from a tri-state (high-
impedance) logic level to a valid high or low logic level.
t
OH
Output hold from address change. The minimum delay from an
address change at the input pins to the time data appears at the
external device output pins.
t
BLZ
Block enable to output in low impedance. The minimum delay
from the time
BE
is asserted to the time the output pins are
driven.
t
BHZ
Block disable to output in high impedance. The delay from the
time the
BE
is de-asserted to the time the SRAM outputs are tri-
stated.
t
OLZ
Output enable to output in low impedance. The minimum delay
from the time the
OE
is asserted to the time the output pins are
driven.
t
SSU
SRAM global clock setup time. The time when the address must
be present at the input pins before the global clock signal is
asserted at the clock pin.
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t
SH
SRAM global clock hold time. The time when the address must
be present at the input pins after the global clock signal is
asserted at the clock pin.
t
SDSU
SRAM delayed global clock setup time. The time when the
address must be present at the input pins before the delayed
global clock signal is asserted at the clock pin.
t
SDH
SRAM delayed global clock hold time. The time when the
address must be present at the input pins after the delayed
global clock signal is asserted at the clock pin.
SRAM Write Cycle Timing Parameters
t
WC
Write cycle time. The time when the address signals must
remain constant.
t
BW
Block enable to end of write. The time during which both the WE
and BE signals are asserted. The WE signal is asserted before the
BE signal.
tAW Address valid to end of write. The setup time required for the
address lines to stabilize before the end of the write pulse.
tAS Address setup time. The time when the address lines must have
stabilized before the beginning of the write pulse.
tWP Write pulse width. The minimum time when both the BE and WE
signals are asserted. The BE signal is asserted before the WE
signal.
tWR Write recovery time. The time after the end of the write pulse
during which the address lines to must remain stable.
tDW Data valid to end of write. The setup time required for the data
lines to stabilize before the end of the write pulse.
tDH Data hold time. The time required for the data lines to stabilize
after the end of the write pulse.
tOHZ Output disable to valid data-in. The delay from the time OE is
de-asserted to the end of valid data output.
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Timing Models Timing models are simplified block diagrams that illustrate the
propagation delays through Altera devices. Logic can be implemented on
different paths. You can trace the actual paths used in your FLASHlogic
device by examining the equations listed in the PLDshell Plus Report File
(.rpt) for the project. You can then add up the appropriate internal timing
parameters to calculate the propagation delays through the device.
Figure 1 shows the timing model for FLASHlogic devices.
Figure 1. FLASHlogic Timing Model
Calculating
Timing Delays
You can calculate approximate pin-to-pin timing delays for any
FLASHlogic device with the timing model shown in Figure 1 and the
internal timing parameters in the FLASHlogic Programmable Logic Device
Family Data Sheet in this data book. Each external timing parameter is
calculated from a combination of internal timing parameters. Figure 2
shows the external timing parameters for FLASHlogic devices. To
calculate the delay for a signal that follows a different path through the
device, refer to the timing model shown in Figure 1 to determine which
internal timing parameters to add together.
Input
Delay
t
IN
Control Delay
t
SOE
t
LAC
t
IC
t
AA
t
IDD
t
WASU
t
WAH
t
WDSU
t
WDH
t
WP
SRAM Delay
Feedback
Delay
t
FD
Logic Arra y
Delay
t
LAD
t
ICOMP
I/O Delay
t
IO
PIA
Delay
t
PIA
Output
Delay
t
OD
t
XZ
t
ZX
Global Clock
Delay
t
GLOB
t
DGLOB
Register
Delay
t
ISU
t
IH
t
IASU
t
IAH
t
RD
t
COMB
t
PRE
t
CLR
t
SISU
t
SIH
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Figure 2. External Timing Parameters (Part 1 of 3)
When an input pin is used instead of an I/O pin, t
IN
can be substituted for t
IO
.
Combinatorial
Logic
Combinatorial Delay
Tri-State Enable/Disable Delay
tPXZ =
t
IO
+
t
PIA
+
t
LAC
+
t
XZ
tPZX =
t
IO
+
t
PIA
+
t
LAC
+
t
ZX
tPD1 =
t
IN
+
t
PIA
+
t
LAD
+
t
COMB
+
t
OD
tPD2 =
t
IO
+
t
PIA
+
t
LAD
+
t
COMB
+
t
OD
Combinatorial
Logic
Comparator Delay
tCOMP =
t
IO
+
t
PIA
+
t
ICOMP
+
t
COMB
+
t
OD
Combinatorial
Logic
Register Clear & Preset Time
tPRE =
t
IO
+
t
PIA
+
t
LAC
+
t
PRE
+
t
OD
tCLR =
t
IO
+
t
PIA
+
t
LAC
+
t
CLR
+
t
OD
Setup Time
Combinatorial
Logic
Combinatorial
Logic
tSU =(
t
IO
+
t
PIA
+
t
LAD
)
–
(
t
IN
+
t
GLOB
)
+
t
ISU
tDSU =(
t
IO
+
t
PIA
+
t
LAD
)
–
(
t
IN
+
t
DGLOB
)
+
t
ISU
Global Clock
Delayed Global Clock
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Figure 2. External Timing Parameters (Part 2 of 3)
Array Clock Hold Time
Combinatorial
Logic
Combinatorial
Logic
Combinatorial
Logic
Combinatorial
Logic
Array Clock Setup Time
Clock-to-Output Delay
tASU =(
t
IO
+
t
PIA
+
t
LAD
) –
(
t
IO
+
t
PIA
+
t
IC
) +
t
IASU
tAH =(
t
IO
+
t
PIA
+
t
IC
) –
(
t
IO
+
t
PIA
+
t
LAD
) +
t
IAH
tCO1 =
t
IN
+
t
GLOB
+
t
RD
+
t
OD
tDCO1 =
t
IN
+
t
DGLOB
+
t
RD
+
t
OD
Global Clock
Delayed Global Clock
Hold Time
Counter Frequency
tCNT =
t
RD
+
t
FD
+
t
PIA
+
t
LAD
+
t
ISU
Combinatorial
Logic
Combinatorial
Logic
Global Clock
Delayed Global Clock tH=(
t
IN
+
t
GLOB
)
–
(
t
IO
+
t
PIA
+
t
LAD
)
+
t
IH
tDH =(
t
IN
+
t
DGLOB
)
–
(
t
IO
+
t
PIA
+
t
LAD
) +
t
IH
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Figure 2. External Timing Parameters (Part 3 of 3)
Figure 3 illustrates the SRAM read cycle external timing parameters.
Figure 3. SRAM Read Cycle External Timing Parameters (Part 1 of 3)
When an input pin is used instead of an I/O pin, t
IN
can be substituted for t
IO
.
Array Clock-to-Output Delay
Combinatorial
Logic
tACO1 =
t
IO
+
t
PIA
+
t
IC
+
t
RD
+
t
OD
Data to Output
tDD =
t
IO
+
t
PIA
+
t
IDD
+
t
COMB
+
t
OD
SRAM
Data-in
Data-out
Address Access Time
tAA =
t
IO
+
t
PIA
+
t
AA
+
t
COMB
+
t
OD
Address
Data-out
Block Enable Access
tABE =
t
IO
+
t
PIA
+
t
SOE
+
t
ZX
Control
Logic
SRAM
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Figure 3. SRAM Read Cycle External Timing Parameters (Part 2 of 3)
tBHZ =
t
IO
+
t
PIA
+
t
SOE
+
t
XZ
Block Disable to Output in High Impedance
Setup Time
tSSU = (
t
IO
+
t
PIA
+
t
AA
)
– (
t
IN
+
t
GLOB
) +
t
SISU
Address
Data-out
Hold Time
tSH =(
t
IN
+
t
GLOB
)
– (
t
IO
+
t
PIA
+
t
AA
) +
t
SIH
D
tOE =
t
IO
+
t
PIA
+
t
SOE
+
t
ZX
Control
Logic
Output Enable to Output Valid
Control
Logic
Address
Data-out D
SRAM
SRAM
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Figure 3. SRAM Read Cycle External Timing Parameters (Part 3 of 3)
Figure 4 shows the SRAM write cycle external timing parameters.
Figure 4. SRAM Write Cycle External Timing Parameters (Part 1 of 2)
When an input pin is used instead of an I/O pin, t
IN
can be substituted for t
IO
.
Data-out
Delay Setup Time
tSDSU = (
t
IO
+
t
PIA
+
t
AA
)
– (
t
IN
+
t
DGLOB
)
+
t
SISU
Delay Hold Time
tSDH =(
t
IN
+
t
DGLOB
)
– (
t
IO
+
t
PIA
+
t
AA
)
+
t
SIH
Address
D
Address
Data-out D
SRAM
SRAM
Write Cycle
tWC = maximum of (
t
WASU
+
t
WP
+
t
WAH
) or (
t
WDSU
+
t
WDH
)
SRAM
/BE
Data-in
Address
/WE
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Figure 4. SRAM Write Cycle External Timing Parameters (Part 2 of 2)
Address Valid to End of Write
tAW =(
t
IO
+
t
PIA
) – (
t
IO
+
t
PIA
)
+
t
WASU
+
t
WP
Address
/BE
SRAM
/WE
Write Recovery Time
tWR =(
t
IO
+
t
PIA
) – (
t
IO
+
t
PIA
) +
t
WAH
Data Hold Time
tDH =(
t
IO
+
t
PIA
) – (
t
IO
+
t
PIA
) +
t
WDH
Data Valid to End of Write
tDW =(
t
IO
+
t
PIA
) – (
t
IO
+
t
PIA
)
+
t
WDSU
Data-in
/BE
/WE
Data-in
/BE
/WE
Address
/BE
SRAM
/WE
SRAM
SRAM
Address Setup Time
tAS =(
t
IO
+
t
PIA
) – (
t
IO
+
t
PIA
) +
t
WASU
Address
/BE
SRAM
/WE
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Examples The following examples show how to use internal timing parameters to
calculate the delays for real applications.
Example 1: First Bit of 7483 TTL Macrofunction
You can analyze the timing delays for macrofunctions that have been
subject to minimization and logic synthesis. The PLDshell Plus Report File
(.rpt) lists the synthesized logic equations. These equations are structured
so that you can quickly determine the logic implementation of any signal.
For example, Figure 5 shows part of a 7483 TTL macrofunction (a 4-bit
full adder). The PLDshell Report File gives the following equations for s1,
the least significant bit of the adder:
s1 = a1 * /b1 * /c0
+ /a1 * b1 * /c0
+ /a1 * /b1 * c0
+ /b1 * /a1 * c0
s1.trst = VCC
Figure 5. Adder Logic Timing for FLASHlogic Architecture
s1
NOT
b1
c0
a1
NOT
NOT
t
LAD
t
COMB
t
OD
t
IO
t
PIA
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The output of the macrocell is s1. To drive the s1 output, the four
products terms are ORed together:
(a1 * /b1 * /c0), (/a1 * b1 * /c0), (/a1 * /b1 * c0), and (b1 * a1 * c0).
Because a macrocell can have four or more product terms, the s1 output
can be generated in one macrocell. Therefore, the timing delay is as
follows:
tIN + tPIA + tLAD + tCOMB + tOD
Example 2: Second Bit of 7483 TTL Macrofunction
For complex logic that requires additional product terms, product terms
from neighboring macrocells can be used. The second bit of the 7483
adder macrofunction, s2, was generated using a macrocell that had only
4 product terms. Because 6 product terms are required to generate this
function, 2 product terms were borrowed from a neighboring macrocell.
The equations are as follows:
s2 = b1 * a1 * a2
+ b1 * c0 * a2
+ a1 * c0 * a2
+ /b1 * /a1 * /a2
+ /b1 * /c0 * /a2
+ /a1 * /c0 * /a2
s2.trst = VCC
Product terms borrowed from neighboring macrocells do not have
additional delays associated with them. As a result, the timing delay for
s2 has the same delay as s1:
tIN + tPIA + tLAD + tCOMB + tOD
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Example 3: 5-Bit Comparator
FLASHlogic devices have a dedicated 12-bit identity comparator in each
LAB. This comparator has the same delay regardless of the width of the
data bits, i.e., a 1-bit comparator has the same delay as a 12-bit
comparator. The following example is a 5-bit comparator between the I/O
pins for busa and busb. The result is sent to the output pin equal. The
equations are as follows:
equal = GND
equal.cmp = [busa4, busa3, busa2, busa1, busa0] == [busb4,
busb3, busb2, busb1, busb0]
equal.trst = VCC
Therefore, the timing delay for equal is as follows:
tIN + tPIA + tICOMP + tCOMB + tOD
Conclusion The FLASHlogic device architecture has fixed internal timing delays that
are independent of routing. Therefore, you can determine the worst-case
timing delays for any design before programming a device. Total delay
paths can be expressed as the sums of internal timing delays. The
FLASHlogic timing model illustrates the internal delay paths for
FLASHlogic devices and shows how these internal timing parameters
affect each other. You can calculate delay paths by adding the internal
timing parameters in the FLASHlogic timing model. With the ability to
predict worst-case timing delays, you can be confident of a design’s in-
system timing performance.
Copyright ©
1995, 1996 Altera Corporation, 2610 Orchard Parkway,
San Jose, California 95134, USA, all rights reserved.
By accessing any information on this CD-ROM, you agree to be
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