ICS843004AGI-02LFT - Integrated Device Technology

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

GENERAL DESCRIPTION

The ICS843004-02 is a 4 output LVPECL

Synthesizer optimized to generate clock

frequencies for a variety of high performance

applications and is a member of the

HiPerClocksTM family of high performance clock

solutions from ICS. This device can select its input reference

clock from either a crystal input or a single-ended clock signal

and can be configured to generate a number of different output

frequencies via the 3 frequency select pins (F_SEL2:0). The

ICS843004-02 uses ICS’ 3rd generation low phase noise VCO

technology and can achieve 1ps or lower typical rms phase

jitter. This ensures that it will easily meet clocking requirements

for high-speed communication protocols such as 10 and 12

Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET. This

device is also suitable for next generation serial I/O

technologies like serial ATA and SCSI and is conveniently

packaged in a small 24-pin TSSOP package.

FEATURES

• Four 3.3V LVPECL outputs

• Selectable crystal oscillator interface

or LVCMOS/LVTTL single-ended input

• Crystal input range: 14MHz - 37.78MHz

• VCO Range: 560MHz - 680MHz

• Supports the following applications:

SONET, Ethernet, Serial ATA, SCSI and HDTV

• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):

0.91ps (typical)

Offset Noise Power

100Hz ............... -97.1 dBc/Hz

1kHz ..............-121.6 dBc/Hz

10kHz ..............-124.9 dBc/Hz

100kHz ..............-125.1 dBc/Hz

• Full 3.3V supply mode

• 0°C to 70°C ambient operating temperature

HiPerClockS™

ICS

PIN ASSIGNMENT

Phase

Detector VCO

÷18

÷24

÷32 (default)

÷40

÷1

÷2

÷3

÷4 (default)

÷8

OSC

ICS843004-02

24-Lead TSSOP

4.40mm x 7.8mm x 0.92mm

package body

G Package

Top View

nQ1

VCCo

nQ0

nPLL_SEL

VCCA

F_SEL0

VCC

nQ2

VCCO

nQ3

F_SEL2

nXTAL_SEL

TEST_CLK

VEE

XTAL_IN

XTAL_OUT

F_SEL1

BLOCK DIAGRAM

nPLL_SEL

XTAL_IN

XTAL_OUT

TEST_CLK

nXTAL_SEL

F_SEL0:2

nQ0

nQ1

nQ2

nQ3

Pulldown

stupnI rediviDM

eulaV

rediviDN

eulaV

2LES_F1LES_F0LES_F

000 813

001 424

010 428

011 231

100 232

10 1 234

110 238

111 048

FUNCTION TABLE

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

rebmuNemaNepyTnoitpircseD

2,11Q,1QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

22,3V

OCC

rewoP.snipylppustuptuO

5,40Qn,0QtupuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

6RMtupnInwodlluP

erasredivid

lanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA

xQnstuptuodetrevniehtdnawologotxQstuptuoeurtehtgnisuac

teser

erastuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgihogot

.slevelecafretniLTTVL/SOMCVL.delbane

7LES

_LLPntupnInwodlluP

nehW.sredividehtottupnisaKLC_TSETdnaLLPehtneewtebstceleS

kcolcecnereferehtstcelesed,HGIHnehW.)elbanELLP(LLPstceles,WOL

.slevelecafretniLTTVL/SOMCVL.)ssapyBLLP(

9,8cndesunU.tcennocoN

01V

ACC

rewoP.nipylppusgolanA

,11

,0LES_F

2LES_F tupnIpulluP.slevelecafretniLTTVL/SOMCVL.sniptcelesycneuqerF

21V

rewoP.nipylppuseroC

311LES_FtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.sniptcelesycneuqerF

,41

,TUO_LATX

NI_L

ATX tupnI ,tuptuoehtsiTUO_LATX.ecafretnilatsyrctnanoserlellaraP

.tupniehtsiNI_LATX

61V

rewoP.nipylppusevitageN

71KLC_TSETtupnInwodlluP.tupnikcolcLTTVL/SOMCVL

81LES_LATXntupnInwodlluP

ecnerefeRLLPehte

htsastupniKLC_TSETrolatsyrcneewtebstceleS

.HGIHnehwKLC_TSETstceleS.WOLnehwstupniLATXstceleS.ecruos

.sle

velecafretniLTTVL/SOMCVL

12,023Q,3QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

42,322Qn,2QtuptuO.sle

velecafretniLCEPVL.riaptuptuolaitnereffiD

:ETON

pulluPdnanwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

PULLUP

rotsiseRpulluPtupnI 15kΩ

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE

stupnI rediviDM

eulaV

rediviDN

eulaV

OCV

)zHM(

tuptuO

ycneuqerF

)zHM(

noitacilppA

2LES_F1LES_F0LES_F ecnerefeR

kcolC

010 57.42428 49552.47VTDH

111 9461538.41048 6604.3955428571.47VTDH

111 61048 04608ISCS

10 1 44.91234 80.22625.551TENOS

110 44.91238 80.22667.77TENOS

011 44.91231 80.

22680.226TENOS

100 44.91232 80.22640.113TENOS

001 52424 006051ATAS

010 52428 00657ATAS

001 5265.62424 5.736573.951lennahCerbiFgiG01

10 1 52135.91234 52652.651t

enrehtEgiG01

000 52.13813 5.2655.781tenrehtEgiG21

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 70°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI 2V

3.0+V

tupnI

egatloVwoL

,LES_LATXn,LES_LLPn

RM,2LES_F:0LES_F 3.0-8.0V

KLC_TSET3.0-3.1V

tupnI

tnerruChgiH

1LES_F,RM,KLC_TSET

LES_LATXn,LES_LLPn V

V564.3=051Aµ

2LES_F,0LES_FV

V564.3=5Aµ

tupnI

tnerruCwoL

1LES_F,RM,KLC_TSET

,LES_LATXn,LES_LLPn V

V,V564.3=

V0=051-Aµ

2LES_F,0LES_FV

V,V564.3=

V0=5-Aµ

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

OCC

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 521Am

ACC

tnerruCylppuSgolanA 21Am

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

TABLE 5. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuFzHM

ycneuqerF 4187.73zHM

)RSE(ecnat

siseRseireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

.latsyrctnanoserlellarapfp81nagnisudeziretcarahC:ETON

TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

OCC

4.1-V

OCC

9.0-V

1ETON;egatloVwoLtuptuOV

OCC

0.2-V

OCC

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

OCC

.V2-

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 71.475.736zHM

OCV

egnaRkcoLOCVLLP 5.265046zHM

0=2LES_F:0LES_F5.265085zHM

)o(ks1ETON;wekStuptuO 51sp

)Ø(tij3,2ETON;rettiJesahPSMRzHM02-zHk21,zHM25.55119.0sp

emiTkcoLLLP DBTsm

emiTllaF/esiRtuptuO%08ot%02054sp

cdoelcyCytuDtuptuO 05%

.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastu

ptuoneewtebwekssadenifeD:1ETON

.stniopssorclaitnereffidtuptuoehttaderusaeM

.desuecruostupniehtnotnednep

edsirettijesahP:2ETON

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:3ETON

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

tPERIOD

PERIOD

odc = x 100%

Q0:Q3

RMS PHASE JITTER

OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

-1.3V±0.165V

OUTPUT RISE/FALL TIME

Clock

Outputs 20%

80% 80%

20%

SWING

VCC,

VCCA, VCCO

VEE

nQ0:nQ3

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

sk(o)

nQy

nQx

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843004-02 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC, VCCA, and VCCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1

illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each VCCA.

POWER SUPPLY FILTERING T ECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

10Ω

VCCA

10µF

.01µF

3.3V

.01µF

VCC

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating. Though

not required, but for additional protection, a 1kΩ resistor can be

tied from XTAL_IN to ground.

TEST CLK INPUT:

For applications not requiring the use of the test clock, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the TEST_CLK to ground.

SELECT PINS:

All select pins have internal pull-ups and pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVPECL OUTPUT

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

CRYSTAL INPUT INTERFACE

The ICS843004-02 has been characterized with 18pF paral-

lel resonant crystals. The capacitor values shown in

Figure 2

Figure 2. CRYSTAL INPUt INTERFACE

below were determined using a 26.5625MHz 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

ICS843004-02

27p

XTAL2

XTAL1

33p

18pF Parallel Crystal

TERMINATION FOR 3.3V LVPECL OUTPUT

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

= 50Ω

FOUT FIN

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION

designed to drive 50Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion.

Figures 3A and

show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers

simulate to guarantee compatibility across all printed cir-

cuit and clock component process variations.

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

LAYOUT GUIDELINE

Figure 4

shows an example of ICS843004-02 application

schematic. In this example, the device is operated at VCC=3.3V.

The decoupling capacitor should be located as close as

possible to the power pin. Both input options are shown. The

device can either be driven using a quartz crystal or a 3.3V

To Logic

Input

pins

VCC

RD2

0.1uF

Ro ~ 7 Ohm

Driv er_LVCMOS

33pF

VCC

RD1

Not Install

F_SEL2

Zo = 50 Ohm

10uF

RU1

VCCO

19.44MHz

To Logic

Input

pins

Zo = 50 Ohm

0.1uF

VCCO

Set Logic

Input to

'1'

VDD

F_SEL1

F_SEL0

843004-02

1213

24 nQ1

VCCO

nQ0

nPLL_SEL

VCCA

F_SEL0

VCCF_SEL1

XTAL_OUT

XTAL_IN

VEE

TEST_CLK

nXTAL_SEL

F_SEL2

nQ3

VCCO

nQ2

(U1-3)

0.1uF

Logic Control Input Examples

Zo = 50 Ohm

133

VCCO=3.3V

Optional

Y-Termination

nPLL_SEL

0.01u

82.5

VDD

27pF

3.3V

VCCA

nXTAL_SEL

(U1-12)

VCC

Set Logic

Input to

'0'

133

VCC

Zo = 50 Ohm

VCC=3.3V

18pF

RU2

Not Install

(U1-22)

LVCMOS signal. For the LVPECL output drivers, only two

termination examples are shown in this schematic. Additional

termination approaches are shown in the LVPECL Termination

Application Note.

FIGURE 4. ICS843004-02 SCHEMATIC EXAMPLE

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS843004-02 is: 3467

TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65°C/W 62°C/W

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

N42

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D07.709.7

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843004-02

CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

PRELIMINARY

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or

for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-

mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use

in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

20-GA400348SCI20A400348SCIPOSSTdaeL42ebutC°07otC°0

20-GA400348SCI20A400348SCIPOSSTdaeL42leer&epat0052C°07otC°0

The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.