fax id: 6102 1CY 7C34 3B CY7C343 CY7C343B 64-Macrocell MAX(R) EPLD Features Functional Description * * * * 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology (CY7C343) * Advanced 0.65-micron CMOS technology to increase performance (CY7C343B) * Available in 44-pin HLCC, PLCC * Lowest power MAX device The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343/CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that doubles as a clock pin when needed. The CY7C343/CY7C343B also has 28 I/O pins, each connected to a macrocell (6 for LABs A and C, and 8 for LABs B and D). The remaining 36 macrocells are used for embedded logic. The CY7C343/CY7C343B is excellent for a wide range of both synchronous and asynchronous applications. Logic Block Diagram 9 INPUT INPUT 35 11 INPUT INPUT/CLK 34 12 INPUT INPUT 33 13 INPUT INPUT 31 DEDICATED INPUTS SYSTEM CLOCK LAB A I/O PINS 2 4 5 6 7 8 LAB D MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 56 MACROCELL 55 MACROCELL 54 MACROCELL 53 MACROCELL 52 MACROCELL 51 MACROCELL 50 MACROCELL 49 MACROCELLS 7 - 16 P I A LAB B I/O PINS 15 16 17 18 19 20 22 23 MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22 MACROCELL 23 MACROCELL 24 1 44 42 41 40 39 38 37 I/O PINS 30 29 28 27 26 24 I/O PINS MACROCELLS57 - 64 LAB C MACROCELL 38 MACROCELL 37 MACROCELL 36 MACROCELL 35 MACROCELL 34 MACROCELL 33 MACROCELLS39 - 48 MACROCELLS 25 - 32 (3, 14, 25, 36) (10, 21, 32, 43) VCC GND C343-1 MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. Warp2Sim is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 January 1990 - Revised March 1997 CY7C343 CY7C343B Selection Guide 7C343-12 7C343B-12 7C343-15 7C343B-15 7C343-20 7C343B-20 7C343-25 7C343B-25 7C343-30 7C343B-30 7C343-35 7C343B-35 Maximum Access Time (ns) 12 15 20 25 30 35 Maximum Operating Current (mA) 135 135 135 135 135 135 225 225 225 225 225 Maximum Standby Current (mA) Commercial Military Industrial 225 225 225 225 225 225 Commercial 125 125 125 125 125 125 200 200 200 200 200 200 200 200 200 200 Military 200 Industrial Shaded area contains preliminary information. HLCC Top View Pin Configuration 6 5 4 3 2 1 44 43 42 41 40 I/O 7 39 I/O I/O 8 38 I/O INPUT 9 37 I/O GND 10 36 VCC INPUT 11 35 INPUT INPUT 12 34 INPUT/CLK INPUT 13 33 INPUT VCC 14 32 GND 31 INPUT 7C343 I/O 15 I/O 16 30 I/O I/O 17 29 I/O 18 19 20 21 22 23 24 25 26 27 28 C343-2 Maximum Ratings DC Program Voltage .................................................... 13.0V Static Discharge Voltage ........................................... >1100V (per MIL-STD-883, method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to+150C Operating Range Ambient Temperature with Power Applied....................................................0C to+70C Range Maximum Junction Temperature (Under Bias)................................................................. 150C Commercial Supply Voltage to Ground Potential ................ -2.0V to+7.0V Industrial Maximum Power Dissipation................................... 2500 mW Military DC VCC or GND Current ............................................ 500 mA Ambient Temperature VCC 0C to +70C 5V 5% -40C to +85C 5V 10% -55C to +125C (Case) 5V 10% Note: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns. DC Output Current, per Pin...................... -25 mA to +25 mA DC Input Voltage[1]......................................... -3.0V to +7.0V 2 CY7C343 CY7C343B Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8 mA VIH Input HIGH Level VIL Input LOW Level IIX Input Current GND < VIN < VCC IOZ Output Leakage Current VO = VCC or GND Min. Max. Unit 2.4 2.2 [3, 4] V 0.45 V VCC+0.3 V -0.3 0.8 V -10 +10 A -40 +40 A -30 -90 mA IOS Output Short Circuit Current VCC = Max., VOUT = 0.5V ICC1 Power Supply Current (Standby) VI = VCC or GND (No Load) Commercial 125 mA Military/Industrial 200 mA VI = VCC or GND (No Load) f = 1.0 MHz[4, 5] Commercial 135 mA Military/Industrial 225 mA ICC2 Power Supply Current[5] tR Recommended Input Rise Time 100 ns tF Recommended Input Fall Time 100 ns Capacitance[6] Max. Unit CIN Parameter Input Capacitance Description VIN = 2V, f = 1.0 MHz Test Conditions 10 pF COUT Output Capacitance VOUT = 2.0V, f = 1.0 MHz 10 pF AC Test Loads and Waveforms[6] R1464 R1464 5V 5V OUTPUT ALLINPUTPULSES OUTPUT R2 250 50 pF 3.0V (a) Equivalent to: R2 250 5 pF INCLUDING JIGAND SCOPE INCLUDING JIGAND SCOPE 10% GND < 6 ns C343-3 90% 90% 10% < 6 ns C343-4 (b) THEVENIN EQUIVALENT(commercial/military) 163 OUTPUT 1.75V Notes: 2. Typical values are for TA = 25C and VCC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed but not 100% tested. 5. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material. 6. 3 Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. CY7C343 CY7C343B Programmable Interconnect Array Timing Considerations The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from a straight input pin. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives. When calculating synchronous frequencies, use t S1 if all inputs are on the input pins. tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAH) is less than 1/(tAS2 + tAH). Timing Delays Timing delays within the CY7C343/CY7C343B may be easily determined using Warp2(R), Warp2SimTM, or Warp3(R) software or by the model shown in Figure 1. The CY7C343/CY7C343B has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information, the Warp3 software provides a timing simulator. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. Design Recommendations The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. Operation of the devices described herein with conditions above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability.The CY7C343/CY7C343B contains circuitry to protect device pins from high static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same clock as the CY7C343/CY7C343B. In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous), then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device's register. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types. 4 CY7C343 CY7C343B EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC INPUT INPUT DELAY tIN LOGIC ARRAY DELAY tLAD REGISTER OUTPUT DELAY tCLR tPRE tRSU tRH tRD tCOMB tLATCH INPUT/ OUTPUT tOD tXZ tZX SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO C343-5 Figure 1. CY7C343/CY7C343B Internal Timing Model 5 CY7C343 CY7C343B External Synchronous Switching Characteristics[6] Over Operating Range 7C343-12 7C343B-12 Parameter tPD1 tPD2 tPD3 tPD4 tEA Description Min. Dedicated Input to Combinatorial Output Delay[7] Com'l /Ind I/O Input to Combinatorial Output Delay[8] Com'l /Ind Dedicated Input to Combinatorial Output Delay with Expander Delay[9] Com'l /Ind I/O Input to Combinatorial Output Delay with Expander Delay[4, 10] Com'l /Ind [4, 7] Com'l /Ind Input to Output Enable Delay Max. 7C343-15 7C343B-15 Min. 12 Mil 20 Mil 18 Mil 26 12 Mil tER Input to Output Disable Delay[4, 7] Com'l /Ind 12 Mil tCO1 tCO2 tS1 tS2 tH tWH Synchronous Clock Input to Output Delay Com'l /Ind Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] Com'l /Ind Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7] Com'l /Ind I/O Input Set-Up Time to Synchronous Clock Input[7, 12] Com'l /Ind Input Hold Time from Synchronous Clock Input[7] Com'l /Ind Synchronous Clock Input HIGH Time Com'l /Ind 6 Mil 14 Mil Synchronous Clock Input LOW Time 8 tRW Asynchronous Clear Mil tRO tPR tPO Unit 15 20 ns 15 20 25 32 25 32 23 30 23 30 33 42 33 42 15 20 15 20 15 20 15 20 7 12 7 12 17 25 ns ns ns ns ns ns ns 12 ns 20 24 ns 20 24 0 0 0 0 5 6 5 6 5 6 5 6 15 20 15 20 15 20 15 20 10 16 Mil 0 Mil 4.5 Com'l /Ind 4.5 Com'l /Ind 12 Mil tRR Max. 10 Mil Width[4, 7] Min. 17 Mil tWL Max. 7C343-20 7C343B-20 Asynchronous Clear Recovery Time[4, 7] Com'l /Ind Asynchronous Clear to Registered Output Delay[7] Com'l /Ind Asynchronous Preset Recovery Time[4, 7] Com'l /Ind Asynchronous Preset to Registered Output Delay[7] Com'l /Ind 12 Mil 12 Mil 12 Mil Mil 6 12 ns ns ns ns ns 15 20 15 20 15 20 15 20 ns ns 15 20 15 20 ns CY7C343 CY7C343B External Synchronous Switching Characteristics[6] Over Operating Range (continued) 7C343-12 7C343B-12 Parameter tCF tP fMAX1 fMAX2 fMAX3 fMAX4 tOH tPW Description Min. Synchronous Clock to Local Feedback Input[4, 13] Com'l /Ind External Synchronous Clock Period (1/fMAX3)[4] Com'l /Ind External Maximum Frequency (1/(tCO1 + tS1))[4, 14] Com'l /Ind Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] Com'l /Ind Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), or (1/tCO1)[4, 16] Com'l /Ind Maximum Register Toggle Frequency (1/(tWL+tWH))[4, 17] Com'l /Ind Output Data Stable Time from Synchronous Clock Input[4, 18] Com'l /Ind Asynchronous Preset Width[4, 7] Max. 7C343-15 7C343B-15 Min. 3 Mil 9 Mil 71.4 Mil 90.9 Mil 111.1 Mil 111.1 Mil 3 Mil Com'l /Ind Mil 12 Max. 7C343-20 7C343B-20 Min. Max. Unit 3 3 ns 3 3 10 12 10 12 58.8 41.6 58.8 41.6 76.9 66.6 76.9 66.6 100 83.3 100 83.3 100 83.3 100 83.3 3 3 3 3 15 20 15 20 ns MHz MHz MHz MHz ns ns Shaded area contains preliminary information. Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested period ically by sampling production material. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. 15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local, originating within the same LAB.. 16. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to dedicated inputs and no expander logic is used. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. 7 CY7C343 CY7C343B External Synchronous Switching Characteristics[6] Over Operating Range (continued) 7C343-25 7C343B-25 Parameter Max. Unit Com'l /Ind 25 30 35 ns Mil 25 30 35 tPD2 I/O Input to Combinatorial Output Delay[8] Com'l /Ind 39 44 53 Mil 39 44 53 tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] Com'l /Ind 37 44 55 Mil 37 44 55 tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4, 10] Com'l/ Ind 51 58 73 Mil 51 58 73 tEA Input to Output Enable Delay[4, 7] Com'l /Ind 25 30 35 Mil 25 30 35 tER Input to Output Disable Delay[4, 7] Com'l/ Ind 25 30 35 Mil 25 30 35 tCO1 Synchronous Clock Input to Output Delay Com'l/ Ind 14 16 20 Mil 14 16 20 tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] Com'l/ Ind 30 35 42 tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7] Com'l/ Ind 15 20 25 Mil 15 20 25 tS2 I/O Input Set-Up Time to Synchronous Clock Input[7, 12] Com'l/ Ind 30 35 42 Mil 30 35 42 tH Input Hold Time from Synchronous Clock Input[7] Com'l/ Ind 0 0 0 Mil 0 0 0 tWH Synchronous Clock Input HIGH Time Com'l/ Ind 8 10 12.5 Mil 8 10 12.5 tWL Synchronous Clock Input LOW Time Com'l/ Ind 8 10 12.5 Mil 8 10 12.5 Com'l /Ind 25 30 35 Width[4, 7] Min. Mil Max. Min. 30 Max. 7C343-35 7C343B-35 Dedicated Input to Combinatorial Output Delay[7] tPD1 Description 7C343-30 7C343B-30 Min. 35 ns ns ns ns Mil 25 30 35 Com'l/ Ind 25 30 35 Mil 25 30 35 tRO Asynchronous Clear to Registered Output Delay[7] Com'l/ Ind tPR Asynchronous Preset Recovery Time[4, 7] Com'l/ Ind 25 30 35 Mil 25 30 35 tPO Asynchronous Preset to Registered Output Delay[7] Com'l/ Ind 25 30 35 Mil 25 30 35 tCF Synchronous Clock to Local Feedback Input[4, 13] Com'l/ Ind 3 3 5 Mil 3 3 5 External Synchronous Clock Period (1/fMAX3)[4] Com'l/ Ind 16 20 25 Mil 16 20 25 8 ns ns Asynchronous Clear Recovery Time[4, 7] tP ns ns tRR 30 25 ns ns Asynchronous Clear Mil ns 42 tRW 25 ns ns ns 35 30 ns 35 ns ns ns ns CY7C343 CY7C343B External Synchronous Switching Characteristics[6] Over Operating Range (continued) 7C343-25 7C343B-25 Parameter fMAX1 Description Min. Max. 7C343-30 7C343B-30 Min. Max. 7C343-35 7C343B-35 Min. External Maximum Frequency (1/(tCO1 + tS1))[4, 14] Com'l/ Ind 34 27 22.2 Mil 34 27 22.2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] Com'l /Ind 55 43 33 Mil 55 43 33 Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), or (1/tCO1)[4, 16] Com'l /Ind 62.5 50 40 Mil 62.5 50 40 Maximum Register Toggle Frequency (1/(tWL+tWH))[4, 17] Com'l/Ind 62.5 50 40 Mil 62.5 50 40 tOH Output Data Stable Time from Synchronous Clock Input[4, 18] Com'l/ Ind 3 3 3 Mil 3 3 3 tPW Asynchronous Preset Width[4, 7] Com'l/ Ind 25 30 35 Mil 25 30 35 fMAX2 fMAX3 fMAX4 Max. Unit MHz MHz MHz MHz ns ns External Asynchronous Switching Characteristics Over Operating Range[6] 7C343-12 7C343B-12 Parameter tACO1 Description Min. Asynchronous Clock Input to Output Delay[7] Com'l/ Ind Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] Com'l/ Ind tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] Com'l/ Ind tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] Com'l/ Ind tAH Input Hold Time from Asynchronous Clock Input[7] Com'l/ Ind tAWH Asynchronous Clock Input HIGH Time[7] Com'l /Ind tAWL Asynchronous Clock Input LOW Time[7, 20] Com'l/ Ind tACF Asynchronous Clock to Local Feedback Input[4, 21] Com'l /Ind tAP External Asynchronous Clock Period (1/fMAXA4)[4] Com'l/ Ind tACO2 Max. 7C343-15 7C343B-15 Min. 12 Mil 20 Mil Max. 7C343-20 7C343B-20 Min. Max. Unit 15 20 ns 15 20 25 32 25 32 3 3.5 3.5 4 12 13.5 15 13.5 15 4.5 5 4.5 5 8.5 9 8.5 9 6.5 7 Mil Mil 4 Mil 8 Mil 6 Mil 4 6.5 9 Mil ns ns ns ns 13 11 14 ns 7 11 Mil ns ns 13 15 16 15 16 ns Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t AWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 9 CY7C343 CY7C343B External Asynchronous Switching Characteristics Over Operating Range[6] (continued) 7C343-12 7C343B-12 Parameter fMAXA1 Description Min. External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[4, 22] Com'l/ Ind fMAXA2 Maximum Internal Asynchronous Frequency[4, 23] Com'l/ Ind fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4, 24] Com'l/ Ind fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] Com'l/ Ind Max. 66.6 Mil 71.4 Mil 71.4 Mil 71.4 Mil 7C343-15 7C343B-15 Min. Max. 7C343-20 7C343B-20 Min. 54.0 41.6 54.0 41.6 66.6 58.8 66.6 58.8 66.6 50 66.6 50 66.6 62.5 66.6 62.5 Max. Unit MHz MHz MHz MHz Shaded area contains preliminary information. External Asynchronous Switching Characteristics Over Operating Range[6] 7C343-25 7C343B-25 Parameter tAOH tACO1 tACO2 Description Min. Max. Min. Asynchronous Clock Input to Output Delay[7] Com'l/ Ind 25 30 35 Mil 25 30 35 Com'l/ Ind 40 46 55 Mil 40 46 55 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] tAH Input Hold Time from Asynchronous Clock Input[7] tAWH Asynchronous Clock Input HIGH Time[7] tAWL Asynchronous Clock Input LOW Time[7, 20] tACF Asynchronous Clock to Local Feedback Input[4, 21] tAP External Asynchronous Clock Period (1/fMAXA4)[4] Com'l/ Ind 5 12 15 12 15 6 5 6 8 Com'l/ Ind 20 25 30 Mil 20 25 30 Com'l/ Ind 6 8 10 Mil 6 8 10 Com'l/ Ind 11 14 16 Mil 11 14 16 Com'l/ Ind 9 11 14 Mil 9 Com'l/ Ind 11 15 ns ns ns ns ns ns ns 14 18 15 Mil ns 8 Mil Unit Max. Mil tAS1 12 Min. 7C343-35 7C343B-35 Output Data Stable Time from Asynchronous Clock Input[4, 26] Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] Com'l/ Ind Max. 7C343-30 7C343B-30 22 18 ns 22 Com'l/ Ind 20 25 30 Mil 20 25 30 ns Note: 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input. 10 CY7C343 CY7C343B External Asynchronous Switching Characteristics Over Operating Range[6] (continued) 7C343-25 7C343B-25 Parameter fMAXA1 Description External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[4, 22] Min. Max. 7C343-30 7C343B-30 Min. Max. 7C343-35 7C343B-35 Min. Com'l/ Ind 33 27 23 Mil 33 27 23 Com'l/ Ind 50 40 33 Mil 50 40 33 Com'l/ Ind 40 33 28 Mil Unit Max. MHz fMAXA2 Maximum Internal Asynchronous Frequency[4, 23] fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4, 24] 40 33 28 fMAXA4 Maximum Asynchronous Register Com'l/ Ind Toggle Frequency 1/(tAWH + tAWL)[4, 25] Mil 50 40 33 50 40 33 tAOH Output Data Stable Time from Asynchronous Clock Input[4, 26] Com'l / Ind 15 15 15 Mil 15 15 15 7C343-12 7C343B-12 7C343-15 7C343B-15 7C343-20 7C343B-20 MHz MHz MHz ns Internal Switching Characteristics Over Operating Range[6] Parameter tIN Description Min. Dedicated Input Pad and Buffer Delay Com'l / Ind Max. Min. 2.5 Mil tIO I/O Input Pad and Buffer Delay Com'l/ Ind 2.5 Mil tEXP Expander Array Delay Com'l/ Ind 6 Mil tLAD Logic Array Data Delay Com'l/ Ind 6 Mil tLAC Logic Array Control Delay Com'l/ Ind 5 Mil tOD Output Buffer and Pad Delay Com'l/ Ind 3 Mil tZX Output Buffer Enable Delay[27] Com'l/ Ind 5 Mil tXZ Output Buffer Disable Delay Com'l/ Ind 5 Mil tRSU tRH tLATCH Register Set-Up Time Relative to Clock Signal at Register Com'l/ Ind Register Hold Time Relative to Clock Signal at Register Com'l/ Ind Flow-Through Latch Delay Com'l /Ind 2 Mil 3 Mil 1 Mil tRD Register Delay Com'l/ Ind 1 Mil tCOMB Transparent Mode Delay[28] Com'l/ Ind Mil 11 1 Max. Min. Max. Unit 3 4 ns 3 4 3 4 3 4 8 10 8 10 8 10 8 10 6 8 6 8 3 4 3 4 6 8 6 8 6 8 6 8 3 4 3 4 3.5 4 3.5 4 ns ns ns ns ns ns ns ns ns 1 2 1 2 1 1 1 1 1 2 1 2 ns ns ns CY7C343 CY7C343B Internal Switching Characteristics Over Operating Range[6] (continued) 7C343-12 7C343B-12 Parameter tCH Description Clock HIGH Time Min. Com'l/ Ind Max. 3 Mil tCL Clock LOW Time Com'l/ Ind 3 Mil tIC Asynchronous Clock Logic Delay Com'l/ Ind 7C343-15 7C343B-15 Min. Synchronous Clock Delay 6 4 6 4 6 4 6 5 Com'l/ Ind 0.5 Mil tFD Feedback Delay Com'l/ Ind 1 Mil tPRE Asynchronous Register Preset Time Com'l/ Ind 3 Mil tCLR Asynchronous Register Clear Time Com'l/ Ind 3 Mil tPCW tPCR tPIA Asynchronous Preset and Clear Pulse Width Com'l /Ind Asynchronous Preset and Clear Recovery Time Com'l/ Ind Programmable Interconnect Array Delay Time Com'l/ Ind 2 Mil 2 Mil Min. 4 Mil tICS Max. 7C343-20 7C343B-20 ns 12 7 12 0.5 2 0.5 2 1 1 1 1 3 4 3 4 3 4 3 4 4 3 4 3 4 3 4 ns ns ns ns ns ns ns 10 12 10 12 7C343-30 7C343B-30 7C343-35 7C343B-35 Mil Unit ns 7 3 8 Max. ns Shaded area contains preliminary information. Internal Switching Characteristics Over Operating Range[6] 7C343-25 7C343B-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ Description Min. Dedicated Input Pad and Buffer Delay Com'l /Ind I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay[27] Output Buffer Disable Delay Max. Min. Max. Min. Max. Unit ns 5 7 9 Mil 5 7 9 Com'l/ Ind 5 5 7 Mil 5 5 7 Com'l/ Ind 12 14 20 Mil 12 14 20 Com'l/ Ind 12 14 16 Mil 12 14 16 Com'l/ Ind 10 12 13 Mil 10 12 13 Com'l /Ind 5 5 6 Mil 5 5 6 Com'l /Ind 10 11 13 Mil 10 11 13 Com'l /Ind 10 11 13 Mil 10 11 13 12 ns ns ns ns ns ns ns CY7C343 CY7C343B Internal Switching Characteristics Over Operating Range[6] (continued) 7C343-25 7C343B-25 Parameter tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Description Min. Max. 7C343-30 7C343B-30 Min. Max. 7C343-35 7C343B-35 Min. Max. Register Set-Up Time Relative to Clock Signal at Register Com'l/ Ind 6 8 10 Mil 6 8 10 Register Hold Time Relative to Clock Signal at Register Com'l/ Ind 6 8 12 Mil 6 8 12 Flow-Through Latch Delay Com'l /Ind 3 4 4 Mil 3 4 4 Com'l /Ind 1 2 2 Mil 1 2 2 Com'l/ Ind 3 4 4 Mil 3 4 4 Register Delay Transparent Mode Delay[28] Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Com'l /Ind 8 10 12.5 Mil 8 10 12.5 Com'l /Ind 8 10 12.5 Mil 8 10 12.5 ns ns 14 16 18 14 16 18 Com'l /Ind 2 2 3 Mil 2 2 3 Com'l /Ind 1 1 2 Mil 1 1 2 Com'l /Ind 5 6 7 Mil 5 6 7 Com'l /Ind 5 6 7 Mil 5 6 7 5 6 7 Mil 5 6 7 Asynchronous Preset and Clear Recovery Time Com'l/ Ind 5 6 7 Mil 5 6 7 Programmable Interconnect Array De- Com'l/ Ind lay Time Mil ns ns ns Mil Com'l /Ind ns ns Com'l /Ind Asynchronous Preset and Clear Pulse Width Unit ns ns ns ns ns ns ns 14 16 20 14 16 20 ns 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. 13 CY7C343 CY7C343B Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT t PD1[7]/t PD2 [7] COMBINATORIAL OUTPUT t ER [7] COMBINATORIAL OR REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE t ER [7] HIGH-IMPEDANCE THREE-ST ATE VALID OUTPUT C343-6 External Synchronous DEDICATED INPUTS OR [7] REGISTERED FEEDBACK tH tS1 t WH tWL SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET [7] tRW /t PW tRR /t PR tOH tRO/t PO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [11] C343-7 External Asynchronous DEDICATEDINPUTSOR REGISTERED FEEDBACK [7 ] tAS1 ASYNCHRONOUS CLOCK INPUT ASYNCHRONOUS CLEAR/PRESET [7 ] tAH tACO1 tAWH tRW/t PW tAOH tRO/t PO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK 14 tAWL tRR/t PR CY7C343 CY7C343B Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN tPIA tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD REGISTER OUTPUT TO LOCAL LAB 15 tCLR,tPRE tFD CY7C343 CY7C343B Switching Waveforms (continued) Internal Synchronous tCH tCL SYSTEM CLOCK PIN tIN tICS tRSU tRH SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY C343-12 Output Mode CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE C343-11 16 CY7C343 CY7C343B Ordering Information Speed (ns) 12 15 20 25 30 35 Ordering Code Package Name Operating Range Package Type CY7C343B-12HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial CY7C343B-12JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-15HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial CY7C343B-15JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-15HMB H67 44-Pin Windowed Leaded Chip Carrier Military CY7C343-20JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-20HC/HI H67 44-Pin Windowed Leaded Chip Carrier CY7C343B-20JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-20HMB H67 44-Pin Windowed Leaded Chip Carrier Military CY7C343-25HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial CY7C343-25JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-25HC/HI H67 44-Pin Windowed Leaded Chip Carrier CY7C343B-25JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343-30HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial CY7C343-30JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-30HC/HI H67 44-Pin Windowed Leaded Chip Carrier CY7C343B-30JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343-30HMB H67 44-Pin Windowed Leaded Chip Carrier Military CY7C343B-30HMB H67 44-Pin Windowed Leaded Chip Carrier CY7C343-35HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial CY7C343-35JC J67 44-Lead Plastic Leaded Chip Carrier CY7C343B-35HC/HI H67 44-Pin Windowed Leaded Chip Carrier CY7C343B-35JC/JI J67 44-Lead Plastic Leaded Chip Carrier CY7C343-35HMB H67 44-Pin Windowed Leaded Chip Carrier Military CY7C343B-35HMB H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial Shaded area contains preliminary information. MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics DC Characteristics Parameters Parameters Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC1 1, 2, 3 Document #: 38-00128-G 17 Subgroups tPD1 7, 8, 9, 10, 11 tPD2 7, 8, 9, 10, 11 tPD3 7, 8, 9, 10, 11 tCO1 7, 8, 9, 10, 11 tS 7, 8, 9, 10, 11 tH 7, 8, 9, 10, 11 tACO1 7, 8, 9, 10, 11 tACO2 7, 8, 9, 10, 11 tAS 7, 8, 9, 10, 11 tAH 7, 8, 9, 10, 11 CY7C343 CY7C343B Package Diagrams 44-Pin Windowed Leaded Chip Carrier H67 18 CY7C343 CY7C343B Package Diagrams (continued) 44-Lead Plastic Leaded Chip Carrier J67 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.