A2C00016642 A(SPANSION) - CYPRESS SEMICONDUCTOR

64-Macro ce ll MAX® EPLD

fax id: 6102

CY7C343

CY7C343B

Cypress Semiconductor Corporation • 3901 North First Street • San Jo se • CA 95134 • 408-943-2600

January 1990 – Revised March 1997

1CY7C343B

Features

• 64 MAX macrocells in 4 LABs

• 8 dedicated inputs, 24 bidirectional I/O pins

• Programmable interconnect array

• 0.8-micron double- metal CMOS EPROM tec hnology

(CY7C343)

• Advanced 0.65-micron CMOS te chnology to increase

performance (CY7C343B)

• Available in 44- pin HLCC, PLCC

• Lowest power MAX device

Functional Description

The CY7C343/CY7C343B is a high-p erformance, hig h-d ensi-

ty erasable programmable logic device, available in 44-pin

PLCC and HLCC packages.

The CY7C343/CY7C343B contains 64 highly flexible macrocells

and 1 28 ex pande r pro duct t erms . Thes e res ource s ar e divi ded in to

four Logic Array Blocks (LABs) connected through the Programma-

ble Inter-connect Array (PIA). There are 8 input pins, one that dou-

bles as a clock pin when needed. The CY7C343/CY7C343B

also has 28 I/O pins, each connected to a macr ocell (6 for

LABs A a nd C, and 8 for LABs B and D). Th e remaini ng 36

macrocel ls are used for embedded logic.

The CY7C3 43/CY7 C343B is ex cellent for a wide range of both

synchronous and asynchronous applications.

MAX is a registered trademark of Altera Corporati o n.

Warp2

and

Warp3

are register ed trademarks of Cypress Semiconductor Corporation.

Warp2

Sim is a trademark of Cypress Semiconduct or Corporation.

MACROCELL17

MACROCELL18

MACROCELL19

MACROCELL20

MACROCELL21

MACROCELL22

MACROCELL23

MACROCELL24

MACROCELL38

MACROCELL37

MACROCELL36

MACROCELL35

MACROCELL34

MACROCELL33

9 INPUT

11 INPUT

12 INPUT

13 INPUT

MACROCELL1

MACROCELL2

MACROCELL3

MACROCELL4

MACROCELL5

MACROCELL6

MACROCELL56

MACROCELL55

MACROCELL54

MACROCELL53

MACROCELL52

MACROCELL51

MACROCELL50

MACROCELL49

MACROCELLS 7 - 16 MACROCELLS57- 64

MACROCELLS 25 - 32 MACROCELLS39- 48

INPUT35

INPUT/CLK34

INPUT33

INPUT31

SYSTEM CLOCK

(3, 14, 25, 36)

(10, 21, 32, 43) VCC

GND

LABA

LAB B

LAB D

LAB C

C343-1

Logic Block Diagram

DEDICATED INPUTS

I/O PINS

CY7C343

CY7C343B

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................–65°C to+150°C

Ambient Temperature with

Power Applied ................ ................. ...................0°C to+70°C

Maximum Junct ion Temperature

(Under Bias)................... ...................... ................. .......150°C

Supply Voltage to Gro und Pot ential.. ........ ......–2.0V to+7.0V

Maximum Power Dissipation...................................2500 mW

DC VCC or GND Current....... ............ ............... ....... ...500 mA

DC Output Curre nt, per Pi n... ............ ....... –25 mA to +25 m A

DC Input Voltage[1]......................................... –3.0V to +7.0V

DC Program Volta ge ... ... ......................................... .....13.0V

Static Discharge Voltage ........................................... >1100V

(per MIL–STD–883, method 3015)

Note:

1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot

to –2.0V for periods less than 20 ns.

Selectio n G uide

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20 7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35

Maximum Access Ti me (ns) 12 15 20 25 30 35

Maximum Operating

Cur rent (mA) Commercial 135 135 135 135 135 135

Military 225 225 225 225 225

Industrial 225 225 225 225 225 225

Maximum Standby

Cur rent (mA) Commercial 125 125 125 125 125 125

Military 200 200 200 200 200

Industrial 200 200 200 200 200 200

Shaded area contains preliminary information.

Pin Configuration

453

1918 20

21 22

HLCC

Top View

23 24 2625 27 28

44 43 4142 40

I/O

VCC

INPUT

INPUT/CLK

INPUT

GND

INPUT

I/O

C343-2

7C343

INPUT

GND

VCC

INPUT

I/O

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ±5%

Industrial –40°C to +85°C 5V ±10%

Military –55°C to +125°C (Case) 5V ±10%

CY7C343

CY7C343B

Notes:

2. Typical values are for TA = 25°C and VCC = 5V.

3. Not more than one output should be tested at a time. Duration of the short

circuit should not be more than one sec ond. VOUT = 0.5V has been chosen

to avoid test problems caused by tester ground degradation.

4. Guaranteed but not 100% tested.

5. Measured with device programmed as a 16-bit counter in each LAB. This

parameter is tested periodically by sampling production material.

6. Par t (a) in AC Test Load and W aveforms is used for al l parameters exc ept

tER and tXZ, wh ich is us ed for part (b) in AC Tes t Load and W aveforms. All

external timing parameters are measured referenced to external pins of

the device.

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test C onditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8 mA 0.45 V

VIH Input HIGH Level 2.2 VCC+0.3 V

VIL Input LOW Level –0.3 0.8 V

IIX Input Current GND < VIN < VCC –10 +10 µA

IOZ Outp ut Leakage Current VO = VCC or GND –40 +40 µA

IOS Output Short Circuit Current VCC = Max., VOUT = 0.5V[3, 4] –30 –90 mA

ICC1 Power Supply Curr ent

(Standby) VI = VCC or GND

(No Load) Commercial 125 mA

Military/Industrial 200 mA

ICC2 Power Supply Curr ent[5] VI = VCC or GND (No Load)

f = 1.0 MHz[4, 5] Commercial 135 mA

Military/Industrial 225 mA

tRRecommended Input Rise

Time 100 ns

tFRecommended Input Fall

Time 100 ns

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capaci tance VIN = 2V, f = 1.0 MHz 10 pF

COUT Output Capacitance VOUT = 2.0V, f = 1.0 MHz 10 pF

AC Test Loads and Waveforms[6]

3.0V

OUTPUT

R1464Ω

250Ω

50 pF

INCLUDING

JIGAND

SCOPE

GND

90%

10% 90%

10%

<6ns <6ns

OUTPUT

R1464Ω

250Ω

5pF

INCLUDING

JIGAND

SCOPE

(a) (b)

OUTPUT 1.75V

Eq uivalent to: THÉ VENIN EQUIVALENT(commercial/military)

ALLINPUTPULSES

C343-3 C343-4

163 Ω

CY7C343

CY7C343B

Programmable Interconnect Array

The Programmable Int erconnect Arra y (PIA) sol ves intercon-

nect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA a re the outputs of every

macro cell within the device and the I/O pin feedback of ever y

pin on the device.

Unlike masked or programmable gate arrays, which induce

variable delay depe ndent on routing, the PIA has a fixed d elay .

This eliminates undesir ed skews among logic signals, which

may cause glitches in internal or external logic. The fixed de-

lay, regardless of programmable interconnect array configura-

tion, simplifies des ign by ensuring that internal s ignal skews or

races are avoided. The result is simpler design implementa-

tion, often in a single pass, without the mult iple internal l ogi c

plac ement and routing iterations required for a programmable

gate arr a y to achieve design timin g obj e ctives.

Timing Delays

Timing delays within the CY7C343/CY7C343B may be easily

determined using

Warp2

, Warp2

Sim™ , or

War p3

® so ftware or

by the model shown in

Figure 1

. The CY7C343/CY7C343B has

fixed internal del ays, allow ing t he user to det erm ine the worst case

timing delays for any design. For complete timing information, the

Warp3

software provides a timi ng simulator .

Design Recommendations

Operation of the devices described herein with conditions

above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stres s rating

only and functional operation of the device at these or any

other conditions above those indicated in the operational sec-

tions of this data sheet is not implied. Exposure to absolute

maximum ratings conditio ns for e xtended periods of time may

af fect device reliability .The CY7C343/CY7 C343B co nta ins c ir-

cuitry to protect de vice pins from high s tatic v oltages o r electric

fields; however, normal pr ecauti ons should be taken to avoid

applying any voltage higher than maximum rat ed vol tages.

For proper operation, input and output pins must be con-

strained to the range GND < (VIN or VOUT) < VCC. Unused inputs

must always be tied to an appropriate logic level (either VCC or GND).

Each set of VCC and GND pins must be connected together directl y

at the device. Power supply decoupling capacitors of at least 0.2 µF

must be connecte d between VCC and GND. For the most effective

decoupling, each VCC pi n should be separately decoupled to GND,

directly at the de vice. D ecoupl ing capacit ors shoul d h ave good f re-

quency response, such as monoli thic ceramic types.

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum ex-

pande r delay tEXP to the overall delay . Similarly , there is an addition-

al tPIA delay for an input from an I/O pin when compared to a signal

from a straight input pin.

When calculating synchronous frequencies, use tS1 i f all inputs

are on the input pins. tS2 should be used if data is applied at an I/O

pin. If tS2 is greater than tCO1, 1/tS2 becomes the l imiting frequency in

the data path mode unless 1/(tWH + tWL) is less t han 1/ tS2.

When expander logic is used in t he data path, add the appro-

priate maximum expander delay, tEXP to tS1. Determine which of

1/(tWH + t WL), 1/tCO1, or 1/( tEXP + tS1) is t he lowest frequency. T he

lowest of these frequencies is the maximum data path frequency for

the synchronous configuration.

When calculating external asyn chronous frequenc ies, use t AS1

if all inputs are on dedicated input pins. If any data is applied to an I/O

pin, tAS2 must be use d as the requir ed set-up time. If (tAS2 + tAH) is

greater than tACO1, 1 /( tAS2 + t AH) becomes t he limiting frequency in

the data path mode unless 1/(tAWH + t AH) i s less than 1/(tAS2 + tAH).

When expander logic is used in t he data path, add the appro-

priate maximum expand er delay, tEXP to tAS1. Determine which of

1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is t he lowest frequency.

The lowest of these frequencies is the maximum data path frequency

for the asynchronous configuration.

The parameter tOH indicates the system compatibility of this device

when driving other synchronous logic with positive input hold times,

which is controlled by the same synchronous clock. If tOH is greater

than the m inim um required input hold time o f the subsequent syn-

chronous logic, then the devices are guaranteed to function properly

with a common synchronous clock under worst-case envi ronmental

and supply voltage conditions.

The parameter tAOH indicates the system compa tibility of t his de-

vice when driving subsequent registered logic with a positive hold

time and using the same clock as the CY7C343/CY7C343B.

In g eneral, if tAOH is greater t han the minimum requir ed input hold

time of the subseq uent logic (synchronou s or asynchronous), then

the devices are guaranteed to function properly under worst-case en-

vironment al and supply vol tage condi tions, provided the clock signal

source is the same. This also applies if expander logic is used in the

clock signal p ath of the driving device, but not for the driven device.

This i s due to the expander logic in the second device’ s clock signal

path adding an additional delay (tEXP), causing the output data from

the preceding device to change prior to the arr ival of the clock signal

at the following device’ s register.

CY7C343

CY7C343B

Figure 1. CY 7C343/CY7C343B Internal Timing Model

LOGIC ARRAY

CONTROL DELAY

tLAC

EXPANDER

DELAY

tEXP

CLOCK

DELAY

tIC

tRD

tCOMB

tLATCH

INPUT

DELAY

tIN

PIA

DELAY

tPIA

OUTPUT

DELAY

tOD

tXZ

tZX

LOGIC ARRAY

DELAY

tLAD

FEEDBACK

DELAY

tFD

I/O DELAY

tIO

INPUT/

OUTPUT

INPUT

C343-5

SYSTEM CLOCK DELAY tICS

tRH

tRSU

tPRE

tCLR

CY7C343

CY7C343B

External Sync hronous Switching Characteristics[6 ] Over Operating Range

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20

UnitMin. Max. Min. Max. Min. Max.

tPD1 Dedicat e d Input to Combinatorial

Output Delay[7] Com’l /Ind 12 15 20 ns

Mil 15 20

tPD2 I/O Input to Combinatorial Output

Delay[8] Com’l /Ind 20 25 32 ns

Mil 25 32

tPD3 Dedicat e d Input to Combinatorial

Output Delay wit h Expander Delay[9] Com’l /Ind 18 23 30 ns

Mil 23 30

tPD4 I/O Input to Combinatorial Output

Delay with Expander Delay[4, 10] Com’l /Ind 26 33 42 ns

33 42

tEA Input to Output Enable Delay[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

tER Input to Output Disable Delay[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

tCO1 Sy nchronous Clock Input to Out put

Delay Com’l /Ind 6 7 12 ns

Mil 7 12

tCO2 Synchronous Clock to Local Feedback

to Combin atorial Output[4, 11] Com’l /Ind 14 17 25 ns

Mil 17

tS1 Dedicat e d Input or Feedback Set- Up

Time to S ynchronous Clock Input[7] Com’l /Ind 8 10 12 ns

Mil 10

tS2 I/O Input Set-Up Time to Synchronous

Clock Input[7, 12] Com’l /Ind 16 20 24 ns

Mil 20 24

tHInput Hold Time from Synchr onous

Clock Input[7] Com’l /Ind 0 0 0 ns

Mil 0 0

tWH Synchronous Clock Input HIGH Time Com’l /Ind 4.5 5 6 ns

Mil 5 6

tWL Synchronous Clock Input LOW Time Com’l / Ind 4.5 5 6 ns

Mil 5 6

tRW Asynchronous Clear Width[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

tRR Asynchronous Clear Recovery

Time[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

tRO Asynchronous Clear to Registered

Output Delay[7] Com’l /Ind 12 15 20 ns

Mil 15 20

tPR Asynchronous Preset Recovery

Time[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

tPO Asynchronous Preset to Registered

Output Delay[7] Com’l /Ind 12 15 20 ns

Mil 15 20

CY7C343

CY7C343B

tCF Synchronous Clock to Local Feed-

back Input[4, 13] Com’l /Ind 3 3 3 ns

Mil 3 3

tPExternal Synchronous Clock P eriod

(1/fMAX3)[4] Com’l /Ind 9 10 12 ns

Mil 10 12

fMAX1 External Maxi mum Frequency

(1/(tCO1 + tS1))[4, 14] Com’l /Ind 71.4 58.8 41.6 MHz

Mil 58.8 41.6

fMAX2 Int ernal Local Feedback Maximum

Frequen cy, lesser of (1/(tS1 + tCF)) or

(1/tCO1)[4, 15]

Com’l /Ind 90.9 76.9 66.6 MHz

Mil 76.9 66.6

fMAX3 Data Path Maximum Frequency, lea s t

of 1/(tWL + tWH), 1/ (tS1 + t H),

or ( 1/tCO1)[4, 16]

Com’l /Ind 111.1 100 83.3 MHz

Mil 100 83.3

fMAX4 Maximum Register Toggle Frequency

(1/(tWL+tWH))[4, 17] Com’l /Ind 111.1 100 83.3 MHz

Mil 100 83.3

tOH Output Data Stable Tim e from Syn-

chronous Clock Input[4, 1 8] Com’l /Ind 3 3 3 ns

Mil 3 3

tPW Asynchronous Preset W idth[4, 7] Com’l /Ind 12 15 20 ns

Mil 15 20

Shaded area contains preliminary information.

Notes:

7. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 1 1, 12, 13, 31, 33, 34, or 35) to combinatorial

output on any output pin. This delay assumes no expander terms are us ed to form the logic function. When this note is applied to any par ameter specification

it indicates that the signal (data, asy nchronous c lock , asynchronous clear , and/or asynchronous preset) is applied to a dedicated input only and no signal path

(either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to tPIA should be added t o the comparabl e delay

for a de dicat ed input. If expanders are used, add the maximum expander delay tEXP to t he overal l delay for the compara ble del ay with out expand ers.

8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used

to form the logic function.

9. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to

combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic

delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.

10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used

to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by

sampling production material.

11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic

array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same

LAB. This parameter is tested periodically by sampling production material.

12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for

synchronous op erat ion and t AS2 fo r async hronous operati on.

13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array

input. This delay plus the register set-up t ime, tS1, is the minimum internal pe riod for an inter nal synchr onous state machi ne configur ation. This d elay is for feedbac k within

the same LAB. T his para meter i s tested p eriodic ally by sampl ing produc tion m ateria l.

14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with exter nal feedback can

operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs.

15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states

must also control exter nal points , this frequency can still be observ ed as long as this frequency is less than 1/tCO1. All feedback is assume d to be local, origi nating

within t he s ame L AB..

16. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to

de dicated inpu ts and no expander logic is used.

17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled.

18. This parameter indicates the minimum t ime after a synchronous register clock input that the previous register output data is maintained on the output pin.

External Sync hronous Switching Characteristics[6 ] Over Operating Range ( continued)

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20

UnitMin. Max. Min. Max. Min. Max.

CY7C343

CY7C343B

External Sync hronous Switching Characteristics[6 ] Over Operating Range (continued)

Parameter D escripti on

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35

UnitMin. Max. Min. Max. Min. Max.

tPD1 Dedicat e d Input to Combinatorial

Output Delay[7] Com’l /Ind 25 30 35 ns

Mil 25 30 35

tPD2 I/O Input to Combinatorial Output

Delay[8] Com’l /Ind 39 44 53 ns

Mil 39 44 53

tPD3 Dedicat e d Input to Combinatorial

Output Delay wit h Expander Delay[9] Com’l /Ind 37 44 55 ns

Mil 37 44 55

tPD4 I/O Input to Combinatorial Output

Delay with Expander Delay[4, 10] Com’l/ Ind 51 58 73 ns

Mil 51 58 73

tEA Input to Output Enable Delay[4, 7] Com’l /Ind 25 30 35 ns

Mil 25 30 35

tER Input to Output Disable Delay[4, 7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tCO1 Sy nchronous Clock Input to Out put

Delay Com’l/ Ind 14 16 20 ns

Mil 14 16 20

tCO2 Synchronous Clock to Local Feedback

to Combin atorial Output[4, 11] Com’l/ Ind 30 35 42 ns

Mil 30 35 42

tS1 Dedicat e d Input or Feedback Set- Up

Time to S ynchronous Clock Input[7] Com’l/ Ind 15 20 25 ns

Mil 15 20 25

tS2 I/O Input Set-Up Time to Synchronous

Clock Input[7, 12] Com’l/ Ind 30 35 42 ns

Mil 30 35 42

tHInput Hold Time from Synchr onous

Clock Input[7] Com’l/ Ind 0 0 0 ns

Mil 0 0 0

tWH Synchronous Clock Input HIGH Time Com’l/ Ind 8 10 12.5 ns

Mil 8 10 12.5

tWL Synchronous Clock Input LOW Time Com’l/ Ind 8 10 12.5 ns

Mil 8 10 12.5

tRW Asynchronous Clear Width[4, 7] Com’l /Ind 25 30 35 ns

Mil 25 30 35

tRR Asynchronous Clear Recovery

Time[4, 7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tRO Asynchronous Clear to Registered

Output Delay[7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tPR Asynchronous Preset Recovery

Time[4, 7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tPO Asynchronous Preset to Registered

Output Delay[7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tCF Synchronous Clock to Local Feed-

back Input[4, 13] Com’l/ Ind 3 3 5 ns

Mil 3 3 5

tPExternal Synchronous Clock P eriod

(1/fMAX3)[4] Com’l/ Ind 16 20 25 ns

Mil 16 20 25

CY7C343

CY7C343B

fMAX1 External Maxi mum

Frequency (1/(tCO1 + tS1))[4, 14] Com’l/ Ind 34 27 22.2 MHz

Mil 34 27 22.2

fMAX2 Int ernal Local Feedback Maximum

Frequen cy, lesser of (1/(tS1 + tCF)) or

(1/tCO1)[4, 15]

Com’l /Ind 55 43 33 MHz

Mil 55 43 33

fMAX3 Data Path Maximum Frequency, lea s t

of 1/(tWL + tWH), 1/ (tS1 + t H), or

(1/tCO1)[4, 16]

Com’l /Ind 62.5 50 40 MHz

Mil 62.5 50 40

fMAX4 Maximum Register Toggle Frequency

(1/(tWL+tWH))[4, 17] Com’l/Ind 62.5 50 40 MHz

Mil 62.5 50 40

tOH Output Data Stable Tim e from Syn-

chronous Clock Input[4, 1 8] Com’l/ Ind 3 3 3 ns

Mil 3 3 3

tPW Asynchronous Preset W idth[4, 7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

External Sync hronous Switching Characteristics[6 ] Over Operating Range (continued)

Parameter D escripti on

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35

UnitMin. Max. Min. Max. Min. Max.

External Asynchronous Switching Characteristics Over Operating Range[6 ]

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20

UnitMin. Max. Min. Max. Min. Max.

tACO1 Asynchronous Clock Input to Output

Delay[7] Com’l/ Ind 12 15 20 ns

Mil 15 20

tACO2 Asynchronous Cl ock Input to L ocal

Feedback to Combinatorial

Output[19]

Com’l/ Ind 20 25 32 ns

Mil 25 32

tAS1 Dedicated Input or Feedback Set-Up

Time to Asynchronous Clock Input[7] Com’l/ Ind 3 3.5 4 ns

Mil 3.5 4

tAS2 I/ O Input Set-Up Tim e to Asynchr o-

nous Clock Input[7] Com’l/ Ind 12 13.5 15 ns

Mil 13.5 15

tAH Input Hold Tim e from Asynchronous

Clock Input[7] Com’l/ Ind 4 4.5 5 ns

Mil 4.5 5

tAWH Asynchronous Clock Input HIGH

Time[7] Com’l /I nd 8 8.5 9 ns

Mil 8.5 9

tAWL Asynchronous Clock I nput LOW

Time[7, 20] Com’l/ Ind 6 6.5 7 ns

Mil 6.5 7

tACF Asynchronous Clock to Local Feed-

back Input[4, 21] Com’l /Ind 9 11 13 ns

Mil 11 13

tAP External Asynchronous Clock Period

(1/fMAXA4)[4] Com’l/ Ind 14 15 16 ns

Mil 15 16

Notes:

19. This specification is a measure of the de lay from an asynchronous register clock input to intern al feedback of the r egister output signal to the input of the LAB

logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous c lock input.

The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.

20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL par ameters mus t be swapped.

If a gi ven input is u sed to c lock multiple r egis ters with bot h pos itiv e and negati ve po larity, tAWH should b e used fo r b oth tAWH and tAWL.

21. This specification is a measure of the delay associated with the internal register feedback path for an asy nchronous clock to LAB logic array input. This delay

plus the asynchronous register set-up time, tAS1, is the mi nimum inte rnal period for an i nte rnal asynchr onousl y clo cked sta te machine confi guration. T his delay is for

feedback w ithin the sa me LAB, ass umes no expander logic in the clock pat h, and as sumes that the cl ock i nput signal is app lied to a dedicated i npu t pin. This par ameter is

tested period ic ally by s ampling pr oduction mater ial.

CY7C343

CY7C343B

fMAXA1 External Maximum Frequency in

Asynchronous Mode

1/(tACO1 + tAS1)[4, 22]

Com’l/ Ind 66.6 54.0 41.6 MHz

Mil 54.0 41.6

fMAXA2 Maximum Internal Asynchronous

Frequency[4, 2 3] Com’l/ Ind 71.4 66.6 58.8 MHz

Mil 66.6 58.8

fMAXA3 Data Path Maximum Frequency in

Asynchronous Mode[4, 24] Com’l/ Ind 71.4 66.6 50 MHz

Mil 66.6 50

fMAXA4 Maximum Asynchronous Register

Toggle Frequency

1/(tAWH + tAWL)[4, 25]

Com’l/ Ind 71.4 66.6 62.5 MHz

Mil 66.6 62.5

Shaded area contains preliminary information.

External Asynchronous Switching Characteristics Over Operating Range[6 ] (continued)

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20

UnitMin. Max. Min. Max. Min. Max.

External Asynchronous Switching Characteristics Over Operating Range[6]

Parameter Description

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35 Unit

Min. Max. Min. Max. Min. Max.

tAOH Output Data Stable Time from Asyn-

chronous Clock Input[4 , 26] Com’l/ Ind 12 12 15 ns

Mil 12 15

tACO1 Asynchronous Clock Input to Output

Delay[7] Com’l/ Ind 25 30 35 ns

Mil 25 30 35

tACO2 Asynchronous Clock Input to Local

Feedback to Combinatorial

Output[19]

Com’l/ Ind 40 46 55 ns

Mil 40 46 55

tAS1 Dedicated Input or Feedback Set-Up

Time to Asynchronous Clock Input[7] Com’l/ Ind 5 6 8ns

Mil 568

tAS2 I/O Input Set-Up Time to Asynchro-

nous Clock Input[7] Com’l/ Ind 20 25 30 ns

Mil 20 25 30

tAH Input Hold Time from Asynchronous

Clock Input[7] Com’l/ Ind 6 8 10 ns

Mil 6 8 10

tAWH Asynchronous Clock Input HIGH

Time[7] Com’l/ Ind 11 14 16 ns

Mil 11 14 16

tAWL Asynchronous Clock Input LO W

Time[7, 20] Com’l/ Ind 9 11 14 ns

Mil 911 14

tACF Asynchronous Clock to Local Feed-

back Input[4, 21] Com’l/ Ind 15 18 22 ns

Mil 15 18 22

tAP External Asynchronous Clock Period

(1/fMAXA4)[4] Com’l/ Ind 20 25 30 ns

Mil 20 25 30

Note:

22. This spec ification indicates the guaranteed maximum frequency at which an as ynchr onously clocked state machine configuration with external feedback can

operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the

clock signal path or data path.

23. This specification indicates the guaranteed maximum frequency at which an asy nchronously clock ed s tate mach ine with internal-only feedbac k can operate.

This parameter is determined by the lesser of (1/tACF + tAS1)) or ( 1/(tAWH +tAWL) ). If r egister outp ut state s must als o control exter nal point s, this fr equency can still be

observ ed as long as this fr equency i s les s than 1/ tACO1.

24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined

by the least of 1/(tAWH + t AWL), 1/(tAS1 + tAH) or 1/t ACO1. It as sumes data an d c lock inpu t signal s ar e applied t o dedic ated input pins a nd no expa nder l ogic is u sed.

25. This spec ification indicates the guaranteed maximum frequency at which an ind ividual output or buried register can be c yc led in asy nchronously clock ed mode

by a clock signal applied to an external dedicated input pin.

26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input.

CY7C343

CY7C343B

fMAXA1 External Maximum Frequency in

Asynchronous Mode

1/(tACO1 + tAS1)[4, 22]

Com’l/ Ind 33 27 23 MHz

Mil 33 27 23

fMAXA2 Maximum Int ernal Asynchronous

Frequency[4, 23] Com’l/ Ind 50 40 33 MHz

Mil 50 40 33

fMAXA3 Data Path Maximum Frequency in

Asynchronous Mode[4, 24] Com’l/ Ind 40 33 28 MHz

Mil 40 33 28

fMAXA4 Maximum Asynchronous Regi ster

Toggle Frequenc y 1 /(tAWH + tAWL)[4, 25] Com’l/ Ind 50 40 33 MHz

Mil 50 40 33

tAOH Output Data Stable Time from Asyn-

chronous Clock Input[4 , 26] Com’l / Ind 15 15 15 ns

Mil 15 15 15

External Asynchronous Switching Characteristics Over Operating Range[6] (continued)

Parameter Description

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35 Unit

Min. Max. Min. Max. Min. Max.

Internal Switching Characteristics Over Operating Range[6]

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20 UnitMin. Max. Min. Max. Min. Max.

tIN Dedicated Input Pad and Buffer Delay Com’l / Ind 2.5 3 4 ns

Mil 3 4

tIO I/O Input Pad and Buff er Delay Com’l/ Ind 2.5 3 4 ns

Mil 3 4

tEXP E xpander Array Delay Com’l/ Ind 6 8 10 ns

Mil 8 10

tLAD L ogic Arr a y Data Delay Com’l/ Ind 6 8 10 ns

Mil 8 10

tLAC L o gic Arr ay Control Delay Com’l/ Ind 5 6 8 ns

Mil 6 8

tOD Output Buffer and Pad Delay Com’l/ Ind 3 3 4 ns

Mil 3 4

tZX Output Buffer Enable Delay[27] Com’l/ Ind 5 6 8 ns

Mil 6 8

tXZ Output Buffer Disable Del a y Com’l/ Ind 5 6 8 ns

Mil 6 8

tRSU Register Set-Up Time Relative t o

Clock Signal at Register Com’l/ Ind 2 3 4 ns

Mil 3 4

tRH Register Hold Ti me Relative to Clo ck

Signal at Register Com’l/ Ind 3 3.5 4 ns

Mil 3.5 4

tLATCH Flow-Thr ough Latch Delay Com’l /Ind 1 1 2 ns

Mil 1 2

tRD Register Delay Com’l/ Ind 1 1 1 ns

Mil 1 1

tCOMB Transparent M ode Delay[28] Com’l/ Ind 1 1 2 ns

Mil 1 2

CY7C343

CY7C343B

Shaded area contains preliminary information.

tCH Clock HIGH Time Com’l/ Ind 3 4 6 ns

Mil 4 6

tCL Clock LOW Time Com’l/ Ind 3 4 6 ns

Mil 4 6

tIC Asynchronous Clock Logic Delay Com’l/ Ind 5 7 12 ns

Mil 7 12

tICS Synchronous Clock Delay Com’l/ Ind 0.5 0.5 2 ns

Mil 0.5 2

tFD Feedback Delay Com’l/ Ind 1 1 1 ns

Mil 1 1

tPRE Asynchronous Regi ster Pre set Time Com’l/ Ind 3 3 4 ns

Mil 3 4

tCLR Asynchronous Register Clear Time Com’l/ Ind 3 3 4 ns

Mil 3 4

tPCW Asynchronous Preset and Clear Pulse

Width Com’l /Ind 2 3 4 ns

Mil 3 4

tPCR Asynchronous Preset and Clear

Recovery Time Com’l/ Ind 2 3 4 ns

Mil 3 4

tPIA Programm able Inter c onnect Array

Delay Time Com’l/ Ind 8 10 12 ns

Mil 10 12

Internal Switching Characteristics Over Operating Range[6] (continued)

Parameter Description

7C343-12

7C343B-12 7C343-15

7C343B-15 7C343-20

7C343B-20

UnitMin. Max. Min. Max. Min. Max.

Internal Switching Characteristics Over Operating Range[6]

Parameter Description

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35

Min. Max. Min. Max. Min. Max. Unit

tIN Dedicated Input Pad and Buffer Delay Com’l /Ind 5 7 9 ns

Mil 5 7 9

tIO I/O Input Pad and Buffer Delay Com’l/ Ind 5 5 7 ns

Mil 5 5 7

tEXP Expander Arr ay Del ay Com’l/ Ind 12 14 20 ns

Mil 12 14 20

tLAD Logic Array Data Delay Com’l/ Ind 12 14 16 ns

Mil 12 14 16

tLAC Logic Array Control Delay Com’l / Ind 10 12 13 ns

Mil 10 12 13

tOD Output Buffer and Pad Delay Com’l /Ind 5 5 6 ns

Mil 5 5 6

tZX Output Buffer Enable Del ay[27] Com’l /Ind 10 11 13 ns

Mil 10 11 13

tXZ Output Buff er Disable Delay Com’l /Ind 10 11 13 ns

Mil 10 11 13

CY7C343

CY7C343B

tRSU Register Set-Up Time Relati ve to

Clock Signal at Register Com’l / Ind 6 8 10 ns

Mil 6 8 10

tRH Register Hold Time Relative to Clock

Signal at Register Com’l/ Ind 6 8 12 ns

Mil 6 8 12

tLATCH Flow- Through Latch Delay Com’l /Ind 3 4 4 ns

Mil 3 4 4

tRD Register Delay Com’l /Ind 1 2 2 ns

Mil 1 2 2

tCOMB Transparent Mode Delay[28] Com’l/ Ind 3 4 4 ns

Mil 3 4 4

tCH Clock HIGH Time Com’l /Ind 8 10 12.5 ns

Mil 8 10 12.5

tCL Clock LOW Time Com’l /Ind 8 10 12.5 ns

Mil 8 10 12.5

tIC Asynchronous Clock L ogic Delay Com’l /Ind 14 16 18 ns

Mil 14 16 18

tICS Synchronous Clock Delay Com’l /Ind 2 2 3 ns

Mil 2 2 3

tFD Feedback Delay Com’l /Ind 1 1 2 ns

Mil 1 1 2

tPRE Asynchronous Register Preset Ti me Com’l /Ind 5 6 7 ns

Mil 5 6 7

tCLR Asynchronous Re gister Clear Time Com’l /Ind 5 6 7 ns

Mil 5 6 7

tPCW Asynchronous Preset and Clear Pulse

Width Com’l /Ind 5 6 7 ns

Mil 5 6 7

tPCR Asynchronous Preset and Clear Re-

covery Time Com’l/ Ind 5 6 7 ns

Mil 5 6 7

tPIA Programmable Interconnect Array De-

lay Time Com’l / Ind 14 16 2 0 n s

Mil 141620

27. Sample tested only for an output change of 500 mV.

28. This s pecification guarantees the maximum combinatorial de lay associated with the macrocell register bypass when the macroce ll is configured for combina-

torial operation.

Internal Switching Characteristics Over Operating Range[6] (continued)

Parameter Description

7C343-25

7C343B-25 7C343-30

7C343B-30 7C343-35

7C343B-35

Min. Max. Min. Max. Min. Max. Unit

CY7C343

CY7C343B

Switching Waveforms

External Combinatorial

External Synchronous

tPD1 /tPD2

tER

VALID OUTPUT

DEDICATED INPUT/

I/O INPUT

COMBINATORIAL

OUTPUT

COMBINATORIAL OR

REGISTERED

C343-6

HIGH-IMPEDANCE

THREE-STATE

HIGH-IMPEDANC

THREE–STATE

tS1 tWH tWL

tRR/tPR

tRW/tPW

tOH

tCO1

tRO/tPO

tCO2

C343-7

DEDICATED INPUTS OR

REGISTERED FEEDBACK

SYNCHRONOUS

CLOCK

ASYNCHRONOUS

CLEAR/PRESET

REGISTERED

OUTPUTS

COMBINATORIAL OUTPUT FROM

REGISTERED FEEDBACK

[7] [7]

[7]

OUTPUT tER[7]

[7]

[11]

tACO1

External Asynchronous

tAH

tAS1 tAWH tAWL

tRR/tPR

tRW/tPW

tAOH

tRO/tPO

tACO2

ASYNCHRONOUS

CLOCK INPUT

ASYNCHRONOUS REGISTERED

OUTPUTS

DEDICATEDINPUTSOR

REGISTERED

FEEDBACK

ASYNCHRONOUS

CLEAR/PRESET

COMBINATORIAL OUTPUT FROM

ASYNCH. REGISTERED FEEDBACK

[7 ]

CY7C343

CY7C343B

Switching Waveforms (continued)

Internal Combinatorial tIN

tIO tPIA

tEXP

tLAC,t

LAD

INPUT PIN

EXPANDER

I/O PIN

LOGIC ARRAY

ARRAY DELAY

OUTPUT

LOGIC ARRAY

INPUT

Internal Asynchronous

tIO tAWH tAWL tF

tIN

tIC

tRSU tRH

tRD,tLATCH tFD tCLR,tPRE tFD

CLOCK PIN

LOGIC ARRAY

CLOCK FROM

DATA FROM

CLOCK INTO

LOGIC ARRAY

TO LOCAL LAB

CY7C343

CY7C343B

Switching Waveforms (continued)

Output Mode

C343-11

tXZ tZX

tOD

HIGH IMPEDANCE

STATE

CLOCK FROM

LOGIC ARRAY

DATA FROM

OUT PUT PIN

tRD

InternalSynchronous

tCH tCL

tIN tICS

tRSU tRH

C343-12

SYSTEM CLOCK PIN

SYSTEM CLOCK

AT REGISTER

DATA FROM

LOGIC ARRAY

CY7C343

CY7C343B

Document #: 38-00128-G

Orde rin g Inf orm a tio n

Speed

(ns) Order ing Code Package

Name Package Type Operating

Range

12 CY7C343B-12HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial

CY7C343B-12JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

15 CY7C343B-15HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial

CY7C343B-15JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

CY7C343B-15HMB H67 44-Pin Windowed Leaded Chip Carrier Military

20 CY7C343-20JC/JI J67 44- Lead Pl a stic Leaded C hip Carr ier Commercial/Industrial

CY7C343B-20HC/HI H67 44-Pin Windowed Leaded Chip Carrier

CY7C343B-20JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

CY7C343B-20HMB H67 44-Pin Windowed Leaded Chip Carrier Military

25 CY7C343-25HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial

CY7C343-25JC/JI J67 44- Lead Pl a stic Leaded C hip Carr ier

CY7C343B-25HC/HI H67 44-Pin Windowed Leaded Chip Carrier

CY7C343B-25JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

30 CY7C343-30HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial

CY7C343-30JC/JI J67 44- Lead Pl a stic Leaded C hip Carr ier

CY7C343B-30HC/HI H67 44-Pin Windowed Leaded Chip Carrier

CY7C343B-30JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

CY7C343-30HMB H67 44-Pin Windowed Leaded Chip Carrier Military

CY7C343B-30HMB H67 44-Pin Windowed Leaded Chip Carrier

35 CY7C343-35HC/HI H67 44-Pin Windowed Leaded Chip Carrier Commercial/Industrial

CY7C343-35JC J67 44-Lead Pl astic Leaded Chip Carrier

CY7C343B-35HC/HI H67 44-Pin Windowed Leaded Chip Carrier

CY7C343B-35JC/JI J67 44-L ead Pl astic Leaded C hip Carrier

CY7C343-35HMB H67 44-Pin Windowed Leaded Chip Carrier Military

CY7C343B-35HMB H67 44-Pin Windowed Leaded Chip Carrier

Shaded area contains preliminary information.

MIL ITARY SPEC IFICAT IONS

Group A Subgroup Testing

DC Characteristics

Parameters Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC1 1, 2, 3

Switching Characteristics

Parameters Subgroups

tPD1 7, 8, 9, 10, 11

tPD2 7, 8, 9, 10, 11

tPD3 7, 8, 9, 10, 11

tCO1 7, 8, 9, 10, 11

tS7, 8, 9, 10, 11

tH7, 8, 9, 10, 11

tACO1 7, 8, 9, 10, 11

tACO2 7, 8, 9, 10, 11

tAS 7, 8, 9, 10, 11

tAH 7, 8, 9, 10, 11

CY7C343

CY7C343B

Package Diagrams

44-Pin Windowed Leaded Chip Carrier H67

CY7C343

CY7C343B

of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze

its products for use as critical components in life- support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems appl ication impl ies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypr ess Semiconductor against all charges.

Package Diagrams (c ontinued)

44-Lead Plastic Leaded Chip Carrier J67