TFP410PAP - Texas Instruments

ErrataSLLZ030A – June 2003 – Revised April 2009

Errata to TFP410 Datasheet

This document describes errata to the TFP410 and its datasheet (literature number SLDS145 ).

Revision History

VERSION DATE DESCRIPTION

1.0 Initial DE generator1.1 1/22/2003 Items 2-4V

, V

clarification, CTL3 encoding,1.2 5/20/2003

pad size update, revision historyA 4/17/2009 Removed pad size information

DE Generator

The DE generator function has a limitation which limits its use in high pixel count formats. The DE_DLYand DE_CNT values are limited by DE_DLY + DE_CNT < 2047.

For resolutions where the timing allows, it may be possible to work around this limitation by using theinactive edge of HSYNC as the starting point for DE_DLY. Appropriate timing allowances may be neededfor the vertical count starting location.

Changes in the Document TextIn the “register descriptions” section, under the pictorial for DE_DLY (Page 20), add after the existingsentence: The value must be less than or equal to (2047 - DE_CNT).In the “register descriptions” section, under the pictorial for DE_CNT (Page 21), add after the existingsentence: The value must be less than or equal to (2047 - DE_DLY)

MSEN Output

The MSEN output description is incorrect in the “Terminal Functions” table. MSEN behavior of the 410with manual configuration is to output the receiver connected status as a high, receiver not connected as alow.

Changes in the Document Text

From: When I

C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at thedifferential outputs. A high level indicates a powered on receiver is not detected. This function isonly valid in dc-coupled systems.To: When I

C is disabled (ISEL = low), a high level indicates a powered on receiver is detected atthe differential outputs. A low level indicates a powered on receiver is not detected. This functionis only valid in dc-coupled systems.

SLLZ030A – June 2003 – Revised April 2009 Errata to TFP410 Datasheet 1Submit Documentation Feedback

Error in Register Capability

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Error in Register Capability

Changes in the Document TextSheet 17, in the register map for sub-address 0B, change the RW column valueFrom: RW To: R

Error in Default Value

Changes in the Document TextSheet 18, Reg sub-address 08 change register defaultFrom: FE To: BE

CTL3 Not Encoded in OutputThe CTL3 input from the device pin or register value is not encoded into the DVI stream. The currentTFP410 is aware of HDCP and encodes the CTL3 signal as 0 in the output. When the device is configuredfor manual input with pins 6-8 selected as CTL[3:1], pin 6 is not encoded. When the device is configuredfor I2C operation, bit 3 of the CTL_# MODE register at Sub-Address 0A can be written and read, but thebit is not encoded.

Changes in the Document TextSheet 2, change pin 6 labelFrom: CTL3/A3/DK3 To: A3/DK3

Sheet 4, in the Terminal Functions table, change the name of pin 6From: CTL3/A3/DK3 To: A3/DK3

Sheet 4, in the Terminal Functions table, change pin 6 DescriptionFrom: When the I

C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low),these three inputs become the control inputs, CTL[3:1], which can be used to send additionalinformation across the DVI link during the blanking interval (DE = low). The CTL3 input isreserved for HDCP compliant DVI TXs (TFP510) and the CTL[2:1] inputs are reserved forfuture use.To: When the I

C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low),pins 7 and 8 become the control inputs, CTL[2:1], which can be used to send additionalinformation across the DVI link during the blanking interval (DE = low). Pin 6 is not used.

Sheet 10, in the first paragraph of the T.M.D.S. pixel data and control signal encoding section, changethe sentence

From: These same three channels are also used to transmit HSYNC, VSYNC, and three userdefinable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low).To: These same three channels are also used to transmit HSYNC, VSYNC, and the control signals,CTL[3:1], during the inactive display or blanking interval (DE = Low).

Errata to TFP410 Datasheet2 SLLZ030A – June 2003 – Revised April 2009Submit Documentation Feedback

CTL[3:1]

2 1

CTL[2:1]

RSVD

2 1

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Input Voltage Clarifications

Sheet 10, in note 8, change the second sentenceFrom: The CTL3 input is reserved for HDCP compliant DVI TXs and the CTL[2:1] inputs are reservedfor future use.To: CTL3 is reserved for HDCP and is always encoded as 0. The CTL[2:1] inputs are reserved forfuture use.

Sheet 19, register CTL_3_MODE, change definition of bits 3:1 in the diagramFrom:

To:

In the text below the diagram, change the CTL bit definition nameFrom: CTL[3:1]:This read/write register contains the values of the three CTL[3:1] bits that are outputon the DVI port during the blanking interval.To: CTL[2:1]:This read/write register contains the values of the three CTL[2:1] bits that are outputon the DVI port during the blanking interval.

Input Voltage Clarifications

In the DC specification table, V

and V

are not clear for signals that are not part of the video input bus.

Changes in the Document TextSheet 7, in the dc specifications table, change the V

and V

specifications to contain the followinginformation:

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Data, DE, VSYNC, V

REF

= DV

0.7 ×V

DDHSYNC andHigh-level inputV

0.5 V ≤V

REF

≤0.95 V V

REF

+ 0.2 VIDCK+/–voltage

Other inputs 0.7 ×V

Data, DE, VSYNC, V

REF

= DV

0.3 ×V

DDHSYNC andLow-level inputV

0.5 V ≤V

REF

≤0.95 V V

REF

– 0.2 VIDCK+/–voltage

Other inputs 0.3 ×V

SLLZ030A – June 2003 – Revised April 2009 Errata to TFP410 Datasheet 3Submit Documentation Feedback

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