ee FAIRCHILD ee SEMICONDUCTOR 100343 Low Power 8-Bit Latch General Description March 1998 Features The 100343 contains eight D-type latches, individual inputs, | Low power operation (D,,), outputs (Q,,), a common enable pin (E), and a latch en- = 2000V ESD protection able pin (LE).AQ output follows its D input when both Eand Voltage compensated operating range = 4.2V to -5.7V LEare LOW. When either E or LE (or both) are HIGH, alatch > Available to industrial grade temperature range stores the last valid data present on its D input priortoEor Available to MIL-STD-883 LE going HIGH. The 100343 outputs are designed to drive a 50Q termination resistor to -2.0V. All inputs have 50 kQ pull-down resistors. Ordering Code: Logic Symbol Dg Dy Dy Dz Dy Ds Dg Dz OJLE oO E Q Ay Oz Q4 Os Qe Q, DS010260-1 Pin Names Description Do-Dz Data Inputs E Enable Input LE Latch Enable Input Qy-Q, Data Inputs NG No Connect 1998 Fairchild Semiconductor Corporation DS010250 www fairchildsemi.com Ydje] Ha-8 4OMOd MO] EVEOOLConnection Diagrams 24-Pin DIP SY Dy! 24;D; Ds 2 23;-D, De3 22D, D4 21F-Dy NC5 20F-E Voo76 19 LE Voca|7 18|-Veg Veca] 8 '7F-Voca ae 16-0 Q10 15-2, O11 14/0, Q4412 13,;-Q5 DS010250-2 28-Pin PCC 24-Pin Quad Cerpak Q Q O53 Vers O4 Q5 Q5 Do E LE Yee YecaQo HOBBOeE [J | fj tt nd halal add 24 23 22 21 20 19 Q% DW! 18F- Qy Voca Dp 42 17} Vee D343 16-0; Vegs 4 15 a, LE De 45 14 im 5 Qs Dp De 6 13} O, 7 8 9 10 11 12 a TTT Tt Dz NC Veo VecaYocaQ7 Dy De Ds Vers D4 Ds Dg D$010260-3 DBS010250-4 Logic Diagram E LE Dp Dy Dp Ds Dg Ds Dg Dy E D E D E D E D E D E D E D E D DS010250-5 www fairchildsemi.com 2Truth Table Inputs Outputs D, E LE Q, L L L L H L L H x H x Latched (Note 1) x x H Latched (Note 1) H = HIGH voltage level L = LOW voltage level X = Dont's care Note 1: Retains data present before either LEor E went HIGH www fairchildsemi.comAbsolute Maximum Ratings (note 2) Storage Temperature (Tsya@) Maximum Junction Temperature (Tj) Commercial Version DC Electrical Characteristics -65C to +150C Ceramic H175C Plastic +150C Vee Pin Potential to Ground Pin -7.0V to +0.5V Input Voltage (DC) Vee to +0.5V Output Current (DC Output HIGH) -50 mA ESD (Note 3) 22000V Recommended Operating Conditions Case Temperature (Tg) Commercial 0C to +85C Industrial -40C to +85C Military -55C to +125C Supply Voltage (Vee) -5.7V to -4.2V Note 2: Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Ver = -4.2V to -5.7V, Vog = Voca = GND, Ty = 0C to +85C (Note 4) Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin = Vin (Max) Loading with VoL Output LOW Voltage -1830 | -1705 | -1620 mV or Vi (Min) 502 to -2.0V Vouc Output HIGH Voltage -1035 mV Vin = Vin (Min) Loading with Vote Output LOW Voltage -1610 mV or Vi_ (Max) 50Q to -2.0V Vin Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vit (Min) lia Input HIGH Current 240 HA Vin = Vin (Max) lee Power Supply Current Inputs Open -95 -55 mA Vee = -4.2V to -4.8V -97 -55 Vee = -4.2V to -5.7V operation under worst case conditions. Commercial Version DIP AC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND Note 4: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee Symbol Parameter Te = 0C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.80 2.00 0.80 2.00 0.80 2.20 ns Figures 1, 2, 3 TeHL D,, to Output (Note 5) teLy Propagation Delay 1.40 2.90 1.40 2.90 1.60 3.10 ns Figures 1, 2, 3 teat LE, E to Output (Note 5) tty Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 3 tra 20% to 80%, 80% to 20% ty Setup Time Dpy-Dz 1.0 1.0 11 ns Figures 1, 4 th Hold Time Dpy-Dz 0.1 0.1 0.1 ns Figures 1, 4 tow(H) Pulse Width HIGH LE,E | 2.00 2.00 2.00 ns | Figures 1, 4 Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. www fairchildsemi.comCommercial Version PCC and Cerpack AC Electrical Characteristics Ver = -4.2V to -5.7V, Vog = Voc, = GND Symbol Parameter To = 0'C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.80 1.80 0.80 1.80 0.80 2.00 ns Figures 1, 2,3 TeHL D, to Output (Note 7) teLy Propagation Delay 1.40 2.70 1.40 2.70 1.60 2.90 ns Figures 1, 2,3 teu LE, E to Output (Note 7) tty Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 3 tra 20% to 80%, 80% to 20% ty Setup Time Dp-Dz | 0.90 0.90 1.00 ns Figures 1, 4 th Hold Time Do-D; 0.0 0.0 0.0 ns Figures 1, 4 tow(H) Pulse Width HIGH LE,E |} 2.00 2.00 2.00 ns Figures 1, 4 tosHL Maximum Skew Common Edge PCC Only Output-to-Output Variation 340 340 340 ps (Note 6) Data to Output Path tosLH Maximum Skew Common Edge PCC Only Output-to-Output Variation 440 440 440 ps (Note 6) Data to Output Path tost Maximum Skew Opposite Edge PCC Only Output-to-Output Variation 480 480 480 ps (Note 6) Data to Output Path tps Maximum Skew PGC Only Pin (Signal) Transition Variation 300 300 300 ps (Note 6) Data to Output Path Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tggH1), or LOW to HIGH (tog_y), or in opposite directions both HL and LH (tost). Parameters togt and tpg guaranteed by design. Note 7: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Industrial Version PCC DC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Voca = GND, Te = -40C to +85C (Note 8) Symbol Parameter To = -40C To = OC to +85C Units Conditions Min Max Min Max Vou Output HIGH Voltage -1085 -870 -1025 -870 mV Vin = Vin (max) Loading with VoL Output LOW Voltage -1830 8 -1575 -1830 -1620 mV or Vit (min) 50Q to -2.0V Vouc Output HIGH Voltage -1095 -1085 mV Vin = Vin min) Loading with Voie Output LOW Voltage -1565 -1610 mV or Vit (max) 50Q to -2.0V Vin Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1480 -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 0.50 HA Vin = Vit (Min) la Input HIGH Current 240 240 HA Vin = Vin (Max) lee Power Supply Current Inputs Open -95 -50 -95 -55 mA Vee = -4.2V to -4.8V -97 -50 -97 -55 Vee = -4.2V to -5.7V 5 www fairchildsemi.comIndustrial Version PCC DC Electrical Characteristics (continued) operation under worst case conditions. Industrial Version PCC AC Electrical Characteristics Vee = -4.2V to -5.7V, Voo = Veca = GND Note 8: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee Symbol Parameter To = -40C To = +25C To = +85C Units Min Max Min Max Min Max teLy Propagation Delay 0.80 1.80 0.80 1.80 0.80 2.00 ns Figures 1, 2, 3 TeHL D,, to Output (Note 9) teLy Propagation Delay 1.40 2.70 1.40 2.70 1.60 2.90 ns Figures 1, 2, 3 teu LE, E to Output (Note 9) tty Transition Time 0.40 2.50 0.45 1.90 0.45 1.90 ns Figures 1, 3 tra 20% to 80%, 80% to 20% ts Setup Time Dpy-Dz 0.60 0.90 1.00 ns Figures 1, 4 th Hold Time Do-Dz 0.8 0.0 0.0 ns Figures 1, 4 tow(H) Pulse Width HIGH LE,E} 2.40 2.00 2.00 ns | Figures 1, 4 Note 9: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Military Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Voeca = GND, To = -55C to +125C Symbol Parameter Min | Max |Units Te Conditions Notes Vou Output HIGH Voltage -1025 | -870 | mV 0C to Vin = Vin (Max) Loading with 1,2,3 +125C or Vi (Min) 50Q to -2.0V -1085 | -870 | mV -55C VoL Output LOW Voltage -1830 |-1620 | mV 0C to +125C -1830 |-1555 | mV -55C Vouc Output HIGH Voltage -1035 mV 0C to Vin = Vin (Max) Loading with 1,2,3 +125C or Vi (Min) 50Q to -2.0V -1085 mV -55C Vote Output LOW Voltage -1610 | mV 0C to +125C -1555 | mV -55C Vin Input HIGH Voltage -1165 | -870 | mV 55C to Guaranteed HIGH Signal for All Inputs 1,2,3,4 +125C Vit Input LOW Voltage -1830 |-1475 | mV -58C to Guaranteed LOW Signal for All Inputs 1,2,3,4 +125C lit Input LOW Current 0.50 HA -58C to Vee = -4.2V 1,2,3 +125C Vin = Vic (Min) lee Power Supply Current -100 |} -35 mA 55 to Vee = -4.2V to -4.8V 1,2,3 -105 | -35 mA +125C Vee = -4.2V to -5.7V www fairchildsemi.com 6Military Version DC Electrical Characteristics (Continued) Ver = -4.2V to -5.7V, Veo = Veca = GND, To = 55C to +125C Symbol Parameter Min Max | Units Te Conditions Notes liq Input HIGH Current 240 HA 0C to Vee = -5.7V 1,2,3 +125C Vin = Vin (Max) 340 HA -55C lee Power Supply Current -58C to Inputs Open -100 |} -35 mA +125C Vee = -4.2V to -4.8V 1,2,3 -105 | -35 Vee = -4.2V to -5.7V Note 10: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immedi- ately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 11: Screen tested 100% on each device at 55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8. Note 12: Sample tested (Method 5005, Table |) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. Note 13: Guaranteed by applying specified input condition and testing VoH/VoL. Military Version AC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND Symbol Parameter To = -55C Te = 425C | To = +125C | Units Conditions Notes Min Max Min Max Min Max teLy Propagation Delay 050 2.70 | 050 230] 050 2.80 ns . (Notes 14, Figures 1, 2, 3 teHL D, to Output 15, 16, 18) teLy Propagation Delay 0.90 3.40 1.0 3.10 1.10 3.90 ns . (Notes 14, = Figures 1, 2, 3 teHL LE, E to Output 15, 16, 18) tty Transition Time 040 250 | 040 240] 040 2.70 ns Figures 1, 3 (Note 17) trae 20% to 80%, 80% to 20% ts Setup Time Dpo-Dz | 0.60 0.60 0.60 ns Figures 1, 4 (Note 17) th Hold Time Do-D, | 1.50 1.50 1.70 ns Figures 1, 4 (Note 17) tow(H) Pulse Width HIGH LE, E | 2.40 2.40 2.40 ns | Figures 1, 4 (Note 17) Note 14: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immedi- ately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 15: Screen tested 100% on each device at +25C temperature only, Subgroup AQ. Note 16: Sample tested (Method 5005, Table |) on each manufactured lot at +25C, Subgroup AQ, and at +125C and 55C temperatures, Subgroups A10 and A11. Note 17: Not tested at +25C, +125C, and -55C temperature (design characterization data). Note 18: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. www fairchildsemi.comTest Circuitry PULSE fy yg SCOPE GENERATOR [47 , CHAN A 1 = 3 8 1H go : 5, 5 oT I = 3 PULSE gy GENERATOR [ 4 2, Ry fy SCOPE D a ws CHAN B | 500 DS010260-6 Note 19: Voc, Voca = +2V, Veg = -2.5V Note 20: L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 HF from GND to Veg and Veg All unused outputs are loaded with 500 to GND C, = Fixture and stray capacitance < 3 pF FIGURE 1. AC Test Circuit Switching Waveforms DATA 0.7 ns0.1 ns 0.7 ns 0.1 ns LE or E OUTPUT DS010260-7 FIGURE 2. Propagation Delays 0.7 ns 0.1 ns 0.7 ns0.1 ns | DATA teu teat OUTPUT 20% THE DS010260-8 FIGURE 3. Propagation and Transition Times DATA LE or E toy (H) DS010250-9 FIGURE 4. Setup, Hold and Pulse Width Times www fairchildsemi.com 8Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100343 D GCG OB Device Type (Basic) LL Special Variation QB = Military grade device with Package Code - environmental and burn-in D = Ceramic DIP processing F = Quad Cerpak P = Plastic DIP Temperature Range Q = Plastic Leaded Chip Carrier (PCC) C = Commercial (0C to + 85C) | = Industrial ( 40C to + 85C) (PCC Only) M = Military ( 55C to + 125C) DS010250-10 9 www. fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted 1.215 i (30.86) 0,025 MAX 0.030 0.055 (0.64) 24 13 (0.76 1.40) RAD PD RAD TYP 0.390 (9.91) MAX >) ~~ 4 Pe ee 1 12 >| je parca, 0.005 < GLASS 0.0500.060 erat. 0.4000.430 0.180 (0.13) SEALANT (127 1.52) YP 0.015 0.055 15 (10.16 10.92) (4.57) MIN TYP (0.38 1.40) 1 AX F 4 ) 0.225 | | p rH (5.72) Vmax Typ 8694 A i 4 \ Y gor190 i (0.008 ~0.012 NP TYP (0.20--0.30) 0.125 TYP 0.055 0.090-0.110 | 0.0150.021 (3.18) 0.435 0.535 (1.40) (2.29 2.79) (0.38 0.53) MIN (11.05-13.59) MAX TYP TYP TYP TYP BOTH ENDS J24E (REV Jy 24-Pin Ceramic Dual-In-Line Package (D) Package Number J24E 1.194-1.214 [30.33-30.84] 0.202 24 [5.13] 13 ODO Oooo ooo g 0:035-0.045 f [0.89-1.14] b) 0.337-0.347 [8.56-8.81] Q Oo OCOCTCICTCIcrcrcy Oo 1 12 PIN NO. 1 IDENT g 0-128 [3.18] 0.125-0.135 4 0.060 0.039 - 3.18-3.43 TYP 4X 0.390-0.410 [ ] [1.52] [0.99] 7] [~~ 0.065 [9.91-10.41] [1.65] 0.145-0.200 | | f 90-100 [3.68-5.08] yo B6-94 0.380 0.020 0.125-0.140 , 4 lel MIN MIN L_ [9.65] [0.51] [3.18-3.56] | | 1 0.047-0.057 +0.040 0.050 | [rt9-1.45] YP 0.428 015 TYP [1.27] [10.87 *1-921 0.015-0.021 0.090-0.110 4. 0,009-0.015 -0.38] [o.38-0.83] TP [2.29-2.79] [0.23-0.38] N24E (REV A) 24-Lead Plastic Dual-In-Line Package (P) Package Number N24E www fairchildsemi.comPhysical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) +0,006 0.450 -0.000 +0.15 [11.43] -0.00 PIN #1 IDENT 4 1 26 0.02940.003 450 x 0-045 Typ [0.4340.10] S [0.7440.08] 1 _| _ [] 25 L] C] L] a L] [Jig 12) 9.050 | 2 TYP [1.27] | 9.300 typ _ [7.62] 0.165-0.180 [4.19-4.57] 0.490+0.005 TYP [12.4540.13] 0.41040.020 yyp [10.4140.51] an SEATING PLANE >| J 0-920 Win Tye [0.51] 0.10540.015 yyp [2.6740.38] [0.004 [0.10] V2BA (REV K} 28-Pin Plastic Leaded Chip Carrier (Q) Package Number V28A 1.14 [1.14] 9.01740.004 yp aml www fairchildsemi.com100343 Low Power 8-Bit Latch Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.366 0.370 MIN 0.360 0.007 ~~ 9.250 TYP TYP 9.250 TYP | * I~ o.o04 TYP (MOLDED BODY) PIN ND. 1 N (24 19 7 11 18 fz o __ a aD 1 a MH + __ a __J I o 6 30 o C7 12 ign 0.018 | 0.075 MAX 0.050 o.o1g "YP 8 PLCS Pl 01035 > 4.080 =-0.005 >| < 0.085 max LIFE SUPPORT POLICY 0.400 MAX ___,,. | TYP GLASS W248 (REV Di 24-Lead Quad Cerpak (F) Package Number W24B FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, failure to perform when properly used and (c) whose in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Corporation Europe Americas Semiconductor Fax: +49 (0) 1 80-530 85 86 Customer Response Center Email: europe.support@nsc.com Tal: 1-888-522-5372 Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy www fairchildsemi.com Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, & Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.