MT45W2MW16BAFB-701WT - Micron Technology, Inc.

09005aef80ec6f63 pdf/09005aef80ec6f46 zip

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

BURST

CellularRAMTM

MT45W2MW16BAFB

Features

• Single device supports asynchronous, page, and burst

operations

•V

CC, VCCQ Voltages

1.70V–1.95V VCC

1.70V–3.30V VCCQ

• Random Access Time: 70ns

• Burst Mode Write Access

Continuous burst

• Burst Mode Read Access

4, 8, or 16 words, or continuous burst

MAX clock rate: 104 MHz (tCLK = 9.62ns)

Burst initial latency: 39ns (4 clocks) @ 104 MHz

tACLK: 6.5ns @ 104 MHz

• Page Mode Read Access

Sixteen-word page size

Interpage read access: 70ns

Intrapage read access: 20ns

•Low Power Consumption

Asynchronous READ < 20mA

Intrapage READ < 15mA

Initial access, burst READ:

(39ns [4 clocks] @ 104 MHz) < 35mA

Continuous burst READ < 15mA

Standby: 90µA Low-power; 110µA Standard

Deep power-down < 10µA

• Low-Power Features

Temperature Compensated Refresh (TCR)

On-Chip Sensor Control

Partial Array Refresh (PAR)

Deep Power-Down (DPD) Mode

Figure 1: 54-Ball VFBGA

Part Number Example:

MT45W2MW16BAFB-706LWT

Options Designator

• Configuration:

2 Meg x 16 MT45W2MW16BA

VCC Core Voltage Supply: 1.8V

VCCQ I/O Voltage: 1.8V

•Package

54-ball VFBGA FB

54-ball VFBGA—Lead-free BB1

• Timing

60ns access -601

70ns access -70

85ns access -85

•Frequency

66 MHz 6

80 MHz 8

104 MHz 11

Options (continued) Designator

• Standby Power

Standard None

Low-power L

• Operating Temperature Range

Wireless (-30°C to +85°C) WT2

Industrial (-40°C to +85°C) IT1

NOTE:

1. Contact factory.

2. -30°C exceeds the CellularRAM Workgroup 1.0

specification of -25°C.

1 2 3 4 5 6

Top View

(Ball Down)

LB#

DQ8

DQ9

VSSQ

VCCQ

DQ14

DQ15

A18

WAIT

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

CLK

A17

A21

A14

A12

ADV#

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A20

A16

A15

A13

A10

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Burst Wrap (BCR[3]) Default = Burst No Wrap (within burst length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . . . . 20

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Latency Counter (BCR[13:11]) Default = Three-Clock Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Temperature Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . . 23

Page Mode Operation (RCR[7]) Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Functional Block Diagram—2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 6: WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 7: Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 8: Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 9: Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 10: Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 11: Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 12: Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation . . . .15

Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation . . . . .16

Figure 15: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 16: Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 17: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 18: WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 19: WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 20: WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 21: Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 22: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 23: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 24: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 25: Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 26: Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 27: Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 28: Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 29: Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 30: 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 31: 4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 32: READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 33: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . .39

Figure 34: CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 35: LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 36: WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 37: Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 38: Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 39: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition .45

Figure 40: Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 41: Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 42: Asynchronous WRITE Followed By Burst READ—ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 43: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 44: Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 45: Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 46: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 47: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 2: Bus Operations—Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 3: Bus Operations—Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 5: Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 6: 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 7: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 8: Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 9: Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 10: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 11: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 12: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 13: Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 14: Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 15: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 16: Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 17: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 18: Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19: Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 20: Asynchronous READ Timing Parameters—Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 21: Burst READ Timing Parameters—Single Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 22: Burst READ Timing Parameters—4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 23: Burst READ Timing Parameters—4-Word Burst with LB#/UB#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 24: Burst READ Timing Parameters—Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 25: Burst READ Timing Parameters—BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 26: Asynchronous WRITE Timing Parameters—CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 27: Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 28: Asynchronous WRITE Timing Parameters—WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 29: Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 30: Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 31: Burst WRITE Timing Parameters—BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 32: WRITE Timing Parameters—Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 33: READ Timing Parameters—Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 34: WRITE Timing Parameters—Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 35: READ Timing Parameters—Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 36: Asynchronous WRITE Timing Parameters—ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 37: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 38: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 39: Asynchronous WRITE Timing Parameters—WE# Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 40: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 41: Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 42: WRITE Timing Parameters—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 43: READ Timing Parameters—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 44: WRITE Timing Parameters—Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 45: READ Timing Parameters—Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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General Description

Micron CellularRAM™ products are high-speed,

CMOS dynamic random access memories developed

for low-power, portable applications. The

MT45W2MW16BA is a 32Mb device organized as 2

Meg x 16 bits. These devices include an industry-

standard burst mode Flash interface that dramatically

increases read/write bandwidth compared with other

low-power SRAM or Pseudo SRAM offerings.

To operate seamlessly on a burst Flash bus, Cellu-

larRAM products incorporate a transparent self-

refresh mechanism. The hidden refresh requires no

additional support from the system memory controller

and has no significant impact on device read/write

performance.

Two user-accessible control registers define device

operation. The bus configuration register (BCR)

defines how the CellularRAM device interacts with the

system memory bus and is nearly identical to its coun-

terpart on burst mode Flash devices. The refresh con-

figuration register (RCR) is used to control how refresh

is performed on the DRAM array. These registers are

automatically loaded with default settings during

power-up and can be updated anytime during normal

operation.

Special attention has been focused on standby cur-

rent consumption during self refresh. CellularRAM

products include three system-accessible mechanisms

to minimize standby current. Partial array refresh

(PAR) limits refresh to only that part of the DRAM array

that contains essential data. Temperature compen-

sated refresh (TCR) uses an on-chip sensor to adjust

the refresh rate to match the device temperature. The

refresh rate decreases at lower temperatures to mini-

mize current consumption during standby. TCR can

also be set by the system for maximum device temper-

atures of +85°C, +45°C, and +15°C. Deep power-down

(DPD) halts the refresh operation altogether and is

used when no vital information is stored in the device.

These three refresh mechanisms are accessed through

the RCR.

Figure 2: Functional Block Diagram—2 Meg x 16

NOTE:

Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing

diagrams for detailed information.

A[20:0]

Input/

Output

MUX

and

Buffers

Control

Logic

2,048K x 16

DRAM

MEMORY

ARRAY

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

DQ[7:0]

DQ[15:8]

Address Decode

Logic

Refresh Configuration

Bus Configuration

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will

be asserted but should be ignored during asynchronous and page mode operations.

Table 1: VFBGA Ball Descriptions

VFBGA

ASSIGNMENT SYMBOL TYPE DESCRIPTION

A3, A4, A5, B3,

B4, C3, C4, D4,

H2, H3, H4, H5,

G3, G4, F3, F4,

E4, D3, H1, G2,

A[20:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations.

Addresses are internally latched during READ and WRITE cycles. The address lines

are also used to define the value to be loaded into the bus configuration register

or the refresh configuration register.

J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during

synchronous operations. When configured for synchronous operation, the address

is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or

LOW) during asynchronous access READ and WRITE operations and during PAGE

READ ACCESS operations.

J3 ADV# Input Address Valid: Indicates that a valid address is present on the address inputs.

Addresses can be latched on the rising edge of ADV# during asynchronous READ

and WRITE operations. ADV# can be held LOW during asynchronous READ and

WRITE operations.

A6 CRE Input Configuration Register Enable: When CRE is HIGH, WRITE operations load the

refresh configuration register or bus configuration register.

B5 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby or deep power-down mode.

A2 OE# Input Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle

is a WRITE to either a configuration register or to the memory array.

A1 LB# Input Lower Byte Enable. DQ[7:0]

B2 UB# Input Upper Byte Enable. DQ[15:8]

B6, C5, C6, D5,

E5, F5, F6, G6,

B1, C1, C2, D2,

E2, F2, F1, G1

DQ[15:0] Input/

Output

Data Inputs/Outputs.

J1 WAIT Output Wait: Provides data-valid feedback during burst READ and WRITE operations. The

signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and

READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.

WAIT is also used to mask the delay associated with opening a new internal page.

WAIT is asserted and should be ignored during asynchronous and page mode

operations. WAIT is High-Z when CE# is HIGH.

E3, J4, J5, J6 NC – Not internally connected.

D6 VCC Supply Device Power Supply: (1.70V–1.95V) Power supply for device core operation.

E1 VCCQ Supply I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.

E6 VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. CLK may be HIGH or LOW, but must be static during async read, async write, and burst suspend modes; and to achieve

standby power during standby and active modes.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are

affected. When only UB# is in the select mode, DQ[15:8] are affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any

external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.

7. DPD is maintained until RCR is reconfigured.

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

Table 2: Bus Operations—Asynchronous Mode

MODE POWER CLK1ADV# CE# OE# WE# CRE

LB#/

UB# WAIT2DQ[15:0]3NOTES

Read Active X L L L H L L Low-Z Data-Out 4

Write Active X L L X L L L Low-Z Data-In 4

Standby Standby X X H X X L X High-Z High-Z 5, 6

No Operation Idle X X L X X L X Low-Z X 4, 6

Configuration

Active XL LHLHXLow-ZHigh-Z

DPD Deep

Power-Down

X X H X X X X High-Z High-Z 7

Table 3: Bus Operations—Burst Mode

MODE POWER CLK1ADV# CE# OE# WE# CRE

LB#/

UB# WAIT2DQ[15:0]3NOTES

Async Read Active X L L L H L L Low-Z Data-Out 4

Async Write Active X L L X L L L Low-Z Data-In 4

Standby Standby X X H X X L X High-Z High-Z 5, 6

No Operation Idle X X L X X L X Low-Z X 4, 6

Initial Burst

Read

Active L L X H L L Low-Z Data-Out 4, 8

Initial Burst

Write

Active L L H L L X Low-Z Data-In 4, 8

Burst

Continue

Active H L X X X L Low-Z Data-In or

Data-Out

4, 8

Burst Suspend Active X X L H X L X Low-Z High-Z 4, 8

Configuration

Active L L H L H X Low-Z High-Z 8

DPD Deep

Power-Down

XXHXXXXHigh-ZHigh-Z7

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Part-Numbering Information

Micron CellularRAM devices are available in several

different configurations and densities (see Figure 3).

Figure 3: Part Number Chart

NOTE:

1. -30°C exceeds the CellularRAM Workgroup 1.0 specification of -25°C.

Valid Part Number Combinations

After building the part number from the part num-

bering chart above, please go to the Micron Part Mark-

ing Decoder Web site at http://www.micron.com/

partsearch to verify that the part number is offered and

valid. If the device required is not on this list, please

contact the factory.

Device Marking

Due to the size of the package, the Micron standard

part number is not printed on the top of the device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross-referenced to the Micron part

numbers at http://www.micron.com/partsearch. To

view the location of the abbreviated mark on the

device, please refer to customer service note, CSN-11,

“Product Mark/Label” at http://www.micron.com/

csn.

MT 45 W 2M W 16 BA FB -70 6 L WT ES

Micron Technology

Product Family

45 = PSRAM/CellularRAM Memory

Operating Core Voltage

W = 1.70V–1.95V

Address Locations

M = Megabits

Operating Voltage

W = 1.70V–3.30V

Bus Configuration

16 = x16

READ/WRITE Operation Mode

BA = Asynchronous/Page/Burst

Package Codes

FB = VFBGA (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball

BB = Lead-free VFBGA (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball (contact factory)

Production Status

Blank = Production

ES = Engineering Sample

MS = Mechanical Sample

Operating Temperature

WT = -30˚C to +85˚C (see Note 1)

IT = -40˚ to +85˚C (contact factory)

Standby Power Options

Blank = Standard

L = Low Power

Frequency

6 = 66 MHz

8 = 80 MHz

1 = 104 MHz (contact factory)

Access/Cycle Time

60 = 60ns (contact factory)

70 = 70ns

85 = 85ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Functional Description

In general, the MT45W2MW16BA device is a high-

density alternative to SRAM and Pseudo SRAM prod-

ucts, popular in low-power, portable applications.

The MT45W2MW16BA contains 33,554,432 bits

organized as 2,097,152 addresses by 16 bits. The device

implements the same high-speed bus interface found

on burst mode Flash products.

The CellularRAM bus interface supports both asyn-

chronous and burst mode transfers. Page mode

accesses are also included as a bandwidth-enhancing

extension to the asynchronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage

sensor used to launch the power-up initialization pro-

cess. Initialization will configure the BCR and the RCR

with their default settings (see Table 17 on page 18 and

Table 22 on page 22). VCC and VCCQ must be applied

simultaneously. When they reach a stable level at or

above 1.70V, the device will require 150µs to complete

its self-initialization process. During the initialization

period, CE# should remain HIGH. When initialization

is complete, the device is ready for normal operation.

Figure 4: Power-Up Initialization

Timing

Bus Operating Modes

The MT45W2MW16BA CellularRAM product incor-

porates a burst mode interface found on Flash prod-

ucts targeting low-power, wireless applications. This

bus interface supports asynchronous, page mode, and

burst mode read and write transfers. The specific

interface supported is defined by the value loaded into

the bus configuration register. Page mode is controlled

by the refresh configuration register (RCR[7]).

Asynchronous Mode

CellularRAM products power up in the asynchro-

nous operating mode. This mode uses the industry-

standard SRAM control bus (CE#, OE#, WE#, LB#/

UB#). READ operations (Figure 5) are initiated by

bringing CE#, OE#, and LB#/UB# LOW while keeping

WE# HIGH. Valid data will be driven out of the I/Os

after the specified access time has elapsed. WRITE

operations (Figure 6) occur when CE#, WE#, and LB#/

UB# are driven LOW. During asynchronous WRITE

operations, the OE# level is a “Don't Care,” and WE#

will override OE#. The data to be written is latched on

the rising edge of CE#, WE#, or LB#/UB# (whichever

occurs first). Asynchronous operations (page mode

disabled) can either use the ADV input to latch the

address, or ADV can be driven LOW during the entire

READ/WRITE operation.

During asynchronous operation, the CLK input must

be static (HIGH or LOW—no transition). WAIT will be

driven while the device is enabled and its state should

be ignored. WE# LOW time must be limited to tCEM.

Figure 5: READ Operation (ADV = LOW)

NOTE:

ADV must remain LOW for page mode operation.

Figure 6: WRITE Operation (ADV = LOW)

Vcc

VccQ Device Initialization

Vcc = 1.70V Device ready for

normal operation

tPU > 150µs

ADDRESS VALID

DATA

CE#

DON’T CARE

DATA VALID

OE#

WE#

LB#/UB#

tRC = READ Cycle Time

ADDRESS

ADDRESS VALID

DATA

CE#

DON’T CARE

DATA VALID

OE#

WE#

LB#/UB#

tWC = WRITE Cycle Time

ADDRESS

CEM

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Page Mode READ Operation

Page mode is a performance-enhancing extension

to the legacy asynchronous READ operation. In page-

mode-capable products, an initial asynchronous read

access is performed, then adjacent addresses can be

read quickly by simply changing the low-order

address. Addresses A[3:0] are used to determine the

members of the 16-address CellularRAM page. Any

change in addresses A[4] or higher will initiate a new

tAA access time. Figure 7 shows the timing for a page

mode access. Page mode takes advantage of the fact

that adjacent addresses can be read in a shorter period

of time than random addresses. WRITE operations do

not include comparable page mode functionality.

During asynchronous page mode operation, the

CLK input must be static (HIGH or LOW—no transi-

tions). CE# must be driven HIGH upon completion of a

page mode access. WAIT will be driven while the

device is enabled and its state should be ignored. Page

mode is enabled by setting RCR[7] to HIGH. ADV must

be driven LOW during all page mode read accesses.

The CE# LOW time is limited by refresh consider-

ations. CE# must not stay LOW longer than tCEM.

Figure 7: Page Mode READ Operation

(ADV = LOW)

Burst Mode Operation

Burst mode operations enable high-speed synchro-

nous READ and WRITE operations. Burst operations

consist of a multi-clock sequence that must be per-

formed in an ordered fashion. After CE# goes LOW, the

address to access is latched on the next rising edge of

CLK that ADV# is LOW. During this first clock rising

edge, WE# indicates whether the operation is going to

be a READ (WE# = HIGH, Figure 8 on page 11) or

WRITE (WE# = LOW, Figure 9 on page 11).

The size of a burst can be specified in the BCR as

either fixed-length or continuous. Fixed-length bursts

consist of four, eight, or sixteen words. Continuous

bursts have the ability to start at a specified address

and burst through the entire memory. The latency

count stored in the BCR defines the number of clock

cycles that elapse before the initial data value is trans-

ferred between the processor and CellularRAM device.

The WAIT output will be asserted as soon as CE#

goes LOW, and will be de-asserted to indicate when

data is to be transferred into (or out of ) the memory.

WAIT will again be asserted if the burst crosses the

boundary between 128-word rows. Once the Cellular-

RAM device has restored the previous row's data and

accessed the next row, WAIT will be de-asserted and

the burst can continue (see Figure 33 on page 39).

The processor can access other devices without

incurring the timing penalty of the initial latency for a

new burst by suspending burst mode. Bursts are sus-

pended by stopping CLK. CLK can be stopped HIGH or

LOW. If another device will use the data bus while the

burst is suspended, OE# should be taken HIGH to dis-

able the CellularRAM outputs; otherwise, OE# can

remain LOW. Note that the WAIT output will continue

to be active, and as a result no other devices should

directly share the WAIT connection to the controller.

To continue the burst sequence, OE# is taken LOW,

then CLK is restarted after valid data is available on the

bus.

The CE# LOW time is limited by refresh consider-

ations. CE# must not stay LOW longer than tCEM unless

row boundaries are crossed at least every tCEM. If a

burst suspension will cause CE# to remain LOW for

longer than tCEM, CE# should be taken HIGH and the

burst restarted with a new CE# LOW/ADV# LOW cycle.

DATA

CE#

DON’T CARE

OE#

WE#

LB#/UB#

ADDRESS

ADDRESS[0] ADDRESS

[1] ADDRESS

[2] ADDRESS

[3]

D[1] D[2] D[3]

tAA tAPA

< tCEM

tAPA tAPA

D[0]

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 8: Burst Mode READ (4-word burst)

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

Figure 9: Burst Mode WRITE (4-word burst)

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

A[20:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

Latency Code 2 (3 clocks)

CLK

UNDEFINEDDON’T CARE

READ Burst Identified

(WE# = HIGH)

ADDRESS

VALID

A[20:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

ADDRESS

VALID

Latency Code 2 (3 clocks)

CLK

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Mixed-Mode Operation

The device can support a combination of synchro-

nous READ and asynchronous WRITE operations

when the BCR is configured for synchronous opera-

tion. The asynchronous WRITE operation requires that

the clock (CLK) remain static (HIGH or LOW) during

the entire sequence. The ADV# signal can be used to

latch the target address, or it can remain LOW during

the entire WRITE operation. CE# must return HIGH

when transitioning between mixed-mode operations.

Note that the tCKA period is the same as a READ or

WRITE cycle. This time is required to ensure adequate

refresh. Mixed-mode operation facilitates a seamless

interface to legacy burst mode Flash memory control-

lers. See Figure 41 on page 47 for the “Asynchronous

WRITE Followed by Burst READ” timing diagram.

WAIT Operation

The WAIT output on a CellularRAM device is typi-

cally connected to a shared, system-level WAIT signal

(see Figure 10 below). The shared WAIT signal is used

by the processor to coordinate transactions with mul-

tiple memories on the synchronous bus.

Figure 10: Wired or WAIT

Configuration

Once a READ or WRITE operation has been initi-

ated, WAIT goes active to indicate that the Cellular-

RAM device requires additional time before data can

be transferred. For READ operations, WAIT will remain

active until valid data is output from the device. For

WRITE operations, WAIT will indicate to the memory

controller when data will be accepted into the Cellu-

larRAM device. When WAIT transitions to an inactive

state, the data burst will progress on successive clock

edges.

CE# must remain asserted during WAIT cycles

(WAIT asserted and WAIT configuration BCR[8] = 1).

Bringing CE# HIGH during WAIT cycles may cause

data corruption. (Note that for BCR[8] = 0, the actual

WAIT cycles end one cycle after WAIT de-asserts, and

for row boundary crossings, start one cycle after the

WAIT signal asserts.)

The WAIT output also performs an arbitration role

when a READ or WRITE operation is launched while

an on-chip refresh is in progress. If a collision occurs,

WAIT is asserted for additional clock cycles until the

refresh has completed (see Figures 11 and 12 on

page 13). When the refresh operation has completed,

the READ or WRITE operation will continue normally.

WAIT is also asserted when a continuous READ or

WRITE burst crosses a row boundary. The WAIT asser-

tion allows time for the new row to be accessed, and

permits any pending refresh operations to be per-

formed.

LB#/UB# Operation

The LB# enable and UB# enable signals support

byte-wide data transfers. During READ operations, the

enabled byte(s) are driven onto the DQs. The DQs

associated with a disabled byte are put into a High-Z

state during a READ operation. During WRITE opera-

tions, any disabled bytes will not be transferred to the

RAM array and the internal value will remain

unchanged. During an asynchronous WRITE cycle, the

data to be written is latched on the rising edge of CE#,

WE#, LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH)

during an operation, the device will disable the data

bus from receiving or transmitting data. Although the

device will seem to be deselected, it remains in an

active mode as long as CE# remains LOW.

CellularRAM

External

Pull-Up/

Pull-Down

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

2 MEG x 16

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Figure 11: Refresh Collision During READ Operation

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

Figure 12: Refresh Collision During WRITE Operation

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

A[20:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

D[2]D[1] D[3]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

UNDEFINED DON’T CARE

D[0]

High-Z

A[20:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

D[1]D[0] D[3]D[2]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

DON’T CARE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL High-Z

2 MEG x 16

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Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is

reduced to the level necessary to perform the DRAM

refresh operation. Standby operation occurs when CE#

is HIGH.

The device will enter a reduced power state upon

completion of a READ or WRITE operation, or when

the address and control inputs remain static for an

extended period of time. This mode will continue until

a change occurs to the address or control inputs.

Temperature Compensated Refresh

Temperature compensated refresh (TCR) allows for

adequate refresh at different temperatures. This

CellularRAM device includes an on-chip temperature

sensor. When the sensor is enabled, it continually

adjusts the refresh rate according to the operating

temperature. The on-chip sensor is enabled by default.

Three fixed refresh rates are also available, corre-

sponding to temperature thresholds of +15°C, +45°C,

and +85°C. The setting selected must be for a tempera-

ture higher than the case temperature of the Cellular-

RAM device. If the case temperature is +35°C, the

system can minimize self-refresh current consump-

tion by selecting the +45°C setting. The +15°C setting

would result in inadequate refreshing and cause data

corruption.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh opera-

tion to a portion of the total memory array. This fea-

ture enables the device to reduce standby current by

refreshing only that part of the memory array required

by the host system. The refresh options are full array,

one-half array, one-quarter array, one-eighth, or none

of the array. The mapping of these partitions can start

at either the beginning or the end of the address map

(see Table 6 on page 23). READ and WRITE operations

to address ranges receiving refresh will not be affected.

Data stored in addresses not receiving refresh will

become corrupted. When re-enabling additional por-

tions of the array, the new portions are available

immediately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled by rewriting the RCR, the CellularRAM

device will require 150µs to perform an initialization

procedure before normal operations can resume. Dur-

ing this 150µs period, the current consumption will be

higher than the specified standby levels, but consider-

ably lower than the active current specification.

DPD cannot be enabled or disabled by writing to

the RCR using the software access sequence; the RCR

should be accessed using CRE instead.

Configuration Registers

Two user-accessible configuration registers define

the device operation. The bus configuration register

(BCR) defines how the CellularRAM interacts with the

system memory bus and is nearly identical to its coun-

terpart on burst mode Flash devices. The refresh config-

uration register (RCR) is used to control how refresh is

performed on the DRAM array. These registers are

automatically loaded with default settings during

power-up, and can be updated any time the devices

are operating in a standby state.

Access Using CRE

The configuration registers are loaded using either a

synchronous or an asynchronous WRITE operation

when the configuration register enable (CRE) input is

HIGH (see Figures 13 and 14 on page 16). When CRE is

LOW, a READ or WRITE operation will access the

memory array. The register values are placed on

address pins A[20:0]. In an asynchronous WRITE, the

values are latched into the configuration register on

the rising edge of ADV#, CE#, or WE#, whichever

occurs first; LB# and UB# are “Don’t Care.” Access

using CRE is WRITE only. The BCR is accessed when

A[19] is HIGH; the RCR is accessed when A[19] is LOW.

2 MEG x 16

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Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ

ARRAY Operation

NOTE:

1. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

A[20:0]

(except A19)

CLK

OPCODE ADDRESS

ADDRESS

DATA VALID

A191

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate Control Register Access

Write Address Bus Value

to Control Register

CRE

tAVS tAVH

tAVH

tAVS

tVP

tVPH

tCPH

tWP

tCW

DON’T CARE

Select Control Register

2 MEG x 16

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Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ

ARRAY Operation

NOTE:

1. Non-default BCR settings for CR WRITE in synchronous mode followed by READ ARRAY operation: Latency code two

(three clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by

refresh collisions require a corresponding number of additional CE# LOW cycles.

CLK

A[20:0]

(except A19)

A192

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tCSP

tSP

tHD

High-Z

DON’T CARE

OPCODE ADDRESS

High-Z

tCW

Latch Control Register Value

Latch Control Register Address

tCBPH3

DATA

VALID

ADDRESS

2 MEG x 16

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Software Access

Software access of the configuration registers uses a

sequence of asynchronous READ and asynchronous

WRITE operations. The contents of the configuration

registers can be read or modified using the software

sequence.

The configuration registers are loaded using a four-

step sequence consisting of two asynchronous READ

operations followed by two asynchronous WRITE

operations (see Figure 15). The read sequence is virtu-

ally identical except that an asynchronous READ is

performed during the fourth operation (see Figure 16).

Note that a third READ cycle of the highest address will

cancel the access sequence until a different address is

read.

The address used during all READ and WRITE oper-

ations is the highest address of the CellularRAM device

being accessed (1FFFFFh for 32Mb); the content at this

address is changed by using this sequence (note that

this is a deviation from the CellularRAM specification).

The data value presented during the third operation

(WRITE) in the sequence defines whether the BCR or

the RCR is to be accessed. If the data is 0000h, the

sequence will access the RCR; if the data is 0001h, the

sequence will access the BCR. During the fourth oper-

ation, DQ[15:0] transfer data into or out of bits 15–0 of

the configuration registers.

The use of the software sequence does not affect the

ability to perform the standard (CRE-controlled)

method of loading the configuration registers. How-

ever, the software nature of this access mechanism

eliminates the need for the control register enable

(CRE) pin. If the software mechanism is used, the CRE

pin can simply be tied to VSS. The port line often used

for CRE control purposes is no longer required.

Software access of the RCR should not be used to

enter or exit DPD.

Figure 15: Load Configuration Register

NOTE:

1. WRITE on third cycle must be CE# controlled.

Figure 16: Read Configuration Register

NOTE:

1. WRITE on third cycle must be CE# controlled.

2. CE# must be HIGH for 150ns before performing the

cycle that reads a configuration register.

ADDRESS

(MAX)

ADDRESS

(MAX)

ADDRESS

(MAX)

XXXXh XXXXh

RCR: 0000h

BCR: 0001h

CR VALUE

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CARE

READ READ WRITE1 WRITE

ADDRESS

(MAX)

ADDRESS

(MAX) ADDRESS

(MAX)

XXXXh XXXXh CR VALUE

OUT

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CAR

READ READ WRITE1 READ

RCR: 0000h

BCR: 0001h

NOTE 2

ADDRESS

(MAX)

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Bus Configuration Register

The BCR defines how the CellularRAM device inter-

acts with the system memory bus. Page mode opera-

tion is enabled by a bit contained in the RCR. Figure 17

describes the control bits in the BCR. At power-up, the

BCR is set to 9D4Fh.

The BCR is accessed using CRE and A[19] HIGH, or

through the configuration register software sequence

with DQ = 0001h on the third cycle.

Figure 17: Bus Configuration Register Definition

NOTE:

1. All burst WRITEs are continuous.

A13

13 12 11 0

Latency

Counter

321

WAIT

Polarity

WAIT

Configuration (WC)

Clock

Configuration (CC)

Output

Impedance

Burst

Wrap (BW)*

A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Operation Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[12] BCR[11]

Latency Counter

BCR[13]

Code 0–Reserved

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4–Reserved

Code 5–Reserved

Code 6–Reserved

Code 7–Reserved

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

Output Impedance

Full Drive (default)

1/4 Drive

BCR[5]

Burst Wrap (Note 1)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

BCR[1] BCR[0] Burst Length (Note 1)

BCR[2]

Burst

Length (BL)*

Reserved

Operating

Mode

Reserved

A14A15

A[18:16]

Select RCR

Select BCR

Must be set to "0"

19 18–16

Select

Reserved

A19A[20]

Reserved

Must be set to "0"Must be set to "0"Must be set to "0"Must be set to "0"

All must be set to "0"

BCR[8]

Clock Configuration

Not supported

Rising edge (default)

BCR[6]

BCR[15]

BCR[19]

4 words

8 words

16 words

Continuous burst (default)

2 MEG x 16

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Burst Length (BCR[2:0])

Default = Continuous Burst

Burst lengths define the number of words the device

outputs during a burst READ operation. The device sup-

ports a burst length of 4, 8, or 16 words. The device can

also be set in continuous burst mode where data is out-

put sequentially without regard to address boundaries;

the internal address wraps to 000000h if the device is

read past the last address. WRITE bursts are always

performed using continuous burst mode.

Burst Wrap (BCR[3])

Default = Burst No Wrap (within burst length)

The burst wrap option determines if a 4-, 8-, or 16-

word burst READ wraps within the burst length, or

steps through sequential addresses. If the wrap option

is not enabled, the device outputs data from sequential

addresses without regard to burst boundaries; the

internal address wraps to 000000h if the device is read

past the last address.

Output Impedance (BCR[5])

Default = Outputs Use Full Drive Strength

The output driver strength can be altered to adjust

for different data bus loading scenarios. The reduced-

strength option should be more than adequate in

stacked chip (Flash + CellularRAM) environments when

there is a dedicated memory bus. The reduced-drive-

strength option is included to minimize noise gener-

ated on the data bus during READ operations. Normal

output impedance should be selected when using a

discrete CellularRAM device in a more heavily loaded

data bus environment. Partial drive is approximately

one-quarter full drive strength. Outputs are configured

at full drive strength during testing.

Table 4: Sequence and Burst Length

BURST WRAP STARTING

ADDRESS

4-WORD

BURST

LENGTH

8-WORD

BURST LENGTH

16-WORD BURST LENGTH CONTINUOUS BURST

BCR[3] WRAP (DECIMAL) LINEAR LINEAR LINEAR LINEAR

0Yes

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-…

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-…

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-…

4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-…

5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-…

6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-

7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-…

... ... ...

14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-..

15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21..

1No

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-…

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-…

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-…

4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-…

5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11…

6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12…

7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13…

... ... ...

14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-…

15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-…

2 MEG x 16

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WAIT Configuration (BCR[8])

Default = WAIT Transitions One Clock

Before Data Valid/Invalid

The WAIT configuration bit is used to determine

when WAIT transitions between the asserted and the

de-asserted state with respect to valid data presented

on the data bus. The memory controller will use the

WAIT signal to coordinate data transfer during synchro-

nous READ and WRITE operations. When BCR[8] = 0,

data will be valid or invalid on the clock edge immedi-

ately after WAIT transitions to the de-asserted or

asserted state, respectively (Figures 18 and 20). When

A8 = 1, the WAIT signal transitions one clock period

prior to the data bus going valid or invalid (Figures 19

and 20).

WAIT Polarity (BCR[10])

Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted

WAIT output should be HIGH or LOW. This bit will

determine whether the WAIT signal requires a pull-up

or pull-down resistor to maintain the de-asserted

state.

Figure 18: WAIT Configuration (BCR[8] = 0)

NOTE:

1. Data valid/invalid immediately after WAIT

transitions (BCR[8] = 0). See Figure 20.

Figure 19: WAIT Configuration (BCR[8] = 1)

NOTE:

1. Valid/invalid data delayed for one clock after WAIT

transitions (BCR[8] = 1). See Figure 20.

Figure 20: WAIT Configuration During Burst Operation

NOTE:

Non-default BCR setting for WAIT during burst operation: WAIT active LOW.

WAIT

DQ[15:0]

CLK

Data[0] Data[1]

Data immediatel

valid (or invalid)

High-Z

WAIT

D[15:0]

CLK

Data[0]

Data valid (or invalid) after one clock delay

High-Z

WAIT

DQ[15:0]

CLK

D[0] D[1]

BCR[8] = 0

Data valid in current cycle.

BCR[8] = 1

Data valid in next cycle.

DON’T CARE

D[2] D[3] D[4]

2 MEG x 16

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Latency Counter (BCR[13:11])

Default = Three-Clock Latency

The latency counter bits determine how many

clocks occur between the beginning of a READ or

WRITE operation and the first data value transferred.

Only latency code two (three clocks) or latency code

three (four clocks) is allowed (see Table 5 and

Figure 21 below).

Operating Mode (BCR[15])

Default = Asynchronous Operation

The operating mode bit selects either synchronous

burst operation or the default asynchronous mode of

operation.

NOTE:

1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met.

Figure 21: Latency Counter

Table 5: Latency Configuration

LATENCY CONFIGURATION CODE

MAX INPUT CLK FREQUENCY (MHz)

-701 -708 -706/-856

2 (3 clocks) 66 (15.2ns) 53 (18.75ns) 441 (22.7ns)

3 (4 clocks) – default 104 (9.62ns) 80 (12.5ns) 66 (15.2ns)

A[20:0]

ADV#

DQ[15:0]

CLK

Code 2

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Code 3 (Default)

DQ[15:0]

DON’T CARE UNDEFINED

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VALID

ADDRESS

2 MEG x 16

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Refresh Configuration Register

The refresh configuration register (RCR) defines

how the CellularRAM device performs its transparent

self refresh. Altering the refresh parameters can dra-

matically reduce current consumption during standby

mode. Page mode control is also embedded into the

RCR. Figure 22 below describes the control bits used in

the RCR. At power-up, the RCR is set to 0010h.

The RCR is accessed using CRE and A[19] LOW; or

through the configuration register software access

sequence with DQ = 0000h on the third cycle (see

“Configuration Registers” on page 14.)

Partial Array Refresh (RCR[2:0])

Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion

of the total memory array. This feature allows the

device to reduce standby current by refreshing only

that part of the memory array required by the host sys-

tem. The refresh options are full array, one-half array,

one-quarter array, one-eighth array, or none of the

array. The mapping of these partitions can start at

either the beginning or the end of the address map

(see Table 6 on page 23.

Figure 22: Refresh Configuration Register Mapping

PAR

A4 A3 A2 A1 A0

Read Configuration

Address Bus

45 1

RESERVED RESERVED

Deep Power-Down

DPD Enable

DPD Disable (default)

RCR[4]

TCR

RCR[6] RCR[5]

Maximum Case Temp.

+85˚C

Internal sensor (default)

+45˚C

+15˚C

All must be set to "0"

A[18:8]

18–8

Select

RESERVED

A20 A19

Select RCR

Select BCR

RCR[19]

All must be set to "0"

RCR[1]

RCR[0]

Refresh Coverage

Full array (default)

Bottom 1/2 array

Bottom 1/4 array

Bottom 1/8 array

RCR[2]

None of array

Top 1/2 array

Top 1/4 array

Top 1/8 array

DPD

Must be set to "0"

PAGE

Page Mode Enable/Disable

Page Mode Disabled (default)

Page Mode Enable

RCR[7]

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Deep Power-Down (RCR[4])

Default = DPD Disabled

The deep power-down bit enables and disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal

operations can resume.

Deep power-down is enabled when RCR[4] = 0, and

remains enabled until RCR[4] is set to “1.” DPD should

not be enabled or disabled with the software access

sequence; instead, use CRE to access the RCR.

Temperature Compensated Refresh (RCR[6:5])

Default = On-Chip Temperature Sensor

This CellularRAM device includes an on-chip tem-

perature sensor that automatically adjusts the refresh

rate according to the operating temperature. The on-

chip TCR is enabled by clearing both of the TCR bits in

the refresh configuration register (RCR[6:5] = 00b). Any

other TCR setting enables a fixed refresh rate. When

the on-chip temperature sensor is enabled, the device

continually adjusts the refresh rate according to the

operating temperature.

The TCR bits also allow for adequate fixed-rate

refresh at three different temperature thresholds

(+15°C, +45°C, and +85°C). The setting selected must

be for a temperature higher than the case tempera-

ture of the CellularRAM device. If the case tempera-

ture is +35°C, the system can minimize self refresh

current consumption by selecting the +45°C setting.

The +15°C setting would result in inadequate

refreshing and cause data corruption.

Page Mode Operation (RCR[7])

Default = Disabled

The page mode operation bit determines whether

page mode is enabled for asynchronous READ opera-

tions. In the power-up default state, page mode is dis-

abled.

Table 6: 32Mb Address Patterns for PAR (RCR[4] = 1)

RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY

0 0 0 Full die 000000h–1FFFFFh 2 Meg x 16 32Mb

0 0 1 One-half of die 000000h–0FFFFFh 1 Meg x 16 16Mb

0 1 0 One-quarter of die 000000h–07FFFFh 512K x 16 8Mb

0 1 1 One-eighth of die 000000h–03FFFFh 256K x 16 4Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 One-half of die 100000h–1FFFFFh 1 Meg x 16 16Mb

1 1 0 One-quarter of die 180000h–1FFFFFh 512K x 16 8Mb

1 1 1 One-eighth of die 1C0000h–1FFFFFh 256K x 16 4Mb

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Absolute Maximum Ratings

Voltage to Any Ball Except VCC, VCCQ Relative to VSS . .

0.50V to (4.0V or VCCQ + 0.3V, whichever is less)

Voltage on VCC Supply Relative to VSS. . -0.2V to +2.45V

Voltage on VCCQ Supply Relative to VSS . -0.2V to +4.0V

Storage Temperature (plastic). . . . . . . . -55ºC to +150ºC

Operating Temperature (case)

Wireless (see Note 1) . . . . . . . . . . . . . . -30ºC to +85ºC

Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40ºC to +85ºC

Soldering Temperature and Time

10s (solder ball only) . . . . . . . . . . . . . . . . . . . . . +260ºC

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

NOTE:

1. -30°C exceeds the CellularRAM Workgroup 1.0 specifi-

cation of -25°C.

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. -30°C exceeds the CellularRAM Workgroup 1.0 specification of -25°C.

2. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions.

3. VIH (MIN) value is not aligned with CellularRAM Workgroup 1.0 specification of VCCQ - 0.4V.

4. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions.

5. BCR[5:4] = 00b.

6. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current

required to drive output capacitance expected in the actual system.

7. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. In order to achieve low standby current,

all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or after

changes to the PAR array partition.

Table 7: Electrical Characteristics and Operating Conditions

Wireless Temperature1 (-30ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Supply Voltage VCC 1.70 1.95 V

I/O Supply Voltage VCCQ W: 1.8V 1.70 3.30 V

Input High Voltage VIH 1.40 VCCQ + 0.2 V 2, 3

Input Low Voltage VIL -0.20 0.4 V 4

Output High Voltage IOH = -0.2mA VOH 0.80 VCCQV5

Output Low Voltage IOL = +0.2mA VOL 0.20 VCCQV 5

Input Leakage Current VIN = 0 to VCCQILI 1µA

Output Leakage Current OE# = VIH or

Chip Disabled

ILO 1µA

Operating Current

Asynchronous Random READ/

WRITE

VIN = VCCQ or 0V

Chip Enabled,

IOUT = 0

ICC1-70 20mA6

-85 17

Asynchronous Page READ ICC1P -70 15 mA 6

-85 12

Initial Access, Burst READ/WRITE ICC2 104 MHz 35 mA 6

80 MHz 35

66 MHz 30

Continuous Burst READ ICC3R 104 MHz 20 mA 6

80 MHz 18

66 MHz 15

Continuous Burst WRITE ICC3W 104 MHz 35 mA 6

80 MHz 35

66 MHz 30

Standby Current VIN = VCCQ or 0V

CE# = VCCQ

ISB Standard 110 µA 7

Low-Power (L) 90

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

ITCR (MAX) values measured with PAR set to FULL ARRAY. MAX values apply across the full temperature range.

NOTE:

IPAR (MAX) values measured with TCR set to 85°C. IPAR might be slightly higher for up to 500ms after changes to the PAR

array partition.

Table 8: Temperature Compensated Refresh Specifications and Conditions

DESCRIPTION CONDITIONS SYMBOL POWER TCR SETTING (RCR[6:5]) MAX UNITS

Temperature

Compensated

Refresh Standby

Current

VIN = VCCQ or 0V

CE# = VCCQ

ITCR Standard

Power

(no desig.)

+85°C 110 µA

+45°C 80

+15°C 70

Low-Power

Option (L)

+85°C 90 µA

+45°C 60

+15°C 55

Table 9: Partial Array Refresh Specifications and Conditions

DESCRIPTION CONDITIONS SYMBOL POWER ARRAY PARTITION MAX UNITS

Partial Array

Refresh Standby

Current

VIN = VCCQ or 0V,

CE# = VCCQ

IPAR Standard

Power

(no desig.)

Full 110 µA

1/2 105

1/4 95

1/8 95

070

Low-Power

Option (L)

Full 90 µA

1/2 85

1/4 75

1/8 75

065

Table 10: Deep Power-Down Specifications

DESCRIPTION CONDITIONS SYMBOL TYP UNITS

Deep Power-Down VIN = VCCQ or 0V; +25°C IZZ 10 µA

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. These parameters are verified in device characterization and are not 100% tested.

Figure 23: AC Input/Output Reference Waveform

NOTE:

1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.

2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not

be shown to scale.

3. Output timing ends at VCCQ/2.

Figure 24: Output Load Circuit

NOTE:

All tests are performed with the outputs configured for

full drive strength (BCR[5] = 0).

Table 11: Capacitance

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input Capacitance TC = +25ºC; f = 1 MHz;

VIN = 0V

CIN 2.0 6.5 pF 1

Input/Output Capacitance (DQ) CIO 3.0 6.5 pF 1

Output

Test Points

Input

VCCQ

VSS

VCCQ/2

VCC/2

DUT

VccQ

R230pF

Test Point

Table 12: Output Load Circuit

VCCQR1/R2

1.8V 2.7K Ω

2.5V 3.7K Ω

3.0V 4.5K Ω

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 24 on page 27. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 24 on page 27. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

4. Page mode enabled only.

Table 13: Asynchronous READ Cycle Timing Requirements

PARAMETER1SYMBOL

-70x -856

UNITS NOTESMIN MAX MIN MAX

Address Access Time tAA 70 85 ns

ADV# Access Time tAADV 70 85 ns

Page Access Time tAPA 20 25 ns

Address Hold from ADV# HIGH tAVH 55ns

Address Setup to ADV# HIGH tAVS 10 10 ns

LB#/UB# Access Time tBA 70 85 ns

LB#/UB# Disable to DQ High-Z Output tBHZ 88ns4

LB#/UB# Enable to Low-Z Output tBLZ 10 10 ns 3

Maximum CE# Pulse Width tCEM 88µs2

CE# LOW to WAIT Valid tCEW 17.517.5ns

Chip Select Access Time tCO 70 85 ns

CE# LOW to ADV# HIGH tCVS 10 10 ns

Chip Disable to DQ and WAIT High-Z Output tHZ 88ns4

Chip Enable to Low-Z Output tLZ 10 10 ns 3

Output Enable to Valid Output tOE 20 20 ns

Output Hold from Address Change tOH 55ns

Output Disable to DQ High-Z Output tOHZ 88ns4

Output Enable to Low-Z Output tOLZ 55ns3

Page Cycle Time tPC 20 25 ns

READ Cycle Time tRC 70 85 ns

ADV# Pulse Width LOW tVP 10 10 ns

ADV# Pulse Width HIGH tVPH 10 10 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh

opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than

15ns.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

4. Low-Z to High-Z timings are tested with the circuit shown in Figure 24 on page 27. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

5. High-Z to Low-Z timings are tested with the circuit shown in Figure 24 on page 27. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

Table 14: Burst READ Cycle Timing Requirements

PARAMETER1SYMBOL

-701 -708 -706/-856

UNITS NOTESMIN MAX MIN MAX MIN MAX

Burst to READ Access Time tABA 35 46.5 56 ns

CLK to Output Delay tACLK 7911ns

Burst OE# LOW to Output Delay tBOE 20 20 20 ns

CE# HIGH between Subsequent Burst

and Mixed-Mode Operations

tCBPH 5 5 5 ns 2

Maximum CE# Pulse Width tCEM 888µs

CE# LOW to WAIT Valid tCEW 17.517.517.5ns

CLK Period tCLK 9.62 20 12.5 20 15 20 ns 3

CE# Setup Time to Active CLK Edge tCSP 4 20 4.5 20 5 20 ns

Hold Time from Active CLK Edge tHD 222ns

Chip Disable to DQ and WAIT High-Z

Output

tHZ 8 8 8 ns 4

CLK Rise or Fall Time tKHKL 1.6 1.8 2.0 ns

CLK to WAIT Valid tKHTL 7911ns

CLK to DQ High-Z Output tKHZ 383838ns4

CLK to Low-Z Output tKLZ 252525ns5

Output HOLD from CLK tKOH 2 2 2 ns

CLK HIGH or LOW Time tKP 3 4 5 ns

Output Disable to DQ High-Z Output tOHZ 8 8 8 ns 4

Output Enable to Low-Z Output tOLZ 5 5 5 ns 5

Setup Time to Active CLK Edge tSP 3 3 3 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. High-Z to Low-Z timings are tested with the circuit shown in Figure 24 on page 27. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 24 on page 27. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

3. WE# LOW time must be limited to tCEM (8µs).

Table 15: Asynchronous WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-70x -856

UNITS NOTESMIN MAX MIN MAX

Address and ADV# LOW Setup Time tAS 00ns

Address Hold from ADV# Going HIGH tAVH 55ns

Address Setup to ADV# Going HIGH tAVS 10 10 ns

Address Valid to End of WRITE tAW 70 85 ns

LB#/UB# Select to End of WRITE tBW 70 85 ns

CE# LOW to WAIT Valid tCEW 17.517.5ns

Async Address-to-Burst Transition Time tCKA 70 85 ns

CE# HIGH between Subsequent Asynchronous Operations tCPH 55ns

CE# LOW to ADV# HIGH tCVS 10 10 ns

Chip Enable to End of WRITE tCW 70 85 ns

Data Hold from WRITE Time tDH 00ns

Data WRITE Setup Time tDW 23 23 ns

Chip Disable to WAIT High-Z Output tHZ 88ns

Chip Enable to Low-Z Output tLZ 10 10 ns 1

End WRITE to Low-Z Output tOW 55ns 1

ADV# Pulse Width tVP 10 10 ns

ADV# Pulse Width HIGH tVPH 10 10 ns

ADV# Setup to End of WRITE tVS 70 85 ns

WRITE Cycle Time tWC 70 85 ns

WRITE to DQ High-Z Output tWHZ 88ns 2

WRITE Pulse Width tWP 46 55 ns 3

WRITE Pulse Width HIGH tWPH 10 10 ns

WRITE Recovery Time tWR 00ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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NOTE:

1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh

opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than

15ns.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

Figure 25: Initialization Period

Table 16: Burst WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-701 -708 -706/-856

UNITS NOTESMIN MAX MIN MAX MIN MAX

CE# HIGH between Subsequent Burst

and Mixed-Mode Operations

tCBPH 5 5 5 ns 1

Minimum CE# Pulse Width tCEM 888µs1

CE# LOW to WAIT Valid tCEW 17.517.517.5ns

Clock Period tCLK 9.62 20 12.5 20 15 20 ns 2

CE# Setup to CLK Active Edge tCSP 4 20 4.5 20 5 20 ns

Hold Time from Active CLK Edge tHD 222ns

Chip Disable to WAIT High-Z Output tHZ 888ns

CLK Rise or Fall Time tKHKL 1.6 1.8 2.0 ns

Clock to WAIT Valid tKHTL 7911ns

CLK HIGH or LOW Time tKP 345ns

Setup Time to Activate CLK Edge tSP 3 3 3 ns

tPU

Vcc, VccQ = 1.70V

Vcc (MIN)

Device ready for

normal operation

Table 17: Initialization Timing Parameters

PARAMETER SYMBOL

-70x -856

UNITS NOTEMIN MAX MIN MAX

Initialization Period (required before normal operations) tPU 150 150 µs

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 26: Asynchronous READ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tRC

tCO

tBHZ

tOHZ

tOE

tCEW tHZ

VALID OUTPUT

High-Z

UNDEFINED

DON’T CARE

tBLZ

tLZ

tOLZ

Table 18: Asynchronous READ Timing Parameters

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tHZ 88ns

tBA 70 85 ns

tLZ 10 10 ns

tBHZ 8 8 ns

tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 8 8 ns

tCEW 1 7.5 1 7.5 ns tOLZ 5 5 ns

tCO 70 85 ns

tRC 70 85 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 27: Asynchronous READ Using ADV#

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tVPH

tAADV

tAA

tVP

tHZ

tBA

High-Z High-Z

tCVS

tCO

tBLZ

tBHZ

tOHZ

tLZ

tOE

tOLZ

VALID OUTPUT

tAVH

tAVS

High-Z

UNDEFINED

DON’T CARE

tCEW tHZ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

Table 19: Asynchronous READ Timing Parameters Using ADV#

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns tCVS 10 10 ns

tAADV 70 85 ns

tHZ 88ns

tAVH 5 5 ns

tLZ 10 10 ns

tAVS 10 10 ns

tOE 20 20 ns

tBA 70 85 ns

tOHZ 8 8 ns

tBHZ 8 8 ns

tOLZ 5 5 ns

tBLZ 10 10 ns

tVP 10 10 ns

tCEW 1 7.5 1 7.5 ns tVPH 10 10 ns

tCO 70 85 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 28: Page Mode READ

A[3:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tCO

tCEM

tBLZ

tBHZ

tOHZ

tLZ

tOE

tOLZ

tCEW tHZ

High-Z

UNDEFINED

DON’T CARE

A[20:4] VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

tRC

VALID

OUTPUT

tAPA

tPC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

tOH

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Table 20: Asynchronous READ Timing Parameters—Page Mode Operation

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tHZ 8 8 ns

tAPA 20 25 ns tLZ 10 10 ns

tBA 70 85 ns

tOE 20 20 ns

tBHZ 8 8 ns

tOH 5 5 ns

tBLZ 10 10 ns

tOHZ 8 8 ns

tCEM 88µs

tOLZ 5 5 ns

tCEW 1 7.5 1 7.5 ns tPC 20 25 ns

tCO 70 85 ns

tRC 70 85 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 29: Single-Access Burst READ Operation

NOTE:

1. Non-default BCR settings for single-access burst READ operation: Latency code two (three clocks); WAIT active LOW;

WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[20:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tSP

tCLK

tACLK

tCEW

tHD

tABA

VALID

OUTPUT

VALID

ADDRESS

High-Z

tKOH

tOHZ

tSP tHD

LB#/UB#

VIH

VIL

tCSP

tCEM

High-Z

OLZ

High-Z

tHD

tSP

tHZ

tKP tKP tKHKL

tHD

tSP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tKHTL

tBOE

Table 21: Burst READ Timing Parameters—Single Access

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHZ 8 8 8 ns

tACLK 79 11ns tKHKL 1.6 1.8 2.0 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCEM 888µs

tKOH 2 2 2 ns

tCEW 1 7.5 1 7.5 1 7.5 ns tKP 345 ns

tCLK 9.62 20 12.5 20 15 20 ns tOHZ 8 8 8 ns

tCSP 4204.520 5 20 ns tOLZ 5 5 5 ns

tHD 22 2 ns

tSP 3 3 3 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 30: 4-Word Burst READ Operation

NOTE:

1. Non-default BCR settings for 4-word burst READ operation: Latency code two (three clocks); WAIT active LOW; WAIT

asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP

tCLK

tKHKL

tHD

tABA

VALID

ADDRESS

High-Z

tKOH

tHZ

tHD

tSP tHD

LB#/UB# VIH

VIL

High-Z

tOLZ

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

tKP tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

tBOE

High-Z

Table 22: Burst READ Timing Parameters—4-Word Burst

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHZ 8 8 8 ns

tACLK 7911ns

tKHKL 1.6 1.8 2.0 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCBPH 5 5 5 ns

tKOH 2 2 2 ns

tCEM 888µs

tKP 345 ns

tCEW 17.517.517.5 ns tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tOLZ 5 5 5 ns

tCSP 4204.520520 ns tSP 3 3 3 ns

tHD 222 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 31: 4-Word Burst READ Operation (with LB#/UB#)

NOTE:

1. Non-default BCR settings for 4-word burst READ operation with LB#/UB#: Latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as specifications are met. BCR configured with a burst length of

four.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP

tCLK

tHD

tABA

High-Z

tKOH tKHZ tKHZ

tKLZ

tHZ

tHD

tSP tHD

LB#/UB# VIH

VIL

High-Z

tOLZ

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

High-Z

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

tBOE

VALID

ADDRESS

High-Z

Table 23: Burst READ Timing Parameters—4-Word Burst with LB#/UB#

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHZ 8 8 8 ns

tACLK 7911ns

tKHTL 7911ns

tBOE 20 20 20 ns tKHZ 383838 ns

tCBPH 5 5 5 ns

tKLZ 252525 ns

tCEM 888µs

tKOH 2 2 2 ns

tCEW 17.517.517.5ns tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tOLZ 5 5 5 ns

tCSP 4204.520520ns tSP 3 3 3 ns

tHD 222ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 32: READ Burst Suspend

NOTE:

1. Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT active LOW; WAIT asserted

during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP tHD

High-Z

tOLZ

tACLK

LB#/UB# VIH

VIL

tCLK

tSP tHD

tCSP

tCEM

tSP tHD

tKOH

VALID

OUTPUT VALID

OUTPUT

UNDEFINED

DON’T CARE

VALID

ADDRESS

High-Z

CBPH

tOHZ

VALID

OUTPUT VALID

OUTPUT

tBOE

OHZ

tBOE

tOLZ

VALID

ADDRESS

High-Z

Table 24: Burst READ Timing Parameters—Burst Suspend

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tHZ 8 8 8 ns

tCBPH 5 5 5 ns

tKOH 222ns

tCEM 888µs

tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tOLZ 5 5 5 ns

tCSP 4204.520520ns tSP 3 3 3 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 33: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for

End-of-Row Condition

NOTE:

1. Non-default BCR settings for continuous burst READ showing an output delay, BCR[8] = 0 for end-of-row condition:

Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

3. WAIT will be asserted a maximum of (2 x LC) cycles (BCR[8] = 0; WAIT asserted during delay). LC = Latency Code

(BCR[13:11]).

4. CE# must not remain LOW longer than tCEM.

tACLK tKOH

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tKHTL tKHTL

tCLK

LB#/UB# VIH

VIL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DON’T CARE

VALID

OUTPUT

NOTE 3

NOTE 4

Table 25: Burst READ Timing Parameters—BCR[8] = 0

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tKHTL 7911ns

tCLK 9.62 20 12.5 20 15 20 ns tKOH 2 2 2 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 34: CE#-Controlled Asynchronous WRITE

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

High-Z High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

DQ[15:0]

OUT

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

High-Z

tCPH

Table 26: Asynchronous WRITE Timing Parameters—CE#-Controlled

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns tLZ 10 10 ns

tBW 70 85 ns tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 88ns

tCPH 55ns

tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 00ns

tDW 23 23 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 35: LB#/UB#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

High-Z

Table 27: Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns

tLZ 10 10 ns

tBW 70 85 ns

tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 8 8 ns

tCW 70 85 ns

tWP 46 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 23 23 ns

tWR 0 0 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 36: WE#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tCW

tLZ

tWP

tDH

tOW

tAS

tWPH

High-Z

Table 28: Asynchronous WRITE Timing Parameters—WE#-Controlled

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tLZ 10 10 ns

tAW 70 85 ns

tOW 55ns

tBW 70 85 ns

tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 8 8 ns

tCW 70 85 ns

tWP 46 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 23 23 ns

tWR 0 0 ns

tHZ 88ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 37: Asynchronous WRITE Using ADV#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[20:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

High-Z High-Z

tCEW tHZ

VALID INPUT

tVS

DON’T CARE

tCW

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tLZ

tWP

tDH

tOW

tAS

tWPH

tAS

tVPH

tAVH

tAVS

tVP

tAW

High-Z

Table 29: Asynchronous WRITE Timing Parameters Using ADV#

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAVH 5 5 ns

tLZ 10 10 ns

tAVS 10 10 ns

tOW 55ns

tAW 70 85 ns

tVP 10 10 ns

tBW 70 85 ns

tVPH 10 10 ns

tCEW 1 7.5 1 7.5 ns tVS 70 85 ns

tCW 70 85 ns

tWHZ 8 8 ns

tDH 0 0 ns

tWP 46 55 ns

tDW 23 23 ns

tWPH 10 10 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 38: Burst WRITE Operation

NOTE:

1. Non-default BCR settings for burst WRITE operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted

during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK tKP

tSP tHD

tCSP

tCEM

D[3]D[2]D[1]D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

tCBPH

tKHTL tHZ

tCEW

tKP tKHKL

Table 30: Burst WRITE Timing Parameters

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856 UNIT

SMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCBPH 5 5 5 ns

tHZ 888ns

tCEM 888µs

tKHKL 1.6 1.8 2.0 ns

tCEW 17.517.517.5ns tKHTL 7911ns

tCLK 9.62 20 12.5 20 15 20 ns tKP 3 4 5 ns

tCSP 4204.520520ns tSP 3 3 3 ns

tHD 222ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 39: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for

End-of-Row Condition

NOTE:

1. Non-default BCR settings for continuous burst WRITE showing an output delay, BCR[8] = 0 for end-of-row condition:

Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

3. WAIT will be asserted a maximum of (2 x LC) + 1 cycles (BCR[8] = 0; WAIT asserted during delay). LC = Latency Code

(BCR[13:11]).

4. CE# must not remain LOW longer than tCEM.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKHTL tKHTL

tCLK

tSP tHD

VALID

INPUT D[n] VALID

INPUT D[n+2]

END OF ROW

NOTE 3

NOTE 4

VALID

INPUT D[n+1] VALID

INPUT D[n+3]

DON’T CARE

VIH

VIL

LB#/UB#

Table 31: Burst WRITE Timing Parameters—BCR[8] = 0

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCLK 9.62 20 12.5 20 15 20 ns tKHTL 7911ns

tHD 222ns

tSP 3 3 3 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 40: Burst WRITE Followed by Burst READ

NOTE:

1. Non-default BCR settings for burst WRITE followed by burst READ: Latency code two (three clocks); WAIT active LOW;

WAIT asserted during delay.

2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh

opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than

15ns. Note that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[20:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tSP tHD

tCSP

D[3]D[2]D[1]

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tSP tHD

VALID

ADDRESS

tABA

tCSP tOHZ

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

High-Z VOH

VOL

LB#/UB# VIH

VIL

tHD

tSP tHD

tHD

High-Z

UNDEFINED

DON’T CARE

tBOE

tCBPH

High-Z

tSP tHD

Table 32: WRITE Timing Parameters—Burst WRITE Followed by Burst READ

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCBPH 5 5 5 ns

tHD 222ns

tCLK 9.62 20 12.5 20 15 20 ns tSP 3 3 3 ns

tCSP 4204.520520ns

Table 33: READ Timing Parameters—Burst WRITE Followed by Burst READ

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHD 222ns

tACLK 7911ns

tKOH 2 2 2 ns

tBOE 20 20 20 ns tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tSP 333ns

tCSP 4204.520520ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 41: Asynchronous WRITE Followed by Burst READ

NOTE:

1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks); WAIT active LOW;

WAIT asserted during delay.

2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is

satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that Cellular-

RAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

tCLK

tSP tHD

VALID

ADDRESS

tOHZ

tKOH

tACLK

High-Z

VALID ADDRESS VALID ADDRESS

tAVS tAVH tAW tWR

tVP tVS

tCKA

A[20:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL

tCW

tWPH

tAS

tWP

tWC

tDH tDW

DATA DATA

High-Z

tCVS tHD

tSP

tCEW

tSP tHD

tCSP

tWC

tBW

tWHZ

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

DON’T CARE UNDEFINED

tABA

tBOE

tCBPH2

tVPH

Table 34: WRITE Timing Parameters—Async WRITE Followed by Burst READ

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 20 23 ns

tAVH 55ns

tVP 10 10 ns

tAVS 10 10 ns tVPH 10 10 ns

tAW 70 85 ns tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCKA 70 85 ns tWHZ 88 ns

tCVS 10 10 ns

tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

Table 35: READ Timing Parameters—Async WRITE Followed by Burst READ

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tCSP 4204.520520 ns

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCBPH 5 5 5 ns

tOHZ 888 ns

tCEW 17.517.517.5 ns tSP 3 3 3 ns

tCLK 9.62 20 12.5 20 15 20 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 42: Asynchronous WRITE Followed By Burst READ—ADV# LOW

NOTE:

1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay.

2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh

opportunity is satisfied by either of these conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note

that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

VALID ADDRESS VALID ADDRESS

A[20:0] VIH

VIL

ADV#

VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

tHZ

DATA

tHZ

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH1tCO

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tWHZ

DON’T CARE UNDEFINED

DATA

Table 36: Asynchronous WRITE Timing Parameters—ADV# LOW

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAW 70 85 ns tWC 70 85 ns

tBW 70 85 ns tWHZ 88 ns

tCKA 70 85 ns tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 0 0 ns

tDW 23 23 ns

Table 37: Burst READ Timing Parameters

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tCSP 4204.520520 ns

tACLK 7911ns

tHD 222 ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCBPH 5 5 5 ns

tOHZ 888 ns

tCEW 17.517.517.5 ns tSP 333 ns

tCLK 9.62 20 12.5 20 15 20 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 43: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportu-

nity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that

CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

A[20:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

ACLK

CEW

ABA

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

CSP

High-Z

OLZ

WPH

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

VALID

ADDRESS

VALID

INPUT

High-Z

CEW

CBPH

Table 38: Burst READ Timing Parameters

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHD 222 ns

tACLK 79 11ns tHZ 8 8 8 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCBPH 555 ns

tKOH 2 2 2 ns

tCEW 17.517.517.5 ns tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tSP 333 ns

tCSP 4204.520520 ns

Table 39: Asynchronous WRITE Timing Parameters—WE# Controlled

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns tWC 70 85 ns

tBW 70 85 ns tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 0 0 ns

tDW 23 23 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 44: Burst READ Followed by Asynchronous WRITE Using ADV#

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is sat-

isfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM

Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

A[20:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

tSP

tCLK

tCEW

tHD

tABA

tVPH tVS

tAVS tAVH

tAW

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

tKOH tDW

tOHZ

tSP tHD tVP

LB#/UB#

tCSP

High-Z

OLZ

tHD

WPH

tHD tBW

tSP

tHZ

tHD

tSP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tKHTL

VALID

ADDRESS

VALID

INPUT

High-Z

tCEW tHZ

tCBPH

tACLK

tBOE

tAS

Table 40: Burst READ Timing Parameters

SYMBOL

-701 -708 -706/-856

UNITS SYMBOL

-701 -708 -706/-856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46.5 56 ns tHD 222ns

tACLK 79 11ns tHZ 8 8 8 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCBPH 555ns

tKOH 222ns

tCEW 17.517.517.5ns tOHZ 8 8 8 ns

tCLK 9.62 20 12.5 20 15 20 ns tSP 333ns

tCSP 4204.520520ns

Table 41: Asynchronous WRITE Timing Parameters Using ADV#

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 23 23 ns

tAVH 5 5 ns

tHZ 88ns

tAVS 10 10 ns

tVP 10 10 ns

tAW 70 85 ns

tVPH 10 10 ns

tBW 70 85 ns

tVS 70 85 ns

tCEW 1 7.5 1 7.5 ns tWP 46 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 0 0 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 45: Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the

appropriate internal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITES.

VALID ADDRESS VALID ADDRESS

A[20:0] VIH

VIL

ADV#

VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

tHZ

DATA

tHZ

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH1tCO

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tWHZ

DON’T CARE UNDEFINED

DATA

Table 42: WRITE Timing Parameters—ADV# LOW

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAW 70 85 ns

tHZ 88ns

tBW 70 85 ns tWC 70 85 ns

tCPH 5 5 ns

tWHZ 88 ns

tCW 70 85 ns

tWP 46 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 23 23 ns

tWR 0 0 ns

Table 43: READ Timing Parameters—ADV# LOW

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tBHZ 88 ns tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 88 ns

tCO 70 85 ns tOLZ 5 5 ns

tHZ 88 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 46: Asynchronous WRITE Followed by Asynchronous READ

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate inter-

nal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITES.

VALID ADDRESS VALID ADDRESS

tAVS tAVH

tVPH tVP tVS

A[20:0] VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADV#

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB#

tVP

tAVH

tCW

tWPH

tAS tWP

tWC

tDH tDW

DATA DATA

High-Z

VALID ADDRESS

tAA

tBHZ

tAADV

tCPH1tCO

VALID

OUTPUT

High-Z

tCVS

tOLZ

tLZ

tAS

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tWHZ

UNDEFINED

DON’T CARE

tOE

tAVS

tCVS

Table 44: WRITE Timing Parameters—Async WRITE Followed by Async READ

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 23 23 ns

tAVH 55ns

tVP 10 10 ns

tAVS 10 10 ns tVPH 10 10 ns

tAW 70 85 ns

tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCPH 5 5 ns

tWHZ 88ns

tCVS 10 10 ns tWP 46 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 00ns

tWR 00ns

Table 45: READ Timing Parameters—Async WRITE Followed by Async READ

SYMBOL

-70x -856

UNITS SYMBOL

-70x -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tCVS 10 10 ns

tAADV 70 85 ns tHZ 88 ns

tAVH 55ns

tLZ 10 10 ns

tAVS 10 10 ns tOE 20 20 ns

tBHZ 88 ns tOHZ 88 ns

tBLZ 10 10 ns

tOLZ 5 5 ns

tCO 70 85 ns tVP 10 10 ns

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc. inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

Figure 47: 54-Ball VFBGA

NOTE:

1. All dimensions in millimeters; MAX/MIN, or typical, as noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

Data Sheet Designation

Released (No Marking): This data sheet contains

minimum and maximum limits specified over the

complete power supply and temperature range for

production devices. Although considered final, these

specifications are subject to change, as further product

development and data characterization sometimes

occur.

BALL A1 ID

0.70 ±0.05

SEATING PLANE

0.10 C

1.00 MAX

BALL A6

BALL A1

BALL A1 ID

0.75

TYP

0.75 TYP

1.875

3.75

6.00 ±0.10

3.00 ±0.05

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-REFLOW

DIAMETER IS Ø0.35.

54X Ø0.37

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag or

96.5% Sn, 3% Ag, 0.5% Cu

SOLDER BALL PAD: Ø0.30 SOLDER MASK DEFINED

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

6.00

3.00

4.00 ±0.05

8.00 ±0.10

2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

09005aef80ec6f63 pdf/09005aef80ec6f46 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Revision History

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04

• Added software access.

• CR WRITE diagram titles updated to reflect WRITEs

followed by READ ARRAY operation.

• Added 80 MHz burst clock (-708).

• Changed PAR options to full, one-half, one-quarter,

one-eighth, or none.

• Corrected Table 17 typo.

• Added Note 3 to Fig. 33 and 39.

•Added

tCO to Figure 45 and Table 44.

• Clarified READ/WRITE operating currents.

• Added clarifying notes for required refresh

opportunity for BCR[15], depending on BCR setting.

• Added ADV# timing parameters and tCO to Fig. 46

and Table 45.

•Changed C

IN and CIO MAX values to 6.5pF.

•Added C

IN and CIO MIN values.

• Clarified CE# LOW time limited by refresh—must

not stay LOW longer than tCEM.

•Added

tCEM to Asynchronous WRITE, Page Mode

READ Operation, and Burst Mode Operation

descriptions and timing diagrams.

•Changed

tCEM MAX to 8.

• Aligned tACLK, tKHTL, tABA, and tCSP with

consortium values.

• Deleted Appendix A (extended timings and all

references).

•Updated I

CC values and symbols.

• Changed doc status to “preliminary.”

• Clarified burst latency at row-boundary crossings.

• Replaced abbreviated component marks with part

numbering chart.

• Added measurement-time clarification to ISB and

IPAR notes.

• Changed tCBPH to tCPH for async–async

transitions.

• Corrected package nomenclature to VFBGA.

• Clarified address A[4] and higher for page mode.

• Clarified CRE in Figure 14.

•Updated

tKP to 4ns for the -108, and 5ns for the -706

and -856 parts.

• Updated package diagram.

•Updated I

TCR and IPAR values.

• Corrected package diagram.

• WE# LOW limited to tCEM for async WRITES.

• Last address changed by software access sequence.

• Noted that the software access third cycle must be a

CE#-controlled WRITE.

• Separated ICC3 for READ and WRITE operations.

•Moved

tCPH to follow only CE#-controlled WRITE

cycles.

• CRE is “Don’t Care” during burst continue.

• Clarified TCR temperatures and setting in Table 8.

• Changed VccQ to 1.70V–3.30V.

• Changed wireless temperature range to -30°C.

• Noted input HIGH voltage not aligned with the

workgroup specification of VCCQ - 0.4.

• Noted wireless temp exceeds the workgroup spec.

• Clarified WAIT assertion for continuous burst with

output delay.

• Noted workgroup spec for burst termination

compliance.

Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04

• Last address not changed by software access

sequence.

• Added on-chip sensor to TCR.

• Clarified software access.

Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03

• Initial Release