IDTSTAC9767XXTAEC1X - IDT, Integrated Device Technology Inc

DATASHEET

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH

STEREO MICROPHONE AND MIC/JACK SENSING STAC9766/9767

IDT™

1STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

FEATURES

•This datasheet is for Rev. CC1 Parts and Beyond

•High Performance Σ∆ Technology

•AC’97 Rev 2.3 Complaint

•20-bit Full Duplex Stereo ADC & DACs

•Independent Sample Rates for ADC & DACs

•5-Wire AC-Link Protocol Compliance

•20-bit SPDIF Output

•Full Stereo Microphone Pre-Amp

•Internal Jack Sensing on Headphone & Line_Out

•Internal Microphone Input Sensing

•Digital PC Beep Option

•Extended AC’97 2.3 Paging Registers

•Digital-ready Status

•General Purpose I/O

•Crystal Elimination Circuit

•Headphone Drive Capability (50 mW)

•0dB, 10dB, 20dB and 30dB Microphone Boost

Capability

•+3.3 V (STAC9767) and +5 V (STAC9766) Analog

Power Supply Options

•Pin Compatible with STAC9700/21/56

•100% Compatible with STAC9750/52

•IDT Surround (SS3D) Stereo Enhancement

•Energy Saving Dynamic Power Modes

•Multi-CODEC Option (Intel AC'97 rev 2.3)

•Six Analog Line-level Inputs

•103dB SNR LINE-LINE

KEY SPECIFICATIONS

•Analog LINE_OUT SNR: 103 dB

•Digital DAC SNR: 95 dB

•Digital ADC SNR: 85 dB

•Full-scale Total Harmonic Distortion: 0.002%

•Crosstalk Between Input Channels: -70 dB

•Spurious Tone Rejection: 100 dB

RELATED MATERIALS

•Data Sheet

•Reference Designs

DESCRIPTION

IDT's STAC9766/9767 (Revision CC1 and beyond) are

general purpose 20-bit, full duplex, audio CODECs con-

forming to the analog component specification of AC'97

(Audio CODEC 97 Component Specification Rev. 2.3).

The STAC9766/9767 incorporates IDT's proprietary Σ∆

technology The AC’97 CODEC is designed to achieve a

DAC SNR in excess of 103dB.

The DACs, ADCs and mixer are integrated with analog I/

Os, which include four analog line-level stereo inputs, two

analog line-level mono inputs, two stereo outputs, and one

mono output channel. The STAC9766/9767 includes digital

input/output capability for support of modern PC systems

with an output that supports the SPDIF format.

The STAC9766/9767 is a standard 2-channel stereo

CODEC. With IDT’s headphone drive capability, head-

phones can be driven with without an external amplifier.

The STAC9766/9767 may be used as a secondary

CODEC, with the STAC9700/21/56/08/84/50/52 as the pri-

mary, in a multiple CODEC configuration conforming to the

AC'97 Rev. 2.3 specification. This configuration can pro-

vide the true six-channel, AC-3 playback required for DVD

applications.

The STAC9766/9767 communicates via the five-wire

AC-Link to any digital component of AC'97, providing flexi-

bility in the audio system design.

Packaged in an AC'97 compliant 48-pin TQFP, the

STAC9766/9767 can be placed on a motherboard, daugh-

ter boards, PCI, AMR, CNR, MDC or ACR cards.

The STAC9766/9767 provides variable sample rate Digi-

tal-to-Analog (DA) and Analog-to-Digital (AD) conversion,

mixing and analog processing.

Supported audio sample rates include 48KHz, 44.1KHz,

32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8KHz; addi-

tional rates are supported in the STAC9766/9767 soft

audio drivers. All ADCs and DACs operate at 20-bit resolu-

tion.

The STAC9766/9767 includes full Stereo Microphone

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

2STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

Table of Contents

1. PRODUCT BRIEF ......................................................................................................................6

1.1. Features (Revision CC1 and beyond) ............................................................................................... 6

1.2. Description ........................................................................................................................................ 6

1.3. STAC9766/9767 Block Diagram ........................................................................................................ 8

1.4. Key Specifications .............................................................................................................................8

1.5. Related Materials .............................................................................................................................. 8

1.6. Additional Support .............................................................................................................................8

2. CHARACTERISTICS AND SPECIFICATIONS .........................................................................9

2.1. Electrical Specifications ..................................................................................................................... 9

2.2. AC Timing Characteristics ...............................................................................................................13

3. TYPICAL CONNECTION DIAGRAM .......................................................................................17

3.1. Split Independent Power Supply Operation ....................................................................................18

4. CONTROLLER, CODEC AND AC-LINK .................................................................................20

4.1. AC-link Physical interface ................................................................................................................20

4.2. Controller to Single CODEC ............................................................................................................20

4.3. Controller to Multiple CODECs ........................................................................................................22

4.4. Clocking for Multiple CODEC Implementations ...............................................................................23

4.5. AC-link Power Management ............................................................................................................24

5. AC-LINK DIGITAL INTERFACE ..............................................................................................27

5.1. Overview .........................................................................................................................................27

5.2. AC-link Serial Interface Protocol ......................................................................................................28

5.3. AC-link Output Frame (SDATA_OUT) .............................................................................................31

5.4. AC-link Input Frame (SDATA_IN) ....................................................................................................34

5.5. AC-link Interoperability Requirements and Recommendations .......................................................38

5.6. Slot Assignments for Audio .............................................................................................................39

6. STAC9766/9767 MIXER ..........................................................................................................41

6.1. Mixer Description .............................................................................................................................41

6.2. Mixer Functional Diagrams ..............................................................................................................42

6.3. Mixer Analog Input .........................................................................................................................43

6.4. Mixer Analog Output .......................................................................................................................43

7. SPDIF AND PC BEEP .............................................................................................................44

7.1. SPDIF Digital Mux ...........................................................................................................................44

7.2. PC Beep Implementation ................................................................................................................44

8. PROGRAMMING REGISTERS ...............................................................................................46

8.1. Register Descriptions ......................................................................................................................47

8.2. General Purpose Input & Outputs ...................................................................................................65

8.3. Extended CODEC Registers Page Structure Definition ..................................................................68

8.4. STAC9766/9767 Paging Registers .................................................................................................69

8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ......................................................................................79

9. LOW POWER MODES ...........................................................................................................81

10. MULTIPLE CODEC SUPPORT ............................................................................................83

10.1. Primary/Secondary CODEC Selection ..........................................................................................83

10.2. Secondary CODEC Register Access Definitions ..........................................................................84

11. TESTABILITY ........................................................................................................................85

11.1. ATE Test Mode .............................................................................................................................85

12. ORDERING INFORMATION ..................................................................................................86

12.1. STAC9766/9767 Family Options and Part Order Numbers ...........................................................86

13. PIN DESCRIPTION ................................................................................................................87

13.1. Digital I/O ......................................................................................................................................88

13.2. Filter/References ..........................................................................................................................88

13.3. Analog I/O ....................................................................................................................................89

13.4. Power and Ground Signals ..........................................................................................................90

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

3STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

14. PACKAGE DRAWING ...........................................................................................................91

14.1. 48-Pin LQFP ..................................................................................................................................91

15. SOLDER REFLOW PROFILE ...............................................................................................92

15.1. Standard Reflow Profile Data ........................................................................................................92

15.2. Pb Free Process - Package Classification Reflow Temperatures .................................................93

16. APPENDIX A: PROGRAMMING REGISTERS .....................................................................94

17. REVISION HISTORY .............................................................................................................96

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

4STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

List of Figures

Figure 1. Block Diagram .................................................................................................................................. 8

Figure 2. Cold Reset Timing .........................................................................................................................13

Figure 3. Warm Reset Timing ........................................................................................................................13

Figure 4. Clocks Timing ................................................................................................................................14

Figure 5. Data Setup and Hold Timing .........................................................................................................15

Figure 6. Signal Rise and Fall Times Timing ................................................................................................15

Figure 7. AC-Link Low Power Mode Timing ..................................................................................................16

Figure 8. ATE Test Mode Timing ..................................................................................................................16

Figure 9. Typical Connection Diagram ..........................................................................................................17

Figure 10. Split Independent Power Supply Operation .................................................................................19

Figure 11. AC-Link to its Companion Controller ...........................................................................................20

Figure 12. CODEC Clock Source Detection .................................................................................................21

Figure 13. STAC9766/9767 Powerdown Timing ..........................................................................................24

Figure 14. Bi-directional AC-link Frame with Slot Assignments ....................................................................27

Figure 15. AC-Link Audio Output Frame ......................................................................................................31

Figure 16. Start of an Audio Output Frame ...................................................................................................31

Figure 17. STAC9766/9767 Audio Input Frame ...........................................................................................34

Figure 18. Start of an Audio Input Frame .....................................................................................................35

Figure 19. Bi-directional AC-link Frame with Slot assignments ....................................................................39

Figure 20. STAC9766 2-Channel Mixer Functional Diagram .......................................................................42

Figure 21. STAC9767 2-Channel Mixer Functional Diagram .......................................................................42

Figure 22. Example of STAC9766/9767 Powerdown/Powerup Flow ...........................................................81

Figure 23. Powerdown/Powerup Flow With Analog Still Alive .......................................................................82

Figure 24. Pin Description Drawing ...............................................................................................................87

Figure 25. 48-Pin LQFP Package Outline and Package Dimensions ...........................................................91

Figure 26. Solder Reflow Profile ...................................................................................................................92

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

5STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

List of Tables

Table 1. Clock Mode Configuration ...............................................................................................................14

Table 2. Common Clocks and Sources .........................................................................................................15

Table 3. Recommended CODEC ID Strapping .............................................................................................23

Table 4. AC-link Output Slots (Transmitted from the Controller) ...................................................................27

Table 5. The AC-link input slots (transmitted from the CODEC) ...................................................................28

Table 6. VRA Behavior ..................................................................................................................................29

Table 7. Output Slot 0 Bit Definitions .............................................................................................................32

Table 8. Command Address Port Bit Assignments ........................................................................................33

Table 9. Status Address Port Bit Assignments ..............................................................................................36

Table 10. Status Data Port Bit Assignments ..................................................................................................36

Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................38

Table 12. Secondary CODEC Addressing: Slot 0 tag bits .............................................................................38

Table 13. AC-link Input Slots To CODEC ......................................................................................................39

Table 14. AC-link Input Slots From CODEC ..................................................................................................39

Table 15. AC-link Output Slots Dedicated To Audio ......................................................................................40

Table 16. AC-link Input Slots Dedicated To Audio .........................................................................................40

Table 17. Audio Interrupt Slot Definitions ......................................................................................................40

Table 18. Digital PC Beep Examples .............................................................................................................45

Table 19. Programming Registers .................................................................................................................46

Table 20. Extended Audio ID Register Functions ..........................................................................................60

Table 21. AMAP Compliant ...........................................................................................................................62

Table 22. Hardware Supported Sample Rates ..............................................................................................63

Table 23. Supported Jack and Mic Sense Functions ....................................................................................72

Table 24. Reg 68h Default Values .................................................................................................................73

Table 25. Gain or Attenuation Examples .......................................................................................................73

Table 26. Register 68h/Page 01h Bit Overview .............................................................................................74

Table 27. Sensed Bits (Outputs) ...................................................................................................................75

Table 28. Sensed Bits (Inputs) ......................................................................................................................76

Table 29. Low Power Modes .........................................................................................................................81

Table 30. CODEC ID Selection .....................................................................................................................83

Table 31. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................84

Table 32. Test Mode Activation .....................................................................................................................85

Table 33. ATE Test Mode Operation .............................................................................................................85

Table 34. STAC9766/9767 Ordering Information ..........................................................................................86

Table 35. Digital Connection Signals .............................................................................................................88

Table 36. Filtering and Voltage References ..................................................................................................88

Table 37. Analog Connection Signals ...........................................................................................................89

Table 38. Power and Ground Signals ............................................................................................................90

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

6STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

1. PRODUCT BRIEF

1.1. Features (Revision CC1 and beyond)

•High Performance Σ∆ Technology

•AC’97 Rev 2.3 Complaint

•20-bit Full Duplex Stereo ADCs, DACs

•Independent Sample Rates for ADCs & DACs

•5-Wire AC-Link Protocol Compliance

•20-bit SPDIF Output

•Full Stereo Microphone Pre-Amp

•Internal Jack Sensing on Headphone and Line_Out

•Internal Microphone Input Sensing

•Digital PC Beep Option

•Extended AC’97 2.3 Paging Registers

•Adjustable VREF Amplifier

•Digital-ready Status

•General Purpose I/Os

•Crystal Elimination Circuit

•Headphone Drive Capability (50 mW)

•0dB, 10dB, 20dB, and 30dB Stereo or Mono Microphone Boost Capability

•+3.3V (STAC9767) and +5V (STAC9766) Analog Power Supply Options

•Pin Compatible with the STAC9700, STAC9721, STAC9756

•100% Pin Compatible with STAC9750 and STAC9752

•IDT Surround (SS3D) Stereo Enhancement

•Energy Saving Dynamic Power Modes

•Multi-CODEC option (Intel AC'97 rev 2.3)

•Six Analog Line-level Inputs

•103dB SNR LINE-LINE

1.2. Description

IDT's STAC9766/9767 (Revision CC1 and beyond) are general purpose 20-bit, full duplex, audio

CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component

Specification Rev. 2.3). The STAC9766/9767 incorporates IDT's proprietary Σ∆ technology to

achieve a DAC SNR in excess of 103dB. The DACs, ADCs and mixer are integrated with analog

I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo

outputs, and one mono output channel. The STAC9766/9767 includes digital output capability for

support of modern PC systems with an output that supports the SPDIF format. The STAC9766/9767

is a standard 2-channel stereo CODEC. With IDT’s headphone drive capability, headphones can be

driven without an external amplifier. The STAC9766/9767 may be used as a secondary CODEC,

with the STAC9700/21/44/56/08/84/50/66 as the primary, in a multiple CODEC configuration con-

forming to the AC'97 Rev. 2.3 specification. This configuration can provide the true six-channel,

AC-3 playback required for DVD applications. The STAC9766/9767 communicates via the five-wire

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

7STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

AC-Link to any digital component of AC'97 providing flexibility in the audio system design. Packaged

in an AC'97 compliant 48-pin TQFP, the STAC9766/9767 can be placed on a motherboard, daughter

boards, PCI, AMR, CNR, MDC or ACR cards.

The STAC9766/9767 block diagram is illustrated in Figure 1. It provides variable sample rate Digi-

tal-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported

audio sample rates include 48KHz, 44.1KHz, 32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8KHz;

additional rates are supported in the STAC9766/9767 soft audio drivers. All ADCs and DACs oper-

ate at 20-bit resolution.

Two 20-bit DACs convert the digital stereo PCM-out content to audio. The MIXER block combines

the PCM_OUT with any analog sources to drive the LINE_OUT and HP_OUT outputs. The

MONO_OUT delivers either microphone only, or a mono mix of sources from the MIXER. The stereo

variable sample rate 20-bit ADCs provide record capability for any mix of mono or stereo sources,

and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input and mono mix

input can be recorded simultaneously, thus allowing for an all digital output in support of the digital

ready initiative. For a digital ready record path, the microphone is connected to the left channel ADC

while the mono output of the stereo mixer is connected to right channel ADC.

The STAC9766/9767 includes full Stereo Microphone Pre-Amp support and can be used with the

10dB, 20dB and 30dB Microphone Boost options. This integration allows for additional cost savings

and options.

The STAC9766/9767 includes jack sensing on the Headphone and Line_Out. The STAC9766/9767

jack sense can detect the presence of devices on the Headphone and Line Outputs and on both Mic

inputs. With proprietary IDT current- and impedance-sensing techniques, the impedance load on the

Headphone and Line Outputs can also be detected. The GPIOs on the STAC9766/9767 remain

available for advanced configurations.

The STAC9766/9767 implementation of jack sense uses the Extended Paging Registers defined by

the AC'97 2.3 Specification. This allows for additional registry space to hold the identification infor-

mation about the CODEC, the jack sensing details and results, and the external surroundings of the

CODEC. The information within the Extended Paging Registers will allow for the automatic configu-

ration of the audio subsystem without end-user intervention. For example, the BIOS can populate

the Extended Paging Registers with valuable information for both the audio driver and the operating

system such as gain and attenuation stages, input population and input phase. With this input infor-

mation, the IDT driver will automatically provide to the Volume Control Panel only the volume sliders

that are implemented in the system, thus improving the end-user's experience with the PC.

The information in the Extended Paging Registers will also allow for automatic configuration of

microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the mas-

ter volume slider to the proper physical output, and SoftEQ configurations. The fully parametric IDT

SoftEQ can be initiated upon jack insertion and sensed impedance levels.

The STAC9766/9767 also offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP is

a new feature added to the AC’97 Specification Rev 2.3.

The STAC9766/9767 is designed primarily to support stereo (2-speaker) audio. True AC-3 playback

can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option avail-

able in the STAC9766/9767 to support multiple CODECs in an AC'97 architecture. Additionally, the

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

8STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767 provides for a stereo enhancement feature, IDT Surround 3D (SS3D). SS3D pro-

vides the listener with several options for improved speaker separation beyond the normal 2- or

4-speaker arrangements.

The STAC9766/9767 can be SoundBlaster ® and Windows Sound System® compatible when used

with IDT’s WDM driver for Windows 98/2K/ME/XP or with Intel/Microsoft driver included with Win-

dows 2K/ME/XP.

SoundBlaster is a registered trademark of Creative Labs.

Windows is a registered trademark of Microsoft Corporation.

1.3. STAC9766/9767 Block Diagram

Figure 1. Block Diagram

1.4. Key Specifications

•Analog LINE_OUT SNR: 103 dB

•Digital DAC SNR: 95 dB

•Digital ADC SNR: 85 dB

•Full-scale Total Harmonic Distortion: 0.002%

•Crosstalk between Input Channels: -70 dB

•Spurious Tone Rejection: 100 dB

1.5. Related Materials

•Product Brief

•Reference Designs for MB, AMR, CNR, and ACR applications

•Audio Precision Performance Plots

1.6. Additional Support

Additional product and company information can be obtained by going to the

IDT web site at: www.IDT.com

HP_OUT

AC-link

Digital

Interface

Registers

64x16 bits

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Power

Management

DAC

ADC

PCM out DACs

PCM in ADCs

4 stereo

sources 2 mono

sources

MONO_OUT

Stereo or

Mono

Mic Boost

0,10,20

or 30 dB

MIC1 (L)

Stereo

Mono

MIXER

Analog mixing

and Gain Control

MIC2 (R)

LINE_OUT

Multi-Codec

CID0

CID1

SPDIF

Variable Sample Rate

20-Bit DACs and

20-Bit ADCs

EAPD GPIO0

GPIO1

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

9STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

2. CHARACTERISTICS AND SPECIFICATIONS

2.1. Electrical Specifications

2.1.1. Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the STAC9766/9767. These ratings, which are standard

values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other

conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the

recommended operating temperature range.

2.1.2. Recommended Operation Conditions

Item Pin Maximum Rating

Analog maximum supply voltage AVdd 6 Volts

Digital maximum supply voltage DVdd 5.5 Volts

VREFOUT output current 5 mA

Voltage on any pin relative to ground Vss - 0.3 V to Vdd + 0.3 V

Operating temperature 0oC to +70oC

Storage temperature -55 oC to +125 oC

Soldering temperature 260 oC for 10 seconds *

Soldering temperature information for all available packages

begins on page 92 .

Parameter Min. Typ. Max. Units

Power Supply Voltage Digital - 3.3 V 3.135 3.3 3.465 V

Analog - 3.3 V 3.135 3.3 3.465 V

Analog - 5 V 4.75 55.25 V

Ambient Operating Temperature 0+70 °C

Case Temperature Tcase (48-LQFP) +90 °C

ESD: The STAC9766/9767 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can

accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the STAC9766/9767

implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality

or performance.

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

10 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

2.1.3. Power Consumption

2.1.4. AC-Link Static Digital Specifications

(Tambient = 25 ºC, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 50 pF external load)

2.1.5. STAC9766 Analog Performance Characteristics

(Tambient =25ºC, AVdd =5.0 V±5%, DVdd =3.3 V±5%, AVss =DVss =0V; 1KHz input sine

wave; Sample Frequency =48 KHz; 0dB =1Vrms, 10 KΩ/50 pF load, Testbench Characterization

BW: 20 Hz –20KHz, 0dB settings on all gain stages)

Parameter Min Typ Max Unit

Digital Supply Current

+ 3.3V Digital -35 -mA

Analog Supply Current

+ 5V Analog -80 -mA

+ 3.3V Analog -70 -mA

Power Down Status

PR0 Supply Current -TBD -mA

PR1 Supply Current -TBD -mA

PR2 Supply Current -TBD -mA

PR3 Supply Current -TBD -mA

PR4 Supply Current -TBD -mA

PR5 Supply Current -TBD -mA

PR6 Supply Current -TBD -mA

Parameter Symbol Min Typ Max Unit

Input Voltage Range Vin -0.30 -DVdd + 0.30 V

Low level input range Vil - - 0.35 x DVdd V

High level input voltage Vih 0.65 x DVdd - - V

High level output voltage Voh 0.90 x DVdd - - V

Low level output voltage Vol - - 0.1 x DVdd V

Input Leakage Current (AC-Link inputs) --10 -10 µA

Output Leakage Current (AC-Link outputs - Hi-Z) --10 -10 µA

Output buffer drive current - - 4-mA

Parameter Min Typ Max Unit

Full Scale Input Voltage:

All Analog Inputs except Mic -1.0 -Vrms

Mic Inputs (Note 1) -0.03 -Vrms

Full Scale Output:

Line Output -1.0 -Vrms

PCM (DAC) to LINE_OUT 1.0 Vrms

MONO_OUT -1.0 -Vrms

HEADPHONE_OUT (32 Ω load) (peak) -50 -mW

Analog S/N: (Note 2)

CD to LINE_OUT -103 -dB

Other to LINE_OUT -103 -dB

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

11 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

Note: 1. With +30 dB Boost on, 1.0 Vrms with Boost off

2. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.

(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).

3. ± 1dB limits for Line Output & 0dB gain

4. 20 KHz BW, 48KHz Sample Frequency

5. ± 0.25dB limits

6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth

28.8 to 100 KHz, with respect to a 1 Vrms DAC output.

8. For all inputs except PC BEEP.

2.1.6. STAC9767 Analog Performance Characteristics

(Tambient =25ºC, AVdd=3.3V±5%, DVdd=3.3V±5%, AVss=DVss=0V; 1KHzinputsine

wave; SampleFrequency=48KHz; 0dB=1Vrms, 10KΩ/50pFload, TestbenchCharacterization

BW: 20Hz–20KHz, 0dB settings on all gain stages)

D/A to LINE_OUT -95 -dB

LINE_IN to A/D with High pass filter enabled -85 -dB

Analog Frequency Response (Note 3) 20 -20,000 Hz

Total Harmonic Distortion: (Note 4)

CD to LINE_OUT -95 -dB

Other to LINE_OUT -95 -dB

D/A to LINE_OUT (full scale) -84 -dB

LINE_IN to A/D with High pass filter enabled 84 - - dB

HEADPHONE_OUT 74 80 -dB

A/D & D/A Digital Filter Pass Band (Note 5) 20 -19,200 Hz

A/D & D/A Digital Filter Transition Band 19,200 -28,800 Hz

A/D & D/A Digital Filter Stop Band 28,800 - - Hz

A/D & D/A Digital Filter Stop Band Rejection (Note 6) 100 - - dB

DAC Out-of-Band Rejection (Note 7) 55 - - dB

Group Delay (48 KHz sample rate) -1ms

Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) 70 - - dB

Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) -100 -dB

Spurious Tone Rejection -100 -dB

Attenuation, Gain Step Size -1.5 -dB

Input Impedance (Note 8) -50 -KΩ

Input Capacitance -15 -pF

VREFout -0.5 x AVdd -V

Interchannel Gain Mismatch ADC - - 0.5 dB

Interchannel Gain Mismatch DAC - - 0.5 dB

Parameter Min Typ Max Unit

Full Scale Input Voltage:

All Analog Inputs except Mic -1.0 -Vrms

Mic Inputs (Note 1) -0.03 -Vrms

Full Scale Output:

Line Output -0.5 -Vrms

Parameter Min Typ Max Unit

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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Note: 1. With +30 dB Boost on, 1.0Vrms with Boost off

2. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.

(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).

3. ± 1dB limits for Line Output & 0 dB gain

4. 20 KHz BW, 48 KHz Sample Frequency

5. ± 0.25dB limits

6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth

28.8 to 100 KHz, with respect to a 1 Vrms DAC output.

8. For all inputs except PC BEEP.

PCM (DAC) to LINE_OUT 0.5 Vrms

MONO_OUT -0.5 -Vrms

HEADPHONE_OUT (32 Ω load) (peak) -12.5 -mW

Analog S/N: (Note 2)

CD to LINE_OUT -97 -dB

Other to LINE_OUT -97 -dB

D/A to LINE_OUT -95 -dB

LINE_IN to A/D with High pass filter enabled -85 -dB

Analog Frequency Response (Note 3) 20 -20,000 Hz

Total Harmonic Distortion: (Note 4)

CD to LINE_OUT -95 -dB

Other to LINE_OUT -95 -dB

D/A to LINE_OUT (full scale) -84 -dB

LINE_IN to A/D with High pass filter enabled -84 -dB

HEADPHONE_OUT 74 80 -dB

A/D & D/A Digital Filter Pass Band (Note 5) 20 -19,200 Hz

A/D & D/A Digital Filter Transition Band 19,200 -28,800 Hz

A/D & D/A Digital Filter Stop Band 28,800 - - Hz

A/D & D/A Digital Filter Stop Band Rejection (Note 6) 100 - - dB

DAC Out-of-Band Rejection (Note 7) 55 - - dB

Group Delay (48 KHz sample rate) - - 1ms

Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) 70 - - dB

Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) -100 -dB

Spurious Tone Rejection -100 -dB

Attenuation, Gain Step Size -1.5 -dB

Input Impedance (Note 8) -50 -KΩ

Input Capacitance -15 -pF

VREFout -0.5 X AVdd -V

Interchannel Gain Mismatch ADC - - 0.5 dB

Interchannel Gain Mismatch DAC - - 0.5 dB

Gain Drift -100 -ppm/ºC

Parameter Min Typ Max Unit

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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2.2. AC Timing Characteristics

(Tambient = 25 °C, AVdd = 3.3V or 5 V ± 5%, DVdd = 3.3V ± 5%, AVss = DVss = 0V; 75pF external

load for BIT_CLK and 60pF external load for SDATA_IN)

2.2.1. Cold Reset

Figure 2. Cold Reset Timing

Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.

2.2.2. Warm Reset

Figure 3. Warm Reset Timing

Parameter Symbol Min Typ Max Units

RESET# active low pulse width Tres_low 1.0 - - µs

RESET# inactive to SDATA_IN or BIT_CLK active delay Tri2actv - - 25 ns

RESET# inactive to BIT_CLK startup delay Trst2clk 0.01628 -400 µs

BIT_CLK active to RESET# asserted (Not shown in diagram) Tclk2rst 0.416 - - µs

Parameter Symbol Min Typ Max Units

SYNC active high pulse width Tsync_high 1.0 1.3 -µs

SYNC inactive to BIT_CLK startup delay Tsync2clk 162.8 - - ns

Tres_low

Trst2clk

RESET#

BIT_CLK

SDATA_IN Ttri2actv

Ttri2actv

Tsync_high Tsync_2clk

SYNC

BIT_CLK

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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2.2.3. Clocks

Figure 4. Clocks Timing

2.2.4. STAC9766/9767 Crystal Elimination Circuit and Clock Frequencies

The STAC9766/9767 supports several clock frequency inputs as described in the following table. In

general, when a 24.576 MHz xtal is not used, the XTALOUT pin should be tied to ground. This short

to ground configures the part into an alternate clock mode and enables an on board PLL.

CODEC Modes:

P = The STAC9766/9767 as a Primary CODEC

S = The STAC9766/9767 as a Secondary CODEC.

Parameter Symbol Min Typ Max Units

BIT_CLK frequency -12.288 -MHz

BIT_CLK period Tclk_period -81.4 -ns

BIT_CLK output jitter -750 -ps

BLT_CLK high pulse width (Note 1) Tclk_high 36 40.7 45 ns

BIT_CLK low pulse width (Note 1) Tclk_low 36 40.7 45 ns

SYNC frequency -48.0 -KHz

SYNC period Tsync_period -20.8 -µs

SYNC high pulse width Tsync_high -1.3 -µs

SYNC low pulse width Tsync_low -19.5 -µs

Note: 1. Worst case duty cycle restricted to 45/55.

Table 1. Clock Mode Configuration

XTL_OUT

Pin Config CID1

Pin Config CID0

Pin Config Clock Source Input CODEC

Mode CODEC

XTAL float float 24.576MHz crystal P0

XTAL or open float pulldown 12.288 MHz BIT_CLK S1

XTAL or open pulldown float 12.288 MHz BIT_CLK S2

XTAL or open pulldown pulldown 12.288 MHz BIT_CLK S3

short to ground float float 14.31818 MHz source P0

short to ground float pulldown 27 MHz source P0

short to ground pulldown float 48 MHz source P0

short to ground pulldown pulldown 24.576 MHz source P0

SYNC

BIT_CLK Tclk_high

Tclk_low

Tclk_period

Tsync_high

Tsync_period

Tsync_low

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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2.2.5. Data Setup and Hold

(50pF external load)Figure 5. Data Setup and Hold Timing

2.2.6. Signal Rise and Fall Times

(BIT_CLK: 75pF external load; from 10% to 90% of Vdd)

(SDATA_IN: 60pF external load; from 10% to 90% of Vdd)

Figure 6. Signal Rise and Fall Times Timing

Table 2. Common Clocks and Sources

Clock Source Clock Frequency

XTAL 24.576MHz

BIT_CLK 12.288MHz

VGA 14.31818MHz

Digital Video 27MHz

USB 48MHz

Parameter Symbol Min Typ Max Units

Setup to falling edge of BIT_CLK Tsetup 10 - - ns

Hold from falling edge of BIT_CLK Thold 10 - - ns

Output Valid Data from rising edge of BIT_CLK tco - - 15 ns

Note: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.

BIT_CLK

Thold

Tsetup

SDATA_OUT

SDATA_IN

SYNC

tco

Vih Vil

Voh

Vol

BIT_CLK

SDATA_IN

TfallclkTriseclk

Trisedin Tfalldin

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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2.2.7. AC-Link Low Power Mode Timing

Figure 7. AC-Link Low Power Mode Timing

2.2.8. ATE Test Mode

Figure 8. ATE Test Mode Timing

Note: 1) All AC-Link signals are normally low through the trailing edge of RESET#. Bringing

SDATA_OUT high for the trailing edge of RESET# causes the STAC9766/9767 AC-Link outputs to

go high-impedance, which is suitable for ATE in-circuit testing.

Note: 2) Once the test mode has been entered, the STAC9766/9767 must be issued another

RESET# with all AC-Link signals low to return to the normal operating mode.

Note: 3) # denotes active low.

Parameter Symbol Min Typ Max Units

BIT_CLK rise time Triseclk - - 6ns

BIT_CLK fall time Tfallclk - - 6ns

SDATA_IN rise time Trisedin - - 6ns

SDATA_IN fall time Tfalldin - - 6ns

Parameter Symbol Min Typ Max Units

End of Slot 2 to BIT_CLK, SDATA_IN low Ts2_pdown - - 1.0 µs

Parameter Symbol Min Typ Max Units

Setup to trailing edge of RESET# (also applies to SYNC) Tsetup2rst 15.0 - - ns

Rising edge of RESET# to Hi-Z delay Toff - - 25.0 ns

BIT_CLK

SDATA_IN

Note: BIT_CLK not to scale

Ts2_pdown

Don't care

Data PR4

Write to

0x20

Slot 2Slot 1

SDATA_OUT

SYNC

Tsetup2rst

Hi-Z

Toff

RESET#

SDATA_OUT

SDATA_IN, BIT_CLK

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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3. TYPICAL CONNECTION DIAGRAM

Figure 9. Typical Connection Diagram

Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown. To Disable SPDIF, use a 1KΩ-10KΩ external pul-

lup. Do NOT leave Pin 48 floating.

The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The

name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any

DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC,

and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.

0.1 µF 1 µF 0.1 µF 0.1 µF 1 µF 0.1 µF

2 Ω*Ferrite Bead

3.3V ± 5%

AVdd1 AVdd2 DVdd1 DVdd2 XTL_IN

XTL_OUT

27 pF

24.576 MHz

13825

PC_BEEP

PHONE

AUX_L

AUX_R

VIDEO_L

VIDEO_R

CD_L

CD_GND

CD_R

MIC1

MIC2

LINE_IN_L

LINE_IN_R

CAP2

*OPTIONAL 0.1 µF

1 µF*

820 pF 29

AFILT1

AFILT2

820 pF

AVss1 AVss2

26 42 4 7

DVss1 DVss2 HP_OUT_R

*Terminate ground

plane as close to codec

as possible

Analog

Ground Digital

Ground

HP_OUT_L 39

MONO_OUT

LINE_OUT_R

LINE_OUT_L

GPIO0

GPIO1

HP_COMM

SPDIF

1 µF

VREF

VREFOUT

EAPD

CID1

CID0

RESET#

SYNC

SDATA_IN

BIT_CLK

SDATA_OUT 5

STAC9767

*OPTIONAL

27 pF

22 ΩEMI

Filter

TUNE TO LAYOUT

HP_COMM should be tied to

ground at the headphone pin.

CLOCK_IN*

*Add resistive divider

when using 5V clock.

(Near Clk source)

0 Ω

OPTIONAL

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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3.1. Split Independent Power Supply Operation

In PC applications, one power supply input to the STAC9766/9767 may be derived from a supply

regulator and the other directly from the PCI power supply bus. When power is applied to the PC, the

regulated supply input to the IC will be applied some time delay after the PCI power supply. Without

proper on-chip partitioning of the analog and digital circuitry, some manufacturer's CODECs would

be subject to on-chip SCR type latch-up.

IDT’s STAC9766/9767 specifically allows power-up sequencing delays between the analog (AVddx)

and digital (VDddx) supply pins. These two power supplies can power-up independently and at dif-

ferent rates with no adverse effects to the CODEC. The IC is designed with independent analog and

digital circuitry that prevents on-chip SCR type latch-up.

However, the STAC9766/9767 is not designed to operate for extended periods with only the analog

supply active.

Note: Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown. To Disable SPDIF, use a

1KΩ-10KΩ external pullup. Do NOT leave Pin 48 floating.

Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally

biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has

confused many designers. It should not have any DC path to GND. Connecting the CD_GND

signal directly to ground will change the internal bias of the entire CODEC, and cause significant

distortion. If there is no analog CD input, then this pin can be No-Connect.

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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Figure 10. Split Independent Power Supply Operation

0.1 µF 1 µF 0.1 µF 0.1 µF 10 µF 0.1 µF

*Suggested

AVdd1 AVdd2 DVdd1 DVdd2 XTL_IN

XTL_OUT

913825

PC_BEEP

PHONE

AUX_L

AUX_R

VIDEO_L

VIDEO_R

CD_L

CD_GND

CD_R

MIC1

MIC2

LINE_IN_L

LINE_IN_R

820 pF 29

820 pF

AVss1 AVss2

26 42 4 7

DVss1 DVss2 HP_OUT_R

*Terminate ground

plane as close to codec

as possible

Analog

Ground Digital

Ground

HP_OUT_L 39

MONO_OUT

LINE_OUT_R

LINE_OUT_L

VREFOUT

EAPD

CID1

CID0

RESET#

SYNC

BIT_CLK

SDATA_OUT 5

827 pF

22 ΩEMI

Filter

3.3V ± 5%3.3V or 5V ± 5%

TUNE TO LAYOUT

CAP2

AFILT1

AFILT2

GPIO0

GPIO1

HP_COMM

SPDIF

VREF

SDATA_IN

STAC9766 (5V Analog)

STAC9767 (3.3V Analog) 1 µF

HP_COMM should be tied to

ground at the headphone pin.

*OPTIONAL 0.1 µF

1 µF*

27 pF

24.576 MHz

CLOCK_IN*

*Add resistive divider

when using 5V clock.

(Near Clk source)

0 Ω

OPTIONAL

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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4. CONTROLLER, CODEC AND AC-LINK

This section describes the physical and high-level functional aspects of the AC‘97-Controller to

CODEC interface, referred to as AC-link.

4.1. AC-link Physical interface

The STAC9766/9767 communicates with its companion Digital Controller via the AC-link digital

serial interface. AC-link has been defined to support connections between a single Controller and up

to four CODECs. All digital audio, modem, and handset data streams, as well as all control (com-

mand/status) information are communicated over this serial interconnect, which consists of a clock

(BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out

(SDATA_OUT), and a reset (RESET#).

4.2. Controller to Single CODEC

The simplest and most common AC‘97 system configuration is a point-to-point AC-link connection

between Controller and the STAC9766/9767, as illustrated in Figure 11.

Figure 11. AC-Link to its Companion Controller

A primary CODEC may act as either a source or a consumer of BIT_CLK, depending on the config-

uration.

While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before

RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK

when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for

instance by the controller or an independent clock chip. In this case the primary CODEC must act as

a consumer of the BIT_CLK signal as if it were a secondary CODEC.

This clock source detection must be done each time the RESET# line is asserted. In the case of a

warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the

clock source, and not begin generating the clock on the assertion of SYNC if the CODEC had previ-

ously determined that it was a consumer of BIT_CLK.

SYNC

Digital DC'97

Controller AC'97 Codec

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

XTAL_IN

XTAL_OUT

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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Figure 12. CODEC Clock Source Detection

The STAC9766/9767 uses the XTAL_OUT pin (pin 3) and the CID0 and CID1 pins (pins 45 & 46) to

determine its alternate clock frequencies. See section 2.2.4: page14 for additional information on

Crystal Elimination and for supported clock frequencies.

If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on

BIT_CLK, as defined in the previous paragraph, then the AC‘97 CODEC derives its clock internally

from an externally attached 24.576 MHz crystal or oscillator (or optionally from an external

14.318 MHz oscillator), and drives a buffered 12.288 MHz clock to its digital companion Controller

over AC-link under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental

impediment to high quality output, and the internally generated clock will provide AC‘97 with a clean

clock that is independent of the physical proximity of AC‘97’s companion Digital Controller (hence-

forth referred to as “the Controller”).

If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by

other than the primary CODEC, for instance by the controller or by a discrete clock source. In this

case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary

CODEC.

AC'97 Clock Source

Detection

RESET# Signal Asserted

BIT_CLK Toggling? 12.288MHz signal on BIT_CLK is

being generated externally; codec

uses this signal as the clock.

Yes

After RESET# Signal

Deasserted

24.576MHz

crystal present?

24.576MHz Crystal on XTL_IN

and XTL_OUT used by codec to

generate clock on BIT_CLK

Yes

24.576MHz

oscillator present?

24.576 MHz signal on XTL_IN

used by codec to generate

12.288MHz clock on BIT_CLK

Yes

14.318MHz

oscillator presnent?

14.318 MHz signal on XTL_IN

used by codec to generate

12.288MHz clock on BIT_CLK

Yes

Error condition - no clock

source present

STAC9766/9767

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The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is synchro-

nized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller gener-

ates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This

yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-link

on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiv-

ing side of AC-link on each immediately following falling edge of BIT_CLK.

4.3. Controller to Multiple CODECs

Several vendor specific methods of supporting multiple CODEC configurations on AC-link have

been implemented or proposed, including CODECs with selective AC-link pass-through and control-

lers with duplicate AC-links.

Potential implementations include:

•6-channel audio using 3 x 2-channel CODECs.

•Separate CODECs for independent audio and modem AFE.

•Docking stations, where one CODEC is in the laptop and another is in the dock.

This specification defines support for up to four CODECs on the AC-link. By definition there can be

one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC

ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets;

each is individually accessible and they do not share registers.

Multiple CODEC AC-link implementations must run off a common BIT_CLK. They can potentially

save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC‘97 Digital Control-

ler. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of

multiple devices on one serial input line.

Support for multiple CODEC operation necessitates a specially designed Controller. An AC‘97 Digi-

tal Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs,

supporting one Primary CODEC and up to three Secondary CODECs.

4.3.1. Primary CODEC Addressing

Primary AC‘97 CODECs respond to register read and write commands directed to CODEC ID 00.

Primary devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID

00, and reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem

ID Register(s).

The Primary CODEC may either drive the BIT_CLK signal or consume a BIT_CLK signal provided

by the digital controller or other clock generator.

4.3.2. Secondary CODEC Addressing

Secondary AC‘97 CODECs respond to register read and write commands directed to CODEC IDs

01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other meth-

ods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended

Modem ID Register(s).

STAC9766/9767

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CODECs configured as Secondary must power up with the BIT_CLK pin configured as an input.

Using the provided BIT_CLK signal is necessary to ensure that everything on the AC-link is synchro-

nous. BIT_CLK is the clock source (multiplied by 2 so that the internal rate is 24.576 MHz).

4.3.3. CODEC ID Strapping

Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping

(i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted

polarity and default to 00 =Primary (via a weak internal pullup) when left floating. This eliminates the

need for external resistors for CODECs configured as Primary, and maintains backward compatibil-

ity with existing layouts that treat pins 45 and 46 as “no connect” or cap to ground. Pulldowns are

typically 1 KΩ-10 KΩ and connected to Digital (not Analog) Ground.

4.4. Clocking for Multiple CODEC Implementations

To keep the system synchronous, all Primary and Secondary CODEC clocking must be derived from

the same clock source, so they are operating on the same time base. In addition, all AC-link protocol

timing must be based on the BIT_CLK signal, to ensure that everything on the AC-link will be syn-

chronous.

The following are potential 24.576 MHz clock options available to a Secondary CODEC:

•Using an external 24.576 MHz signal source (external oscillator or AC‘97 Digital Controller)

•Using the Primary’s XTAL_OUT

•Using the Primary’s BIT_CLK output to derive 24.576 MHz

See section 2.2.3: page14 for clock frequencies supported and configurations.

4.4.1. STAC9766/9767 as a Primary CODEC

Primary devices are required to support correctly either of the following clocking options:

•24.576 MHz crystal attached to XTAL_IN and XTAL_OUT

•24.576 MHz external oscillator provided to XTAL_IN

•12.288 MHz oscillator provided to the BIT_CLK input

The Primary device may also optionally support the following clocking option:

• 14.318 MHz external oscillator provided to XTAL_IN

See section 2.2.3: page14 for clock frequencies supported and configurations.

Table 3. Recommended CODEC ID Strapping

CID1 (pin 46) CID0 (pin 45) Configuration

NC (weak internal pullup) NC (weak internal pullup) Primary ID 00

NC (weak internal pullup) pulldown Secondary ID 01

pulldown NC (weak internal pullup) Secondary ID 10

pulldown pulldown Secondary ID 11

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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4.4.2. STAC9766/9767 as a Secondary CODEC

Secondary devices are required to function correctly using one or more of the following clocking

options:

•24.576 MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary

24.576 MHz clock)

•BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored.

See section 2.2.3: page14 for clock frequencies supported and configurations.

4.5. AC-link Power Management

4.5.1. Powering down the AC-link

The AC-link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h)

is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a

logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to

play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.

Figure 13. STAC9766/9767 Powerdown Timing

BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Pow-

erdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to

program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream

in the audio output frame.

After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required

to drive and keep SYNC and SDATA_OUT low.

Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be

used to bring the AC-link to the active mode, since normal audio output and input frames can not be

communicated in the absence of BIT_CLK.

4.5.2. Waking up the AC-link

There are two methods for bringing the AC-link out of a low power, halted mode. Regardless of the

method, it is the AC‘97 Controller that performs the wake-up task.

SYNC

BIT_CLK

SDATA_OUT

Note: BIT_CLK not to scale

SDATA_IN

TAG Write to

0x20

slot 2

per

frame DATA

PR4

TAG

slot 2

per

frame

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AC-link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current power

down state would ultimately dictate which form of AC‘97 reset is appropriate. Unless a “cold” or “reg-

ister” reset (a write to the Reset Register) is performed, wherein the AC‘97 registers are initialized to

their default values, registers are required to keep state during all power down modes.

Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur

for a minimum of four audio frame times following the frame in which the power down was triggered.

When AC-link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit

15).

4.5.3. CODEC Triggers Wake-up

The STAC9766/9767 (running off Vaux) can trigger a wake event (PME#) by transitioning

SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the

AC-link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID,

etc.

Note that when the AC-link is either programmed to the low power mode or shut off completely,

BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-link clock

to the Secondary CODEC1. In order for a Secondary CODEC to react to an external event (phone

ringing), it must support an independent clocking scheme for any PME# associated logic that must

be kept alive when the AC-link is down. This includes logic to asynchronously drive SDATA_IN to a

logic high-level which signals a wake request to the AC‘97 Digital Controller.

4.5.4. CODEC Reset

There are three types of AC‘97 reset:

•A cold reset where all AC‘97 logic (most registers included) is initialized to its default state.

•A warm reset where the contents of the AC‘97 register set are left unaltered.

•A register reset which only initializes the AC‘97 registers to their default states.

4.5.4.1. Cold AC‘97 Reset

A cold reset is achieved by asserting RESET# low for the minimum specified time, then subse-

quently de-asserting RESET# high. BIT_CLK and SDATA_IN will be activated, or re-activated as the

case may be, and all AC‘97 control registers will be initialized to their default power-on reset values.

RESET# is an asynchronous AC‘97 input.

4.5.4.2. Warm AC‘97 Reset

A warm AC‘97 reset will re-activate the AC-link without altering the current AC‘97 register values. A

warm reset is signaled by driving SYNC high for a minimum of 1 µs in the absence of BIT_CLK.

1. Secondary CODEC always configures its BIT_CLK pin as an input.

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Within normal audio frames SYNC is a synchronous AC‘97 input. However, in the absence of

BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to

AC‘97.

AC‘97 MUST NOT respond with the activation of BIT_CLK until SYNC has been sampled low again

by AC‘97. This will preclude the false detection of a new audio frame.

4.5.4.3. Register AC‘97 Reset

Most registers in an AC device can be restored to their default values by performing a write (any

value) to the Reset Register, 00h.

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5. AC-LINK DIGITAL INTERFACE

5.1. Overview

AC-link is the 5 pin digital serial interface that links AC‘97 CODEC to Controller. The AC-link protocol

is a bi-directional, fixed clock rate, serial digital stream. AC-link handles multiple input and output

PCM audio streams, as well as control register accesses, employing a time division multiplexed

(TDM) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams, each

with 20-bit sample resolution.

The STAC9766/9767 DACs, ADCs and SPDIF can be assigned to slots 3&4, 6&9, 7&8 or 10&11.

Figure 14. Bi-directional AC-link Frame with Slot Assignments

Table 4. AC-link Output Slots (Transmitted from the Controller)

Slot Name Description

0SDATA_OUT TAG MSBs indicate which slots contain valid data; LSBs convey

CODEC ID

1Control CMD ADDR write port Read/write command bit plus 7-bit CODEC register address

2Control DATA write port 16-bit command register write data

3, 4 PCM L&R DAC playback 20-bit PCM data for Left and Right channels

5Modem Line 1 DAC 16-bit modem data for modem Line 1 output

6, 7, 8, 9 PCM Center, Surround L&R, LFE 20-bit PCM data for Center, Surround L&R, LFE channels

10 Modem Line 2 DAC 16-bit modem data for modem Line 2 output

11 Modem handset DAC 16-bit modem data for modem Handset output

12 Modem IO control GPIO write port for modem Control

12 CODEC IRQ Can be used by CODEC if a modem CODEC is not present.

10-11 SPDIF Out Optional AC-link bandwidth for SPDIF output

10-12 Double rate audio Optional AC-link bandwidth for 88.26KHz or 96KHz on L, C, R

channels

PCM

MIC Vendor

RSVD Vendor

RSVD LINE2

ADC HSET

ADC

Vendor

RSVD

STATUS

ADDR

OUTGOING STREAMS

(Controller output - SDATA_OUT)

INCOMING STREAMS

(codec output - SDATA_IN)

SYNC

TAG PHASE DATA PHASE

PCM

LEFT

CMD

ADDR NA PCM

LSURR PCM

LFE SPDIFTAG CMD

DATA PCM

RT PCM

CTR PCM

RSURR SPDIF IO

CTRL

PCM

LEFT LINE1

ADC

TAG STATUS

DATA PCM

RT IO

STATUS

SLOTS 012345678910 11 12

Slot 12 can be used by the

AC'97 Codec if a Modem

Codec is not present.

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5.2. AC-link Serial Interface Protocol

The AC‘97 Controller signals synchronization of all AC-link data transactions. The AC‘97 CODEC,

Controller, or external clock source drives the serial bit clock (BIT_CLK) onto the AC-link, which the

AC‘97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed

at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz,

provides the necessary clocking granularity to support twelve 20-bit outgoing and incoming time

slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link

data (CODEC for outgoing data and Controller for incoming data) samples each serial bit on the fall-

ing edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid

tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0

indicates that the corresponding time slot within the current audio frame has been assigned to a data

stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the

data, (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit

positions with 0 during that slot’s active time.

SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The

portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the

audio frame where SYNC is low is defined as the “Data Phase”.

Additionally, for power savings, BIT_CLK, SYNC, and all data signals can be halted. This requires

that an AC‘97 CODEC be implemented as a static design to allow its register contents to remain

intact when entering a power savings mode.

5.2.1. AC-link Variable Sample Rate Operation

The AC-link serial interconnect defines a digital data and control pipe between the Controller and the

CODEC. The AC-link supports twelve 20-bit slots at 48 KHz on SDATA_IN and SDATA_OUT. The

time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastructure

that the source of each slot’s data sets or clears to indicate the validity of the slot data within the cur-

rent audio frame. This tag infrastructure can be used to support transfers between Controller and

CODEC at any sample rate.

Table 5. The AC-link input slots (transmitted from the CODEC)

Slot Name Description

0SDATA_IN TAG MSBs indicate which slots contain valid data

1STATUS ADDR read port MSBs echo register address; LSBs indicate which slots request data

2STATUS DATA read port 16-bit command register read data

3, 4 PCM L&R ADC record 20-bit PCM data from Left and Right inputs

5Modem Line 1 ADC 16-bit modem data from modem Line1 input

6-11 PCM ADC Record 20-bit PCM data - Alternative Slots for Input

12 GPIO Status GPIO read port and interrupt status

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5.2.2. Variable Sample Rate Signaling Protocol

AC-link’s tag infrastructure imposes FIFO requirements on both sides of the AC-link. For example, in

passing a 44.1 KHz stream across the AC-link, for every 480 audio output frames that are sent

across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441

PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave

valid and non-valid slots? Each possible method brings with it different FIFO requirements. To

achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different man-

ufacturers, it is necessary to standardize the scheme for at least one side of the AC-link so that the

FIFO requirements will be common to all designs. The CODEC side of the AC-link is the focus of this

standardization.

The new standard approach calls for the addition of “on demand” slot request flags. These flags are

passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time

the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)

in a given audio input frame, it knows that it must pass along the next PCM sample for the corre-

sponding slot(s) in the AC-link output frame that immediately follows.

The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to

1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:

1. Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate

Registers 2C-34h.

2. Enables the on-demand CODEC-to-Controller signaling protocol using SLOTREQ bits that

becomes necessary when a DACs sample rate varies from the 48 KHz AC-link serial frame rate

The table below summarizes the behavior:

Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should

NOT be used.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-link output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current

AC-link input frame signal which active output slots require data from the AC‘97 Digital Controller in

the next audio output frame. An active output slot is defined as any slot supported by the CODEC

that is not in a power-down state. For fixed 48 KHz operation the SLOTREQ bits are always set

active (low) and a sample is transferred in each frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame.

Table 6. VRA Behavior

AC‘97 Functionality VRA = 0 VRA = 1

SLOTREQ bits always 0 (data each frame) 0 or 1 (data on demand)

sample rate registers forced to 48 KHz writable

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The VRM (Variable Rate Mic Audio) bit in the Extended Audio Status and Control Register controls

the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.

5.2.3. SLOTREQ Behavior and Power Management

SLOTREQ bits for fixed rate, powered down, and all unsupported slots should be driven with 0 for

maximum compatibility with the original AC '97 Component Specification. When a DAC channel is

powered down, it disappears completely from the serial frame: output tag and slot are ignored, and

the SLOTREQ bit is absent (forced to zero).

When the Controller wants to power-down a channel, all it needs to do is:

1. Disable source of DAC samples in Controller.

2. Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh.

When it wants to power up the channel, all it needs to do is:

1. Clear PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh.

2. Enable source of DAC samples in Controller.

5.2.4. Primary and Secondary CODEC Register Addressing

The 2-bit CODEC ID field in the LSBs of Output Slot 0 is an addition to the original AC-link protocol

that enables an AC‘97 Digital Controller to independently access Primary and Secondary CODEC

registers.

For Primary CODEC access, the AC‘97 Digital Controller:

1. Sets the AC-link Frame valid bit (Slot 0, bit 15).

2. Validates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13).

3. Sets a zero value (00) into the CODEC ID field (Slot 0, bits 1 and 0).

4. Transmits the desired Primary CODEC Command Address and Command Data in Slots 1 and

For Secondary CODEC access, the AC‘97 Digital Controller:

1. Sets the AC-link Frame valid bit (Slot 0, bit 15).

2. Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0).

3. Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1

and 2.

Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13)

tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command

Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.

Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state

of the Secondary CODEC ID bits) if it is not valid. AC‘97 Digital Controllers should set the frame valid

bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the

Secondary CODEC ID bits are set.

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5.3. AC-link Output Frame (SDATA_OUT)

The AC-link output frame data streams correspond to the multiplexed bundles of all digital output

data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-link output

frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot

containing 16-bits which are used for AC-link protocol infrastructure.

Figure 15 illustrates the time slot based AC-link protocol.

Figure 15. AC-Link Audio Output Frame

A new AC-link output frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-

troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-

tion is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97

CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 16. Start of an Audio Output Frame

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions

stuffed with 0 by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid

time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0.

As an example, consider an 8-bit sample stream that is being played out to one of the STAC9766/

9767 DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next

SYNC

BIT_CLK

SDATA_OUT slot1 slot2

End of previous audio frame

slot(12) "0" 19

Data Phase

20.8 uS (48 kHZ)Tag Phase

12.288 MHz

Time Slot "Valid" Bits Slot 1 Slot 2 Slot 3 Slot 12

("1" = time slot contains valid PCM data)

CID1 CID0

valid "0" 19 19"0"

Frame 19"0" "0"

SYNC

BIT_CLK

SDATA_OUT slot1 slot2

End of previous audio frame

valid

Frame

SYNC

asserted

first

SDATA_OUT

bit of frame

SYNC

detected by

codec

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12 bit positions, which are stuffed with 0 by the AC‘97 Controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least

significant bits.

When mono audio sample streams are output from the AC‘97 Controller it is necessary that BOTH

left and right sample stream time slots be filled with the same data.

5.3.1. Slot 0: TAG / CODEC ID

Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the

corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can

be transmitted across AC-link at its fixed 48 KHz audio frame rate.

The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC

5.3.2. Slot 1: Command Address Port

The command port is used to control features, and monitor status (see AC-link input frame Slots 1

and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings and power manage-

ment (refer to the control register section of this specification).

Table 7. Output Slot 0 Bit Definitions

Bit Description

15 Frame Valid

14 Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)

13 Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)

Slot 3-12 Valid Data bits

12 Slot 3: PCM Left channel

11 Slot 4: PCM Right channel

10 Slot 5: Modem Line 1 (not used on STAC9766/9767)

9Slot 6: Alternative PCM1 Left

8Slot 7: Alternative PCM2 Left

7Slot 8: Alternative PCM2 Right

6Slot 9: Alternative PCM1 Right

5Slot 10: SPDIF Left

4Slot 11: SPDIF Right

3Slot 12: Audio GPIO

2Reserved (Set to 0)

1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)

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The control interface architecture supports up to 64 16-bit read/write registers, addressable on even

byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd registers (01h,

03h, etc.) are reserved for future expansion.

Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the

implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless

required to be readable as well as writeable to provide more robust testability.

AC-link output frame slot 1 communicates control register address, and write/read command infor-

mation to the STAC9766/9767.

The first bit (MSB) sampled by AC‘97 indicates whether the current control transaction is a read or a

write operation. The following 7 bit positions communicate the targeted control register address. The

trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC‘97 Control-

ler.

5.3.3. Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the cur-

rent command port operation is a write cycle. (as indicated by Slot 1, bit 19)

• Bit(19:4) Control Register Write Data (Stuffed with 0 if current operation is a read)

• Bit(3:0) Reserved (Stuffed with 0)

If the current command port operation is a read, then the entire slot time must be stuffed with 0 by

the AC‘97 Controller.

5.3.4. Slot 3: PCM Playback Left Channel

AC-link output frame slot 3 is the composite digital audio left playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.5. Slot 4: PCM Playback Right Channel

AC-link output frame slot 4 is the composite digital audio right playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

Table 8. Command Address Port Bit Assignments

Bit Description Comments

19 Read/Write command 1 = read, 0 = write

18:12 Control Register Index Sixty-four 16-bit locations, addressed on even byte boundaries

11:0 Reserved Stuffed with 0s

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olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.6. Slot 5: Not Used by STAC9766/9767 (Modem Line 1 Output Channel)

Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9766/9767.

5.3.7. Slot 6 -11: DAC

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.8. Slot 12: Audio GPIO Control Channel

AC-link output frame slot 12 contains the audio GPIO control outputs.

5.4. AC-link Input Frame (SDATA_IN)

The AC-link input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC‘97 Controller. As is the case for audio output frame, each AC-link input frame con-

sists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are

used for AC-link protocol infrastructure.

The following diagram illustrates the time slot-based AC-link protocol.

Figure 17. STAC9766/9767 Audio Input Frame

A new AC-link input frame begins with a low to high transition of SYNC. SYNC is synchronous to the

rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97 CODEC

samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are

aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 CODEC transi-

tions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit position is pre-

sented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97 Controller

on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subse-

quent sample points for both incoming and outgoing data streams are time aligned.

SYNC

BIT_CLK

SDATA_IN slot1 slot2

End of previous audio frame

slot(12) "0" 19

Data Phase

20.8 uS (48 kHZ)Tag Phase

12.288 MHz

Time Slot "Valid" Bits Slot 1 Slot 2 Slot 3 Slot 12

("1" = time slot contains valid PCM data)

valid "0" 19 19"0"

Frame 19"0" "0""0" "0"

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Figure 18. Start of an Audio Input Frame

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0 by the AC‘97 CODEC. SDATA_IN data is

sampled on the falling edges of BIT_CLK.

5.4.1. Slot 0: TAG

Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15), which flags whether the AC‘97

CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that

the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-

tion of power on reset for example, while the AC‘97 CODEC’s voltage references settle. When the

AC-link “CODEC Ready” indicator bit is a 1 it indicates that the AC-link and AC‘97 CODEC control

and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within

400 µs after it starts receiving valid SYNC pulses from the controller, to provide indication of connec-

tion to the link and Control/Status registers are available for access. The AC`97 Controller and

related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set

before attempting any register writes, or attempting to enable any audio stream, to avoid undesirable

audio artifacts.

Prior to any attempts at putting an AC‘97 CODEC into operation, the AC‘97 Controller should poll the

first bit in the AC-link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone

“CODEC Ready”. Once an AC‘97 CODEC is sampled “CODEC Ready” 1, then the next 12 bit posi-

tions sampled by the AC‘97 Controller indicate which of the corresponding 12 time slots are

assigned to input data streams and contain valid data.

5.4.2. Slot 1: Status Address Port / SLOTREQ signaling bits

5.4.2.1. Status Address Port

The status port is used to monitor status for the STAC9766/9767 functions including, but not limited

to, mixer settings and power management. AC-link input frame slot 1’s stream echoes the control

1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready. It is the responsibility of the AC’97

controller to probe more deeply into the AC‘97 CODEC’s register file to determine which subsections are actually ready (refer to

section 6.3 for more information).

SYNC

BIT_CLK

SDATA_IN slot1 slot2

End of previous audio frame

Codec

Ready

SYNC

detected

first

SDATA_OUT

bit of frame

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and 2 had been tagged “valid” by the AC‘97 CODEC during slot 0.

The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions com-

municate the associated control register address, the next 10 bits support AC‘97’s variable sample

rate signaling protocol, and the trailing 2 bit positions are stuffed with 0 by AC‘97.

5.4.2.2. SLOTREQ signaling bits

AC-link input frame Slot 1, the Status Address Port, now delivers CODEC control register read

address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved

least significant bits have been defined as data request flags for output slots 3-12.

The AC-link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indi-

cates valid Status Address Port data (Control Register Index). The CODEC should only set

SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-

ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the

Slot 1 tag bit.

SLOTREQ bits are always 0 in the following cases

•Fixed rate mode (VRA = 0)

•Inactive (powered down) ADC channel

SLOTREQ bits are only set to 1 by the CODEC in the following case

•Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48 KHz ADC

sample rate and CODEC does not need a sample

5.4.3. Slot 2: Status Data Port

The status data port delivers 16-bit control register read data.

If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0 by AC‘97.

Table 9. Status Address Port Bit Assignments

Bit Description Comments

19 Reserved Stuffed with 0

18:12 Control Register Index Echo of register index for which data is being returned

11:2 SLOTREQ See Next Section

1:0 Reserved Stuffed with 0

Table 10. Status Data Port Bit Assignments

Bit Description Comments

19:4 Control Register Read Data Stuffed with 0 if tagged “invalid”

3:0 Reserved Stuffed with 0

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5.4.4. Slot 3: PCM Record Left Channel

Audio input frame slot 3 is the left channel output of STAC9766/9767 input MUX, post-ADC.

STAC9766/9767 ADCs are implemented to support 20-bit resolution.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.5. Slot 4: PCM Record Right Channel

Audio input frame slot 4 is the right channel output of STAC9766/9767 input MUX, post-ADC.

STAC9766/9767 ADCs are implemented to support 20-bit resolution.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.6. Slot 5: Modem Line 1 ADC

Audio input frame slot 5 is not used by the STAC9766/9767 and is always stuffed with 0.

5.4.7. Slot 6-9: ADC

The left and right ADC channels of the STAC9766/9767 may be assigned to slots 6&9 by Register

6Eh.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.8. Slots 7-8: Vendor Reserved

The left and right ADC channels of the STAC9766/9767 may be assigned to slots 7&8 by Register

6Eh.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.9. Slot 10 & 11: ADC

The left and right ADC channels of the STAC9766/9767 may be assigned to slots 10&11 by Register

6Eh.

NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.4.10. Slot 12: Reserved

AC-link input frame slot 12 contains the GPIO status inputs and allows for audio interrupts. Audio

output frame slot 12 is Reserved for modem operations and is not used by the STAC9766/9767.

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5.5. AC-link Interoperability Requirements and Recommendations

5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data

Command or Status Address and Data cannot be split across multiple AC-link frames. The following

transactions require that valid Slot 1 Address and valid Slot 2 Data be treated as “atomic” (insepara-

ble) with Slot 0 Tag bits for Address and Data set accordingly (that is, both valid):

1. AC‘97 Digital Controller write commands to Primary CODECs

2. AC‘97 CODEC status responses

Whenever the AC‘97 Digital Controller addresses a Primary CODEC or an AC‘97 CODEC responds

to a read command, Slot 0 Tag bits should always be set to indicate actual Slot 1 and Slot 2 data

validity.

When the AC‘97 Digital Controller addresses a Secondary CODEC, the Slot 0 Tag bits for Address

and Data must be 0. A non-zero, 2-bit CODEC ID in the LSBs of Slot 0 indicates a valid Read or

Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid data in Slot 2.

Table 11. Primary CODEC Addressing: Slot 0 Tag Bits

Function Slot 0, bit 15

(Valid Frame) Slot 0, bit 14

(Valid Slot 1 Address) Slot 0, bit 13

(Valid Slot 2 Data) Slot 0, Bits 1-0

(CODEC ID)

AC‘97 Digital Controller

Primary Read Frame N,

SDATA_OUT 1 1 0 00

AC‘97 Digital Controller

Primary Write Frame N,

SDATA_OUT 1 1 1 00

AC‘97 CODEC Status

Frame N+1,

SDATA_IN 1 1 1 00

Table 12. Secondary CODEC Addressing: Slot 0 tag bits

Function Slot 0, bit 15

(Valid Frame) Slot 0, bit 14

(Valid Slot 1 Address) Slot 0, bit 13

(Valid Slot 2 Data) Slot 0, Bits 1-0

(CODEC ID)

AC‘97 Digital Controller

Secondary Read Frame N,

SDATA_OUT 1 0 0 01, 10, or 11

AC‘97 Digital Controller

Secondary Write Frame N,

SDATA_OUT 1 0 0 01, 10, or 11

AC‘97 CODEC Status

Frame N+1,

SDATA_IN 1 1 1 00

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5.6. Slot Assignments for Audio

Figure 19. Bi-directional AC-link Frame with Slot assignments

Note: The DAC & ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

The AC-link input slots (transmitted to the Codec) are defined as follows:

The AC-link input slots (transmitted from the Codec) are defined as follows:

Table 13. AC-link Input Slots To CODEC

Slot Name Description

0SDATA_OUT TAG MSBs indicate which slots contain valid data; LSBs convey Codec ID

1Control CMD ADDR write port Read/write command bit plus 7-bit Codec register address

2Control DATA write port 16-bit command register write data

3,4 PCM L & R DAC playback 16, 18, or 20-bit PCM data for left and right channels

5Modem Line 1 DAC 16-bit modem data for modem line 1 output

6, 7,

8, 9 PCM Center, Rear, LFE 16, 18, or 20-bit PCM data for Center, L & R Rear, LFE channels

10 Modem Line 2 DAC 16-bit modem data for modem line 2 output

11 Modem handset DAC 16-bit modem data for modem handset output

12 Modem IO control GPIO write port for modem control

10-12 Double rate audio Optional AC-link bandwidth for 88.2 or 96 kHz on L, C, R channels

Table 14. AC-link Input Slots From CODEC

Slot Name Description

0SDATA_IN TAG MSBs indicate which slots contain valid data

1STATUS ADDR read port MSBs echo register address; LSBs indicate which slots request data

2STATUS DATA read port 16-bit command register read data

3,4 PCM L & R ADC record 16-bit PCM data from left and right inputs

5Modem Line 1 ADC 16-bit modem data from modem line 1 input

6Dedicated Microphone ADC 16-bit PCM data from optional 3rd ADC input

PCM

MIC Vendor

RSVD Vendor

RSVD LINE2

ADC HSET

ADC

Vendor

RSVD

STATUS

ADDR

OUTGOING STREAMS

(Controller output - SDATA_OUT)

INCOMING STREAMS

(codec output - SDATA_IN)

SYNC

TAG PHASE DATA PHASE

PCM

LEFT

CMD

ADDR NA PCM

LSURR PCM

LFE SPDIFTAG CMD

DATA PCM

RT PCM

CTR PCM

RSURR SPDIF IO

CTRL

PCM

LEFT LINE1

ADC

TAG STATUS

DATA PCM

RT IO

STATUS

SLOTS 012345678910 11 12

Slot 12 can be used by the

AC'97 Codec if a Modem

Codec is not present.

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The AC-link output slots dedicated to audio are defined as follows:

The AC-link input slots dedicated to audio are defined as follows:

Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

7, 8, 9 Vendor reserved Vendor specific (enhanced input for docking, array mic, etc.)

10 Modem Line 2 ADC 16-bit modem data from modem line 2 input

11 Modem handset input 16-bit modem data for modem handset input

12 Modem IO status GPIO read port for modem control

Table 15. AC-link Output Slots Dedicated To Audio

Slot Name Description

3PCM L DAC playback 20-bit PCM data for left channel

4 PCM R DAC playback 20-bit PCM data for right channel

6PCM Center 20-bit PCM data for Center channel

7 PCM L Surround 20-bit PCM data for L Surround channel

8PCM R Surround 20-bit PCM data for R Surround channel

9PCM LFE 20-bit PCM data for LFE channel

10:11 SPDIF Out 20-bit SPDIF Output

12 Reserved Reserved

Table 16. AC-link Input Slots Dedicated To Audio

Slot Name Description

3PCM L ADC record 20-bit PCM data from left input

4PCM R ADC record 20-bit PCM data from right inputs

6Dedicated Microphone ADC 20-bit PCM data from optional 3rd ADC input

7Vendor reserved vendor specific (enhanced input for docking, array mic, etc.)

8Vendor reserved vendor specific (enhanced input for docking, array mic, etc.)

9Vendor reserved vendor specific (enhanced input for docking, array mic, etc.)

12 Audio Interrupt Provides optional interrupt capability for Audio CODEC (not usable

when a modem is present)

Table 17. Audio Interrupt Slot Definitions

Bit Description

19-1 Reserved (Audio CODEC will return zeros in bits 19-1)

0Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system

interrupt. See register 24h definition for enabling mechanism.

Table 14. AC-link Input Slots From CODEC

Slot Name Description

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6. STAC9766/9767 MIXER

6.1. Mixer Description

The STAC9766/9767 includes an analog mixer for maximum flexibility. The analog mixer is designed

to the AC'97 specification to manage the playback and record of all digital and analog audio sources

in the PC environment. The analog mixer also includes several extensions of the AC’97 specification

to support “all analog record” capability as well as “POP BYPASS” mode for all digital playback. The

analog sources include:

•System Audio: Digital PCM input and output for business, games & multimedia

•CD/DVD: Analog CD/DVD-ROM audio with internal connections to CODEC mixer

•Stereo or Mono microphone: Choice of desktop mic, with programmable boost and gain

•Speakerphone: Use of system mic and speakers for telephone, DSVD, and video conferencing

•Video: TV tuner or video capture card with internal connections to CODEC mixer

•AUX/Synth: Analog FM or wavetable synthesizer, or other internal source

•Line in: External analog line level source from consumer audio, video camera, etc.

Source Function Connection

PC_BEEP PC BEEP pass through to LINE_OUT From PC_BEEP output

PHONE MONO input From telephony subsystem

MIC1 Desktop microphone From stereo or mono mic jack

MIC2 Second microphone From stereo or second mono mic jack

LINE_IN External audio source From line-in jack

CD Audio from CD-ROM Cable from CD-ROM

VIDEO Audio from TV tuner or video camera Cable from TV or VidCap card

AUX Upgrade synth or other external source Internal connector

PCM out Digital audio output from AC'97 Controller AC-Link

Destination Function Connection

HP_OUT Stereo mix of all sources To headphone out jack

LINE_OUT Stereo mix of all sources To output jack

MONO_OUT Mic or MONO Analog mixer output To telephony subsystem

PCM in Digital data from the CODEC to the AC'97 Controller AC-Link

SPDIF SPDIF digital audio output To SPDIF output connector

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6.2. Mixer Functional Diagrams

Figure 20. STAC9766 2-Channel Mixer Functional Diagram

Figure 21. STAC9767 2-Channel Mixer Functional Diagram

0Ah

0Ch

0Eh

10h

12h

16h

14h

PC_BEEP

Phone

AUX

VIDEO

LINEIN

MIC1

MIC2

20h:D8 10, 20 or

30 dB

AllAnalog

AllRecord

6Eh:D12

-6dB

MUX

ADC

04h

Mono

Volume

Master

Volume3D LINE_OUT

3D HP_OUT

02h

06h

MUX

1Ch

20h:D15

Analog

Audio

Sources

Slot

Select

Slot

Select

MUX

PCM to

SPDIF SPDIF

PCMOut

2Ah:D5-D4

28h: D5-D4

PCMIn

20h:D13

22h:D2-D3

1Ah

-6dB

MonoAnalog

StereoAnalog

Digital

KEY

20h:D9

ADCRecord

MUX

vol mute

MUX

DAC

Record

Volume

6Ah:D1

18h

Headphone

Volume

MONO_OUT

0Eh:D6 & 6E:D2

Slot

Select

Digital

PCBeep

38h:D5-D4

20h:D13

22h:D2-D3

0Ah

0Ch

0Eh

10h

12h

16h

14h

PC_BEEP

Phone

AUX

VIDEO

LINEIN

MIC1

MIC2

20h:D8 10, 20 or

30 dB

AllAnalog

AllRecord

6Eh:D12

-6dB

MUX

ADC

04h

Mono

Volume

Master

Volume3D LINE_OUT

3D HP_OUT

02h

06h

MUX

1Ch

20h:D15

Analog

Audio

Sources

Slot

Select

Slot

Select

MUX

PCM to

SPDIF SPDIF

PCMOut

2Ah:D5-D4

28h: D5-D4

PCMIn

20h:D13

22h:D2-D3

1Ah

-6dB

MonoAnalog

StereoAnalog

Digital

KEY

20h:D9

ADCRecord

MUX

vol mute

MUX

DAC

Record

Volume

6Ah:D1

18h

Headphone

Volume

MONO_OUT

0Eh:D6 & 6E:D2

Slot

Select

Digital

PCBeep

38h:D5-D4

20h:D13

22h:D2-D3

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6.3. Mixer Analog Input

The mixer provides recording and playback of any audio sources or output mix of all sources. The

STAC9766/9767 supports the following input sources:

•Any mono or stereo source

•Mono or stereo mix of all sources

•Two-channel input with mono output reference (mic or stereo mix)

Note: All unused inputs should be tied together and connected to ground through a capacitor

(0.1 µF suggested).

Note: The MIC should be tied to ground separately through its own 0.1 µf capacitor.

6.4. Mixer Analog Output

The Mixer generates three distinct outputs:

•A stereo mix of all sources for output to the LINE_OUT

•A stereo mix of all sources for output to HP_OUT

•A mono, mic only or mix of all sources for MONO_OUT

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7. SPDIF AND PC BEEP

7.1. SPDIF Digital Mux

The STAC9766/9767 incorporates a digital output that supports SPDIF formats. A multiplexer deter-

mines which of two digital input streams are used for the digital output conversion process. These

two streams include the PCM OUT data from the audio controller and the ADC recorded output. The

normal analog LINE_OUT signal can be converted to the SPDIF formats by using the internal ADC

to record the “MIX” output, which is the combination of all analog and all digital sources. In the case

of digital controllers with support for four or more channels, the SPDIF output mode can be used to

support compressed 6-channel output streams for delivery to home theater systems. These can be

routed on alternate AC-Link slots to the SPDIF output, while the standard 2-channel output is deliv-

ered as selected by bits D5 and D4 in Register 6E. If the digital controller supports 6 channels, a

SPDIF output with four analog channels can also be configured.

If the Digital Controller has independent DMA engines, SPDIF and Analog can be used simulta-

neously and independently.

7.2. PC Beep Implementation

The STAC9766/9767 offers two styles of PC BEEP, Analog and Digital. The digital PC Beep is a

new feature added to the AC’97 Specification Rev 2.3. This style of PC Beep will eventually replace

the Analog style, thus eliminating the need for a PC Beep pin. Until this feature is widely accepted,

IDT will provide BOTH styles of PC Beep. Both PC Beep styles use Reg 0Ah. Additional information

about Reg0Ah can be found in Section8.1.5: page50.

7.2.1. Analog PC Beep

PC Beep is active on power up and defaults to an un-muted state. The PC-BEEP input is routed

directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because the PC_BEEP

input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is rec-

ommended to keep the beep tone within reasonable volume levels. The user should mute this input

before using any other mixer input because the PC Beep input can contribute noise to the lineout

during normal operation. This style of PC Beep is related to the AC’97 Specification Rev 2.2. To use

the analog PC Beep, write a value of 00h to bits F[7:0](D[12:5]) to disable generation of the Digital

PC Beep. PV[3:0] (D[4:1]) controls the volume level from 0dB to 45dB of attenuation in 3dB steps.

7.2.2. Digital PC Beep

The Digital PC Beep uses the identical register as the Analog style, Reg 0Ah. This register controls

the level and frequency for the PC Beep. The beep frequency is the result of dividing the 48 KHz

clock by 4 times the number specified in F[7:0], allowing tones from 47Hz to 12 KHz. A value of 00h

written to bits F[7:0] disables the digital PC Beep generation and enables the analog style PC Beep.

The volume control bits, PV[3:0] operate identically to the analog PC Beep mode. Applying a signal

to the PC Beep pin, pin 12, may cause the digital PC Beep signal to become distorted or inaudible.

When using the digital PC Beep feature, leave the PC Beep input pin unconnected or connected to

analog ground through a capacitor. Connecting a capacitor from the PC Beep input pin to ground will

create a more pleasing sound by changing the digital output to a more sinusoidal output.

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This will be programmed directly by the BIOS.

Table 18. Digital PC Beep Examples

Value Reg 0Ah Frequency

10x01 12,000Hz

10 0x0A 1200Hz

25 0x19 480Hz

50 0x32 240Hz

100 0x64 120Hz

127 0x0F 94.48Hz

255 0xFF 47.05Hz

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8. PROGRAMMING REGISTERS

Table 19. Programming Registers

Address Name Default Location

00h Reset 6A90h 8.1.1; page47

02h Master Volume 8000h 8.1.2; page48

04h HP_OUT Mixer Volume 8000h 8.1.3; page48

06h Master Volume MONO 8000h 8.1.4; page49

0Ah PC Beep Mixer Volume 0000h 8.1.5; page50

0Ch Phone Mixer Volume 8008h 8.1.6; page50

0Eh Mic Mixer Volume 8008h 8.1.7; page51

10h Line In Mixer Volume 8808h 8.1.8; page51

12h CD Mixer Volume 8808h 8.1.9; page52

14h Video Mixer Volume 8808h 8.1.10; page53

16h Aux Mixer Volume 8808h 8.1.11; page53

18h PCM Out Mixer Volume 8808h 8.1.12; page54

1Ah Record Select 0000h 8.1.13; page54

1Ch Record Gain 8000h 8.1.14; page55

20h General Purpose 0000h 8.1.15; page56

22h 3D Control 0000h 8.1.16; page56

24h Audio Int. & Paging 0000h 8.1.17: page57

26h Powerdown Ctrl/Stat 000Fh 8.1.18; page58

28h Extended Audio ID 0A05h 8.1.19; page59

2Ah Extended Audio Control/Status 0400h* 8.1.20; page60

2Ch PCM DAC Rate BB80h 8.1.22; page63

32h PCM LR ADC Rate BB80h 8.1.23; page63

3Ah SPDIF Control 2000h 8.1.24; page64

3Eh Extended Modem Stat/Ctrl 0100h 8.2.4; page66

4Ch GPIO Pin Configuration 0003h 8.2.5; page66

4Eh GPIO Pin Polarity/Type FFFFh 8.2.6; page66

50h GPIO Pin Sticky 0000h 8.2.7; page67

52h GPIO Wake-up 0000h 8.2.8; page67

54h GPIO Pin Status 0000h 8.2.9; page67

60h CODEC Class/Rev 1201h 8.3; page68

62h (Page 01h) PCI SVID FFFFh 8.4.2; page70

64h (Page 01h) PCI SSID FFFFh 8.4.3; page70

66h (Page 01h) Function Select 0000h 8.4.4; page71

68h (Page 01h) Function Information xxxxh 8.4.5; page72

6Ah Digital Audio Control 0000h 8.4.6; page74

6Ah (Page01h) Sense Details NA8.4.7: page74

6Ch Revision Code xxxxh 8.4.7; page74

6Ch (Page01h) Reserved 0000h NA

6Eh Analog Special 1000h 8.4.9: page76

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Note: * depends upon CODECID

8.1. Register Descriptions

8.1.1. Reset (00h)

Default: 6A90h

Writing any value to this register performs a register reset, which causes all registers to revert to

their default values. This register reset also resets all the digital block. Reading this register returns

the ID code of the part.

6Eh (Page01h) Reserved 0000h NA

70h Enable Register 0000h NA

72h Analog Current Adjust 0000h 8.4.10; page77

74h EAPD Access 0800h 8.4.11; page78

78h High Pass Filter Bypass 0000h 8.4.12; page79

7Ah Reserved NA NA

7Ch Vendor ID1 8384h 8.5.1; page80

7Eh Vendor ID2 7652h 8.5.2; page80

D15 D14 D13 D12 D11 D10 D9 D8

RSRVD SE4 SE3 SE2 SE1 SE0 ID9 ID8

D7 D6 D5 D4 D3 D2 D1 D0

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Bit(s) Reset Value Name Description

15 0 RESERVED Bit not used, should read back 0

14:10 11010 SE4:SE0 IDT ID for SS3D

9 1 ID9 20 bit ADC resolution (supported)

8 0 ID8 18 bit ADC resolution

7 1 ID7 20 bit DAC resolution (supported)

6 0 ID6 18 bit DAC resolution

5 0 ID5 Loudness (bass boost)

4 1 ID4 Headphone out (supported)

3 0 ID3 Simulated stereo (mono to stereo)

2 0 ID2 Bass & treble control

1 0 ID1 Reserved

0 0 ID0 Dedicated MIC PCM in channel

Table 19. Programming Registers

Address Name Default Location

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8.1.2. Master Volume Registers (02h)

Default: 8000h

8.1.3. Headphone Volume Registers (04h)

Default: 8000h

D15 D14 D13 D12 D11 D10 D9 D8

Mute RSRVD ML5 ML4 ML3 ML2 ML1 ML0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED MR5 MR4 MR3 MR2 MR1 MR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = no mute

1 = Mutes both left & right channels

14 0 RESERVED Bit not used, should read back 0

13 0 ML5 0 = Lineout attenuation is a function of bits12-8

1 = Forces register bits 12-8 to be 11111

Always reads back 0

12:8 0ML<4:0>

Left Lineout Volume Control

00000 = 0dB attenuation

00001 = 1.5dB attenuation

.....

11111 = 46.5dB attenuation

7:6 0RESERVED Bits not used, should read back 0

5 0 MR5 0 = Lineout attenuation is a function of bits 4-0

1 = Forces register bits 4-0 to be 11111

Always reads back 0

4:0 0MR<4:0>

Right Channel Lineout Volume Control

00000 = 0dB attenuation

00001 = 1.5dB attenuation

.....

11111 = 46.5dB attenuation

D15 D14 D13 D12 D11 D10 D9 D8

Mute RSRVD HPL5 HPL4 HPL3 HPL2 HPL1 HPL0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED HPR5 HPR4 HPR3 HPR2 HPR1 HPR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = no mute

1 = Mutes both left & right channels

14 0 RESERVED Bit not used, should read back 0

13 0 ML5 0 = Headphone attenuation is a function of bits12-8

1 = forces register bits 12-8 to be 11111

Always reads back 0

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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8.1.4. Master Volume MONO (06h)

Default: 8000h

12:8 0ML<4:0>

Left Headphone Volume Control

00000 = 0dB attenuation

00001 = 1.5dB attenuation

.....

11111 = 46.5dB attenuation

7:6 0RESERVED Bits not used, should read back 0

5 0 MR5 0 = Headphone attenuation is a function of bits 4-0

1 = forces register bits 4-0 to be 11111

Always reads back 0

4:0 0MR<4:0>

Right Channel Headphone Volume Control

00000 = 0dB attenuation

00001 = 1.5dB attenuation

.....

11111 = 46.5dB attenuation

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED MM5 MM4 MM3 MM2 MM1 MM0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute mono

14:6 0RESERVED Bit not used, should read back 0

5 0 MM5 0 = Mono attenuation is a function of bits 4-0

1 = Forces register bits 4-0 to be 11111

Always reads back 0

4:0 0MM<4:0>

Mono Volume Control

00000 = 0dB attenuation

00001 = 1.5dB attenuation

.....

11111 = 46.5dB attenuation

Bit(s) Reset Value Name Description

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8.1.5. PC BEEP Volume (0Ah)

Default: 0000h

Additional information on the PC Beep can be found in Section 7.2: page44.

8.1.6. Phone Volume (Index 0Ch)

Default: 8008h.

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED F7 F6 F5 F4 F3

D7 D6 D5 D4 D3 D2 D1 D0

F2 F1 F0 PV3 PV2 PV1 PV0 RSRVD

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute PC BEEP

14:13 0RESERVED Bit not used, should read back 0

12:5 00h F[7:0]

The Beep frequency is the result of dividing the 48KHz clock by 4 times

the number specified in F[7:0] allowing tones from 47Hz to 12KHz.

A value of 00h in bits F[7:0] disables internal PC BEEP generation and

enables external PC BEEP input if available.

4:1 0PV(3:0)

PCBEEP Volume Control

0000 = 0dB attenuation

0001 = 3dB attenuation

.....

1111 = 45dB attenuation

0 0 RESERVED Bit not used, should read back 0

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GN4 GN3 GN2 GN1 GN0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute phone

14:5 0RESERVED Bit not used, should read back 0

4:0 0GN<4:0>

Phone Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

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8.1.7. Stereo or Mic Volume (Index 0Eh)

To enable Stereo Mic, Register 78h (unlocked), bit D6 must be enabled.

In Stereo mode, the left and right volume are controlled by GN4:GN0.

Default: 8008h.

8.1.8. LineIn Volume (Index 10h)

Default: 8808h.

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED BOOSTEN RESERVED GN4 GN3 GN2 GN1 GN0

Bit(s) Reset Value Name Description

15 1 Mute 0 = no mute

1 = mute phone

14:7 0RESERVED Bit not used, should read back 0

6 0 BOOSTEN

Works with MICGAINVAL (Register 6Eh Bit D2)

BOOSTEN MICGAINVAL = Mic Gain Boost

0 0 = 0 dB

0 1 = 10 dB

1 0 = 20 dB

1 1 = 30 dB

5 0 RESERVED

4:0 0GN<4:0>

Phone Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL4 GL3 GL2 GL1 GR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR4 GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute linein

14:13 0RESERVED Bit not used, should read back 0

12:8 0GL<4:0>

Left LineIn Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

STAC9766/9767

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8.1.9. CD Volume (Index 12h)

Default: 8808h.

7:5 0RESERVED Bit not used, should read back 0

4:0 0GR<4:0>

Right LineIn Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL4 GL3 GL2 GL1 GR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR4 GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute CD

14:13 0RESERVED Bit not used, should read back 0

12:8 0GL<4:0>

Left CD Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

7:5 0RESERVED Bit not used, should read back 0

4:0 0GR<4:0>

right CD Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

Bit(s) Reset Value Name Description

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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8.1.10. Video Volume (Index 14h)

Default: 8808h.

8.1.11. Aux Volume (Index 16h)

Default: 8808h.

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL4 GL3 GL2 GL1 GR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR4 GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute video

14:13 0RESERVED Bit not used, should read back 0

12:8 0GL<4:0>

Left Video Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

7:5 0RESERVED Bit not used, should read back 0

4:0 0GR<4:0>

Right video Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL4 GL3 GL2 GL1 GR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR4 GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute aux

14:13 0RESERVED Bit not used, should read back 0

12:8 0GL<4:0>

Left Aux Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

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8.1.12. PCMOut Volume (Index 18h)

Default: 8808h.

8.1.13. Record Select (1Ah)

Default: 0000h (corresponding to Mic in)

Used to select the record source independently for right and left.

7:5 0RESERVED Bit not used, should read back 0

4:0 0GR<4:0>

Right Aux Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL4 GL3 GL2 GL1 GR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR4 GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 Mute 0 = No mute

1 = Mute PCM out

14:13 0RESERVED Bit not used, should read back 0

12:8 0GL<4:0>

Left PCM Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

7:5 0RESERVED Bit not used, should read back 0

4:0 0GR<4:0>

Right PCM Volume Control

00000 = 12dB gain

00001 = 10.5dB gain

.....

01000 = 0dB gain

.....

11111 = -34.5dB gain

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED SL2 SL1 SL0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED SR2 SR1 SR0

Bit(s) Reset Value Name Description

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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8.1.14. Record Gain (1Ch)

Default: 8000h (corresponding to 0 dB gain with mute on)

Bit(s) Reset Value Name Description

15:11 0RESERVED Bits not used, should read back 0

10:8 0SL2:SL0

Left Channel Input Select

000 = Mic

001 = CD In (left)

010 = Video In (left)

011 = Aux In (left)

100 = Line In (left)

101 = Stereo Mix (left)

110 = Mono Mix

111 = Phone

7:3 0RESERVED Bits not used, should read back 0

2:0 0SR2:SR0

Right Channel Input Select

000 = Mic

001 = CD In (right)

010 = Video In (right)

011 = Aux In (right)

100 = Line In (right)

101 = Stereo Mix (right)

110 = Mono Mix

111 = Phone

D15 D14 D13 D12 D11 D10 D9 D8

Mute RESERVED GL3 GL2 GL1 GL0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GR3 GR2 GR1 GR0

Bit(s) Reset Value Name Description

15 1 MUTE Mutes Record Gain

14:12 0RESERVED Bits not used, should read back 0

11:8 0GL<3:0>

Left Channel Volume Control

0000 = 0dB gain

0001 = 1.5dB gain

....

1111 = 22.5dB gain

7:4 0RESERVED Bits not used, should read back 0

3:0 0GR<3:0>

Right Channel Volume Control

0000 = 0dB gain

0001 = 1.5dB gain

....

1111 = 22.5dB gain

STAC9766/9767

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8.1.15. General Purpose (20h)

Default: 0000h

8.1.16. 3D Control (22h)

Default: 0000h

This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built

into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios

in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending beyond the nor-

mal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to

1 to enable SS3D functionality to allow the bits in 22h to take effect.

D15 D14 D13 D12 D11 D10 D9 D8

POP BYP RESERVED 3D RESERVED MIX MS

D7 D6 D5 D4 D3 D2 D1 D0

LOOPBACK RESERVED

Bit(s) Reset

Value Name Description

15 0POP BYPASS 0 = Normal

1 = DAC bypasses mixer and connects directly to Line Out, Headphone

Out and Mono Out.

14 0RESERVED Bit not used, should read back 0

13 03D 0 = 3D Effect Disabled

1 = 3D Effect Enabled

12:10 0RESERVED Bit not used, should read back 0

9 0 MIX Mono Output select (0 = Mix, 1 = Mic)

8 0 MS Mic select (0 = Mic1, 1 = Mic2)

7 0 LOOPBACK 1 = Enables ADC to DAC loopback test

0 = Loopback Disabled

Do not send in conflicting data on AC-LINK while running this.

6:0 0RESERVED Bit not used, should read back 0

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED DP3 DP2 RESERVED

Bit(s) Reset Value Name Description

15:4 0RESERVED Bits not used, should read back 0

3:2 0DP3,DP2

LINE_OUT SEPARATION RATIO

DP3 DP2 effect

0 0 0 ( OFF )

0 1 3 ( LOW )

1 0 4.5 ( MED )

1 1 6 ( HIGH )

1:0 0RESERVED Bits not used, should read back 0

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The three separation ratios are implemented. The separation ratio defines a series of equations that

determine the amount of depth difference (High, Medium, and Low) perceived during two-channel

playback. The ratios provide for options to narrow or widen the soundstage.

8.1.17. Audio Interrupt and Paging (24h)

Default: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

I4 I3 I2 I1 I0 RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED PG3 PG2 PG1 PG0

Bit(s) Reset Value Access Name Description

15 0 Read / Write I4

0 = Interrupt is clear

1 = Interrupt is set

Interrupt event is cleared by writing a 1 to this bit.

The interrupt bit will change regardless of condition of interrupt

enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink

will follow this bit change when interrupt enable (I0) is unmasked.

14-13 0Read Only I3-I2

Interrupt Cause

00 = Reserved

01 = Sense cycle complete, sense info available.

10 = Change in GPIO input status

11 = Sense cycle complete and change in GPIO input status.

These bits will reflect the general cause of the first interrupt event

generated. It should be read after interrupt status has been

confirmed as interrupting. The information should be used to scan

possible interrupting events in proper pages.

12 0 Read / Write I1

Sense Cycle

0 = Sense Cycle not in Progress

1 = Sense Cycle Start.

Writing a 1 to this bit causes a sense-cycle start, if supported. If

sense cycle is not supported, this bit is read only.

11 0 Read / Write I0

Interrupt Enable

0 = Interrupt generation is masked.

1 = Interrupt generation is un-masked.

The driver should not un-mask the interrupt unless ensured by the

AC‘97 controller that no conflict is possible with modem slot 12 -

GPI functionality. Some AC’97 2.2 compliant controllers will not

likely support audio CODEC interrupt infrastructure. In either case,

software should poll the interrupt status after initiating a sense

cycle and wait for Sense Cycle Max Delay to determine if an

interrupting event has occurred.

STAC9766/9767

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8.1.18. Powerdown Ctrl/Stat (26h)

Default: 000Fh

10:4 0Read Only RESERVED Bits not used, should read back 0

3:0 0Read / Write PG3:PG0

Page Selector

0h = Vendor Specific

1h = Page ID 01 (See Section 8.4 for additional information on the

Paging Registers)

Fh = Reserved Pages

This register is used to select a descriptor of 16 word pages

between registers 60h to 6Fh. Value 0h is used to select vendor

specific space to maintain compatibility with AC’97 2.2 vendor

specific registers.

System software determines implemented pages by writing the

page number and reading the value back. All implemented pages

must be consecutive. (i.e., page 2h cannot be implemented without

page 1h).

These registers are not reset on RESET#.

D15 D14 D13 D12 D11 D10 D9 D8

EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED REF ANL DAC ADC

Bit(s) Reset Value Name Description

15 0 EAPD 1 = Forces EAPD pad to VDDD

0 = Forces EAPD pad to GNDD

14 0 PR6 0 = Headphone Amp powered up

1 = Headphone Amp powered down

13 0 PR5 0 = Digital Clk active

1 = Digital Clk disable

12 0 PR4 0 = Digital active

1 = Powerdown: PLL, AC-Link, crystal oscillator

11 0 PR3 0 = VREF and VREFOUT are active

1 = VREF and VREFOUT are powered down, and PR2 is asserted in

analog block

10 0 PR2 0 = Analog active

1 = All signal path analog is powered down

9 0 PR1 0 = DAC powered up

1 = DAC powered down

8 0 PR0 0 = ADC powered up

1 = ADC powered down

7:4 0RESERVED Bit not used, should read back 0

3 1 REF Read Only --- VREF status

1 = VREF enabled

2 1 ANL Read Only ---- ANALOG MIXERS, etc. Status

1 = Analog mixers ready.

Bit(s) Reset Value Access Name Description

STAC9766/9767

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8.1.18.1. Ready Status

The lower half of this register is read only status, a 1 indicating that each subsection is “ready”.

Ready is defined as the subsection's ability to perform in its nominal state. When this register is writ-

ten, the bit values that come in on AC-Link will have no effect on read only bits 0-7.

When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the

AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller

must further probe this Powerdown Control/Status Register to determine exactly which subsections,

if any, are ready. When this register is written, the bit values that come in on AC-Link will have no

effect on read only bits 0-7.

8.1.18.2. Powerdown Controls

The STAC9766/9767 is capable of operating at reduced power when no activity is required. The

power-down state is controlled by the Powerdown Register (26h). See the section “Low Power

Modes” for more information.

8.1.18.3. External Amplifier Power Down Control Output

The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output

of the EAPD output, pin 45, and produces a logical 1 when this bit is set to logic high. This function is

used to control an external audio amplifier power down. EAPD = 0 places approximately 0 V on the

output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output

pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will

likely require an external inverter to maintain software driver compatibility.

EAPD can also act as a GPIO. See Section 8.4.11: page78. The GPIO controls in Section8.2:

page65 have no effect on EAPD.

8.1.19. Extended Audio ID (28h)

Default: 0A05h

The Extended Audio ID register is a read only register except for bits D4 and D5. ID1 and ID0 echo

the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. The

primary CODEC returns 00, while any other code (01, 10, 11) identifies the CODEC as one of three

secondary CODEC possibilities. The AMAP bit, D9, will return a 1 indicating that the CODEC sup-

1 1 DAC Read Only ---- DAC Status

1 = DAC ready to playback

0 1 ADC Read Only ---- ADC Status

1 = ADC ready to record

D15 D14 D13 D12 D11 D10 D9 D8

ID1 ID0 RESERVED AMAP RSVD

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED DSA1 DSA0 RESVD SPDIF RSVD VRA

Bit(s) Reset Value Name Description

STAC9766/9767

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ports the optional “AC’97 2.3 compliant AC-link slot to audio DAC mappings”.The default condition

assumes that 0, 0 are loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With

0s in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification rec-

ommendations. If the DSA1 and DSA0 bits do not contain 0s, the slot assignments are as per the

table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1

indicating that the CODEC supports the optional variable sample rate conversion as defined by the

AC’97 specification.

1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin

45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in

primary mode only. Secondary mode can either be through BIT CLK driven or 24MHz clock

driver, with XTAL_OUT floating.

2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not avail-

able. Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown. To Disable SPDIF, use a

1KΩ-10KΩ external pullup. Do NOT leave Pin 48 floating.

8.1.20. Extended Audio Control/Status (2Ah)

Default: 0400h* (*default depends on CODEC ID)

Table 20. Extended Audio ID Register Functions

Bit Name Access Reset Value Function

15:14 ID [1,0] Read only Variable 00 = XTAL_OUT grounded (Note 1)

CID1#,CID0# = XTAL_OUT crystal or floating

13:12 RESERVED Read only 00 Bits not used, should read back 00

11:10 REV[1:0] Read only 10 Indicates CODEC is AC’97 Rev 2.3 compliant

9:6 RSVD Read only 0Reserved

5:4 DSA [1,0] Read/Write 00

DAC slot assignment

If CID[1:0] = 00 then DSA[1:0] resets to 00

If CID[1:0] = 01 then DSA[1:0] resets to 01

If CID[1:0] = 10 then DSA[1:0] resets to 01

If CID[1:0] = 11 then DSA[1:0] resets to 10

00 = left slot 3, right slot 4

01 = left slot 7, right slot 8

10 = left slot 6, right slot 9

11 = left slot 10, right slot 11

3RSVD Read only 0Reserved

2SPDIF Read only 10 = SPDIF pulled high on reset, SPDIF disabled

1 = default, SPDIF enabled (Note 2)

1RSVD Read only 0Reserved

0VRA Read only 1Variable sample rates supported (Always = 1)

D15 D14 D13 D12 D11 D10 D9 D8

VCFG RESERVED SPCV RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED SPSA1 SPSA0 RSRVD SPDIF RSRVD VRA enable

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Note: If pin 48 is held high at powerup, the SPDIF is not available and bits D15:D1 can not be

written and will read back zero. Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown.

To Disable SPDIF, use a 1KΩ-10KΩ external pullup. Do NOT leave Pin 48 floating.

8.1.20.1. Variable Rate Sampling Enable

The Extended Audio Status Control register also contains one active bit to enable or disable the

Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1, the variable

Bit(s) Reset Value Name Description

15 VCFG

Determines the SPDIF transmitter behavior when data is not being

transmitted. When asserted, this bit forces the deassertion of the SPDIF

“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit

is defined in the SPDIF Control Register (Reg 3Ah).

If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),

bit<28> “Validity” flag reflects whether or not an internal CODEC

transmission error has occurred. Specifically an internal CODEC error

should result in the “Validity” flag being set to 1.

If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does

not receive a valid sample from the AC'97 controller, (Left or Right), the S/

PDIF transmitter should set the “Validity” flag to 0 and pad the “Audio

Sample Word” with 0 for sub-frame in question. If a valid sample (Left or

Right) was received and successfully transmitted, the “Validity” flag

should be 0 for that sub-frame.

Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.

These bits are set via driver .inf options.

14-11 RESERVED Reserved

10 0 SPCV 0 = Invalid SPDIF configuration

1 = Valid SPDIF configuration

9:6 0RESERVED Bit not used, should read back 0

5:4 0SPSA1:SPSA0

SPDIF slot assignment

If CID[1:0] = 00 then SPSA[1:0] resets to 01

If CID[1:0] = 01 then SPSA[1:0] resets to 10

If CID[1:0] = 10 then SPSA[1:0] resets to 10

If CID[1:0] = 11 then SPSA[1:0] resets to 11

00 = Left slot 3, right slot 4

01 = Left slot 7, right slot 8

10 = Left slot 6, right slot 9

11 = Left slot 10, right slot 11

3RESERVED Reserved

2 0 SPDIF

0 = Disables SPDIF (SPDIF_OUT is high Z) (note 1)

1 = Enable SPDIF

SPDIF is a control register for Reg 3Ah, this bit must be set low i.e. SPDIF

disabled in order to write to Reg 3Ah Bits D15,D13:D0.

1 0 RESERVED Bit not used, should read back 0

0 0 VRA Enable 0 = VRA disabled, DAC and ADC set to 48 KHz (Registers 2Ch and 32h

loaded with the value BB80h)

1 = VRA ENABLED, Reg. 2Ch & 32h control sample rate

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sample rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers

are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.

The STAC9766/9767 supports “on-demand” slot request flags. These flags are passed from the

CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active

low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot

in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable

“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-

fers and every audio frame will include an active slot request flag and data is transferred every

frame.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current

audio input frame for active output slots, which will require data in the next audio output frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. When VRA is set

to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).

8.1.20.2. SPDIF

The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the

SPDIF functionality within the STAC9766/9767. If the SPDIF is set to a 1, then the function is

enabled. When set to a 0, it is disabled.

8.1.20.3. SPCV (SPDIF Configuration Valid)

The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When

SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the sys-

tem configuration is valid.

8.1.20.4. SPSA1, SPSA0 (SPDIF Slot Assignment)

SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following

details the slot assignment relationship between SPSA1 and SPSA0.

The STAC9766/9767 are AMAP compliant with the following table.

Table 21. AMAP Compliant

CODEC

ID Function SPSA = 00

slot assignment SPSA = 01

slot assignment SPSA = 10

slot assignment SPSA = 11

slot assignment

00 2-ch Primary w/SPDIF 3 & 4 7 & 8* 6 & 9 10 & 11

01 2-ch Dock CODEC w/SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11

10 +2-ch Surr w/ SPDIF 3 & 4 7 & 8 6 & 9* 10 & 11

11 +2-ch Cntr/LFE w/ SPDIF 3 & 4 7 & 8 6 & 9 10 & 11*

Note: * is the default slot assignment

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8.1.21. PCM DAC Rate Registers (2Ch and 32h)

The internal sample rate for the DACs and ADCs is controlled by the value in these read/write regis-

ters that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in

Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,

that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample

rate is supported and returned. Per PC 99 /PC 2001 specification, independent sample rates are

supported for record and playback.

Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h) will be loaded with BB80h

(48 KHz).

If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48 KHz.

8.1.22. PCM DAC Rate (2Ch)

Default: BB80h (see table22: page63)

8.1.23. PCM LR ADC Rate (32h)

Default: BB80h (see table22: page63)

Table 22. Hardware Supported Sample Rates

Sample Rate SR15-SR0 Value

8 KHz 1F40h

11.025 KHz 2B11h

16 KHz 3E80h

22.05 KHz 5622h

32 KHz 7D00h

44.1 KHz AC44h

48 KHz BB80h

D15 D14 D13 D12 D11 D10 D9 D8

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8

D7 D6 D5 D4 D3 D2 D1 D0

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

D15 D14 D13 D12 D11 D10 D9 D8

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8

D7 D6 D5 D4 D3 D2 D1 D0

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

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8.1.24. SPDIF Control (3Ah)

Default: 2000h

D15 D14 D13 D12 D11 D10 D9 D8

VDRS SPSR1 SPSR2 LCC6 CC5 CC4

D7 D6 D5 D4 D3 D2 D1 D0

CC3 CC2 CC1 CC0 PRE COPY /AUDIO PRO

Bit(s) Reset Value Access Name Description (note 1-2)

15 in 2.3 V

Validity: This bit affects the “Validity” flag, bit<28> transmitted in

each S/PDIF subframe, and enables the S/PDIF transmitter to

maintain connection during error or mute conditions. Subframe

bit<28> = 0 indicates that data is valid for conversion at the

receiver, 1 indicates invalid data (not suitable for conversion at

the receiver).

If “V” = 1, then each S/PDIF subframe (Left & Right) should have

bit<28> “Validity” flag = 1 or set based on the assertion or

de-assertion of the AC '97 “VFORCE” bit within the Extended

Audio Status and Control Register (D15, register 2Ah).

14 0 Read Only DRS 1 = Double Rate SPDIF support (always = 0)

13:12 10 Read & Write SPSR[1,0]

SPDIF Sample Rate.

00 - 44.1 KHz Rate

01 - Reserved

10 - 48 KHz Rate (default)

11 - 32 KHz Rate

11 0 Read & Write LGeneration Level is defined by the IEC standard, or as

appropriate.

10:4 0Read & Write CC[6, 0] Category Code is defined by the IEC standard or as appropriate

by media.

3 0 Read & Write PRE 0 = 0 µsec Pre-emphasis

1 = Pre-emphasis is 50/15 µsec

2 0 Read & Write COPY 0 = Copyright not asserted

1 = Copyright is asserted

1 0 Read & Write /AUDIO 0 = PCM data

1 = Non-Audio or non-PCM format

0 0 Read & Write PRO 0 = Consumer use of the channel

1 = Professional use of the channel

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8.2. General Purpose Input & Outputs

8.2.1. EAPD

EAPD can act as a GPIO, but is unaffected by the following registers. To use EAPD as a GPIO, use

about EAPD can also be found in Section 8.1.18.3: page59.

8.2.2. GPIO Pin Definitions

GPIO pins are programmable to have input/output functionality. The data values (status) for these

pins are all in one register with input/output configuration in a separate register. Control of GPIO pins

configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO

pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins

that are configured for output, based upon the value of the corresponding bit position of the control

slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins config-

ured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic

level detected at each GPIO pin configured for input. A GPIO output pin value that is written via slot

12 in the current frame will not affect the GPIO status that is returned in that particular write frame.

This slot-12 based control/status protocol minimizes the latency and complexity, especially for

host-based Controllers and host data pump software, and provides high speed monitoring and con-

trol, above what could be achieved with command/status slots. For host-based implementations,

most AC‘97 registers can be shadowed by the driver in order to provide immediate response when

read by the processor, and GPIO pins configured as inputs should be capable of triggering an inter-

rupt upon a change of status.

The AC-link request for GPIO pin status is always delayed by at least one frame time. Read-Mod-

ify-Writes across the AC-link incur latency issues which must be accounted for by the software driver

or AC‘97 Digital Controller firmware. PCI retries should be kept to a minimum wherever possible.

8.2.3. GPIO Pin Implementation

The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC‘97 Digi-

tal Controller to first enable the output after setting it to the desired state.

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8.2.4. Extended Modem Status and Control Register (3Eh)

Default: 0100h

8.2.5. GPIO Pin Configuration Register (4Ch)

Default: 0003h

8.2.6. GPIO Pin Polarity/Type Register (4Eh)

Default: FFFFh

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED PRA

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GPIO

Bit(s) Access Reset Value Name Description

15:9 Read Only 0RESERVED Bit not used, should read back 0

8Read / Write 1PRA 0 = GPIO powered up / enabled

1 = GPIO powered down / disabled

7:1 Read Only 0RESERVED Bit not used, should read back 0

0Read Only 0GPIO 0 = GPIO not ready (powered down)

1 = GPIO ready (powered up)

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GC1

(GPIO1) GC0

(GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0RESERVED Bit not used, should read back 0

1Read / Write 1GC1 0 = GPIO1 configured as output

1 = GPIO1 configured as input

0Read / Write 1GC0 0 = GPIO0 configured as output

1 = GPIO0 configured as input

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GP1

(GPIO1) GP0

(GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0RESERVED Bit not used, should read back 0

1Read / Write 1GP1 0 = GPIO1 Input Polarity Inverted, CMOS output drive.

1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive.

0Read / Write 1GP0 0 = GPIO0 Input Polarity Inverted, CMOS output drive.

1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.

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8.2.7. GPIO Pin Sticky Register (50h)

Default: 0000h

8.2.8. GPIO Pin Mask Register (52h)

Default: 0000h

8.2.9. GPIO Pin Status Register (54h)

Default: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GS1 (GPIO1) GS0 (GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0RESERVED Bit not used, should read back 0

1Read / Write 0GS1 0 = GPIO1 Non Sticky configuration.

1 = GPIO1 Sticky configuration.

0Read / Write 0GS0 0 = GPIO0 Non Sticky configuration.

1 = GPIO0 Sticky configuration.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GW1 (GPIO1) GW0 (GPIO0)

Bit(s) Access Reset Value Name Description

15:2 Read Only 0RESERVED Bit not used, should read back 0

1Read / Write 0GW1 0 = GPIO1 interrupt not passed to GPIO_INT slot 12.

1 = GPIO1 interrupt is passed to GPIO_INT slot 12.

0Read / Write 0GW0 0 = GPIO0 interrupt not passed to GPIO_INT slot 12.

1 = GPIO0 interrupt is passed to GPIO_INT slot 12.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED GI1 (GPIO1) GI0 (GPIO0)

Bit(s) Access Reset

Value Name Description

15:2 Read Only 0RESERVED Bit not used, should read back 0

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8.3. Extended CODEC Registers Page Structure Definition

Registers 60h-68h are the Extended CODEC Registers: These registers allow for the defi-

nition of further capabilities. These bits provide a paged address space for extended

CODEC information. The Page Selector bits in the Audio Interrupt and Paging register

(Register 24h bits 3:0) control the page of information viewed through this page window.

8.3.1. Extended Registers Page 00

Page 00 of the Extended CODEC Registers is reserved for vendor specific use. Driver writ-

ers should not access these registers unless the Vendor ID register has been checked first

to ensure that the vendor of the AC '97 component has been identified and the usage of the

vendor defined registers understood.

8.3.2. Extended Registers Page 01

The usage of Page 01 of the Extended CODEC Registers is defined in Register 24h found

in Section 8.1.17: page57.

8.3.3. Extended Registers Page 02, 03

Pages 02 and 03 of the Extended CODEC Registers are reserved for future use.

1Read / Write xGI1

When GPIO1 is configured as output and Register h74 bit[0] = 0 (default),

the value of this register will be placed on the GPIO1 pad.

When GPIO1 is configured as output and Register h74 bit[0] = 1, the

GPIO1 pad will get its value from slot12.

When GPIO1 is configured as input and configured as a sticky, writing a

1 does nothing, writing a 0 clears this bit.

When GPIO1 is configured as input, this register reflects the value on the

GPIO1 pad after interpretation of the polarity and sticky configurations.

0Read / Write xGI0

When GPIO0 is configured as output and Register h74 bit[0] = 0 (default),

the value of this register will be placed on the GPIO0 pad.

When GPIO0 is configured as output and Register h74 bit[0] = 1, the

GPIO0 pad will get its value from slot12.

When GPIO0 is configured as input and configured as a sticky, writing a

1 does nothing, writing a 0 clears this bit.

When GPIO0 is configured as input, this register reflects the value on the

GPIO0 pad after interpretation of the polarity and sticky configurations.

Bit(s) Access Reset

Value Name Description

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8.4. STAC9766/9767 Paging Registers

The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of regis-

ters. The registers currently used in the paging are 60h to 6Eh. Additional information about the

Extended CODEC Registers, please refer to Section 8.3: page68.

One of two pages can be made active at any time, set in Register 24h. Register 24h is the Audio

Interrupt and Paging Register. Additional details about Register 24h is located in Section 8.1.17:

page57.

If page 00h is active, registers 60h to 6Eh are Vendor Specific.

If page 01h is active, registers 60h to 6Eh have the following functionality:

8.4.1. CODEC Class/Rev (60h Page 01h)

Default: 12xxh

Reg NAME FUNCTION Location

60h CODEC Class/Revision Provides the CODEC Class and a Vendor specified revision

identifier. 8.4.1: page69

62h PCI SVID Allows for population by the system BIOS to identify the PCI Sub

System Vendor ID. 8.4.2: page70

64h PCI SSID Allows for population by the system BIOS to identify the PCI Sub

System ID. Note:: page70

66h Function Select Provides the type of audio function being selected and which jack

conductor the selected value is measured from. Note:: page71

68h Function Information Includes information about Gain, Inversion, Buffer delays,

Information Validity, and Function Information presence. 8.4.5: page72

6Ah Sense Register Includes information about the connector/jack location, Input verses

Output sensing, the Order of the sense results, and the IDT specific

sense results. 8.4.7: page74

6Ch Reserved

6Eh Reserved

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED CL4 CL3 CL2 CL1 CL0

D7 D6 D5 D4 D3 D2 D1 D0

RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0

Bit(s) Reset Value Name Description

15-13 RESERVED Reserved - not defined

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8.4.2. PCI SVID (62h Page 01h)

Default: FFFFh

Note: This register is populated by the BIOS and does not reset on RESET#.

8.4.3. PCI SSID (64h Page 01h)

Default: FFFFh

12-8 CL4:CL0

CODEC Compatibility Class (RO)

This is a CODEC vendor specific field to define software compatibility for

the CODEC. Software read this field together with CODEC vendor ID

(reg 7C-7Eh) to determine vendor specific programming interface

compatibility. Software can rely on vendor specific register behavior to be

compatible among vendor CODECs of the same class.

00h - Field not implemented

01h-1Fh - Vendor specific compatibility class code

Equals Vendor ID2(Reg 7Eh) bits D7 to D0

7-0 RV7:RV0

Revision ID: (RO)

This register specifies a device specific revision identifier. The value is

chosen by the vendor. Zero is an acceptable value. This field should be

viewed as a vendor defined extension to the CODEC ID. This number

changes with new CODEC stepping of the same CODEC ID.

Equals Major Rev bits (Reg 6Ch) bits D7 to D0.

D15 D14 D13 D12 D11 D10 D9 D8

PVI15 PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8

D7 D6 D5 D4 D3 D2 D1 D0

PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI1 PVI0

Bit(s) Reset Value Name Description

15-0 PVI15:PVI0

PCI Sub System Vendor ID:

This field provides the PCI Sub System Vendor ID of the Audio or Modem Sub

Assembly Vendor (i.e., CNR manufacturer, Motherboard Vendor). This is NOT the

CODEC vendor PCI Vendor ID, nor the AC '97 controller PCI Vendor ID.

If data is not available, returns FFFFh.

D15 D14 D13 D12 D11 D10 D9 D8

PI15 PI14 PI13 PI12 PI11 PI10 PI9 PI8

D7 D6 D5 D4 D3 D2 D1 D0

PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0

Bit(s) Reset Value Name Description

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Note: This register is populated by the BIOS and does not reset on RESET#.

8.4.4. Function Select (66h Page 01h)

Default: 0000h

Bit(s) Reset Value Name Description

15-0 PI15:PVI0

PCI Sub System ID:

This field provides the PCI Sub System ID of the Audio or Modem Sub Assembly

(i.e., CNR Model, Motherboard SKU). This is NOT the CODEC vendor PCI ID, nor

the AC '97 controller PCI ID. Information in this field must be available for AC '97

controller reads when CODEC ready is asserted in AC link.If data is not available,

returns FFFFh.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED FC3 FC2 FC1 FC0 T/R

Bit(s) Reset Value Name Description

15-5 Reserved Reserved

4-1 00h FC3:FC0

Function Code bits:

00h - Line Out (Master Out)

01h - Head Phone Out (AUX Out)

Setting the T/R bit to 0 = Left,1 = Right

02h - DAC 3 (C/LFE) - Not Supported

03h - SPDIF out

04h - Phone In

05h - Mic1 (Mic select = 0)

06h - Mic2 (Mic select = 1)

07h - Line In

08h - CD In

09h - Video In

0Ah - Aux In

0Bh - Mono Out

0C-0Fh - Reserved

For supported Jack and Mic Sense Functions, see Table23: page72.

The Function Code Bits are used to read Register 68h (Page 01h) and Register

6Ah (Page 01h).

Mono I/O should report relevant sense and function information on Tip, and report

not supported on Ring.

Setting the function code to unsupported values will return a 0 when accessing the

Information Valid Bit in page 01 register 68h bit 5.

0 0 T/R

Tip or Ring selection Bit.This bit sets which jack conductor the sense value is

measured from. Software will program the corresponding the Ring/Tip selector bit

together with the I/O number in bits FC[3:0].

0 - Tip (Left)

1 - Ring (Right)

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Note: This register does not reset on RESET#.

8.4.5. Function Information (68h Page 01h)

Default: 00xxh, see table 24: page73.

Function Code I/O Sense Capability

00h Line_Out Jack Sense

01h Headphone_Out Jack Sense

05h Mic1 Mic Sense

06h Mic2 Mic Sense

Table 23. Supported Jack and Mic Sense Functions

D15 D14 D13 D12 D11 D10 D9 D8

G4 G3 G2 G1 G0 INV DL4 DL3

D7 D6 D5 D4 D3 D2 D1 D0

DL2 DL1 DL0 IV RESERVED FIP

Bit(s) Reset Value Name Description

15 0 G4

Gain Sign Bit: The CODEC updates this bit with the sign of the gain value

present in G[3:0]. The BIOS updates this to take into consideration external

amplifiers or other external logic when relevant.

G[4] indicates whether the value is a gain or attenuation.

Gain in the G4 bit is in terms of dB.

This bit is Read/Write and only reset on POR and not by RESET#.

14-11 0G3:G0

Gain Bits: The CODEC updates these bits with the gain value (dB relative to

level-out) in 1.5dBV increments. The BIOS updates these to take into

consideration external amplifiers or other external logic when relevant.

G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a

gain or attenuation.

For Gain/Attenuation settings, see Table 25: page74.

These bits are read/write and are not reset on RESET#.

10 INV

Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the

signal.

0h - No inversion reported

1h - Inverted

This bit is read/write and is not reset on RESET#.

BIOS should invert for each inverting gain stage.

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9-5 DL4:DL0

Buffer delays: CODEC will provide a delay measurement for the input and output

channels. Software will use this value to accurately calculate audio stream

position with respect to what is been reproduced or recorded. These values are

in 20.83 microsecond (1/48000 second) units.

For output channels, this timing is from the end of AC Link frame in which the

sample is provided, until the time the analog signal appears at the output pin. For

input streams, this is from when the analog signal is presented at the pin until the

representative sample is provided on the AC Link.

Analog in and out paths are not considered as part of this delay.

The measurement is a 'typical' measurement, at a 48 KHz sample rate, with

minimal in-CODEC processing (i.e., 3D effects are turned off.)

00h - Information not provided

01h…1Eh - Buffer delay in 20.83 µs units

1Fh - reserved

These bits are read/write and are not reset on RESET#.

The default value is the delay internal to the CODEC. The BIOS may add to this

value the known delays external to the CODEC, such as for an external

amplifier.

4 1 IV

Information Valid Bit: Indicates whether a sensing method is provided by the

CODEC and if information field is valid. This field is updated by the CODEC.

0h--After CODEC RESET# de-assertion, it indicates the CODEC does NOT

provides sensing logic and this bit will be Read Only. After a sense cycle is

completed indicates that no information is provided on the sensing method.

1h--After CODEC RESET# de-assertion, it indicates the CODEC provides

sensing logic for this I/O and this bit is Read/Write. After clearing this bit by

writing 1, when a sense cycle is completed the assertion of this bit indicates

that there is valid information in the remaining descriptor bits. Writing “0” to

this bit has no effect.

BIOS should NOT write this bit, as it is reset on RESET#.

3-1 0RESERVED Bit not used, should read back 0

0NA FIP

Function Information Present

This bit is set to a 1 indicates that the G[4:0], INV, DL[4:0](Register 68h, Page

01h) and ST[2:0](register 6Ah, Page 01h) are supported and R/W capable.

This bit is Read Only.

Table 24. Reg 68h Default Values

Reg 66h Function Code Reg 68h Default Value

00h Line Out 0010h

01h Headphone Out 0010h

05h Mic1 0010h

06h Mic2 0010h

All other Function Codes 0000h

For RESET#: Reg 68h default value is 0000h.

Bit(s) Reset Value Name Description

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8.4.6. Digital Audio Control (6Ah, Page 00h)

To access Register 6Ah, Page 00h must be selected in Register 24h.

Default: 0000h

8.4.7. Sense Details (6Ah Page 01h)

Default: NA

Table 25. Gain or Attenuation Examples

G[4:0] Gain or Attenuation (dB relative to level-out)

00000 0 dBV

00001 +1.5 dBV

01111 +24 dBV

10001 -1.5 dBV

11111 -24 dBV

Table 26. Register 68h/Page 01h Bit Overview

Bit Bit R/W Overview

D5:D15 Read/Write and only reset on POR (Power on Reset) and not by RESET#.

D4 Read/Write and should NOT be set by the BIOS

D3:1 Reserved

D0 Read Only.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED SPOR DO1 RSVD

Bit(s) Reset Value Name Description

15:3 0RESERVED Bits not used, should read back 0

2 0 SPOR Over-ride Register 2Ah, D12 write-lock when SPDIF_EN = 1.

All bits except SPDIF sample-rate are affected (D13-D12). Allows for sub-code

changing on-the-fly.

1 0 DO1 SPDIF Digital Output Source Selection:

DO1 = 0; PCM data from the AC-Link to SPDIF

DO1 = 1; ADC record data to SPDIF

0 0 RESERVED Bits not used, should read back 0

D15 D14 D13 D12 D11 D10 D9 D8

ST2 ST1 ST0 S4 S3 S2 S1 S0

D7 D6 D5 D4 D3 D2 D1 D0

OR1 OR0 SR5 SR4 SR3 SR2 SR1 SR1

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Bit(s) Reset Value Name Description

15-13 ST2:ST0

Connector/Jack location bits

This field describes the location of the jack in the system.

0h - Rear I/O Panel

1h - Front Panel

2h - Motherboard

3h - Dock/External

4h:6h - Reserved

7h - No Connection/unused I/O

These bits are Read/Write.

12-8 S4:S0

Sensed bits meaning relates to the I/O being sense as output or inputs.

Sensed bits (outputs): See Table 27: page75.

This field allows for the reporting of the type of output peripheral/device plugged

in the jack. Values specified below should be interrogated in conjunction with

the SR[5:0] and OR[1:0] bits for accurate reporting.

Sensed bits (inputs): See Table 28: page76.

This field allows for the reporting of the type of input peripheral/device plugged

in the jack. Values specified below should be interrogated in conjunction with

the SR[5:0] and OR[1:0] bits for accurate reporting.

This field is Read Only.

7-6 OR1:0

Order Bits. These bits indicate the order the sense result bits SR[5:0] are using.

00 - 100 (i.e., Ohms)

01 - 101 (i.e., 10 Ohms)

10 - 102 (i.e., 100 Ohms)

11 - 103 (i.e., 1K Ohms)

5-0 SR5:SR0

Sense Result bits

These bits are used to report a vendor specific fingerprint or value. (Resistance,

impedance, reactance, etc.) This field is Read Only.

Table 27. Sensed Bits (Outputs)

Reported Value Output Peripheral/Device

0h Data not valid. Indicates that the reported value(s) is invalid.

1h No connection. Indicates that there are no connected devices.

2h Fingerprint. Indicates a specific fingerprint value for devices that are not specified or unknown.

3h Speakers (8 ohms)

4h Speakers (4 ohms)

5h Powered Speakers

6h Stereo Headphone

7h RESERVED

8h RESERVED

9h Headset (mono speaker left channel and mic.)

Ah Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with

OR[1:0] provide information regarding the type of device sensed.

Bh-Eh Reserved

Fh Unknown (use fingerprint)

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8.4.8. Revision Code (6Ch)

To access Register 6Ch, Page 00h must be selected in Register 24h.

Default: 00xxh

8.4.9. Analog Special (6Eh)

To access Register 6Eh, Page 00h must be selected in Register 24h.

Default: 1000h

Table 28. Sensed Bits (Inputs)

Reported Value Input Peripheral/Device

0h Data not valid. Indicates that the reported value(s) is invalid.

1h No connection. Indicates that there are no connected devices.

2h Fingerprint. Indicates a specific fingerprint value for devices that are not specified.

3h Microphone (mono)

4h Reserved

5h Stereo Line In (CE device attached)

6h Reserved

7h Reserved

8h Reserved

9h Headset (mono speaker left channel and mic.)

Ah Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with

OR[1:0] provide information regarding the type of device sensed.

Bh-Eh Reserved

Fh Unknown (use fingerprint)

D15 D14 D13 D12 D11 D10 D9 D8

MINORREV

D7 D6 D5 D4 D3 D2 D1 D0

MAJORREV

Bit(s) Reset Value Name Description

15:8 00h MINORREV Minor Revision ID. These bits are read only and will be updated based on minor

device changes which will not require software changes.

7:0 xx MAJORREV Major Revision ID. These bits are read only and will be updated based on major

device changes.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED AC97MIX RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RSVD MUTEFIX

DISABLE ADCSLT1 ADCSLT0 RSVD MIC GAIN VAL SPLYOVR EN SPLYOVR VAL

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8.4.10. Analog Current Adjust (72h)

To unlock Register 72h, write 0xABBA to Register 70h.

Default: 0000h

Bit(s) Reset Value Name Description

15:13 0RESERVED Bits not used, should read back 0

12 1AC97MIX

0 = mixer record contains a mix of all mono and stereo analog input signals,

not the DAC (ALL ANALOG mode)

1 = mixer record contains a mix of all mono and stereo analog input signals

plus the DAC signal (AC97 mode)

This bit only has an effect when either Stereo Mix or Mono Mix is selected as

the record source in Reg. 1Ah.

The “ALL” mode is useful in conjunction with the POP BYPASS mode (Reg.

20h;D15) to record all analog sources, perform further processing in the

digital domain, including combining with other PCM data, and routing through

the DACs directly to Line Out, Headphone Out, or Mono Out.

A Stereo Mix recording will be affected by the setting of the 3D Effects bit

(Reg. 20h;D13)

11:7 0 RESERVED Bits not used, should read back 0

6 0 MUTEFIX

DISABLE

0 = MUTE FIX Enabled

1 = MUTE FIX Disabled

When this bit is zero, and either channel is set to -46.5dB attenuation, 1Fh,

then that channel is fully muted. When this bit is one, then operation is per

AC’97 specification.

5:4 0ADCSLT1:0

Select slots for ADC data on ACLINK

00 = left slot 3, right slot 4

01 = left slot 7, right slot 8

10 = left slot 6, right slot 9

11 = left slot 10, right slot 11

3 0 RESERVED Reserved

2 0 MIC GAIN VAL

Adds +10dB gain to the selected MIC input. Use in conjunction with

BOOSTEN (Reg. 0Eh;D6)

BOOSTEN MICGAINVAL

0 0 = 0 dB

0 1 = 10 dB

1 0 = 20 dB

1 1 = 30 dB

1 0 SPLYOVR_EN

Supply Override bit allows override of the supply detect.

0 = no override on supply detect

1 = override supply detect with bit 0

0 0 SPLYOVR_VA

Supply Override Value provides the analog voltage operation values.

0 = force 3.3V operation

1 = force 5V operation

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

INT APOP RESERVED

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8.4.11. EAPD Access Register (74h)

Default: 0800h

Bit(s) Reset Value Name Description

15:8 0 RESERVED Reserved

7 0 INT_APOP

0 = Anti Pop Enabled

1 = Anti Pop Disabled

The STAC9766/9767 includes an internal power supply anti-pop circuit that

prevents audible clicks and pops from being heard when the CODEC is powered

on and off. This function is accomplished by delaying the charge/discharge of the

VREF capacitor (Pin 27). CVREF value of 1 µF will cause a turn-on delay of roughly

3 seconds, which will allow the power supplies to stabilize before the CODEC

outputs are enabled. The delay will be extended to 30 seconds if a CVREF value of

10 µF is used. The CODEC outputs are also kept stable for the same amount of

time at power-off to allow the system to be gracefully turned off. The INT_APOP bit

allows this delay circuit to be bypassed for rapid production testing. Any external

component anti-pop circuit is unaffected by the internal circuit.

6:0 0RESERVED Reserved

D15 D14 D13 D12 D11 D10 D9 D8

EAPD RESERVED EAPD_OEN RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED INTDIS GPIOACC GPIOSLT12

Bit(s) Reset Value Name Description

15 0 EAPD EAPD data Enable

EAPD data output on EAPD when bit D11 = 1

EAPD data input from pin when bit D11 = 0

14:12 0RESERVED Bit not used, should read back 0

11 1 EAPD_OEN EAPD Pin Enable

0 = EAPD configured as input pin

1 = EAPD configured as output pin

10:3 0RESERVED Bit not used, should read back 0

2 0 INTDIS

Interrupt disable option.

Interrupts cleared by writing a 1 to I4 (Reg24h:D15)

0 = will clear both SENSE and GPIO interrupts

1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in

Reg54h.

1 0 GPIOACC GPIO ACCESS

0 = ACLINK access from GPIO Pads

1 = ACLINK access from GPIO Register 54h

0 0 GPIOSLT12

0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot12

data will be 0h.

1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs

Reg54h will not be updated.

This can only be used if a modem CODEC is not present in the system and using

Slot12.

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8.4.12. High Pass Filter Bypass (78h*)

To unlock portion of Register 78h, write 0xABBA to Register 76h.

Default: 0000h

8.4.13. Stereo Mic Enable Register (78h*)

To unlock portion of Register 78h, write 0x7272 to Register 72h.

Default: 0000h

8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh)

These two registers contain four 8-bit ID codes. The first three codes have been assigned by

Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a IDT, Inc. assigned

code identifying the STAC9766/9767. The ID1 register (index 7Ch) contains the value 8384h, which

is the first (83h) and second (84h) bytes of the Microsoft ID code. The ID2 register (index 7Eh) con-

tains the value 7666h, which is the third (76h) byte of the Microsoft ID code, and 66h which is the

STAC9766/9767 ID code.

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RESERVED ADC HPF BYP

Bit(s) Reset Value Name Description

15:1 0RESERVED Bits not used, should read back 0

0 0 ADC HPF BYP 0 = Normal operation, (ADC High Pass Filter active)

1 = ADC High Pass Filter Bypass

D15 D14 D13 D12 D11 D10 D9 D8

RESERVED

D7 D6 D5 D4 D3 D2 D1 D0

RSVD STEREO_

MIC RESERVED

Bit(s) Reset Value Name Description

15:7 0 RESERVED Bits not used, should read back 0

6 0 STEREO_MIC 0 = Stereo Mic Disabled (default)

1 = Stereo Mic Enabled

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8.5.1. Vendor ID1 (7Ch)

Default: 8384h

8.5.2. Vendor ID2 (7Eh)

Default: 7666h

D15 D14 D13 D12 D11 D10 D9 D8

1 0 0 0 0 0 1 1

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 1 0 0

D15 D14 D13 D12 D11 D10 D9 D8

0 1 1 1 0 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 0 0 1 1 0

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9. LOW POWER MODES

The STAC9766/9767 is capable of operating at reduced power when no activity is required. The

power-down state is controlled by the Powerdown Register (26h). There are seven separate

power-down commands. The power down options are listed in Table 29. The first three bits,

PR0..PR2, can be used individually or in combination with each other, and control power distribution

to the ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and refer-

ence voltages, and can only be used in combination with PR1, PR2 and PR3. PR3 essentially

removes power from all analog sections of the CODEC and is generally only asserted when the

CODEC will not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only.

PR2 and PR3 do not need to be “set” before a PR4, but PR0 and PR1 should be “set” before PR4.

PR5 disables the DSP clock and does not require an external cold reset for recovery. PR6 disables

the headphone driver amplifier for additional analog power saving.

Figure 22. Example of STAC9766/9767 Powerdown/Powerup Flow

Figure 22 illustrates an example procedure to do a complete power down of STAC9766/9767. From

normal operation, sequential writes to the Powerdown Register are performed to power down

STAC9766/9767 a section at a time. After everything has been shut off, a final write (of PR4) can be

executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding

their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,

issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9766/9767 can

also be woken up with a cold reset. A cold reset will reset all of the registers to their default states

(Paged Registers are semi-exempt). When a section is powered back on, the Powerdown Control/

Status register (index 26h) should be read to verify that the section is ready (stable) before attempt-

ing any operation that requires it.

Table 29. Low Power Modes

GRP Bits Function

PR0 PCM in ADCs & Input Mux Powerdown

PR1 PCM out DACs Powerdown

PR2 Analog Mixer power down (VREF still on)

PR3 Analog Mixer power down (VREF off)

PR4 Digital Interface (AC-Link) power down (BIT_CLK forced low)

PR5 Digital Clock disable, BIT_CLK still on

PR6 Powerdown HEADPHONE_OUT

Warm Reset

Cold ResetReady =1

Normal ADCs off PR0 DACs off PR1 Analog off

PR2 or PR3 Digital I/F off

PR4 Shut off

AC-Link

Default

PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1

PR0=1 PR1=1 PR2=1 PR4=1

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Figure 23. Powerdown/Powerup Flow With Analog Still Alive

Figure 23 illustrates a state when all the mixers work with the static volume settings that are con-

tained in their associated registers. This configuration can be used when playing a CD (or external

LINE_IN source) through STAC9766/9767 to the speakers, with most of the system in low power

mode. The procedure for this follows the previous example except that the analog mixer is never

shut down.

Warm Reset

Normal ADCs off PR0 DACs off PR1 Digital I/F off

PR4 Shut off

AC-Link

PR0=0 & ADC=1 PR1=0 & DAC=1

PR0=1 PR1=1 PR4=1

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10.MULTIPLE CODEC SUPPORT

The STAC9766/9767 provides support for the multi-CODEC option according to the Intel AC'97, rev

2.3 specification. By definition there can be only one Primary CODEC (CODEC ID 00) and up to

three Secondary CODECs (CODEC IDs 01, 10 and 11). The CODEC ID functions as a chip select.

Secondary devices therefore have completely orthogonal register sets; each is individually accessi-

ble and they do not share registers.

10.1. Primary/Secondary CODEC Selection

In a multi-CODEC environment the CODEC ID is provided by external programming of pins 45 and

46 (CID0 and CID1). The CID pin electrical function is logically inverted from the CODEC ID desig-

nation. The corresponding pin state and its associated CODEC ID are listed in the “CODEC ID

Selection” table. Also see slot assignment discussion, “Multi-Channel Programming Register

(Index 74h)”.

10.1.1. Primary CODEC Operation

As a Primary device the STAC9766/9767 is completely compatible with existing AC'97 definitions

and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component

Specification and AC'97 Extensions. The STAC9766/9767operates as Primary by default, and the

external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for

primary operation.

When used as the Primary CODEC, the STAC9766/9767 generates the master AC-Link BIT_CLK

for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9766/9767can support

up to four loads of 10 KΩ/50 pF on the BIT_CLK output. This is to ensure that up to four CODECs

will not load down the clock output.

10.1.2. Secondary CODEC Operation

When the STAC9766/9767 is configured as a Secondary device the BIT_CLK pin is configured as an

input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything on

the AC-Link will be synchronous. As a Secondary device it can be defined as CODEC ID 01, 10, or

11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).

Table 30. CODEC ID Selection

CID1 State CID0 State CODEC ID CODEC Status

Dvdd or floating Dvdd or floating 00 Primary

Dvdd or floating 0V 01 Secondary

0V Dvdd or floating 10 Secondary

0V 0V 11 Secondary

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10.2. Secondary CODEC Register Access Definitions

The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by

using a 2-bit CODEC ID field (chip select) which is defined as the LSBs of Output Slot 0. For Sec-

ondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2

Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into

the CODEC ID field (Slot 0, bits 1 and 0).

As a Secondary CODEC, the STAC9766/9767 will disregard the Command Address and Command

Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit CODEC ID value (Slot 0, bits 1 and 0) that

matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative

Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary

writes) tag indicator.

Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state

of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid

bit for a frame with a secondary register access, even if no other bits in the output tag slot except the

Secondary CODEC ID bits are set.

This method is designed to be backward compatible with existing AC'97 controllers and CODECs.

There is no change to output Slot 1 or 2 definitions.

Using three CODECs typically requires a controller to support SDATA_IN2.

Table 31. Secondary CODEC Register Access Slot 0 Bit Definitions

Output Tag Slot (16-bits)

Bit Description

15 Frame Valid

14 Slot 1 Valid Command Address bit (†Primary CODEC only)

13 Slot 2 Valid Command Data bit (†Primary CODEC only)

12-3 Slot 3-12 Valid bits as defined by AC'97

2Reserved (Set to “0”)

†1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate

Secondary)

Note: † New definitions for Secondary CODEC Register Access

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

11.TESTABILITY

The STAC9766/9767 has two test modes. One is for ATE in-circuit test and the other is restricted for

IDT’s internal use. STAC9766/9767 enters the ATE in-circuit test mode if SDATA_OUT is sampled

high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs

(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of

the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC

from the AC-Link when another CODEC is to be used as the primary. This case will never occur dur-

ing standard operating conditions. Once either of the two test modes have been entered, the

STAC9766/9767 must be issued another RESET# with all AC-link signals held low to return to the

normal operating mode.

11.1. ATE Test Mode

ATE test mode allows for in-circuit testing to be completed at the board level. For this to work, the

outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O

pins must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a

cold reset will exit the ATE Test Mode.

Table 32. Test Mode Activation

SYNC SDATA_OUT Description

0 0 Normal AC '97 operation

0 1 ATE Test Mode

1 0 IDT Internal Test Mode

1 1 Reserved

Table 33. ATE Test Mode Operation

Pin Name Pin # Function Description

SDATA_OUT 5 1 Must be held high at the rising edge of RESET#

BIT_CLK 6Z

SDATA_IN 8Z

SYNC 10 0 Must be held low at rising edge of RESET#

RESET# 11 1

No Connect 31 ZAlways an input

No Connect 33 ZAlways an input

No Connect 34 ZAlways an input

GPIO0 43 Z

GPIO1 44 Z

CID0 45 Z

CID1 46 Z

EAPD 47 Z

SPDIF 48 Z

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

12.ORDERING INFORMATION

12.1. STAC9766/9767 Family Options and Part Order Numbers

NOTE: When ordering these parts the “yy” will be replaced with the CODEC revision. Add an “R” to

the end of any of these part numbers for delivery on Tape and Reel. The minimum order quantity for

Tape and Reel is 2,000 units for both package options.

Table 34. STAC9766/9767 Ordering Information

Part Order Number Supply Range Package

STAC9766XXTAEyyX DVdd = 3.3V, AVdd = 5.0V 48-pin RoHS QFP 7mm x 7mm x 1.4mm

STAC9767XXTAEyyX DVdd = 3.3V, AVdd = 3.3V 48-pin RoHS QFP 7mm x 7mm x 1.4mm

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

87 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

13.PIN DESCRIPTION

Figure 24. Pin Description Drawing

Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown. To Disable SPDIF, use a

1KΩ-10KΩ external pullup. Do NOT leave Pin 48 floating.

The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at

about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many

designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to

ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is

no analog CD input, then this pin can be No-Connect.

DVdd1 1

XTL_IN2

XTL_OUT3

DVss1 4

SDATA_OUT5

BIT_CLK6

DVss2 7

SDATA_IN8

DVdd2 9

SYNC 10

RESET# 11

PC_BEEP 12

24 LINE_IN_R

23 LINE_IN_L

22 MIC2

21 MIC1

20 CD_R

19 CD_GND

18 CD_L

17 VIDEO_R

16 VIDEO_L

15 AUX_R

14 AUX_L

13 PHONE

MONO_OUT 37

AVdd2 38

HP_OUT_L 39

HP_COMM 40

HP_OUT_R 41

AVss2 42

GPIO0 43

GPIO1 44

CID0 45

CID1 46

EAPD 47

SPDIF 48

48-Pin TQFP

36 LINE_OUT_R

35 LINE_OUT_L

34 NC

33 NC

32 CAP2

31 NC

30 AFILT2

29 AFILT1

28 VREFout

27 VREF

26 AVss1

25 AVdd1

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

88 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

13.1. Digital I/O

These signals connect the STAC9766/9767 to its AC'97 controller counterpart, an external crystal,

multi-CODEC selection and external audio amplifier.

13.2. Filter/References

These signals are connected to resistors, capacitors, or specific voltages.

Table 35. Digital Connection Signals

Pin Name Pin # Type Description

XTL_IN 2I24.576 MHz Crystal or External Clock Source

XTL_OUT 3I/O 24.576 MHz Crystal

SDATA_OUT 5ISerial, time division multiplexed, AC'97 input stream

BIT_CLK 6I/O 12.288 MHz serial data clock

SDATA_IN 8OSerial, time division multiplexed, AC'97 output stream

SYNC 10 I48 KHz fixed rate sample sync

RESET# 11 IAC'97 Master H/W Reset

No Connect 31 IIDT Internal Test mode only.

No Connect 33 IIDT Internal Test mode only

No Connect 34 I/O IDT Internal Test mode only

GPIO0 43 I/O General Purpose I/O

GPIO1 44 I/O General Purpose I/O

CID0 45 IMulti-CODEC ID select – bit 0

CID1 46 IMulti-CODEC ID select – bit 1

EAPD 47 I/O External Amplifier Power Down/GPIO

SPDIF 48 I/O

SPDIF digital output

Pin 48: To Enable SPDIF, use a 1KΩ-10KΩ external pulldown. To

Disable SPDIF, use a 1KΩ-10KΩ external pullup. Do NOT leave Pin 48

floating.

Table 36. Filtering and Voltage References

Signal Name Pin Number Type Description

VREF 27 OAnalog ground (0.45*Vdd, at 5V; 0.41*Vdd at 3V)

VREFOUT 28 OReference Voltage out 5mA drive (intended for mic bias) (~Vdd/2)

AFILT1 29 OAnti-Aliasing Filter Cap - ADC left channel

AFILT2 30 OAnti-Aliasing Filter Cap - ADC right channel

CAP2 32 OADC Reference Cap

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

13.3. Analog I/O

These signals connect the STAC9766/9767 to analog sources and sinks, including microphones and

speakers.

Note: * Any unused input pins should be tied together through a capacitor (0.1 µF suggested) to

ground, except the MIC inputs which should have their own capacitor to ground if not used.

Note: † The CD_GND signal is an AC signal return for the two CD input channels. It is normally

biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has

confused many designers. It should not have any DC path to GND. Connecting the CD_GND

signal directly to ground will change the internal bias of the entire CODEC, and cause significant

distortion. If there is no analog CD input, then this pin can be No-Connect.

Table 37. Analog Connection Signals

Pin Name Pin # Type Description

PC-BEEP 12 I* PC Speaker beep pass-through

PHONE 13 I* From telephony subsystem speakerphone

AUX_L 14 I* Aux Left Channel

AUX_R 15 I* Aux Right Channel

VIDEO_L 16 I* Video Audio Left Channel

VIDEO_R 17 I* Video Audio Right Channel

CD_L 18 I* CD Audio Left Channel

CD_GND†19 I* CD Audio analog signal return †

CD_R 20 I* CD Audio Right Channel

MIC1 21 I* Desktop Stereo or Mono Microphone Input

MIC2 22 I* Stereo or Second Mono Microphone Input

LINE_IN_L 23 I* Line In Left Channel

LINE_IN_R 24 I* Line In Right Channel

LINE_OUT_L 35 OLine Out Left Channel

LINE_OUT_R 36 OLine Out Right Channel

MONO_OUT 37 OTo telephony subsystem speakerphone

HP_OUT_L 39 OHeadphone Out Left Channel

HP_COMM 40 OHeadphone Ground Return

HP_OUT_R 41 OHeadphone Out Right Channel

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

13.4. Power and Ground Signals

Table 38. Power and Ground Signals

Pin Name Pin # Type Description

AVdd1 25 IAnalog Vdd = 5.0 V or 3.3 V

AVdd2 38 IAnalog Vdd = 5.0 V or 3.3 V

AVss1 26 IAnalog Gnd

AVss2 42 I Analog Gnd

DVdd1 1IDigital Vdd = 3.3 V

DVdd2 9IDigital Vdd = 3.3 V

DVss1 4IDigital Gnd

DVss2 7IDigital Gnd

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

14.PACKAGE DRAWING

14.1. 48-Pin LQFP

Figure 25. 48-Pin LQFP Package Outline and Package Dimensions

Key LQFP Dimensions in mm

Min Nom Max

A1.40 1.50 1.60

A1 0.05 0.10 0.15

A2 1.35 1.40 1.45

D8.80 9.00 9.20

D1 6.90 7.00 7.10

E8.80 9.00 9.20

E1 6.90 7.00 7.10

L0.45 0.60 0.75

e0.50

C0.09 -0.20

b0.17 0.22 0.27

48 pin LQFP

Pin 1

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

15.SOLDER REFLOW PROFILE

15.1. Standard Reflow Profile Data

Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds.

FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount

Devices” (www.jedec.org/download).

Figure 26. Solder Reflow Profile

Profile Feature Pb Free Assembly

Average Ramp-Up Rate (Tsmax - Tp) 3 oC / second max

Preheat

Temperature Min (Tsmin)

Temperature Max

(Tsmax)

Time (tsmin - tsmax)

150 oC

200 oC

60 - 180 seconds

Time maintained above Temperature (TL)

Time (tL)217 oC

60 - 150 seconds

Peak / Classification Temperature (Tp) See “Package Classification Reflow Temperatures”

on page 93.

Time within 5 oC of actual Peak Temperature (tp) 20 - 40 seconds

Ramp-Down rate 6 oC / second max

Time 25 oC to Peak Temperature 8 minutes max

Note: All temperatures refer to topside of the package, measured on the package body surface.

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

93 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

15.2. Pb Free Process - Package Classification Reflow Temperatures

Package Type MSL Reflow Temperature

LQFP 48-pin 3260 oC

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

94 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

16.APPENDIX A: PROGRAMMING REGISTERS

Reg # Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset RSRVD SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6A90h

02h Master

Volume Mute RSVD ML5 ML4 ML3 ML2 ML1 ML0 RSVD MR5 MR4 MR3 MR2 MR1 MR0 8000h

04h HP_OUT

Mixer Volume Mute RSVD HPL5 HPL4 HPL3 HPL2 HPL1 HPL0 RSVD HPR5 HPR4 HPR3 HPR2 HPR1 HPR0 8000h

06h Master

Volume

Mono Mute RSVD MM5 MM4 MM3 MM2 MM1 MM0 8000h

0Ah PC_BEEP

Volume Mute X X F7 F6 F5 FF3 F2 F1 F0 PV3 PV2 PV1 PV0 RSRVD 0000h

0Ch Phone

Volume Mute RSVD GN4 GN3 GN2 GN1 GN0 8008h

0Eh Mic

Volume Mute RSVD BOOSTEN RSVD GN4 GN3 GN2 GN1 GN0 8008h

10h Line In

Volume Mute RSVD GL4 GL3 GL2 GL1 GL0 RSVD GR4 GR3 GR2 GR1 GR0 8808h

12h CD

Volume Mute RSVD GL4 GL3 GL2 GL1 GL0 RSVD GR4 GR3 GR2 GR1 GR0 8808h

14h Video

Volume Mute RSVD GL4 GL3 GL2 GL1 GL0 RSVD GR4 GR3 GR2 GR1 GR0 8808h

16h AUX

Volume Mute RSVD GL4 GL3 GL2 GL1 GL0 RSVD GR4 GR3 GR2 GR1 GR0 8808h

18h PCM Out

Volume Mute RSVD GL4 GL3 GL2 GL1 GL0 RSVD GR4 GR3 GR2 GR1 GR0 8808h

1Ah Record

Select RSVD SL2 SL1 SL0 RSVD SR2 SR1 SR0 0000h

1Ch Record

Gain Mute RSVD GL3 GL2 GL1 GL0 RSVD GR3 GR2 GR1 GR0 8000h

20h General

Purpose POP BYP RSRVD 3D RSVD MIX MS LPBK RSVD 0000h

22h 3D

Control RSVD DP3 DP2 RSVD 0000h

24h Audio Int.

& Paging I4 I3 I2 I1 I0 RSVD PG3 PG2 PG1 PG0 0000h

26h Powerdown

Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 RSVD REF ANL DAC ADC 000Fh

28h Extended

Audio ID ID1 ID0 RSVD REV1REV0AMAP LDAC SDAC CDAC DSA1 DSA0 RSVD SPDIF DRA VRA 0A05h

2Ah Extended

Audio Control

/Status VCFG PRL/RSVD PRK/RSVD PRJ/RSVD PRI/RSVD SPCV MADC/

RSVD LDAC/

RSVD SDAC/

RSVD CDAC/

RSVD SPSA1 SPSA0 VRM/

RSVD SPDIF DRA/

RSVD VRA 0400h*

2Ch PCM DAC

Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

32h PCM LR

ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

3Ah SPDIF

Control VDRS SPSR1 SPSR2 LCC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY #PCM/

AUDIO PRO 2000h

3Eh Extended

Modem

Status RSVD PRA RSVD GPIO 0100h

4Ch GPIO Pin

Config RSVD GC1

(GPIO1) GC0

(GPIO0) 0300h

4Eh GPIO Pin

Polarity/Type RSVD GP1

(GPIO1) GP0

(GPIO0) FFFFh

50h GPIO Pin

Sticky RSVD GS1

(GPIO1) GS0

(GPIO0) 0000h

52h GPIO Pin

Mask RSVD GW1

(GPIO1) GW0

(GPIO0) 0000h

54h GPIO Pin

Status RSVD GI1

(GPIO1) GI0

(GPIO0) 0000h

60h

Page 01h CODEC

Class/Rev RSVD CL4 CL3 CL2 CL1 CL0 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0 12xxh

62h VENDOR RESERVED

62h

Page 01h PCI SVID PVI15 PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI1 PVI0 FFFFh

64h VENDOR RESERVED

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

95 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

*depends upon chip ID

64h

Page 01h PCI SID PI15 PI14 PI13 PI12 PI11 PI10 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 FFFFh

66h VENDOR RESERVED

66h

Page 01h Function

Select RSVD FC3 FC2 FC1 FC0 T/R 0000h

68h VENDOR RESERVED

68h

Page 01h Function

Information G4 G3 G2 G1 G0 INV DL4 DL3 DL2 DL1 DL0 IV RSVD FIP xxxxh

6Ah Digital

Audio

Control RSVD SPOR DO1 RSVD 0000h

6Ah

Page 01h Sense

Details ST2 ST1 ST0 S4 S3 S2 S1 S0 OR1 OR0 SR5 SR4 SR3 SR2 SR1 SR0 NA

6Ch Revision

Code 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 00xxh

6Ch

Page 01h RSVD

6Eh Analog

Special RSVD AC97

ALL MIX RSVD MUTE

FIX

DISBLE

ADC

slot1 ADC

slot0 RSVD MIC

GAIN

VALUE

SPLY

OVR

SPLY

OVR

VAL 1000h

6Eh

Page 01h RSVD

70h VENDOR RESERVED 0000h

72h Analog

Current

Adjust RSVD INT APOP RSVD 0000h

74h EAPD

Access EAPD RESERVED EAPD_OEN RSVD INTDIS GPIO

ACC GPIO

SLT12 0800h

76h VENDOR RESERVED 0000h

78h*High Pass

Filter

Bypass RSVD ADC

HPF

BYP 0000h

78h* Stereo Mic

Enable RSVD STEREO_MIC RSVD 0000h

7Ah RSVD RSVD 0000h

7Ch Vendor

ID1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 8384h

7Eh Vendor

ID2

9766 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 7666h

Reg # Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO

IDT™

96 STAC9766/9767 V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

17.REVISION HISTORY

Revision Date Description of Change

7.1 History not included in Datasheet

7.2 October 2003

Removed BIT_CLK as an input option from clocking table, it was incorrectly included in 3-1 version

Added CD_GND elaboration note on connection diagram, pin list and pin out diagrams:

“The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased

at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused

many designers. It should not have any DC path to GND. Connecting the CD_GND signal

directly to ground will change the internal bias of the entire CODEC, and cause significant

distortion. If there is no analog CD input, then this pin can be No-Connect.”

7.3 03 November 2006 Released in IDT format.

7.4 Dec 2006 corrected orderable part number

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

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+44 1372 363 339

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

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Innovate with IDT audio for high fidelity. Contact:

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STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING PC AUDIO