1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 1 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
Document Title
1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM
The attached data sheets are prepared and approved by SAMSUNG Elec tronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Elect ronics will evaluate and reply to your requests an d questions on the parameters of this device. If you have any que s-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1.0
2.0
2.1
Remark
Advance
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
History
1. Initial document.
1. Pin name change from DLL to D o ff
2. Update JTAG test conditions.
3. Reserved pin for high density name change from NC to Vss/SA
4. Delete AC test condition about Clock Input timing Reference Level
5. Delete clock description on page 2 and add HSTL I/O comment
6. Deleted R/W control pin description on page 2
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
1. Add AC electrical characteristics.
2. Change AC timing characteristics.
3. Change DC electrical characteristics(ISB1)
1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
1. Change the JTAG Block diagram
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1. Final spec release
1. Delete the x8 Org. part
1. Change the operating current parameter
before after
Isb1 -25 : 230 250
-20 : 200 230
-16 : 190 220
Draft Date
July, 15 2001
Dec, 14 2001
July, 29. 2002
Sep. 6. 2002
Oct. 7. 2002
Dec. 16, 2002
Dec. 26, 2002
Mar. 20, 2003
April. 4, 2003
Oct. 31, 2003
Dec. 1, 2003
Dec. 13, 2004
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 2 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• 1.8V+0.1V/-0. 1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply V ol tage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
• Separate independent read and write data ports
• HSTL I/O
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• Full data coherency, providing most current data.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to min i mize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmab le output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
R/W
ADDRESS
LD
C
C
D(Data in)
ADD
REG
DATA
REG
CLK
GEN
CTRL
LOGIC
1Mx36
(2Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
BWX
36 (or 18)
4(or 2)
SELECT OUTPUT CONTROL
SENSE AMPS
WRITE/READ DECODE
OUTPUT REG
OUTPUT SELECT
OUTPUT DRIVER
Notes: 1. Numbers in ( ) are for x18 device.
19
19 (or 20)
Q(Da ta Ou t)
36 (or 18)
36 72
(Echo Clock out)
CQ, CQ
Organization Part
Number Cycle
Time Access
Time Unit
X36 K7J323682M-FC25 4.0 0.45 ns
K7J323682M-FC20 5.0 0.45 ns
K7J323682M-FC16 6.0 0.50 ns
X18 K7J321882M-FC25 4.0 0.45 ns
K7J321882M-FC20 5.0 0.45 ns
K7J321882M-FC16 6.0 0.50 ns
DD R II S R AM an d Double Data Ra te II com pr ise a ne w fa m ily of prod uct s de ve lope d b y C ypr ess , Hita ch i, IDT, Micron, NE C an d S a m sung technology.
(or 18) (or 36) (or 18)
36
(or 20)
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 3 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
PIN CONFIGURATIONS(TOP VIEW) K7J323682M(1Mx36)
Notes : 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A for 288Mb.
2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.
12345678910 11
ACQ VSS/SA* NC/SA* R/W BW2KBW1LD SA VSS/SA* CQ
BQ27 Q18 D18 SA BW3KBW0SA D17 Q17 Q8
CD27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8
DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
HDoff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
ND34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1
PQ35 D35 Q26 SA SA C SA SA Q9 D0 Q0
RTDO TCK SA SA SA C SA SA SA TMS TDI
PIN NAME
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL P IN NUMBERS DESCRIPTION NOTE
K, K 6B, 6A Input Clock
C, C 6P, 6R Input Clock for Output Data 1
CQ, CQ 11A, 1A Output Echo Clock
Doff 1H DLL Disable when low
SA 9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs
D0-35 10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P Data Inputs
Q0-35 11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P Data Outputs
R/W 4A Read, Write Control Pin, Read active
when high
LD 8A Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW37B,7A,5A,5B Block Write Control Pin,active when low
VREF 2H,10H Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 2
VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V )
VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V )
VSS 2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
8M,4N,8N Ground
TMS 10R JTAG Test Mode Select
TDI 11R JTAG Test Data Input
TCK 2R JTAG Test Clock
TDO 1R JTAG Test Data Output
NC 3A No Connect 3
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 4 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
PIN CONFIGURATIONS(TOP VIEW) K7J321882M(2Mx18)
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
12345678910 11
ACQ VSS/SA* SA R/W BW1KNC LD SA VSS/SA* CQ
BNC Q9 D9 SA NC K BW0SA NC NC Q8
CNC NC D10 VSS SA SA SA VSS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HDoff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS SA SA SA VSS NC NC D1
PNC NC Q17 SA SA C SA SA NC D0 Q0
RTDO TCK SA SA SA C SA SA SA TMS TDI
PIN NAME
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL P IN NUMBERS DESCRIPTION NOTE
K, K 6B, 6A Input Clock
C, C 6P, 6R Input Clock for Output Data 1
CQ, CQ 11A, 1A Output Echo Clock
Doff 1H DLL Disable when low
SA 3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs
D0-17 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N Data Inputs
Q0-17 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P Data Outputs
R/W 4A Read, Write Control Pin, Read active
when high
LD 8A Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW17B, 5A Block Write Control Pin,active when low
VREF 2H,10H I nput Reference Voltage
ZQ 11H Output Driver Impedance Control Input 2
VDD 5F, 7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V )
VDDQ 4E,8E,4F,8F,4G, 8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V )
VSS 2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground
TMS 10R JTAG Test Mode Select
TDI 11R JTAG Test Data Input
TCK 2R JTAG Test Clock
TDO 1R JTAG Test Data Output
NC 7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P No Connect 3
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 5 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
The K7J323682M and K7J321882M are 37,748,736-bits DDR Separate I/O
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7J323682M and 2,097,152 words by 18 bits for K7J321882M.
The DDR SIO operation is possible by supporting DDR read and write operations through separat e data output and input ports.
Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports
eliminate bus turn around cycle.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.
Nybble write operation is supported with NW0 and NW1 pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7J323682M and K7J321882M are implemented with SAMSU NG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7J323682M and K7J321882M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assur e the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same struct ures
as output driver.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as l ong as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 6 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 8-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7J323682M and K7J321882M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7J323682M and K7J321882M support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7J321882M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7J323682M BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Write Operations
Programmable Impedance Output Buffer Operation
Single Clock Mode
Depth Expansion
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance upda tes are transparen t to the user and do not produce access tim e "push-outs" or other anom alous behav-
ior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
K7J323682M and K7J321882M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can′t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal
for each bank.
Before chip deselected, all read and write pending operations are completed.
Clock Consideration
K7J323682M and K7J321882M utlizes internal DLL(Delay-Lock ed Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 7 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
STATE DIAGRAM
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.
3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low
LOAD
LOAD
LOAD
LOAD
POWER-UP
NOP
LOAD NEW ADDRESS
DDR READ DDR WRITE
LOAD
LOAD
READ WRITE
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 8 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
WRITE TRUTH TABLE(x18)
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
K K BW0BW1OPERATION
↑L L WRITE ALL BYTEs ( K↑ )
↑L L WRITE ALL BYTEs ( K↑ )
↑L H WRITE BYTE 0 ( K↑ )
↑L H WRITE BYTE 0 ( K↑ )
↑H L WRITE BYTE 1 ( K↑ )
↑H L WRITE BYTE 1 ( K↑ )
↑H H WRITE NOTHING ( K↑ )
↑H H WRITE NOTHING ( K↑ )
WRITE TRUTH TABLE(x36)
Notes: 1. X means "Do n′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
K K BW0BW1BW2BW3OPERATION
↑LLLL WRITE ALL BYTEs ( K↑ )
↑LLLL WRITE ALL BYTEs ( K
↑ )
↑L H H H WRITE BYTE 0 ( K↑ )
↑L H H H WRITE BYTE 0 ( K↑ )
↑H L H H WRITE BYTE 1 ( K↑ )
↑H L H H WRITE BYTE 1 ( K↑ )
↑H H L L WRITE BYTE 2 and BYTE 3 ( K↑ )
↑H H L L WRITE BYTE 2 and BYTE 3 ( K↑ )
↑HHHH WRITE NOTHING ( K↑ )
↑HHHH WRITE NOTHING ( K
↑ )
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
KLD R/W D Q OPERATION
D(A0) D(A1) Q(A0) Q(A1)
Stopped X X Previous state Previous state Previous state Previous state Clock S top
↑H X X X High-Z High-Z No Operation
↑LHX XD
OUT at C(t+1) DOUT at C(t+2) R ead
↑L L Din at K(t+1) Din at K(t+1) High-Z High-Z Write
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 9 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
ABSOLUTE MAXIMUM RATINGS*
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.5 to 2.9 V
Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V
Voltage on Input Pin Relative to VSS VIN -0.5 to VDD+0.3 V
Storage Temperature TSTG -65 to 150 °C
Operating Temperatur e TOPR 0 to 70 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=-0.3 V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current IIL VDD=Max ; VIN=VSS to VDDQ -2 +2 µA
Output Leakage Current IOL Output Disabled, -2 +2 µA
Operating Current (x36): DDR ICC VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-25 - 700
mA 1,5-20 - 600
-16 - 500
Operating Current (x18): DDR ICC VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-25 - 670
mA 1,5-20 - 570
-16 - 470
Standby Current(NO P ): DDR ISB1
Device deselected, IOUT=0mA,
f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-25 - 250
mA 1,6-20 - 230
-16 - 220
Output High Voltage VOH1 VDDQ/2-0.12 VDDQ/2+0.12 V 2,7
Output Low Voltage VOL1 VDDQ/2-0.12 VDDQ/2+0.12 V 3,7
Output High Voltage VOH2 IOH=-1.0mA VDDQ-0.2 VDDQ V4
Output Low Voltage VOL2 IOL=1.0mA VSS 0.2 V 4
Input Low Voltage VIL -0.3 VREF-0.1 V 8,9
Input High Voltage VIH VREF+0.1 VDDQ+0.3 V 8,10
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 10 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms
VDDQ
VIL
VDDQ+0.5V 20% tKHKH(MIN)
VSS
VIH
VSS-0.5V 20% tKHKH(MIN)
Undershoot TimingOverershoot Timing
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER SYMBOL MIN MAX UNIT
Supply Voltage VDD 1.7 1.9 V
VDDQ 1.4 1.9 V
Reference Voltage VREF 0.68 0.95 V
Ground VSS 00V
VDDQ/2
50Ω
SRAM Zo=50Ω
0.75V
VREF
ZQ 250Ω
AC TEST OUTPUT LOAD
AC TEST CONDITIONS
Note: Parameters are tested with RQ=250Ω
Parameter Symbol Value Unit
Core Power Supply Voltage VDD 1.7~1.9 V
Output Power Supply Voltage VDDQ 1.4~1.9 V
Input High/Low Level VIH/VIL 1.25/0.25 V
Input Reference Level V REF 0.75 V
Input Rise/Fall Time TR/TF0.3/0.3 ns
Output Timing Reference Level VDDQ/2 V
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
PARAMETER SYMBOL MIN MAX UNIT NOTES
Input High Voltage VIH (AC) VREF + 0.2 - V 1,2
Input Low Voltage VIL (AC) - VREF - 0.2 V 1,2
VDDQ+0.25V
VSS-0.25V
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 11 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signal are R and W.
In case of BW0,BW1 (BW2, BW3, also for x36) signal follow the data setup/hold times.
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
PARAMETER SYMBOL -25 -20 -16 UNITS NOTES
MIN MAX MIN MAX MIN MAX
Clock
Clock Cycle Ti me (K, K, C, C)tKHKH 4.00 6.30 5.00 7.88 6.00 8.40 ns
Clock Phase Jitter (K, K, C, C )tKC var 0.20 0.20 0.20 ns 5
Clock High Ti me (K , K, C, C)tKHKL 1.60 2.00 2.40 ns
Clock Low Time (K, K, C, C)tKLKH 1.60 2.00 2.40 ns
Clock to Clock (K↑ → K↑, C↑ → C↑)tKHKH1.80 2.20 2.70 ns
Clock to data clock (K↑ → C↑, K↑→ C↑)tKHCH 0.00 1.80 0.00 2.30 0.00 2.80 ns
DLL Lock Time (K, C) tKC lock 1024 1024 1024 cycle 6
K Static to DL L reset tKC reset 30 30 30 ns
Output Times
C, C High to Output Valid tCHQV 0.45 0.45 0.50 ns 3
C, C High to Output Hold tCHQX -0.45 -0.45 -0.50 ns 3
C, C High to Echo Clock Valid tCHCQV 0.45 0.45 0.50 ns
C, C High to Echo Clock Hold tCHCQX -0.45 -0.45 -0.50 ns
CQ, CQ High to Output Valid tCQHQV 0.30 0.35 0.40 ns
CQ, CQ High to Output Hold tCQHQX -0.30 -0.35 -0.40 ns
C, High to Output High-Z tCHQZ 0.45 0.45 0.50 ns 3
C, High to Output Low-Z tCHQX1 -0.45 -0.45 -0.50 ns 3
Setup Times
Address valid to K rising edge tAVKH 0.50 0.60 0.70 ns
Control inputs valid to K rising edge tIVKH 0.50 0.60 0.70 ns 2
Data-in valid to K, K rising edge tDVKH 0.35 0.40 0.50 ns
Hold Times
K rising edge to address hold tKHAX 0.50 0.60 0.70 ns
K rising edge to control inputs hold tKHIX 0.50 0.60 0.70 ns
K, K rising edge to data-in hold tKHDX 0.35 0.40 0.50 ns
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 12 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
APPLICATION INRORMATION
THERMAL RESISTANCE
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
PRMETER SYMBOL TYP Unit NOTES
Junction to Ambient θJA 20.8 °C/W
Junction to Case θJC 2.3 °C/W
Junction to Pins θJB 4.3 °C/W
PIN CAPACITANCE
Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
PRMETER SYMBOL TESTCONDITION Typ MAX Unit NOTES
Address Control Input Capacitance CIN VIN=0V 4 5 pF
Input and Output Capacitance COUT VOUT=0V 6 7 pF
Clock Capacitance CCLK -56pF
SRAM#1
D
SA RWBW0Q
ZQ
K
CC
SRAM#4
R
Vt
Vt
Vt
R=50Ω Vt=VREF
Vt
Vt
R
R=250Ω
BW1KD
SA RW BW0QK
CCBW1K
Data In
Data Out
Address
R
W
BW
Return CLK
Source CLK
Return CLK
Source CLK
MEMORY
CONTROLLER
CQ
CQ
ZQ R=250Ω
CQ
CQ ZQ
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 13 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
TIMING WAVE FORMS OF READ,WRITE AND NOP
D3- 1
12345678
NOP READ READ
WRITE WRITE
READ
NOP NOP
(burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2)
D3-2 D4-1 D4-2
Q1-1 Q1-2 Q2-1 Q2-2
tDVKH
tKHDX tDVKH
tKHDX
tCHQV tCHQV
tCHQX1 tCHQX
tCHQX
tCHQZ
Q5-1 Q5-2
tCQHQV
tKHKL tKLKH tKHKH tKHKH
tCHCQV
tCHCQX
tCHCQX
tKHCH
tKHCH
tKHKL tKLKH tKHKH tKHKH
tIVKH tKHIX
A2A1 A3 A4 A5
K
LD
R/W
K
A
D
Q
C
C
CQ
CQ
tAVKH tKHAX
tCHCQV
Qxx
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
3. D3-1 refers to input to address A3+0, D3-2 refers to input to address A3+1, i.e the next internal burst address following A3+0.
4. If address A4=A5, data Q5-1=D4-1, data Q5-2=D4-2.
Write data is forwarded immediately as read results.
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 14 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to suppor t connectivity testing dur ing manufacturing and system diagnostics. I nternal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use t his device without utilizing the TAP. To disab le the TAP cont roller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V DD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
011
1
1
00
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled a s an input to the firs t ID reg i ster to allow for th e ser ial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded T DI when exiting the Shift D R
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 RESERVED Do Not Use 6
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 RESERVED Do Not Use 6
1 1 1 BYPASS Bypass Register 4
CQ
K,K
C,C
A,D
Q
CQ
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 15 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
ID REGISTER DEFINITION
Note : Part C onfiguration
/def=010 for 36Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
Part Revision Number
(31:29) Part Configuration
(28:12) Samsung JEDEC Code
(11: 1) Start Bit(0)
1Mx36 000 00def0wx0t0q0b0s0 00001001110 1
2Mx18 000 00def0wx0t0q0b0s0 00001001110 1
SCAN REGISTER DEFINITION
Part In str uction Register Bypass Register ID Register Boundar y Scan
1Mx36 3 bits 1 bit 32 bits 109 bits
2Mx18 3 bits 1 bit 32 bits 109 bits
Note: 1. NC pin s are read as "X" ( i.e. don′t care.)
ORDER PIN ID
37 10D
38 9E
39 10C
40 11D
41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 10A
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 2A
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D
71 3C
72 1D
ORDER PIN ID
73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1H
85 1J
86 2J
87 3K
88 3J
89 2K
90 1K
91 2L
92 3L
93 1M
94 1L
95 3N
96 3M
97 1N
98 2M
99 3P
100 2N
101 2P
102 1P
103 3R
104 4R
105 4P
106 5P
107 5N
108 5R
109 Internal
ORDER PIN ID
16R
26P
36N
47P
57N
67R
78R
88P
99R
10 11P
11 10P
12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 10L
22 11K
23 10K
24 9J
25 9K
26 10J
27 11J
28 11H
29 10G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E
BOUNDARY SCAN EXIT ORDER
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 16 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
JTAG DC OPERATING CONDITIONS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.7 1.8 1.9 V
Input High Level VIH 1.3 - VDD+0.3 V
Input Low Level VIL -0.3 - 0.5 V
Output High Voltage(IOH=-2mA) VOH 1.4 - VDD V
Output Low Voltage(IOL=2mA) VOL VSS -0.4V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 - ns
TCK Hig h Pulse Width tCHCL 20 - ns
TCK Low Pulse Width tCLCH 20 - ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Tim e tCHSX 5-ns
Clock Low to Output Valid tCLQV 010ns
JTAG AC TEST CONDITIONS
Note: 1. See SRAM AC test output load on page 11.
Parameter Symbol Min Unit Note
Input High/Low Level VIH/VIL 1.8/0.0 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level 0.9 V 1
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
- 17 - Rev 2.1
Dec. 2004
K7J323682M
K7J321882M
165 FBGA PACKAGE DIMENSIONS
CSide View
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
FB
∅ H
G
A
Bottom Vie w
Top View
B
A
D
E
E
Symbol Value Units Note Symbol Value Units Note
A15 ± 0.1 mm E1.0 mm
B17 ± 0.1 mm F14.0 mm
C1.3 ± 0.1 mm G10.0 mm
D0.35 ± 0.05 mm H0.5 ± 0.05 mm
