LTC3786IUD#PBF - Linear Technology Corporation

LTC3786

3786fa

Typical applicaTion

FeaTures DescripTion

Low IQ Synchronous

Boost Controller

The LTC

3786 is a high performance synchronous boost

converter controller that drives all N-channel power

MOSFETs. Synchronous rectification increases efficiency,

reduces power losses and eases thermal requirements,

allowing the LTC3786 to be used in high power boost

applications.

A 4.5V to 38V input supply range encompasses a wide

range of system architectures and battery chemistries.

When biased from the output of the boost converter or

another auxiliary supply, the LTC3786 can operate from

an input supply as low as 2.5V after start-up. The 55µA

no-load quiescent current extends operating run time in

battery-powered systems.

The operating frequency can be set for a 50kHz to 900kHz

range or synchronized to an external clock using the

internal PLL. The LTC3786 also features a precision 1.2V

reference and a power good output indicator. The SS pin

ramps the output voltage during start-up. The PLLIN/MODE

pin selects among Burst Mode

operation, pulse-skipping

mode or continuous inductor current mode at light loads.

12V to 24V/5A Synchronous Boost Converter

applicaTions

n Synchronous Operation For Highest Efficiency and

Reduced Heat Dissipation

n Wide VIN Range: 4.5V to 38V (40V Abs Max) and

Operates Down to 2.5V After Start-Up

n Output Voltages Up to 60V

n ±1% 1.2V Reference Voltage

n RSENSE or Inductor DCR Current Sensing

n 100% Duty Cycle Capability for Synchronous MOSFET

n Low Quiescent Current: 55µA

n Phase-Lockable Frequency (75kHz to 850kHz)

n Programmable Fixed Frequency (50kHz to 900kHz)

n Adjustable Output Voltage Soft-Start

n Power Good Output Voltage Monitor

n Low Shutdown Current IQ: <8µA

n Internal 5.4V LDO for Gate Drive Supply

n Thermally Enhanced 16-Pin 3mm × 3mm QFN and

MSOP Packages

n Industrial and Automotive Power Supplies

n Automotive Start-Stop Systems

n Medical Devices

n High Voltage Battery-Powered Systems

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are

registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U. S. Patents, including

5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131.

SENSE+

VBIAS

SENSE–

0.1µF

220pF

LTC3786

0.1µF

15nF

220µF

3786 TA01a

VOUT

24V

4.7µF

VIN 4.5V TO 24V

4mΩ

3.3µH

BOOST

GND

INTVCC

VFB

ITH

12.1k

8.66k

232k

FREQ

RUN

PLLIN/MODE

PGOOD

Efficiency and Power Loss

vs Load Current

OUTPUT CURRENT (A)

0.010.0010.00010.00001

EFFICIENCY (%)

POWER LOSS (mW)

0.1 1 10

3786 TA01b

100

1000

0.1

10000

VIN = 12V

VOUT = 24V

Burst Mode OPERATION

FIGURE 8 CIRCUIT

BURST

EFFICIENCY BURST

LOSS

LTC3786

3786fa

absoluTe MaxiMuM raTings

VBIAS ........................................................ –0.3V to 40V

BOOST ........................................................–0.3V to 71V

SW ............................................................. –0.3V to 65V

RUN ............................................................. –0.3V to 8V

Maximum Current Sourced into Pin

from Source >8V ..............................................100µA

PGOOD, PLLIN/MODE .................................. –0.3V to 6V

INTVCC, (BOOST – SW) ............................... –0.3V to 6V

(Notes 1, 3)

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3786EMSE#PBF LTC3786EMSE#TRPBF 3786 16-Lead Plastic MSOP –40°C to 125°C

LTC3786IMSE#PBF LTC3786IMSE#TRPBF 3786 16-Lead Plastic MSOP –40°C to 125°C

LTC3786EUD#PBF LTC3786EUD#TRPBF LFXW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C

LTC3786IUD#PBF LTC3786IUD#TRPBF LFXW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

VFB

SENSE+

SENSE–

ITH

PLLIN/MODE

FREQ

RUN

PGOOD

BOOST

VBIAS

INTVCC

GND

TOP VIEW

GND

MSE PACKAGE

16-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

16 15 14 13

5678

TOP VIEW

GND

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

1SW

PGOOD

VFB

SENSE+

GND

RUN

FREQ

BOOST

VBIAS

INTVCC

SENSE–

ITH

PLLIN/

MODE

TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

pin conFiguraTion

SENSE+, SENSE– ........................................ –0.3V to 40V

SENSE+ – SENSE– ..................................... –0.3V to 0.3V

SS, ITH, FREQ, VFB...............................–0.3V to INTVCC

Operating Junction Temperature Range ...–40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

MSE Package Only ............................................300°C

LTC3786

3786fa

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

VBIAS Chip Bias Voltage Operating Range 4.5 38 V

VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) l1.188 1.200 1.212 V

IFB Feedback Current (Note 4) ±5 ±50 nA

VREFLNREG Reference Line Voltage Regulation VBIAS = 6V to 38V 0.002 0.02 %/V

VLOADREG Output Voltage Load Regulation (Note 4)

Measured in Servo Loop;

∆ITH Voltage = 1.2V to 0.7V

Measured in Servo Loop;

∆ITH Voltage = 1.2V to 2V

0.01

–0.01

0.1

–0.1

gmError Amplifier Transconductance ITH = 1.2V 2 mmho

IQInput DC Supply Current

Pulse-Skipping or Forced Continuous Mode

Sleep Mode

Shutdown

(Note 5)

RUN = 5V; VFB = 1.25V (No Load)

RUN = 0V

0.8

µA

UVLO INTVCC Undervoltage Lockout Thresholds VINTVCC Ramping Up

VINTVCC Ramping Down

3.6

4.1

3.8

4.3 V

VRUN RUN Pin On Threshold VRUN Rising l1.18 1.28 1.38 V

VRUNHYS RUN Pin Hysteresis 100 mV

IRUNHYS RUN Pin Hysteresis Current VRUN > 1.28V 4.5 µA

IRUN RUN Pin Current VRUN < 1.28V 0.5 µA

ISS Soft-Start Charge Current VSS = 0V 7 10 13 µA

VSENSE(MAX) Maximum Current Sense Threshold VFB = 1.1V l68 75 82 mV

VSENSE(CM) SENSE Pins Common Mode Range (BOOST

Converter Input Supply Voltage VIN)

2.5 38 V

ISENSE+SENSE+ Pin Current VFB = 1.1V 200 300 µA

ISENSE–SENSE– Pin Current VFB = 1.1V ±1 µA

tr(TG) Top Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns

tf(TG) Top Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns

tr(BG) Bottom Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns

tf(BG) Bottom Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns

RUP(TG) Top Gate Pull-Up Resistance 1.2 Ω

RDN(TG) Top Gate Pull-Down Resistance 1.2 Ω

RUP(BG) Bottom Gate Pull-Up Resistance 1.2 Ω

RDN(BG) Bottom Gate Pull-Down Resistance 1.2 Ω

tD(TG/BG) Top Gate Off to Bottom Gate On Switch-On

Delay Time

CLOAD = 3300pF (Each Driver) 80 ns

tD(BG/TG) Bottom Gate Off to Top Gate On Switch-On

Delay Time

CLOAD = 3300pF (Each Driver) 80 ns

DFMAXBG Maximum BG Duty Factor 96 %

tON(MIN) Minimum BG On-Time (Note 7) 110 ns

LTC3786

3786fa

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3786 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3786E is guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3786I is guaranteed over the –40°C to 125°C operating junction

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors. The junction temperature

(TJ in °C) is calculated from the ambient temperature (TA in °C) and power

dissipation (PD in Watts) according to the formula:

TJ = TA + (PD • θJA)

where θJA = 68°C for the QFN package and θJA = 40°C for the MSOP

package.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

INTVCC Linear Regulator

VINTVCC(VIN) Internal VCC Voltage 6V < VBIAS < 38V 5.2 5.4 5.6 V

VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 %

Oscillator and Phase-Locked Loop

fPROG Programmable Frequency RFREQ = 25k

RFREQ = 60k

RFREQ = 100k

335

105

400

760

465

kHz

fLOW Lowest Fixed Frequency VFREQ = 0V 320 350 380 kHz

fHIGH Highest Fixed Frequency VFREQ = INTVCC 485 535 585 kHz

fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l75 850 kHz

PGOOD Output

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V

IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA

VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage

VFB Ramping Negative

Hysteresis

VFB Ramping Positive

Hysteresis

–12

–10

2.5

–8

tPGOOD(DELAY) PGOOD Delay PGOOD Going High to Low 25 µs

BOOST Charge Pump

IBOOST BOOST Charge Pump Available

Output Current

VSW = 12V; VBOOST – VSW = 4.5V;

FREQ = 0V, Forced Continuous or

Pulse-Skipping Mode

85 µA

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 4: The LTC3786 is tested in a feedback loop that servos VFB to the

output of the error amplifier while maintaining ITH at the midpoint of the

current limit range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: see Minimum On-Time Considerations in the Applications

Information section.

LTC3786

3786fa

Typical perForMance characTerisTics

Efficiency vs Input Voltage

Load Step

Forced Continuous Mode

Load Step

Burst Mode Operation

Load Step

Pulse-Skipping Mode Inductor Current at Light Load Soft Start-Up

Efficiency and Power Loss

vs Output Current

Efficiency and Power Loss

vs Output Current

OUTPUT CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (mW)

0.1 1 10

3786 G01

100

1000

0.1

10000

CCM EFFICIENCY

CMM LOSS

BURST EFFICIENCY

BURST LOSS

PULSE-SKIPPING EFFICIENCY

PULSE-SKIPPING LOSS

VIN = 12V

VOUT = 24V

FIGURE 8 CIRCUIT

OUTPUT CURRENT (A)

0.010.0010.00010.00001

EFFICIENCY (%)

POWER LOSS (mW)

0.1 1 10

3786 G02

100

1000

0.1

10000

VIN = 12V

VOUT = 24V

Burst Mode OPERATION

FIGURE 8 CIRCUIT

BURST

EFFICIENCY BURST

LOSS

INPUT VOLTAGE (V)

100

3786 G03

5 10 15 25

EFFICIENCY (%)

VOUT = 12V VOUT = 24V

ILOAD = 2A

FIGURE 8 CIRCUIT LOAD STEP

2A/DIV

VOUT

500mV/DIV

200µs/DIV 3786 G04

VIN = 12V

VOUT = 24V

LOAD STEP FROM 200mA TO 2.5A

FIGURE 8 CIRCUIT

INDUCTOR

CURRENT

5A/DIV

LOAD STEP

2A/DIV

VOUT

500mV/DIV

200µs/DIV 3786 G05

VIN = 12V

VOUT = 24V

LOAD STEP FROM 200mA TO 2.5A

FIGURE 8 CIRCUIT

INDUCTOR

CURRENT

5A/DIV

LOAD STEP

2A/DIV

VOUT

500mV/DIV

200µs/DIV 3786 G06

VIN = 12V

VOUT = 24V

LOAD STEP FROM 200mA TO 2.5A

FIGURE 8 CIRCUIT

INDUCTOR

CURRENT

5A/DIV Burst Mode

OPERATION

5A/DIV

PULSE-

SKIPPING MODE

5µs/DIV 3786 G07

VIN = 12V

VOUT = 24V

ILOAD = 200µA

FIGURE 8 CIRCUIT

FORCED

CONTINUOUS

MODE VOUT

5V/DIV

20ms/DIV 3786 G08

VIN = 12V

VOUT = 24V

FIGURE 8 CIRCUIT

LTC3786

3786fa

Typical perForMance characTerisTics

Shutdown Current

vs Input Voltage Quiescent Current vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Undervoltage Lockout Threshold

vs Temperature INTVCC Line Regulation INTVCC Line Regulation

Regulated Feedback Voltage

vs Temperature

Soft-Start Pull-Up Current

vs Temperature Shutdown Current vs Temperature

TEMPERATURE (°C)

–45

REGULATED FEEDBACK VOLTAGE (V)

1.209

3786 G09

1.200

1.194

–20 5 55

1.191

1.188

1.212

1.206

1.203

1.197

80 105 130

TEMPERATURE (°C)

–45

SOFT-START CURRENT (µA)

10.5

3786 G10

–20 5 55

9.0

11.0

10.0

9.5

80 105 130 –45 30

–20 5 55 80 105 130

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

7.0

9.5

10.0

10.5

11.0

6.0

8.5

6.5

9.0

5.5

5.0

8.0

7.5

3786 G11

VIN = 12V

0 15

5 10 20 25 30 35 40

INPUT VOLTAGE (V)

SHUTDOWN CURRENT (µA)

3786 G12 TEMPERATURE (°C)

–45

RUN PIN VOLTAGE (V)

3786 G14

1.25

1.15

–20 5 55

1.10

1.40

1.35

1.30

1.20

80 105 130

RUN FALLING

RUN RISING

–45 30

–20 5 55 80 105 130

TEMPERATURE (°C)

INTVCC VOLTAGE (V)

3.6

4.1

4.2

4.3

4.4

3.9

3.5

4.0

3.4

3.8

3.7

3786 G15

INTVCC RISING

INTVCC FALLING

TEMPERATURE (°C)

–45

QUIESCENT CURRENT (µA)

30 80

3786 G13

–20 5 55 105 130

VIN = 12V

VFB = 1.25V

INPUT VOLTAGE (V)

4.5

INTVCC VOLTAGE (V)

4.6

4.8

4.9

5.0

5.5

5.2

10 20 25

3786 G16

4.7

5.3

5.4

5.1

5 15 30 35 40

NO LOAD

INPUT VOLTAGE (V)

4.5

INTVCC VOLTAGE (V)

4.7

4.9

5.1

4.75 5.0 5.25 5.5

3786 G17

5.75

5.3

5.5

4.6

4.8

5.0

5.2

5.4

6.0

NO LOAD

LTC3786

3786fa

Typical perForMance characTerisTics

Oscillator Frequency

vs Input Voltage

Maximum Current Sense

Threshold vs ITH Voltage

SENSE Pin Input Current

vs Temperature

SENSE Pin Input Current

vs ITH Voltage

SENSE Pin Input Current

vs VSENSE Voltage

Maximum Current Sense

Threshold vs Duty Cycle

INTVCC vs Load Current INTVCC vs Load Current

Oscillator Frequency

vs Temperature

TEMPERATURE (°C)

–45

300

FREQUENCY (kHz)

350

600

450

555 80

500

550

400

–20 30 105 130

3786 G20

FREQ = GND

FREQ = INTVCC

5 10 20 25 30 35 40

INPUT VOLTAGE (V)

OSCILLATOR FREQUENCY (kHz)

344

354

356

358

360

350

342

352

340

348

346

3786 G21

FREQ = GND

TEMPERATURE (°C)

–45

SENSE CURRENT (µA)

555 80

160

200

240

120

100

180

220

260

140

–20 30 105 130

3786 G23

SENSE+ PIN

SENSE– PIN

VSENSE = 12V

ITH VOLTAGE (V)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

120

100

0.6 1.0

3786 G22

0.2 0.4 0.8 1.2 1.4

–40

–20

–60

PULSE-SKIPPING MODE

FORCED CONTINUOUS MODE

Burst Mode OPERATION

ITH VOLTAGE (V)

SENSE CURRENT (µA)

122.5

160

200

240

120

100

180

220

260

140

0.5 1.5 3

3786 G24

SENSE+ PIN

SENSE– PIN

VSENSE = 12V

VSENSE COMMON MODE VOLTAGE (V)

2.5

SENSE CURRENT (µA)

17.5 27.5 32.5

160

200

240

120

100

180

220

260

140

7.5 12.5 22.5 37.5

3786 G25

SENSE+ PIN

SENSE– PIN

DUTY CYCLE (%)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

100

20 40

10 90

30 50 80

60 100

120

3786 G26

LOAD CURRENT (mA)

5.15

INTVCC VOLTAGE (V)

5.20

5.30

5.35

12040

5.50

3786 G18

5.25

20 60 100 160140

80 180

5.40

5.45

VIN = 12V

LOAD CURRENT (mA)

4.0

INTVCC VOLTAGE (V)

4.2

4.4

4.6

4.8

5.2

10 20 30 40

3786 G19

50 60

5.0

VIN = 5V

LTC3786

3786fa

Typical perForMance characTerisTics

Charge Pump Charging Current

vs Operating Frequency

Charge Pump Charging Current

vs Switch Voltage

pin FuncTions

(MSOP/QFN)

VFB (Pin 1/Pin 3): Error Amplifier Feedback Input. This

pin receives the remotely sensed feedback voltage from

an external resistive divider connected across the output.

SENSE+ (Pin 2/Pin 4): Positive Current Sense Comparator

Input. The (+) input to the current comparator is normally

connected to the positive terminal of a current sense resis-

tor. The current sense resistor is normally placed at the

input of the boost controller in series with the inductor.

This pin also supplies power to the current comparator.

SENSE– (Pin 3/Pin 5): Negative Current Sense Comparator

Input. The (–) input to the current comparator is normally

connected to the negative terminal of a current sense re-

sistor connected in series with the inductor. The common

mode voltage range on the SENSE+ and SENSE– pins is

2.5V to 38V (40V abs max).

ITH (Pin 4/Pin 6): Current Control Threshold and Error

Amplifier Compensation Point. The voltage on this pin

sets the current trip threshold.

SS (Pin 5/Pin 7): Output Soft-Start Input. A capacitor to

ground at this pin sets the ramp rate of the output voltage

during start-up.

PLLIN/MODE (Pin 6/Pin 9): External Synchronization Input

to Phase Detector and Forced Continuous Mode Input.

When an external clock is applied to this pin, it will force

the controller into forced continuous mode of operation

and the phase-locked loop will force the rising BG signal

to be synchronized with the rising edge of the external

clock. When not synchronizing to an external clock, this

input determines how the LTC3786 operates at light loads.

Pulling this pin to ground selects Burst Mode operation.

An internal 100k resistor to ground also invokes Burst

Mode operation when the pin is floated. Tying this pin

to INTVCC forces continuous inductor current operation.

Tying this pin to a voltage greater than 1.2V and less than

INTVCC – 1.3V selects pulse-skipping operation. This can

be done by adding a 100k resistor between the PLLIN/

MODE pin and INTVCC.

OPERATING FREQUENCY (kHz)

50 150

CHARGE PUMP CHARGING CURRENT (µA)

250 350 450 550 650

3786 G27

750

110

100

–45°C

130°C

25°C

VBOOST = 16.5V

VSW = 12V

SWITCH VOLTAGE (V)

CHARGE PUMP CHARGING CURRENT (µA)

100

120

20 30

3786 G28

10 15 25 35 40

FREQ = 0V

FREQ = INTVCC

LTC3786

3786fa

pin FuncTions

(MSOP/QFN)

FREQ (Pin 7/Pin 9): The Frequency Control Pin for the

Internal VCO. Connecting the pin to GND forces the VCO

to a fixed low frequency of 350kHz. Connecting the pin

to INTVCC forces the VCO to a fixed high frequency of

535kHz. The frequency can be programmed from 50kHz

to 900kHz by connecting a resistor from the FREQ pin to

GND. The resistor and an internal 20µA source current

create a voltage used by the internal oscillator to set the

frequency. Alternatively, this pin can be driven with a DC

voltage to vary the frequency of the internal oscillator.

RUN (Pin 8/Pin 10): Run Control Input. Forcing this pin

below 1.28V shuts down the controller. Forcing this pin

below 0.7V shuts down the entire LTC3786, reducing

quiescent current to approximately 8µA. An external

resistor divider connected to VIN can set the threshold

for converter operation. Once running, a 4.5µA current is

sourced from the RUN pin allowing the user to program

hysteresis using the resistor values.

GND (Pin 9, Exposed Pad Pin 17/ Pin 11, Exposed Pad

Pin 17): Ground. Connects to the source of the bottom

(main) N-channel MOSFET and the (–) terminal(s) of CIN

and COUT

. All small-signal components and compensa-

tion components should also connect to this ground.

The exposed pad must be soldered to the PCB for rated

thermal performance.

BG (Pin 10/Pin 12): Bottom Gate. Connect to the gate of

the main N-channel MOSFET.

INTVCC (Pin 11/Pin 13): Output of Internal 5.4V LDO.

Power supply for control circuits and gate drivers. De-

couple this pin to GND with a minimum 4.7µF low ESR

ceramic capacitor.

VBIAS (Pin 12/Pin 14): Main Supply Pin. It is normally

tied to the input supply VIN or to the output of the boost

converter. A bypass capacitor should be tied between this

pin and the GND pin. The operating voltage range on this

pin is 4.5V to 38V (40V abs max).

BOOST (Pin 13/Pin 15): Floating Power Supply for the

Synchronous MOSFET. Bypass to SW with a capacitor

and supply with a Schottky diode connected to INTVCC.

TG (Pin 14/Pin 16): Top Gate. Connect to the gate of the

synchronous NMOS.

SW (Pin 15/Pin 1): Switch Node. Connect to the source

of the synchronous top MOSFET, the drain of the main

bottom MOSFET, and the inductor.

PGOOD (Pin 16/Pin 2): Power Good Indicator. Open-drain

logic output that is pulled to ground when the output volt-

age is more than ±10 % away from the regulated output

voltage. To avoid false trips the output voltage must be

outside of the range for 25µs before this output is activated.

LTC3786

3786fa

block DiagraM

SWITCHING

LOGIC

AND

CHARGE

PUMP

3.8V

VBIAS

VIN

CIN

INTVCC

PLLIN/

MODE

PGOOD

1.32V

1.08V

–

VFB

5.4V

LDO

VCO

PFD

0.425V

SENS LO

BOOST

TG CB

COUT

VOUT

INTVCC

VFB

1.32V

1.2V

RSENSE

10µA

SHDN

2.5V

SENS

ITH CC

CSS

CC2

0.7V

2.8V

SLOPE COMP

2mV SENSE–

SENSE+

SLEEP

SHDN

CLK

RUN

GND

INTVCC

FREQ

–

3786 BD

20µA

100k

SYNC

DET

0.5µA/

4.5µA

11V

–

ICMP IREV

LTC3786

3786fa

operaTion

(Refer to the Block Diagram)

Main Control Loop

The LTC3786 uses a constant-frequency, current mode

step-up control architecture. During normal operation,

the external bottom MOSFET is turned on when the clock

sets the RS latch, and is turned off when the main current

comparator, ICMP

, resets the RS latch. The peak inductor

current at which ICMP trips and resets the latch is con-

trolled by the voltage on the ITH pin, which is the output

of the error amplifier, EA. The error amplifier compares

the output voltage feedback signal at the VFB pin, (which

is generated with an external resistor divider connected

across the output voltage, VOUT

, to ground) to the internal

1.200V reference voltage. In a boost converter, the required

inductor current is determined by the load current, VIN and

VOUT

. When the load current increases, it causes a slight

decrease in VFB relative to the reference, which causes the

EA to increase the ITH voltage until the average inductor

current in each channel matches the new requirement

based on the new load current.

After the bottom MOSFET is turned off each cycle, the

top MOSFET is turned on until either the inductor current

starts to reverse, as indicated by the current comparator

IR, or the beginning of the next clock cycle.

INTVCC Power

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTVCC pin. The

VBIAS LDO (low dropout linear regulator) supplies 5.4V

from VBIAS to INTVCC.

Shutdown and Start-Up (RUN and SS Pins)

The LTC3786 can be shut down using the RUN pin. Pulling

this pin below 1.28V shuts down the main control loop.

Pulling this pin below 0.7V disables the controller and

most internal circuits, including the INTVCC LDOs. In this

state, the LTC3786 draws only 8µA of quiescent current.

Note: Do not apply load while the chip is in shutdown. The

output MOSFET will be turned off during shutdown and

the output load may cause excessive power dissipation

in the body diode.

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low imped-

ance source, do not exceed the absolute maximum rating

of 8V. The RUN pin has an internal 11V voltage clamp

that allows the RUN pin to be connected through a resis-

tor to a higher voltage (for example, VIN), as long as the

maximum current into the RUN pin does not exceed 100µA.

An external resistor divider connected to VIN can set the

threshold for converter operation. Once running, a 4.5µA

current is sourced from the RUN pin allowing the user to

program hysteresis using the resistor values.

The start-up of the controller’s output voltage, VOUT

, is

controlled by the voltage on the SS pin. When the voltage

on the SS pin is less than the 1.2V internal reference, the

LTC3786 regulates the VFB voltage to the SS pin voltage

instead of the 1.2V reference. This allows the SS pin to

be used to program a soft-start by connecting an external

capacitor from the SS pin to GND. An internal 10µA pull-

up current charges this capacitor creating a voltage ramp

on the SS pin. As the SS voltage rises linearly from 0V to

1.2V, the output voltage rises smoothly to its final value.

Light Load Current Operation—Burst Mode Operation,

Pulse-Skipping or Continuous Conduction

(PLLIN/MODE Pin)

The LTC3786 can be enabled to enter high efficiency Burst

Mode operation, constant-frequency pulse-skipping mode

or forced continuous conduction mode at low load cur-

rents. To select Burst Mode operation, tie the PLLIN/MODE

pin to ground. To select forced continuous operation, tie

the PLLIN/MODE pin to INTVCC. To select pulse-skipping

mode, tie the PLLIN/MODE pin to a DC voltage greater

than 1.2V and less than INTVCC – 1.3V.

When the controller is enabled for Burst Mode opera-

tion, the minimum peak current in the inductor is set to

approximately 30% of the maximum sense voltage even

though the voltage on the ITH pin indicates a lower value.

If the average inductor current is higher than the required

current, the error amplifier, EA, will decrease the voltage

on the ITH pin. When the ITH voltage drops below 0.425V,

the internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off. The ITH pin is

then disconnected from the output of the EA and parked

at 0.450V.

LTC3786

3786fa

operaTion

(Refer to the Block Diagram)

In sleep mode, much of the internal circuitry is turned off

and the LTC3786 draws only 55µA of quiescent current.

In sleep mode, the load current is supplied by the output

capacitor. As the output voltage decreases, the EA’s output

begins to rise. When the output voltage drops enough,

the ITH pin is reconnected to the output of the EA, the

sleep signal goes low, and the controller resumes normal

operation by turning on the bottom external MOSFET on

the next cycle of the internal oscillator.

When the controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse-

current comparator (IR) turns off the top external MOSFET

just before the inductor current reaches zero, preventing

it from reversing and going negative. Thus, the controller

operates in discontinuous current operation.

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

the Frequency Selection and Phase-Locked Loop section),

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as

in normal operation. In this mode, the efficiency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantages of lower output

voltage ripple and less interference to audio circuitry, as

it maintains constant-frequency operation independent

of load current.

When the PLLIN/MODE pin is connected for pulse-skipping

mode, the LTC3786 operates in PWM pulse-skipping mode

at light loads. In this mode, constant-frequency operation

is maintained down to approximately 1% of designed

maximum output current. At very light loads, the current

comparator ICMP may remain tripped for several cycles

and force the external bottom MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

The selection of switching frequency is a trade-off between

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3786’s controllers can

be selected using the FREQ pin.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to GND, tied to

INTVCC, or programmed through an external resistor. Tying

FREQ to GND selects 350kHz while tying FREQ to INTVCC

selects 535kHz. Placing a resistor between FREQ and GND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 5.

A phase-locked loop (PLL) is available on the LTC3786

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3786’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of the external bottom MOSFET to the rising edge

of the synchronizing signal.

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of BG. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

LTC3786

3786fa

operaTion

(Refer to the Block Diagram)

The typical capture range of the LTC3786’s PLL is from

approximately 55kHz to 1MHz, and is guaranteed to lock

to an external clock source whose frequency is between

75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

Operation When VIN > Regulated VOUT

When VIN rises above the regulated VOUT voltage, the boost

controller can behave differently depending on the mode,

inductor current and VIN voltage. In forced continuous

mode, the loop keeps the top MOSFET on continuously once

VIN rises above VOUT

. The internal charge pump delivers

current to the boost capacitor to maintain a sufficiently

high TG voltage. (The amount of current the charge pump

can deliver is characterized by two curves in the Typical

Performance Characteristics section.)

In pulse-skipping mode, if VIN is between 100% and 110%

of the regulated VOUT voltage, TG turns on if the inductor

current rises above a certain threshold and turns off if the

inductor current falls below this threshold. This threshold

current is set to approximately 4% of the maximum ILIM

current. If the controller is programmed to Burst Mode

operation under this same VIN window, then TG remains

off regardless of the inductor current.

If VIN rises above 110% of the regulated VOUT voltage in

any mode, the controller turns on TG regardless of the

inductor current. In Burst Mode operation, however, the

internal charge pump turns off if the chip is asleep. With

the charge pump off, there would be nothing to prevent

the boost capacitor from discharging, resulting in an

insufficient TG voltage needed to keep the top MOSFET

completely on. To prevent excessive power dissipation

across the body diode of the top MOSFET in this situa-

tion, the chip can be switched over to forced continuous

or pulse-skipping mode to enable the charge pump, or a

Schottky diode can also be placed in parallel to the top

MOSFET.

Power Good

The PGOOD pin is connected to an open-drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the PGOOD pin low when the VFB pin voltage is not

within ±10% of the 1.2V reference voltage. The PGOOD

pin is also pulled low when the corresponding RUN pin

is low (shut down). When the VFB pin voltage is within

the ±10% requirement, the MOSFET is turned off and the

pin is allowed to be pulled up by an external resistor to a

source of up to 6V (abs max).

Operation at Low SENSE Pin Common Mode Voltage

The current comparator in the LTC3786 is powered directly

from the SENSE+ pin. This enables the common mode

voltage of SENSE+ and SENSE– pins to operate as low

as 2.5V, which is below the INTVCC UVLO threshold. The

figure on the first page shows a typical application when

the controller’s VBIAS is powered from VOUT while VIN

supply can go as low as 2.5V. If the voltage on SENSE+

drops below 2.5V, the SS pin will be held low. When the

SENSE+ voltage returns to the normal operating range, the

SS pin will be released, initiating a new soft-start cycle.

BOOST Supply Refresh and Internal Charge Pump

The top MOSFET driver is biased from the floating boot-

strap capacitor, CB, which normally recharges during each

cycle through an external diode when the bottom MOSFET

turns on. There are two considerations to keep the BOOST

supply at the required bias level. During start-up, if the

bottom MOSFET is not turned on within 100µs after UVLO

goes low, the bottom MOSFET will be forced to turn on

for ~400ns. This forced refresh generates enough BOOST-

SW voltage to allow the top MOSFET to be fully enhanced

instead of waiting for the initial few cycles to charge the

bootstrap capacitor, CB. There is also an internal charge

pump that keeps the required bias on BOOST. The charge

pump always operates in both forced continuous mode

and pulse-skipping mode. In Burst Mode operation, the

charge pump is turned off during sleep and enabled when

the chip wakes up. The internal charge pump can normally

supply a charging current of 85µA.

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applicaTions inForMaTion

The Typical Application on the first page is a basic LTC3786

application circuit. LTC3786 can be configured to use either

inductor DCR (DC resistance) sensing or a discrete sense

resistor (RSENSE) for current sensing. The choice between

the two current sensing schemes is largely a design trade-

off between cost, power consumption and accuracy. DCR

sensing is becoming popular because it does not require

current sensing resistors and is more power efficient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection is

driven by the load requirement, and begins with the se-

lection of RSENSE (if RSENSE is used) and inductor value.

Next, the power MOSFETs are selected. Finally, input and

output capacitors are selected.

SENSE+ and SENSE– Pins

The SENSE+ and SENSE– pins are the inputs to the cur-

rent comparators. The common mode input voltage range

of the current comparators is 2.5V to 38V. The current

sense resistor is normally placed at the input of the boost

controller in series with the inductor.

The SENSE+ pin also provides power to the current com-

parator. It draws ~200µA during normal operation. There

is a small base current of less than 1µA that flows into

the SENSE– pin. The high impedance SENSE– input to the

current comparators allows accurate DCR sensing.

Filter components mutual to the sense lines should be

placed close to the LTC3786, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 1). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmed current limit unpredictable. If DCR sensing

is used (Figure 2b), sense resistor R1 should be placed

close to the switching node, to prevent noise from coupling

into sensitive small-signal nodes.

Sense Resistor Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 2a. RSENSE is chosen based on the required

output current.

The current comparator has a maximum threshold

VSENSE(MAX) of 75mV. The current comparator threshold

sets the peak of the inductor current, yielding a maximum

average inductor current, IMAX, equal to the peak value

VIN

TO SENSE FILTER,

NEXT TO THE CONTROLLER

INDUCTOR OR RSENSE 3786 F01

(OPTIONAL)

VIN

VOUT

3786 F02a

LTC3786

INTVCC

BOOST

SENSE+

SENSE–

VBIAS

SGND

INDUCTOR

DCR

LTC3786

INTVCC

BOOST

SENSE+

SENSE–

R2C1

VBIAS VIN

VOUT

PLACE C1 NEAR SENSE PINS

SGND

3786 F02b

(R1||R2) • C1 = L

DCR RSENSE(EQ) = DCR • R2

R1 + R2

(2b) Using the Inductor DCR to Sense Current(2a) Using a Resistor to Sense Current

Figure 2. Two Different Methods of Sensing Current

Figure 1. Sense Lines Placement with Inductor or Sense Resistor

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applicaTions inForMaTion

less half the peak-to-peak ripple current, ∆IL. To calculate

the sense resistor value, use the equation:

RSENSE =VSENSE(MAX)

IMAX +∆IL

When using the controller in low VIN and very high voltage

output applications, the maximum inductor current and

correspondingly the maximum output current level will

be reduced due to the internal compensation required to

meet stability criterion for boost regulators operating at

greater than 50% duty factor. A curve is provided in the

Typical Performance Characteristics section to estimate

this reduction in peak inductor current level depending

upon the operating duty factor.

Inductor DCR Sensing

For applications requiring the highest possible efficiency

at high load currents, the LTC3786 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor can be less than 1mΩ

for high current inductors. In a high current application

requiring such an inductor, conduction loss through a

sense resistor could reduce the efficiency by a few percent

compared to DCR sensing.

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

the inductor DCR multiplied by R2/(R1 + R2). R2 scales the

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature. Consult

the manufacturer’s data sheets for detailed information.

Using the inductor ripple current value from the inductor

value calculation section, the target sense resistor value is:

RSENSE(EQUIV) =VSENSE(MAX)

IMAX +∆IL

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the maximum current sense threshold

(VSENSE(MAX)).

Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of resistance, which is approximately 0.4%/°C. A

conservative value for the maximum inductor temperature

(TL(MAX)) is 100°C.

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

RD=

SENSE(EQUIV)

DCRMAX at T

L(MAX)

C1 is usually selected to be in the range of 0.1µF to 0.47µF.

This forces R1|| R2 to around 2k, reducing error that might

have been caused by the SENSE– pin’s ±1µA current.

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

R1|| R2 =L

DCR at 20°C

( )

•C1

The sense resistor values are:

R1=R1|| R2

; R2 =R1•RD

1– RD

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at VIN = 1/2 VOUT :

PLOSS _ R1 =VOUT •V

( )

•V

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

to the extra switching losses incurred through R1. However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

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Inductor Value Calculation

The operating frequency and inductor selection are in-

terrelated in that higher operating frequencies allow the

use of smaller inductor and capacitor values. Why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

of MOSFET gate charge and switching losses. Also, at

higher frequency, the duty cycle of body diode conduction

is higher, which results in lower efficiency. In addition to

this basic trade-off, the effect of inductor value on ripple

current and low current operation must also be considered.

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆IL decreases with higher

inductance or frequency and increases with higher VIN:

∆IL=V

f•L1– V

VOUT













Accepting larger values of ∆IL allows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ∆IL = 0.3(IMAX). The maximum

∆IL occurs at VIN = 1/2 VOUT

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit determined by RSENSE. Lower

inductor values (higher ∆IL) will cause this to occur at

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease. Once the value of L is known, an

inductor with low DCR and low core losses should be

selected.

Power MOSFET Selection

Two external power MOSFETs must be selected for the

LTC3786: one N-channel MOSFET for the bottom (main)

switch, and one N-channel MOSFET for the top (synchro-

nous) switch.

The peak-to-peak gate drive levels are set by the INTVCC

voltage. This voltage is typically 5.4V. Consequently, logic-

level threshold MOSFETs must be used in most applica-

tions. Pay close attention to the BVDSS specification for

the MOSFETs as well; many of the logic level MOSFETs

are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, RDS(ON), Miller capacitance, CMILLER, input

voltage and maximum output current. Miller capacitance,

CMILLER, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturer’s data

sheet. CMILLER is equal to the increase in gate charge

along the horizontal axis while the curve is approximately

flat divided by the specified change in VDS. This result is

then multiplied by the ratio of the application applied VDS

to the gate charge curve specified VDS. When the IC is

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

Main Switch Duty Cycle =

OUT

– V

VOUT

Synchronous Switch Duty Cycle = V

VOUT

If the maximum output current is IOUT(MAX) and each chan-

nel takes one-half of the total output current, the MOSFET

power dissipations in each channel at maximum output

current are given by:

PMAIN =VOUT – V

( )

VOUT

IN2•IOUT(MAX)2•1+ δ

( )

•RDS(ON) +k•VOUT3•IOUT(MAX)

•RDR

• CMILLER •f

SYNC =V

VOUT

•IOUT(MAX)2•1+ δ

( )

•RDS(ON)

where δ is the temperature dependency of RDS(ON)

(approximately 1Ω) is the effective driver resistance at the

MOSFET’s Miller threshold voltage. The constant k, which

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applicaTions inForMaTion

accounts for the loss caused by reverse recovery current,

is inversely proportional to the gate drive current and has

an empirical value of 1.7.

Both MOSFETs have I2R losses while the bottom N-channel

equation includes an additional term for transition losses,

which are highest at low input voltages. For high VIN the

high current efficiency generally improves with larger

MOSFETs, while for low VIN the transition losses rapidly

increase to the point that the use of a higher RDS(ON) device

with lower CMILLER actually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the bottom switch duty factor is low or dur-

ing overvoltage when the synchronous switch is on close

to 100% of the period.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

CIN and COUT Selection

The input ripple current in a boost converter is relatively

low (compared with the output ripple current), because

this current is continuous. The input capacitor, CIN, volt-

age rating should comfortably exceed the maximum input

voltage. Although ceramic capacitors can be relatively

tolerant of overvoltage conditions, aluminum electrolytic

capacitors are not. Be sure to characterize the input voltage

for any possible overvoltage transients that could apply

excess stress to the input capacitors.

The value of the CIN is a function of the source impedance,

and in general, the higher the source impedance, the higher

the required input capacitance. The required amount of

input capacitance is also greatly affected by the duty cycle.

High output current applications that also experience high

duty cycles can place great demands on the input supply,

both in terms of DC current and ripple current.

In a boost converter, the output has a discontinuous current,

so COUT must be capable of reducing the output voltage

ripple. The effects of ESR (equivalent series resistance)

and the bulk capacitance must be considered when choos-

ing the right capacitor for a given output ripple voltage.

The steady ripple voltage due to charging and discharging

the bulk capacitance in a single phase boost converter is

given by:

VRIPPLE =IOUT(MAX) •VOUT – VIN(MIN)

( )

COUT •VOUT •f V

where COUT is the output filter capacitor.

The steady ripple due to the voltage drop across the ESR

is given by:

∆VESR = IL(MAX) • ESR

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefficient.

Capacitors are now available with low ESR and high ripple

current ratings (i.e., OS-CON and POSCAP).

Setting Output Voltage

The LTC3786 output voltage is set by an external feedback

resistor divider carefully placed across the output, as shown

in Figure 3. The regulated output voltage is determined by:

VOUT =1.2V 1+RB











Great care should be taken to route the VFB line away

from noise sources, such as the inductor or the SW line.

Also, keep the VFB node as small as possible to avoid

noise pickup.

LTC3786

VFB

VOUT

3786 F03

Figure 3. Setting Output Voltage

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Soft-Start (SS Pin)

The start-up of the VOUT is controlled by the voltage on

the SS pin. When the voltage on the SS pin is less than

the internal 1.2V reference, the LTC3786 regulates the VFB

pin voltage to the voltage on the SS pin instead of 1.2V.

Soft-start is enabled by simply connecting a capacitor from

the SS pin to ground, as shown in Figure 4. An internal

10µA current source charges the capacitor, providing a

linear ramping voltage at the SS pin. The LTC3786 will

regulate the VFB pin (and hence, VOUT) according to the

voltage on the SS pin, allowing VOUT to rise smoothly

from VIN to its final regulated value. The total soft-start

time will be approximately:

tSS =CSS •

1.2V

10µA

temperature, the LTC3786 INTVCC current is limited to

less than 20mA in the QFN package from a 40V supply:

TJ = 70°C + (20mA)(40V)(68°C/W) = 125°C

In an MSOP package, the INTVCC current is limited to less

than 34mA from a 40V supply:

TJ = 70°C + (34mA)(40V)(40°C/W) = 125°C

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (PLLIN/MODE

= INTVCC) at maximum VBIAS.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors, CB, connected to the

BOOST pin supplies the gate drive voltage for the topside

MOSFET. Capacitor CB in the Block Diagram is charged

though external diode, DB, from INTVCC when the SW pin

is low. When the topside MOSFET is to be turned on, the

driver places the CB voltage across the gate-source of the

desired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

VOUT and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the output voltage: VBOOST

= VOUT + VINTVCC. The value of the boost capacitor, CB,

needs to be 100 times that of the total input capacitance

of the topside MOSFET(s). The reverse breakdown of the

external Schottky diode must be greater than VIN(MAX).

The external diode DB can be a Schottky diode or silicon

diode, but in either case it should have low leakage and fast

recovery. Pay close attention to the reverse leakage at high

temperatures where it generally increases substantially.

The topside MOSFET driver includes an internal charge

pump that delivers current to the bootstrap capacitor from

the BOOST pin. This charge current maintains the bias

voltage required to keep the top MOSFET on continuously

during dropout/overvoltage conditions. The Schottky/

silicon diode selected for the topside driver should have a

reverse leakage less than the available output current the

charge pump can supply. Curves displaying the available

charge pump current under different operating conditions

can be found in the Typical Performance Characteristics

section.

LTC3786

CSS

SGND

3786 F04

Figure 4. Using the SS Pin to Program Soft-Start

INTVCC Regulator

The LTC3786 features an internal P-channel low dropout

linear regulator (LDO) that supplies power at the INTVCC

pin from the VBIAS supply pin. INTVCC powers the gate

drivers and much of the LTC3786’s internal circuitry. The

VBIAS LDO regulates INTVCC to 5.4V. It can supply at least

50mA and must be bypassed to ground with a minimum

of 4.7µF ceramic capacitor. Good bypassing is needed to

supply the high transient currents required by the MOSFET

gate drivers.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the

maximum junction temperature rating for the LTC3786

to be exceeded. The power dissipation for the IC is equal

to VBIAS • IINTVCC. The gate charge current is dependent

on operating frequency, as discussed in the Efficiency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 2 of the

Electrical Characteristics. For example, at 70°C ambient

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A leaky diode DB in the boost converter can not only

prevent the top MOSFET from fully turning on but it can

also completely discharge the bootstrap capacitor CB and

create a current path from the input voltage to the BOOST

pin to INTVCC. This can cause INTVCC to rise if the diode

leakage exceeds the current consumption on INTVCC.

This is particularly a concern in Burst Mode operation

where the load on INTVCC can be very small. The external

Schottky or silicon diode should be carefully chosen such

that INTVCC never gets charged up much higher than its

normal regulation voltage.

Fault Conditions: Overtemperature Protection

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on-chip

(such as an INTVCC short to ground), the overtemperature

shutdown circuitry will shut down the LTC3786. When the

junction temperature exceeds approximately 170°C, the

overtemperature circuitry disables the INTVCC LDO, causing

the INTVCC supply to collapse and effectively shut down

the entire LTC3786 chip. Once the junction temperature

drops back to approximately 155°C, the INTVCC LDO turns

back on. Long-term overstress (TJ > 125°C) should be

avoided as it can degrade the performance or shorten

the life of the part.

Since the shutdown may occur at full load, beware that

the load current won’t result in high power dissipation in

the body diodes of the top MOSFET. In this case, PGOOD

output may be used to turn the system load off.

Phase-Locked Loop and Frequency Synchronization

The LTC3786 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the bottom MOSFET to be locked to the rising

edge of an external clock signal applied to the PLLIN/MODE

pin. The phase detector is an edge-sensitive digital type

that provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC, then current is sourced continu-

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than fOSC,

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP

, holds the voltage at the VCO input.

Typically, the external clock (on PLLIN/MODE pin) input

high threshold is 1.6V, while the input low threshold is 1.2V.

Note that the LTC3786 can only be synchronized to an

external clock whose frequency is within range of the

LTC3786’s internal VCO, which is nominally 55kHz to

1MHz. This is guaranteed to be between 75kHz and 850kHz.

Rapid phase locking can be achieved by using the FREQ pin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

FREQ PIN RESISTOR (kΩ)

FREQUENCY (kHz)

600

800

1000

35 45 5525

3786 F05

400

200

500

700

900

300

100

065 75 85 95 105 115 125

Figure 5. Relationship Between Oscillator Frequency

and Resistor Value at the FREQ Pin

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Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN PLLIN/MODE PIN FREQUENCY

0V DC Voltage 350kHz

INTVCC DC Voltage 535kHz

Resistor DC Voltage 50kHz to 900kHz

Any of the Above External Clock Phase Locked to External Clock

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC3786 is capable of turning on the bottom

MOSFET. It is determined by internal timing delays and

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum

on-time limit.

In forced continuous mode, if the duty cycle falls below

what can be accommodated by the minimum on-time,

the controller will begin to skip cycles but the output will

continue to be regulated. More cycles will be skipped when

VIN increases. Once VIN rises above VOUT

, the loop keeps

the top MOSFET continuously on. The minimum on-time

for the LTC3786 is approximately 110ns.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the greatest improvement. Percent efficiency

can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc., are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, five main sources usually account for most of the

losses in LTC3786 circuits: 1) IC VBIAS current, 2) INTVCC

regulator current, 3) I2R losses, 4) Bottom MOSFET transi-

tion losses and 5) Body diode conduction losses.

1. The VBIAS current is the DC supply current given in the

Electrical Characteristics table, which excludes MOSFET

driver and control currents. VBIAS current typically

results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power MOS-

FETs. Each time a MOSFET gate is switched from low to

high to low again, a packet of charge, dQ, moves from

INTVCC to ground. The resulting dQ/dt is a current out

of INTVCC that is typically much larger than the control

circuit current. In continuous mode, IGATECHG = f(QT +

QB), where QT and QB are the gate charges of the topside

and bottom side MOSFETs.

3. DC I2R losses. These arise from the resistances of the

MOSFETs, sensing resistor, inductor and PC board

traces and cause the efficiency to drop at high output

currents.

4. Transition losses apply only to the bottom MOSFET(s),

and become significant only when operating at low input

voltages. Transition losses can be estimated from:

Transition Loss = 1.7

( )

VOUT3

IMAX •CRSS •f

5. Body diode conduction losses are more significant at

higher switching frequency. During the dead time, the loss

in the top MOSFETs is IL • VDS, where VDS is around 0.7V.

At higher switching frequency, the dead time becomes

a good percentage of switching cycle and causes the

efficiency to drop.

Other hidden losses, such as copper trace and internal

battery resistances, can account for an additional efficiency

degradation in portable systems. It is very important to

include these system-level losses during the design phase.

LTC3786

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Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in load current.

When a load step occurs, VOUT shifts by an amount equal

to ∆ILOAD(ESR), where ESR is the effective series resistance

of COUT

. ∆ILOAD also begins to charge or discharge COUT

generating the feedback error signal that forces the regula-

tor to adapt to the current change and return VOUT to its

steady-state value. During this recovery time VOUT can

be monitored for excessive overshoot or ringing, which

would indicate a stability problem. OPTI-LOOP

compen-

sation allows the transient response to be optimized over

a wide range of output capacitance and ESR values. The

availability of the ITH pin not only allows optimization of

control loop behavior, but it also provides a DC-coupled

and AC-filtered closed-loop response test point. The DC

step, rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The ITH external components shown

in the Figure 8 circuit will provide an adequate starting

point for most applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

to optimize transient response once the final PCB layout

is complete and the particular output capacitor type and

value have been determined. The output capacitors must

be selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1µs to

10µs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Placing a power MOSFET and load resistor directly

across the output capacitor and driving the gate with an

appropriate pulse generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current

may not be within the bandwidth of the feedback loop,

so this signal cannot be used to determine phase margin.

This is why it is better to look at the ITH pin signal which

is in the feedback loop and is the filtered and compensated

control loop response.

The gain of the loop will be increased by increasing

RC and the bandwidth of the loop will be increased by

decreasing CC. If RC is increased by the same factor that

CC is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual overall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT

, causing a rapid drop in VOUT

. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited to

approximately 25 • CLOAD. Thus, a 10µF capacitor would

require a 250µs rise time, limiting the charging current

to about 200mA.

Design Example

As a design example, assume VIN = 12V(nominal),

VIN = 22V (max), VOUT = 24V, IOUT(MAX) = 4A, VSENSE(MAX)

= 75mV and f = 350kHz.

The inductance value is chosen first based on a 30% ripple

current assumption. Tie the MODE/PLLIN pin to GND,

generating 350kHz operation. The minimum inductance

for 30% ripple current is:

∆IL=V

f•L1– V

VOUT













The largest ripple happens when VIN = 1/2VOUT = 12V,

where the average maximum inductor is IMAX = IOUT(MAX)

• (VOUT/VIN) = 8A. A 6.8µH inductor will produce a 31%

ripple current. The peak inductor current will be the maxi-

mum DC value plus one-half the ripple current, or 9.25A.

LTC3786

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The RSENSE resistor value can be calculated by using the

maximum current sense voltage specification with some

accommodation for tolerances:

RSENSE ≤

75mV

9.25A

=0.008Ω

Choosing 1% resistors: RA = 5k and RB = 95.3k yields an

output voltage of 24.072V.

The power dissipation on the topside MOSFET in each chan-

nel can be easily estimated. Choosing a Vishay Si7848BDP

MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF. At

maximum input voltage with T(estimated) = 50°C:

PMAIN =24V – 12V

( )

24V

12V

( )

2•4A

( )

•1+0.005

( )

50°C – 25°C

( )





•0.008Ω

+1.7

( )

24V

( )

34A

12V

150pF

( )

350kHz

( )

=0.7W

COUT is chosen to filter the square current in the output.

The maximum output current peak is:

IOUT(PEAK) =IOUT(MAX) •1+RIPPLE%













=4•1+31%









=4.62A

A low ESR (5mΩ) capacitor is suggested. This capacitor

will limit output voltage ripple to 23.1mV (assuming ESR

dominate ripple).

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 6. Figure 7 illustrates the current

waveforms present in the various branches the synchro-

nous regulator operating in the continuous mode. Check

the following in your layout:

1. Put the bottom N-channel MOSFET MBOT and the top

N-channel MOSFET MTOP in one compact area with

COUT

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

of CINTVCC must return to the combined COUT (–)

terminals. The path formed by the bottom N-channel

MOSFET and the capacitor should have short leads and

PC trace lengths. The output capacitor (–) terminals

should be connected as close as possible to the (–)

source terminal of the bottom MOSFET.

3. Does the LTC3786 VFB pin’s resistive divider connect

to the (+) terminal of COUT? The resistive divider must

be connected between the (+) terminal of COUT and

signal ground and placed close to the VFB pin. The

feedback resistor connections should not be along the

high current input feeds from the input capacitor(s).

4. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The filter capacitor between

SENSE+ and SENSE– should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor.

5. Is the INTVCC decoupling capacitor connected close

to the IC, between the INTVCC and the power ground

pin? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1µF ceramic capacitor placed

immediately next to the INTVCC and GND pins can help

improve noise performance substantially.

6. Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes. All of these nodes have very large and fast

moving signals and, therefore, should be kept on the

output side of the LTC3786 and occupy a minimal PC

trace area.

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTVCC

decoupling capacitor, the bottom of the voltage feedback

resistive divider and the GND pin of the IC.

LTC3786

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applicaTions inForMaTion

PC Board Layout Debugging

It is helpful to use a DC-50MHz current probe to monitor

the current in the inductor while testing the circuit. Moni-

tor the output switching node (SW pin) to synchronize

the oscilloscope to the internal oscillator and probe the

actual output voltage. Check for proper performance over

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold— typically 10% of the maximum designed

current level in Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well designed, low noise PCB implementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pick-up at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

Reduce VIN from its nominal level to verify operation with

high duty cycle. Check the operation of the undervoltage

lockout circuit by further lowering VIN while monitoring

the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hook-up will still

be maintained, but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

LTC3786

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applicaTions inForMaTion

SENSE+

SENSE–

PGOOD VPULLUP

VIN

VOUT

BOOST

BGfIN

GND

3786 F06

L1 RSENSE

VBIAS

GND

LTC3786

FREQ

PLLIN/MODE

RUN

VFB

ITH

INTVCC

L1 SW

RSENSE VOUT

COUT

3786 F07

VIN

CIN

RIN

BOLD LINES INDICATE HIGH SWITCHING CURRENT.

KEEP LINES TO A MINIMUM LENGTH

Figure 6. Recommended Printed Circuit Layout Diagram

Figure 7. Branch Current Waveforms

LTC3786

3786fa

applicaTions inForMaTion

SENSE+

SENSE–

CB 0.1µF

CITHA 220pF

LTC3786

CSS 0.1µF

CITH 15nF

CIN

22µF

MTOP

MBOT

CINT

4.7µF

3786 F08

VOUT

24V

5A*

VIN

5V TO 24V

RSENSE

4mΩ

3.3µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

RA 12.1k 100k

RITH 8.66k

232k

CIN, COUTA: TDK C4532X5R1E226M

COUTB: SANYO 50CE220LX

D: BAS140W

L: PULSE PA1494.362NL

MBOT, MTOP: RENESAS HAT2169H

*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

FREQ

RUN

PLLIN/MODE

COUTA

22µF

×4

COUTB

220µF

Figure 8. High Efficiency 24V Boost Converter

Figure 9. High Efficiency 28V Boost Converter

SENSE+

SENSE–

CB 0.1µF

CITHA 220pF

LTC3786

CSS 0.1µF

CITH 15nF

CIN

6.8µF

×4

MTOP

MBOT

CINT

4.7µF

3786 F09

VOUT

28V

4A*

VIN

5V TO 28V

RSENSE

4mΩ

3.3µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

RA 12.1k 100k

RITH 8.66k

261k

FREQ

RUN

PLLIN/MODE

COUTA

6.8µF

×4

COUTB

220µF

CIN, COUTA: TDK C4532X7R1H685K

COUTB: SANYO 63CE220KX

D: BAS140W

L: PULSE PA1494.362NL

MBOT, MTOP: RENESAS HAT2169H

*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

LTC3786

3786fa

applicaTions inForMaTion

Figure 10. High Efficiency 36V Boost Converter

Figure 11. 10.5V Nonsynchronous SEPIC Converter

SENSE+

SENSE–

CB 0.1µF

CITHA 220pF

LTC3786

CSS 0.1µF

CITH 15nF

CIN

6.8µF

×4

MTOP

MBOT

CINT

4.7µF

3786 F10

VOUT

36V

3A*

VIN

5V TO 36V

RSENSE

5mΩ

10.2µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

RA 12.1k 100k

RITH 8.66k

357k

FREQ

RUN

PLLIN/MODE

COUTA

6.8µF

×4

COUTB

220µF

CIN, COUTA: TDK C4532X7R1H685K

COUTB: SANYO 63CE220KX

D: BAS170W

L: PULSE PA2050.103NL

MBOT, MTOP: RENESAS RJIC0652DPB

*WHEN VIN < 9V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

SENSE+

SENSE–

CITHA 10pF

LTC3786

CSS 0.1µF

CITH 100nF

CIN

22µF

MBOT

CINT

4.7µF

3786 F11

VOUT

10.5V

1.2A

VIN

5.8V TO 34V

RSENSE

9mΩ

10µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

RA 115k 100k

RITH 13k

887k

FREQ

RUN

PLLIN/MODE

COUT

270µF

10µF

• •

CIN: SANYO 50CE220LX

COUT: SANYO SVPC270M

D: DIODES, INC. B360A-13-F

L: COOPER BUSSMANN DRQ125-100

MBOT: BSZ097NO4L

LTC3786

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applicaTions inForMaTion

Figure 12. High Efficiency 10V Boost Converter

OUTPUT CURRENT (A)

321

EFFICIENCY (%)

4 5 6

3786 F12b

100

VIN = 12V

VIN = 9V

VIN = 6V

SENSE+

SENSE–

0.1µF

CITHA

100pF

LTC3786

CSS

0.1µF

CITH

10nF

CIN

22µF

MBOT

MTOP

CINT

4.7µF

3786 F12a

VOUT*

10V

VIN

4.5V TO 24V START-UP

VOLTAGE OPERATES THROUGH

TRANSIENTS DOWN TO 2.5V

3.2µH

BOOST

VBIAS

GND

PLLIN/MODE

PGOOD

INTVCC

VFB

ITH

12.1k 100k

100k

RITH

4.64k

60.4k

fSW = 400kHz

88.7k

FREQ

RUN

COUTA

22µF

×3

RSENSE

5mΩ

COUTB

150µF

CIN, COUTA: TDK C4532X5R1E226M

COUTB: SANYO 35HVH150M

L: SUMIDA CDEP106-3R2-88

MBOT, MTOP: RENESAS HAT2170

D: INFINEON BAS140W

*WHEN VIN > 10V, VOUT FOLLOWS VIN.

LTC3786

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applicaTions inForMaTion

Figure 13. Low IQ Lithium-Ion to 5V/4A Boost Converter

SENSE+

SENSE–

0.1µF

CITHA

100pF

LTC3786

CSS

0.1µF

CITH

6.8nF

CIN

47µF

×2

MTOP

MBOT

3786 F13a

VOUT

VIN

2.7V TO 4.2V

10µF

CF LY

1µF

RSENSE

6mΩ

0.67µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

150k

100k

RITH

5.11k

475k

FREQ

RUN

PLLIN/MODE

COUT

47µF

×4

VOUT

LTC1754-5

C+

C–

VIN

SHDN

GND

CIN, COUT: TDK C3225X5R1A476M

L: TOKO FDV0840-R67M

MBOT, MTOP: INFINEON BSC046N02KS

Q: VISHAY SILICONIX Si1499DH

D1: INFINEON BAS140W

D2: NXP PMEG2005EJ

CF LY : MURATA GRM39X5R105K6.3AJ

C1, C2: MURATA GRM40X5R106K6.3AJ

CINT

4.7µF

1M C2

10µF

OUTPUT CURRENT (A)

3210

EFFICIENCY (%)

3786 F13b

VIN = 4.2V

VIN = 3.3V

VIN = 2.7V

LTC3786

3786fa

applicaTions inForMaTion

Figure 14. High Efficiency 24V Boost Converter with Inductor DCR Current Sensing

OUTPUT CURRENT (A)

3210

EFFICIENCY (%)

3786 F14b

100

VIN = 12V

SENSE+

SENSE–

CITHA

220pF

0.1µF

LTC3786

CSS

0.1µF

CITH

15nF

CIN

22µF

MBOT

MTOP

CINT

4.7µF

3786 F14a

VOUT

24V

VIN

5V TO 24V

RS2

26.1k

0.1µF

10.2µH

BOOST

VBIAS

GND

PLLIN/MODE

PGOOD

INTVCC

VFB

ITH

12.1k 100k

RITH

8.87k

232k

FREQ

RUN

COUTA

22µF

×4

COUTB

220µF

C1: TDK C1005X7R1C104K

CIN, COUTA: TDK C4532X5R1E226M

COUTB: SANYO, 50CE220AX

L: PULSE PA2050.103NL

MBOT, MTOP: RENESAS RJK0305

D: INFINEON BAS140W

RS1

53.6k

LTC3786

3786fa

applicaTions inForMaTion

Figure 15. Low IQ High Voltage Flyback Power Supply

SENSE+

SENSE–

CITHA

100pF

LTC3786

CSS

0.1µF

CITH

22nF

CIN

22µF

×2

MBOT

CINT

4.7µF

3786 F15

VOUT

350V

10mA

VIN

5V TO 12V

10nF RSENSE

15mΩ

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

16.2k

1.5M

100k

22Ω

220pF

RITH

8.66k

25k

fSW = 105kHz

FREQ

RUN

PLLIN/MODE

COUT

68nF

×2

1:10

CIN: TDK C3225X7R1C226M

COUT: TDK C3225X7R2J683K

D: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES

MBOT: VISHAY SILICONIX Si7850DP

T: TDK DCT15EFD-U44S003

DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

•

Figure 16. Low IQ Nonsynchronous 24V/2A Boost Converter

SENSE+

SENSE–

CITHA 100pF

LTC3786

CSS 0.1µF

CITH 22nF

CIN

10µF

×2

MBOT

CINT

4.7µF

3786 F15

VOUT

24V

VIN

5V TO 24V

RSENSE

6mΩ

10µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

12.1k

1% 100k

RITH 8.66k

232k

FREQ

RUN

PLLIN/MODE

COUTA

10µF

COUTB

47µF

×4

CIN, COUTA: MURATA GRM31CR61E106KA12

COUTB: KEMET T495X476K035AS

D: ON SEMI MBRS340T3G

L: VISAY SILICONIX IHLP-5050FD-01 10µH

MBOT: VISHAY SILICONIX Si4840BDP

LTC3786

3786fa

package DescripTion

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev C)

MSOP (MSE16) 0910 REV C

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ± 0.102

(.112 ± .004)

2.845 ± 0.102

(.112 ± .004)

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

1.651 ± 0.102

(.065 ± .004)

1.651 ± 0.102

(.065 ± .004)

0.1016 ± 0.0508

(.004 ± .002)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.280 ± 0.076

(.011 ± .003)

REF

4.90 ± 0.152

(.193 ± .006)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.12 REF

0.35

REF

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3786

3786fa

package DescripTion

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

3.00 ± 0.10

(4 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.45 ± 0.05

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

15 16

0.50 BSC

0.200 REF

2.10 ± 0.05

3.50 ± 0.05

0.70 ±0.05

0.00 – 0.05

(UD16) QFN 0904

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3786

3786fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 9/11 Updated the Topside MOSFET Driver Supply (CB, DB) section.

Updated Figure 12.

LTC3786

3786fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0911 REV A • PRINTED IN USA

relaTeD parTs

Typical applicaTion

High Efficiency 48V Boost Converter

SENSE+

SENSE–

CB 0.1µF

CITHA 220pF

LTC3786

CSS 0.1µF

CITH 15nF

CIN

6.8µF

×4

MTOP

MBOT

CINT

4.7µF

3786 TA02

VOUT

48V

2A*

VIN

5V TO 38V

RSENSE

8mΩ

16µH

BOOST

VBIAS

GND

PGOOD

INTVCC

VFB

ITH

RA 12.1k 100k

RITH 8.66k

475k

FREQ

RUN

PLLIN/MODE

COUTA

6.8µF

×4

COUTB

220µF

CIN, COUTA: TDK C4532X7R1H685K

COUTB: SANYO 63CE220KX

D: BAS170W

L: PULSE PA2050.163NL

MBOT, MTOP: RENESAS RJK0652DPB

*WHEN VIN < 13V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

PART NUMBER DESCRIPTION COMMENTS

LTC3788/LTC3788-1 2-Phase Dual Output Synchronous Step-Up Controllers 4.5V ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz, 5mm × 5mm

QFN-32 and SSOP-28 Packages

LTC3787 2-Phase Single Output Synchronous Boost Controller 4.5V ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz, 5mm × 5mm

QFN-28 and SSOP-28 Packages

LTC3859 Low IQ, Triple Output, Buck/Buck/Boost Synchronous

Controller

4.5V ≤ VIN ≤ 38V, Boost Output Voltage Up to 60V, 50kHz to 900kHz,

5mm × 7mm QFN-38 and TSSOP-38 Packages

LTC3862/LTC3862-1 Multiphase Current Mode Step-Up DC/DC Controllers 4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz, SSOP-24,

TSSOP-24, 5mm × 5mm QFN-24

LTC3813/LTC3814-5 100V/60V Maximum VOUT Current Mode Synchronous

Step-Up DC/DC Controllers

No RSENSE, Large 1Ω Gate Driver, Adjustable Off-Time, SSOP-28,

TSSOP-16

LTC1871, LTC1871-1,

LTC1871-7

Wide Input Range, No RSENSE™ Low Quiescent Current

Flyback, Boost and SEPIC Controllers

Adjustable Switching Frequency, 2.5V ≤ VIN ≤ 36V, Burst Mode

Operation at Light Load, MSOP-10

3757/LT3758 Boost, Flyback, SEPIC and Inverting Controllers VIN Up to 40V/100V, 100kHz to 1MHz Programmable Operation

Frequency, 3mm × 3mm DFN-10 and MSOP-10E

LTC3780 High Efficiency Synchronous 4-Switch Buck-Boost DC/

DC Controller

4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 30V, SSOP-24, 5mm × 5mm QFN-32