ADSPBF514BBCZ4F16 - ANALOG DEVICES

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin

Embedded Processor

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Technical Support www.analog.com

FEATURES

Up to 400 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a range of supply voltages for internal and I/O opera-

tions. See Operating Conditions on Page 26

Internal 32M bit flash (available on ADSP-BF504F and

ADSP-BF506F processors)

Internal ADC (available on ADSP-BF506F processor)

Off-chip voltage regulator interface

88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504

and ADSP-BF504F processors

120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F

processor

MEMORY

68K bytes of L1 SRAM (processor core-accessible) memory

(See Table 1 on Page 3 for L1 and L3 memory size details)

External (interface-accessible) memory controller with glue-

less support for internal 32M bit flash and boot ROM

Flexible booting options from internal flash and SPI memory

or from host devices including SPI, PPI, and UART

Memory management unit providing memory protection

PERIPHERALS

Two 32-bit up/down counters with rotary support

Eight 32-bit timers/counters with PWM support

Two 3-phase 16-bit center-based PWM units

2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I

S channels

2 serial peripheral interface (SPI) compatible ports

2 UARTs with IrDA support

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

Removable storage interface (RSI) controller for MMC, SD,

SDIO, and CE-ATA

Internal ADC with 12 channels, 12 bits, and up to 2 MSPS

ADC controller module (ACM), providing a glueless interface

between Blackfin processor and internal or external ADC

Controller Area Network (CAN) controller

2-wire interface (TWI) controller

12 peripheral DMAs

2 memory-to-memory DMA channels

Event handler with 52 interrupt inputs

35 general-purpose I/Os (GPIOs), with programmable

hysteresis

Debug/JTAG interface

On-chip PLL capable of frequency multiplication

Figure 1. Processor Block Diagram

SPORT1–0

VOLTAGE REGULATOR INTERFACE

GPIO

PORT F

PORT G

PORT H

JTAG TEST AND EMULATION

PERIPHERAL

ACCESS BUS

PWM 1–0

WATCHDOG TIMER

SPI1–0

RSI

ACM

PPI

CAN

COUNTER1–0

TWI

BOOT

ROM

DMA

ACCESS

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1 DATA

MEMORY

L1 INSTRUCTION

MEMORY

DCB

EAB

MEMORY PORT

FLASH CONTROL

UART1–0

DEB

32M BIT

FLASH

TIMER7–0

ADC

Rev. B | Page 2 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

Flash Memory ...................................................... 9

DMA Controllers .................................................. 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Up/Down Counters and Thumbwheel Interfaces ........ 10

3-Phase PWM Units ............................................ 10

Serial Ports ........................................................ 10

Serial Peripheral Interface (SPI) Ports ...................... 11

UART Ports (UARTs) .......................................... 11

Parallel Peripheral Interface (PPI) ........................... 11

RSI Interface ...................................................... 12

Controller Area Network (CAN) Interface ................ 12

TWI Controller Interface ...................................... 13

Ports ................................................................ 13

Dynamic Power Management ................................ 13

ADSP-BF50x Voltage Regulation ............................ 15

Clock Signals ..................................................... 15

Booting Modes ................................................... 16

Instruction Set Description ................................... 17

Development Tools ............................................. 17

ADC and ACM Interface ...................................... 18

Internal ADC ..................................................... 20

ADC Application Hints ........................................ 21

Additional Information ........................................ 21

Related Signal Chains ........................................... 21

Signal Descriptions ................................................. 22

Specifications ........................................................ 26

Operating Conditions ........................................... 26

Electrical Characteristics ....................................... 28

Processor—Absolute Maximum Ratings ................... 31

ESD Sensitivity ................................................... 32

Package Information ............................................ 32

Processor—Timing Specifications ........................... 33

Processor—Output Drive Currents .......................... 50

Processor—Test Conditions ................................... 51

Processor—Environmental Conditions ..................... 53

Flash—Specifications .............................................. 54

Flash—Program and Erase Times and Endurance

Cycles ............................................................ 54

Flash—Absolute Maximum Ratings ......................... 54

ADC—Specifications ............................................... 55

ADC—Operating Conditions ................................. 55

ADC—Timing Specifications ................................. 58

ADC—Absolute Maximum Ratings ......................... 58

ADC—Typical Performance Characteristics .............. 59

ADC—Terminology ............................................ 61

ADC—Theory of Operation ................................... 62

ADC—Modes of Operation ................................... 68

ADC—Serial Interface .......................................... 71

120-Lead LQFP Lead Assignment ............................... 73

88-Lead LFCSP Lead Assignment ............................... 76

Outline Dimensions ................................................ 79

Automotive Products .............................................. 81

Ordering Guide ..................................................... 81

REVISION HISTORY

04/14—Rev. A to Rev. B

Updated Development Tools .................................... 17

Corrected RCKFE bit setting and description in

Table 9, The SPORTx Receive Configuration 1 Register

(SPORTx_RCR1) ................................................... 19

Updated footnote 6 in Operating Conditions ................ 26

Updated Table 18 with revised data for

Static Current—IDD-DEEPSLEEP (mA) ..................... 30

Revised package diagram (Figure 93) to include U-Groove in

Outline Dimensions ................................................ 79

Package thickness changed from 0.75/0.80/0.85 to

0.75/0.85/0.90 in Figure 94 in Outline Dimensions ......... 79

Rev. B | Page 3 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

GENERAL DESCRIPTION

The ADSP-BF50x processors are members of the Blackfin

fam-

ily of products, incorporating the Analog Devices/Intel Micro

Signal Architecture (MSA). Blackfin processors combine a dual-

MAC state-of-the-art signal processing engine, the advantages

of a clean, orthogonal RISC-like microprocessor instruction set,

and single-instruction, multiple-data (SIMD) multimedia capa-

bilities into a single instruction-set architecture.

The ADSP-BF50x processors are completely code compatible

with other Blackfin processors. ADSP-BF50x processors offer

performance up to 400 MHz and reduced static power con-

sumption. Differences with respect to peripheral combinations

are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which provides the ability to vary both the

voltage and frequency of operation to significantly lower overall

power consumption. This capability can result in a substantial

reduction in power consumption, compared with just varying

the frequency of operation. This allows longer battery life for

portable appliances.

SYSTEM INTEGRATION

The ADSP-BF50x processors are highly integrated system-on-a-

chip solutions for the next generation of embedded industrial,

instrumentation, and power/motion control applications. By

combining industry-standard interfaces with a high perfor-

mance signal processing core, cost-effective applications can be

developed quickly, without the need for costly external compo-

nents. The system peripherals include a watchdog timer; two

32-bit up/down counters with rotary support; eight 32-bit tim-

ers/counters with PWM support; six pairs of 3-phase 16-bit

center-based PWM units; two dual-channel, full-duplex syn-

chronous serial ports (SPORTs); two serial peripheral interface

(SPI) compatible ports; two UARTs with IrDA

support; a par-

allel peripheral interface (PPI); a removable storage interface

(RSI) controller; an internal ADC with 12 channels, 12 bits, up

to 2 MSPS, and ACM controller; a controller area network

(CAN) controller; a 2-wire interface (TWI) controller; and an

internal 32M bit flash.

PROCESSOR PERIPHERALS

The ADSP-BF50x processors contain a rich set of peripherals

connected to the core via several high-bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see the block diagram on Page 1). These

Blackfin processors contain high-speed serial and parallel ports,

an interrupt controller for flexible management of interrupts

from the on-chip peripherals or external sources, and power

management control functions to tailor the performance and

power characteristics of the processor and system to many

application scenarios.

The SPORT, SPI, UART, PPI, and RSI peripherals are sup-

ported by a flexible DMA structure. There are also separate

memory DMA channels dedicated to data transfers between the

processor’s various memory spaces, including boot ROM and

internal 32M bit synchronous burst flash. Multiple on-chip

buses running at up to 100 MHz provide enough bandwidth to

keep the processor core running along with activity on all of the

on-chip and external peripherals.

The ADSP-BF50x processors include an interface to an off-chip

voltage regulator in support of the processor’s dynamic power

management capability.

Table 1. Processor Comparison

Feature

ADSP-BF504

ADSP-BF504F

ADSP-BF506F

Up/Down/Rotary Counters 2 2 2

Timer/Counters with PWM 8 8 8

3-Phase PWM Units 2 2 2

SPORTs 2 2 2

SPIs 2 2 2

UARTs 2 2 2

Parallel Peripheral Interface 1 1 1

Removable Storage Interface 1 1 1

CAN 1 1 1

TWI 1 1 1

Internal 32M Bit Flash – 1 1

ADC Control Module (ACM) 1 1 1

Internal ADC – – 1

GPIOs 35 35 35

Memory (bytes)

L1 Instruction SRAM 16K 16K 16K

L1 Instruction SRAM/Cache 16K 16K 16K

L1 Data SRAM 16K 16K 16K

L1 Data SRAM/Cache 16K 16K 16K

L1 Scratchpad 4K 4K 4K

L3 Boot ROM 4K 4K 4K

Maximum Speed Grade

For valid clock combinations, see Table 14, Table 15, Table 16, and Table 24.

400 MHz

Maximum System Clock Speed 100 MHz

Package Options 88-Lead

LFCSP

88-Lead

LFCSP

120-Lead

LQFP

Rev. B | Page 4 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

operands for compute operations come from the multiported

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2

multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used

to support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Figure 2. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

16 16

8888

40 40

A0 A1

BARREL

SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ASTAT

40 40

32 32

32LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

DA1

DA0

PREG

RAB

TO MEMORY

Rev. B | Page 5 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The data memory holds data,

and a dedicated scratchpad data memory stores stack and local

variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low latency core-accessible memory

as cache or SRAM and to provide larger, lower cost and perfor-

mance interface-accessible memory systems. See Figure 3.

The core-accessible L1 memory system is the highest perfor-

mance memory available to the Blackfin processor. The

interface-accessible memory system, accessed through the

external bus interface unit (EBIU), provides access to the inter-

nal flash memory and boot ROM.

The memory DMA controller provides high bandwidth data

movement capability. It can perform block transfers of code

or data between the internal memory and the external

memory spaces.

Internal (Core-Accessible) Memory

The processor has three blocks of core-accessible memory,

providing high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

32K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second core-accessible memory block is the L1 data mem-

ory, consisting of 32K bytes of SRAM, of which 16K bytes may

be configured as cache. This memory block is accessed at full

processor speed.

The third memory block is 4K bytes of scratchpad SRAM, which

runs at the same speed as the L1 memories, but this memory is

only accessible as data SRAM and cannot be configured as cache

memory.

External (Interface-Accessible) Memory

External memory is accessed via the EBIU memory port. This

16-bit interface provides a glueless connection to the internal

flash memory and boot ROM. Internal flash memory ships from

the factory in an erased state except for Block 0 of the parameter

bank. Block 0 of the Flash memory parameter bank ships from

the factory in an unknown state. An erase operation should be

performed prior to programming this block.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space.

On-chip I/O devices have their control registers mapped into

memory-mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks. One contains the control MMRs for all core functions,

and the other contains the registers needed for setup and con-

trol of the on-chip peripherals outside of the core. The MMRs

are accessible only in supervisor and emulation modes and

appear as reserved space to on-chip peripherals.

Figure 3. Internal/External Memory Map

INTERNAL

(CORE-ACCESSIBLE)

MEMORY MAP

EXTERNAL

(INTERFACE-ACCESSIBLE)

MEMORY MAP

0x0000 0000

0x2000 0000

0x2040 0000

0xEF00 0000

0xEF00 1000

0xFF80 0000

0xFF80 4000

0xFF80 8000

0xFFA0 0000

0xFFA0 4000

0xFFA0 8000

0xFFA1 4000

0xFFB0 0000

0xFFB0 1000

0xFFC0 0000

0xFFE0 0000

0xFFFF FFFF

SYNC FLASH (32M BITS) *

RESERVED

BOOT ROM (4K BYTES)

L1 DATA BANK A SRAM (16K BYTES)

RESERVED

L1 DATA BANK A SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K BYTES)

RESERVED

L1 INSTRUCTION BANK A SRAM (16K BYTES)

RESERVED

INTERNAL SCRATCHPAD RAM (4K BYTES)

RESERVED

SYSTEM MEMORY MAPPED REGISTERS

CORE MEMORY MAPPED REGISTERS

* AVAILABLE ON PARTS WITH SYNC FLASH (F)

Rev. B | Page 6 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Booting

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 16.

Event Handling

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher priority event takes precedence over servicing of a

lower priority event. The controller provides support for five

different types of events:

• Emulation—An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset—This event resets the processor.

• Nonmaskable Interrupt (NMI)—The NMI event can be

generated either by the software watchdog timer, by the

NMI input signal to the processor, or by software. The

NMI event is frequently used as a power-down indicator to

initiate an orderly shutdown of the system.

• Exceptions—Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts—Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, an interrupt service routine (ISR) must

save the state of the processor to the supervisor stack.

The processor event controller consists of two stages: the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by

writing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class EVT Entry

0Emulation/Test ControlEMU

1 Reset RST

2 Nonmaskable Interrupt NMI

3Exception EVX

4 Reserved —

5 Hardware Error IVHW

6 Core Timer IVTMR

7 General-Purpose Interrupt 7 IVG7

8 General-Purpose Interrupt 8 IVG8

9 General-Purpose Interrupt 9 IVG9

10 General-Purpose Interrupt 10 IVG10

11 General-Purpose Interrupt 11 IVG11

12 General-Purpose Interrupt 12 IVG12

13 General-Purpose Interrupt 13 IVG13

14 General-Purpose Interrupt 14 IVG14

15 General-Purpose Interrupt 15 IVG15

Rev. B | Page 7 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Source

General-Purpose

Interrupt (at Reset)

Peripheral

Interrupt ID

Default Core

Interrupt ID SIC Registers

PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0

DMA Error (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0

PPI Status IVG7 2 0 IAR0 IMASK0, ISR0, IWR0

SPORT0 Status IVG7 3 0 IAR0 IMASK0, ISR0, IWR0

SPORT1 Status IVG7 4 0 IAR0 IMASK0, ISR0, IWR0

UART0 Status IVG7 5 0 IAR0 IMASK0, ISR0, IWR0

UART1 Status IVG7 6 0 IAR0 IMASK0, ISR0, IWR0

SPI0 Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0

SPI1 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0

CAN Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0

RSI Mask 0 Interrupt IVG7 10 0 IAR1 IMASK0, ISR0, IWR0

Reserved — 11 — IAR1 IMASK0, ISR0, IWR0

CNT0 Interrupt IVG8 12 1 IAR1 IMASK0, ISR0, IWR0

CNT1 Interrupt IVG8 13 1 IAR1 IMASK0, ISR0, IWR0

DMA Channel 0 (PPI Rx/Tx) IVG9 14 2 IAR1 IMASK0, ISR0, IWR0

DMA Channel 1 (RSI Rx/Tx) IVG9 15 2 IAR1 IMASK0, ISR0, IWR0

DMA Channel 2 (SPORT0 Rx) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0

DMA Channel 3 (SPORT0 Tx) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0

DMA Channel 4 (SPORT1 Rx) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0

DMA Channel 5 (SPORT1 Tx) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0

DMA Channel 6 (SPI0 Rx/Tx) IVG10 20 3 IAR2 IMASK0, ISR0, IWR0

DMA Channel 7 (SPI1 Rx/Tx) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0

DMA Channel 8 (UART0 Rx) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0

DMA Channel 9 (UART0 Tx) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0

DMA Channel 10 (UART1 Rx) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0

DMA Channel 11 (UART1 Tx) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0

CAN Receive IVG11 26 4 IAR3 IMASK0, ISR0, IWR0

CAN Transmit IVG11 27 4 IAR3 IMASK0, ISR0, IWR0

TWI IVG11 28 4 IAR3 IMASK0, ISR0, IWR0

Port F Interrupt A IVG11 29 4 IAR3 IMASK0, ISR0, IWR0

Port F Interrupt B IVG11 30 4 IAR3 IMASK0, ISR0, IWR0

Reserved — 31 — IAR3 IMASK0, ISR0, IWR0

Timer 0 IVG12 32 5 IAR4 IMASK1, ISR1, IWR1

Timer 1 IVG12 33 5 IAR4 IMASK1, ISR1, IWR1

Timer 2 IVG12 34 5 IAR4 IMASK1, ISR1, IWR1

Timer 3 IVG12 35 5 IAR4 IMASK1, ISR1, IWR1

Timer 4 IVG12 36 5 IAR4 IMASK1, ISR1, IWR1

Timer 5 IVG12 37 5 IAR4 IMASK1, ISR1, IWR1

Timer 6 IVG12 38 5 IAR4 IMASK1, ISR1, IWR1

Timer 7 IVG12 39 5 IAR4 IMASK1, ISR1, IWR1

Port G Interrupt A IVG12 40 5 IAR5 IMASK1, ISR1, IWR1

Port G Interrupt B IVG12 41 5 IAR5 IMASK1, ISR1, IWR1

MDMA Stream 0 IVG13 42 6 IAR5 IMASK1, ISR1, IWR1

Rev. B | Page 8 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Event Control

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

• CEC interrupt latch register (ILAT)—Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and is cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK)—Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

written while in supervisor mode. (Note that general-

purpose interrupts can be globally enabled and disabled

with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND)—The IPEND

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask registers (SIC_IMASKx)—Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, the corresponding

peripheral event is unmasked and is forwarded to the CEC

when asserted. A cleared bit in these registers masks the

corresponding peripheral event, preventing the event from

propagating to the CEC.

• SIC interrupt status registers (SIC_ISRx)—As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates that the

peripheral is asserting the interrupt, and a cleared bit indi-

cates that the peripheral is not asserting the event.

• SIC interrupt wakeup enable registers (SIC_IWRx)—By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor should the

core be idled or in sleep mode when the event is generated.

For more information, see Dynamic Power Management

on Page 13.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

MDMA Stream 1 IVG13 43 6 IAR5 IMASK1, ISR1, IWR1

Software Watchdog Timer IVG13 44 6 IAR5 IMASK1, ISR1, IWR1

Port H Interrupt A IVG13 45 6 IAR5 IMASK1, ISR1, IWR1

Port H Interrupt B IVG13 46 6 IAR5 IMASK1, ISR1, IWR1

ACM Status Interrupt IVG7 47 0 IAR5 IMASK1, ISR1, IWR1

ACM Interrupt IVG10 48 3 IAR6 IMASK1, ISR1, IWR1

Reserved — 49 — IAR6 IMASK1, ISR1, IWR1

Reserved — 50 — IAR6 IMASK1, ISR1, IWR1

PWM0 Trip Interrupt IVG10 51 3 IAR6 IMASK1, ISR1, IWR1

PWM0 Sync Interrupt IVG10 52 3 IAR6 IMASK1, ISR1, IWR1

PWM1 Trip Interrupt IVG10 53 3 IAR6 IMASK1, ISR1, IWR1

PWM1 Sync Interrupt IVG10 54 3 IAR6 IMASK1, ISR1, IWR1

RSI Mask 1 Interrupt IVG10 55 3 IAR6 IMASK1, ISR1, IWR1

Reserved — 56 through 63 — — IMASK1, ISR1, IWR1

Table 3. System Interrupt Controller (SIC) (Continued)

Peripheral Interrupt Source

General-Purpose

Interrupt (at Reset)

Peripheral

Interrupt ID

Default Core

Interrupt ID SIC Registers

Rev. B | Page 9 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

FLASH MEMORY

The ADSP-BF504F and ADSP-BF506F processors include an

on-chip 32M bit (×16, multiple bank, burst) Flash memory. The

features of this memory include:

• Synchronous/asynchronous read

• Synchronous burst read mode: 50 MHz

• Asynchronous/synchronous read mode

• Random access times: 70 ns

• Synchronous burst read suspend

• Memory blocks

• Multiple bank memory array: 4M bit banks

• Parameter blocks (top location)

•Dual operations

• Program erase in one bank while read in others

• No delay between read and write operations

• Block locking

• All blocks locked at power-up

• Any combination of blocks can be locked or locked

down

•Security

• 128-bit user programmable OTP cells

• 64-bit unique device number

• Common Flash interface (CFI)

• 100,000 program/erase cycles per block

Flash memory ships from the factory in an erased state except

for block 0 of the parameter bank. Block 0 of the Flash memory

parameter bank ships from the factory in an unknown state. An

erase operation should be performed prior to programming this

block.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that

support automated data transfers with minimal overhead for

the processor core. DMA transfers can occur between the pro-

cessor’s internal memories and any of its DMA-capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interface. DMA-

capable peripherals include the SPORTs, SPI ports, UARTs,

RSI, and PPI. Each individual DMA-capable peripheral has at

least one dedicated DMA channel.

The processor DMA controller supports both one-dimensional

(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-

fer initialization can be implemented from registers or from sets

of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to ±32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the processor DMA con-

troller include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels, which are provided for transfers

between the various memories of the processor system with

minimal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state through generation of a core and system reset, nonmas-

kable interrupt (NMI), or general-purpose interrupt, if the

timer expires before being reset by software. The programmer

initializes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

If configured to generate a reset, the watchdog timer resets both

the core and the processor peripherals. After a reset, software

can determine whether the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

The timer is clocked by the system clock (SCLK) at a maximum

frequency of f

SCLK

TIMERS

There are nine general-purpose programmable timer units in

the processors. Eight timers have an external pin that can be

configured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, to an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs

to measure the width of the pulses in the data stream to provide

a software auto-baud detect function for the respective serial

channels.

Rev. B | Page 10 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

UP/DOWN COUNTERS AND

THUMBWHEEL INTERFACES

Two 32-bit up/down counters are provided that can sense 2-bit

quadrature or binary codes as typically emitted by industrial

drives or manual thumbwheels. The counters can also operate

in general-purpose up/down count modes. Then, count direc-

tion is either controlled by a level-sensitive input pin or by two

edge detectors.

A third counter input can provide flexible zero marker support

and can alternatively be used to input the push-button signal of

thumb wheels. All three pins have a programmable debouncing

circuit.

Internal signals forwarded to each timer unit enable these tim-

ers to measure the intervals between count events. Boundary

registers enable auto-zero operation or simple system warning

by interrupts when programmable count values are exceeded.

3-PHASE PWM UNITS

The two/dual 3-phase PWM generation units each feature:

• 16-bit center-based PWM generation unit

•Programmable PWM pulse width

• Single/double update modes

• Programmable dead time and switching frequency

• Twos-complement implementation which permits smooth

transition to full ON and full OFF states

• Possibility to synchronize the PWM generation to either

externally-generated or internally-generated synchroniza-

tion pulses

• Special provisions for BDCM operation (crossover and

output enable functions)

• Wide variety of special switched reluctance (SR) operating

modes

• Output polarity and clock gating control

• Dedicated asynchronous PWM shutdown signal

Each PWM block integrates a flexible and programmable

3-phase PWM waveform generator that can be programmed

to generate the required switching patterns to drive a 3-phase

voltage source inverter for ac induction motor (ACIM) or

permanent magnet synchronous motor (PMSM) control. In

addition, the PWM block contains special functions that

considerably simplify the generation of the required PWM

switching patterns for control of the electronically commutated

motor (ECM) or brushless dc motor (BDCM). Software can

enable a special mode for switched reluctance motors (SRM).

The six PWM output signals (per PWM unit) consist of three

high-side drive signals (PWMx_AH, PWMx_BH, and PWMx-

_CH) and three low-side drive signals (PWMx_AL, PWMx_BL,

and PWMx_CL). The polarity of the generated PWM signal can

be set with software, so that either active HI or active LO PWM

patterns can be produced.

The switching frequency of the generated PWM pattern is pro-

grammable using the 16-bit PWM_TM register. The PWM

generator can operate in single update mode or double update

mode. In single update mode, the duty cycle values are pro-

grammable only once per PWM period, so that the resultant

PWM patterns are symmetrical about the midpoint of the PWM

period. In the double update mode, a second updating of the

PWM registers is implemented at the midpoint of the PWM

period. In this mode, it is possible to produce asymmetrical

PWM patterns that produce lower harmonic distortion in

3-phase PWM inverters.

Pulses synchronous to the switching frequency can be generated

internally and output on the PWMx_SYNC pin. The PWM unit

can also accept externally generated synchronization pulses

through PWMx_SYNC.

Each PWM unit features a dedicated asynchronous shutdown

pin, PWMx_TRIP, which (when brought low) instantaneously

places all six PWM outputs in the OFF state.

SERIAL PORTS

The processors incorporate two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

•I

S capable operation.

• Bidirectional operation—Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports—Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking—Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

• Word length—Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most significant bit

first or least significant bit first.

• Framing—Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware—Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

Rev. B | Page 11 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

• DMA operations with single-cycle overhead—Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts—Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

• Multichannel capability—Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF50x processors have two SPI-compatible ports

that enable the processor to communicate with multiple SPI-

compatible devices.

The SPI interface uses three pins for transferring data: two data

pins MOSI (Master Output-Slave Input) and MISO (Master

Input-Slave Output) and a clock pin, serial clock (SCK). An SPI

chip select input pin (SPIx_SS) lets other SPI devices select the

processor, and three SPI chip select output pins (SPIx_SEL3–1)

let the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are

programmable, and it has an integrated DMA channel,

configurable to support transmit or receive data streams. The

SPI’s DMA channel can only service unidirectional accesses at

any given time.

The SPI port’s clock rate is calculated as:

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS (UARTS)

The ADSP-BF50x Blackfin processors provide two full-duplex

universal asynchronous receiver/transmitter (UART) ports.

Each UART port provides a simplified UART interface to other

peripherals or hosts, enabling full-duplex, DMA-supported,

asynchronous transfers of serial data. A UART port includes

support for five to eight data bits; one or two stop bits; and

none, even, or odd parity. Each UART port supports two modes

of operation:

• PIO (programmed I/O). The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access). The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates. Flexi-

ble interrupt timing options are available on the transmit

side.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

SCLK

/1,048,576) to

SCLK

) bits per second.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as

Where the 16-bit UART divisor comes from the UARTx_DLH

significant eight bits), and the EDBO is a bit in the

UARTx_GCTL register.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The UARTs feature a pair of UAx_RTS (request to send) and

UAx_CTS (clear to send) signals for hardware flow purposes.

The transmitter hardware is automatically prevented from

sending further data when the UAx_CTS input is de-asserted.

The receiver can automatically de-assert its UAx_RTS output

when the enhanced receive FIFO exceeds a certain high-water

level. The capabilities of the UARTs are further extended with

support for the Infrared Data Association (IrDA®) Serial Infra-

red Physical Layer Link Specification (SIR) protocol.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

SPI Clock Rate fSCLK

2 SPI_BAUD

------------------------------------

UART Clock Rate fSCLK

16 1EDBO–

UART_Divisor

------------------------------------------------------------------------

Rev. B | Page 12 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input mode—Frame syncs and data are inputs into the PPI.

• Frame capture mode—Frame syncs are outputs from the

PPI, but data are inputs.

• Output mode—Frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in PPI_-

CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF50x processors

control when to read from the video source(s). PPI_FS1 is an

HSYNC output and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

• Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

RSI INTERFACE

The removable storage interface (RSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), secure digital input/output cards (SDIO), and CE-

ATA hard disk drives. The following list describes the main fea-

tures of the RSI controller.

• Support for a single MMC, SD memory, SDIO card or CE-

ATA hard disk drive

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for 4-bit and 8-bit CE-ATA hard disk drives

• A ten-signal external interface with clock, command, and

up to eight data lines

• Card detection using one of the data signals

• Card interface clock generation from SCLK

• SDIO interrupt and read wait features

• CE-ATA command completion signal recognition and

disable

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF50x processors provide a CAN controller that is a

communication controller implementing the Controller Area

Network (CAN) V2.0B protocol. This protocol is an asynchro-

nous communications protocol used in both industrial and

automotive control systems. CAN is well suited for control

applications due to its capability to communicate reliably over a

network since the protocol incorporates CRC checking, message

error tracking, and fault node confinement.

The CAN controller is based on a 32-entry mailbox RAM and

supports both the standard and extended identifier (ID) mes-

sage formats specified in the CAN protocol specification,

revision 2.0, part B.

Rev. B | Page 13 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Each mailbox consists of eight 16-bit data words. The data is

divided into fields, which includes a message identifier, a time

stamp, a byte count, up to 8 bytes of data, and several control

bits. Each node monitors the messages being passed on the net-

work. If the identifier in the transmitted message matches an

identifier in one of its mailboxes, the module knows that the

message was meant for it, passes the data into its appropriate

mailbox, and signals the processor of message arrival with an

interrupt.

The CAN controller can wake up the processor from sleep mode

upon generation of a wake-up event, such that the processor can

be maintained in a low-power mode during idle conditions.

Additionally, a CAN wake-up event can wake up the on-chip

internal voltage regulator from the powered-down

hibernate state.

The electrical characteristics of each network connection are

very stringent. Therefore, the CAN interface is typically divided

into two parts: a controller and a transceiver. This allows a sin-

gle controller to support different drivers and CAN networks.

The ADSP-BF50x CAN module represents the controller part of

the interface. This module’s network I/O is a single transmit

output and a single receive input, which connect to a line

transceiver.

The CAN clock is derived from the processor system clock

(SCLK) through a programmable divider and therefore does not

require an additional crystal.

TWI CONTROLLER INTERFACE

The processors include a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is compatible with the widely used

bus standard. The TWI module offers the capabilities of

simultaneous master and slave operation, support for both 7-bit

addressing and multimedia data arbitration. The TWI interface

utilizes two pins for transferring clock (SCL) and data (SDA)

and supports the protocol at speeds up to 400K bits/sec. The

TWI interface pins are compatible with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

PORTS

Because of the rich set of peripherals, the processor groups the

many peripheral signals to three ports—Port F, Port G, and

Port H. Most of the associated pins are shared by multiple sig-

nals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The processor has 35 bidirectional, general-purpose I/O (GPIO)

pins allocated across three separate GPIO modules—PORTFIO,

PORTGIO, and PORTHIO, associated with Port F, Port G, and

Port H, respectively. Each GPIO-capable pin shares functional-

ity with other processor peripherals via a multiplexing scheme;

however, the GPIO functionality is the default state of the device

upon power-up. Neither GPIO output nor input drivers are

active by default. Each general-purpose port pin can be individ-

ually controlled by manipulation of the port control, status, and

interrupt registers:

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a differ-

ent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 volt core supply voltage, the

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power

Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

Rev. B | Page 14 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF50x Blackfin Pro-

cessor Hardware Reference.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally, an external event wakes up the processor. When in the

sleep mode, asserting a wakeup enabled in the SIC_IWRx regis-

ters causes the processor to sense the value of the BYPASS bit in

the PLL control register (PLL_CTL). If BYPASS is disabled, the

processor transitions to the full on mode. If BYPASS is enabled,

the processor transitions to the active mode.

DMA accesses to L1 memory are not supported in sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals

may still be running but cannot access internal resources or

external memory. This powered-down mode can only be exited

by assertion of the reset pin (RESET). Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the peripherals (SCLK). This setting sets the internal power sup-

ply voltage (V

DDINT

) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (for

example, memory contents, register contents, and other infor-

mation) must be written to a non-volatile storage device prior to

removing power if the processor state is to be preserved.

Writing 0 to the HIBERNATE bit causes EXT_WAKE to transi-

tion low, which can be used to signal an external voltage

regulator to shut down.

Since V

DDEXT

can still be supplied in this mode, all of the exter-

nal pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to still

have power applied without drawing unwanted current.

The processor can be woken up by asserting the RESET pin. All

hibernate wakeup events initiate the hardware reset sequence.

Individual sources are enabled by the VR_CTL register. The

EXT_WAKE signal indicates the occurrence of a wakeup event.

As long as V

DDEXT

is applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state.

Power Savings

As shown in Table 5, the processor supports three different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from other I/O, the processor can take advan-

tage of dynamic power management without affecting the other

I/O devices. There are no sequencing requirements for the vari-

ous power domains, but all domains must be powered

according to the appropriate Specifications table for processor

operating conditions; even if the feature/peripheral is not used.

The dynamic power management feature of the processor

allows both the processor’s input voltage (V

DDINT

) and clock fre-

quency (f

CCLK

) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Table 4. Power Settings

Mode/State PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full On Enabled No Enabled Enabled On

Active Enabled/

Disabled

Yes Enabled Enabled On

Sleep Enabled — Disabled Enabled On

Deep Sleep Disabled — Disabled Disabled On

Hibernate Disabled — Disabled Disabled Off

Table 5. Power Domains

Power Domain Power Supply

All internal logic, except Memory V

DDINT

Flash Memory V

DDFLASH

All other I/O V

DDEXT

ADC digital supply

(Logic, I/O)

On ADSP-BF506F processor only.

, V

DRIVE

ADC analog supply

Power Savings Factor

fCCLKRED

fCCLKNOM

-------------------------- VDDINTRED

VDDINTNOM

--------------------------------





TRED

TNOM

---------------









% Power Savings 1 Power Savings Factor–100%=

Rev. B | Page 15 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

where the variables in the equations are:

CCLKNOM

is the nominal core clock frequency

CCLKRED

is the reduced core clock frequency

DDINTNOM

is the nominal internal supply voltage

DDINTRED

is the reduced internal supply voltage

NOM

is the duration running at f

CCLKNOM

RED

is the duration running at f

CCLKRED

ADSP-BF50x VOLTAGE REGULATION

The ADSP-BF50x processors require an external voltage regula-

tor to power the V

DDINT

domain. To reduce standby power

consumption, the external voltage regulator can be signaled

through EXT_WAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, all external supplies (V

DDEXT

DDFLASH

) can still be applied, eliminating the need for external

buffers. The external voltage regulator can be activated from

this power down state by asserting the RESET pin, which then

initiates a boot sequence. EXT_WAKE indicates a wakeup to

the external voltage regulator.

The power good (PG) input signal allows the processor to start

only after the internal voltage has reached a chosen level. In this

way, the startup time of the external regulator is detected after

hibernation. For a complete description of the power good

functionality, refer to the ADSP-BF50x Blackfin Processor Hard-

ware Reference.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 4. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the

500 k range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 4 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 4 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in (EE-168) Using Third Overtone

Crystals with the ADSP-218x DSP on the Analog Devices web-

site (www.analog.com)—use site search on “EE-168.”

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 5, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable multiplication factor

(bounded by specified minimum and maximum VCO frequen-

cies). The default multiplier is 6×, but it can be modified by a

software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages V

DDINT

and V

DDEXT

;

the VCO is always permitted to run up to the CCLK frequency

specified by the part’s speed grade. The EXTCLK pin can be

configured to output either the SCLK frequency or the input

buffered CLKIN frequency, called CLKBUF. When configured

to output SCLK (CLKOUT), the EXTCLK pin acts as a refer-

ence signal in many timing specifications. While active by

default, it can be disabled using the EBIU_AMGCTL register.

Figure 4. External Crystal Connections

CLKIN

CLKOUT (SCLK)

XTAL

SELECT

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

18 pF *

330 ⍀*

Blackfin Processor

560 ⍀

EXTCLK

Rev. B | Page 16 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f

SCLK

. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The maximum CCLK frequency both depends on the part’s

speed grade and depends on the applied V

DDINT

voltage. See

Table 14 for details. The maximal system clock rate (SCLK)

depends on the applied V

DDINT

and V

DDEXT

voltages (see

Table 16).

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by the BMODE input pins dedi-

cated to this purpose. There are two categories of boot modes.

In master boot modes, the processor actively loads data from

parallel or serial memories. In slave boot modes, the processor

receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time.

Some boot modes require a boot host wait (HWAIT) signal,

which is a GPIO output signal that is driven and toggled by the

boot kernel at boot time. If pulled high through an external pull-

up resistor, the HWAIT signal behaves active high and will be

driven low when the processor is ready for data. Conversely,

when pulled low, HWAIT is driven high when the processor is

ready for data. When the boot sequence completes, the HWAIT

pin can be used for other purposes. The BMODE pins of the

reset configuration register, sampled during power-on resets

and software-initiated resets, implement the modes shown in

Table 8.

• IDLE State / No Boot (BMODE = 0x0)—In this mode, the

boot kernel transitions the processor into Idle state. The

processor can then be controlled through JTAG for recov-

ery, debug, or other functions.

• Boot from stacked parallel flash in 16-bit asynchronous

mode (BMODE = 0x1)—In this mode, conservative timing

parameters are used to communicate with the flash device.

The boot kernel communicates with the flash device

asynchronously.

• Boot from stacked parallel flash in 16-bit synchronous

mode (BMODE = 0x2)—In this mode, fast timing parame-

ters are used to communicate with the flash device. The

boot kernel configures the flash device for synchronous

burst communication and boots from the flash

synchronously.

Figure 5. Frequency Modification Methods

Table 6. Example System Clock Ratios

Signal Name

SSEL3–0

Divider Ratio

VCO/SCLK

Example Frequency Ratios

(MHz)

VCO SCLK

0001 1:1 50 50

0110 6:1 300 50

1010 10:1 400 40

Table 7. Core Clock Ratios

Signal Name

CSEL1–0

Divider Ratio

VCO/CCLK

Example Frequency Ratios

(MHz)

VCO CCLK

00 1:1 300 300

01 2:1 300 150

10 4:1 400 100

11 8:1 200 25

PLL

0.5uto 64u

÷1to15

÷1,2,4,8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK dCCLK

Table 8. Booting Modes

BMODE2–0 Description

000 Idle/No Boot

001 Boot from internal parallel flash in async mode

This boot mode applies to ADSP-BF504F and ADSP-BF506F processors only.

010 Boot from internal parallel flash in sync mode

011 Boot through SPI0 master from SPI memory

100 Boot through SPI0 slave from host device

101 Boot through PPI from host

110 Reserved

111 Boot through UART0 slave from host device

Rev. B | Page 17 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3)—8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PF13 GPIO

pin to select a single SPI EEPROM/flash device (connected

to the SPI0 interface) and submits a read command and

successive address bytes (0x00) until a valid 8-, 16-, 24-, or

32-bit addressable device is detected. Pull-up resistors are

required on the SPI0_SEL1 and MISO pins. By default, a

value of 0x85 is written to the SPI_BAUD register.

• Boot from SPI host device (BMODE = 0x4)—The proces-

sor operates in SPI slave mode and is configured to receive

the bytes of the LDR file from an SPI host (master) agent.

The HWAIT signal must be interrogated by the host before

every transmitted byte. A pull-up resistor is required on the

SPI0_SS input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

• Boot from PPI host device (BMODE = 0x5)—The proces-

sor operates in PPI slave mode and is configured to receive

the bytes of the LDR file from a PPI host (master) agent.

• Boot from UART0 host on Port G (BMODE = 0x7)—

Using an autobaud handshake sequence, a boot-stream for-

matted program is downloaded by the host. The host

selects a bit rate within the UART clocking capabilities.

When performing the autobaud detection, the UART

expects an “@” (0x40) character (eight bits data, one start

bit, one stop bit, no parity bit) on the UA0_RX pin to deter-

mine the bit rate. The UART then replies with an

acknowledgement composed of 4 bytes (0xBF, the value of

UART0_DLL, the value of UART0_DLH, then 0x00). The

host can then download the boot stream. The processor

deasserts the UA0_RTS output to hold off the host;

UA0_CTS functionality is not enabled at boot time.

For each of the boot modes, a 16 byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the address stored in the EVT1 register.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

later case. Bits 6-4 in the system reset configuration (SYSCR)

kernel in case of a software reset. They can also be used to simu-

late a wakeup-from-hibernate boot in the software reset case.

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to speed up

booting by managing the PLL, clock frequencies, wait states, or

serial bit rates.

The boot ROM also features C-callable functions that can be

called by the user application at run time. This enables second-

stage boot or boot management schemes to be implemented

with ease.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to

provide a flexible, densely encoded instruction set that compiles

to a very small final memory size. The instruction set also

provides fully featured multifunction instructions that allow the

programmer to use many of the processor core resources in a

single instruction. Coupled with many features more often seen

on microcontrollers, this instruction set is very efficient when

compiling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore

Embed-

ded Studio and/or VisualDSP++

), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

The newest IDE, CrossCore Embedded Studio, is based on the

Eclipse

framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

www.analog.com/cces.

Rev. B | Page 18 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite

evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders

, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

•www.analog.com/ucos3

•www.analog.com/ucfs

•www.analog.com/ucusbd

•www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

ADC AND ACM INTERFACE

This section describes the ADC and ACM interface. System

designers should also consult the ADSP-BF50x Blackfin Proces-

sor Hardware Reference for additional information.

The ADC control module (ACM) provides an interface that

synchronizes the controls between the processor and the inter-

nal analog-to-digital converter (ADC) module. The ACM is

available on the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors, and the ADC is available on the

ADSP-BF506F processor only. The analog-to-digital conver-

sions are initiated by the processor, based on external or

internal events.

The ACM allows for flexible scheduling of sampling instants

and provides precise sampling signals to the ADC.

Rev. B | Page 19 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

The ACM synchronizes the ADC conversion process; generat-

ing the ADC controls, the ADC conversion start signal, and

other signals. The actual data acquisition from the ADC is done

by the SPORT peripherals.

The serial interface on the ADC allows the part to be directly

connected to the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors using serial interface protocols.

Figure 6 shows how to connect an external ADC to the ACM

and one of the two SPORTs on the ADSP-BF504 or

ADSP-BF504F processors.

The ADC is integrated into the ADSP-BF506F product. Figure 7

shows how to connect the internal ADC to the ACM and to one

of the two SPORTs on the ADSP-BF506F processor.

The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F proces-

sors interface directly to the ADC without any glue logic

required. The availability of secondary receive registers on the

serial ports of the Blackfin processors means only one serial port

is necessary to read from both D

OUT

pins simultaneously.

Figure 7 (ADC (Internal), ACM, and SPORT Connections)

shows both D

OUT

A and D

OUT

B of the ADC connected to one of

the processor’s serial ports. The SPORTx Receive Configuration

1 register and SPORTx Receive Configuration 2 register should

be set up as outlined in Table 9 (The SPORTx Receive Configu-

ration 1 Register (SPORTx_RCR1)) and Table 10 (The SPORTx

Receive Configuration 2 Register (SPORTx_RCR2)).

Figure 6. ADC (External), ACM, and SPORT Connections

SPORTx

DRxSEC

DRxPRI

RCLKx

RFSx

ADC

(EXTERNAL)

DOUTB

DOUTA

ADSCLK

RANGE

SGL/DIFF

A[2:0]

ACM CS

ACLK

ACM_RANGE

ACM_SGLDIFF

ACM_A[2:0]

ADSP-BF504 / ADSP-BF504F

SPORT

SELECT

MUX

Figure 7. ADC (Internal), ACM, and SPORT Connections

Table 9. The SPORTx Receive Configuration 1 Register

(SPORTx_RCR1)

Setting Description

RCKFE = 0 Sample data with falling edge of RSCLK

LRFS = 1 Active low frame signal

RFSR = 1 Frame every word

IRFS = 0 External RFS used

RLSBIT = 0 Receive MSB first

RDTYPE = 00 Zero fill

IRCLK = 0 External receive clock

RSPEN = 1 Receive enabled

TFSR = RFSR = 1

SPORTx

DRxSEC

DRxPRI

RCLKx

RFSx

ADC

(INTERNAL)

DOUTB

DOUTA

ADSCLK

RANGE

SGL/DIFF

A[2:0]

ACM CS

ACLK

ACM_RANGE

ACM_SGLDIFF

ACM_A[2:0]

ADSP-BF506F

SPORT

SELECT

MUX

Rev. B | Page 20 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

NOTE: The SPORT must be enabled with the following set-

tings: external clock, external frame sync, and active low frame

sync.

To implement the power-down modes, SLEN should be set to

1001 to issue an 8-bit SCLK burst. A Blackfin driver for the

ADC is available to download at www.analog.com.

INTERNAL ADC

An ADC is integrated into the ADSP-BF506F product. All ADC

signals are connected out to package pins to enable maximum

interconnect flexibility in mixed signal applications.

The internal ADC is a dual, 12-bit, high speed, low power, suc-

cessive approximation ADC that operates from a single 2.7 V to

5.25 V power supply and features throughput rates up to

2 MSPS. The device contains two ADCs, each preceded by a

3-channel multiplexer, and a low noise, wide bandwidth track-

and-hold amplifier that can handle input frequencies in excess

of 30 MHz.

Figure 8 shows the functional block diagram of the internal

ADC. The ADC features include:

• Dual 12-bit, 3-channel ADC

• Throughput rate: up to 2 MSPS

• Specified for DV

and AV

of 2.7 V to 5.25 V

• Pin-configurable analog inputs

• 12-channel single-ended inputs

• 6-channel fully differential inputs

• 6-channel pseudo differential inputs

• Accurate on-chip voltage reference: 2.5 V

• Dual conversion with read 437.5 ns, 32 MHz ADSCLK

• High speed serial interface

• SPI-/QSPI

-/MICROWIRE

-/DSP-compatible

•Low power shutdown mode

The conversion process and data acquisition use standard con-

trol inputs allowing easy interfacing to microprocessors or

DSPs. The input signal is sampled on the falling edge of CS; con-

version is also initiated at this point. The conversion time is

determined by the ADSCLK frequency. There are no pipelined

delays associated with the part.

The internal ADC uses advanced design techniques to achieve

very low power dissipation at high throughput rates. The part

also offers flexible power/throughput rate management when

operating in normal mode as the quiescent current consump-

tion is so low.

The analog input range for the part can be selected to be a 0 V to

REF

(or 2 × V

REF

) range, with either straight binary or twos

complement output coding. The internal ADC has an on-chip

2.5 V reference that can be overdriven when an external refer-

ence is preferred.

Additional highlights of the internal ADC include:

• Two complete ADC functions allow simultaneous sam-

pling and conversion of two channels—Each ADC has

three fully/pseudo differential pairs, or six single-ended

channels, as programmed. The conversion result of both

channels is simultaneously available on separate data lines,

or in succession on one data line if only one serial connec-

tion is available.

• High throughput with low power consumption

• The internal ADC offers both a standard 0 V to V

REF

input

range and a 2 × V

REF

input range.

• No pipeline delay—The part features two standard succes-

sive approximation ADCs with accurate control of the

sampling instant via a CS input and once off conversion

control.

Table 10. The SPORTx Receive Configuration 2 Register

(SPORTx_RCR2)

Setting Description

RXSE = 1 Secondary side enabled

SLEN = 1111 16-bit data-word (or may be set to 1101 for

14-bit data-word)

Figure 8. ADC (Internal) Functional Block Diagram

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

DOUTA

OUTPUT

DRIVERS

CONTROL

LOGIC

T/H

BUF

VA1

VA2

VA3

VA4

VA5

VA6

MUX

REF

ADC

VDRIVE

REF SELECT DCAPAAVDD DVDD

BUF

DOUTB

OUTPUT

DRIVERS

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

VB1

VB2

VB3

VB4

VB5

VB6

MUX

AGND AGND AGND DCAPB DGND DGND

ADSCLK

RANGE

SGL/DIFF

Rev. B | Page 21 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC APPLICATION HINTS

The following sections provide application hints for using the

ADC.

Grounding and Layout Considerations

The analog and digital supplies to the ADC are independent and

separately pinned out to minimize coupling between the analog

and digital sections of the device. The printed circuit board

(PCB) that houses the ADC should be designed so that the ana-

log and digital sections are separated and confined to certain

areas of the board. This design facilitates the use of ground

planes that can be easily separated.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All AGND pins should be sunk

in the AGND plane. Digital and analog ground planes should be

joined in only one place. If the ADC is in a system where multi-

ple devices require an AGND to DGND connection, the

connection should still be made at one point only, a star ground

point that should be established as close as possible to the

ground pins on the ADC.

Avoid running digital lines under the device as this couples

noise onto the die. Avoid running digital lines in the area of the

AGND pad as this couples noise onto the ADC die and into the

AGND plane. The power supply lines to the ADC should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line.

To avoid radiating noise to other sections of the board, fast

switching signals, such as clocks, should be shielded with digital

ground, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. To reduce

the effects of feed through within the board, traces on opposite

sides of the board should run at right angles to each other.

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum capacitors in parallel with

0.1 μF capacitors to GND. To achieve the best results from these

decoupling components, they must be placed as close as possible

to the device, ideally right up against the device. The 0.1 μF

capacitors should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types or surface-mount types. These low ESR and ESI capacitors

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

ADDITIONAL INFORMATION

The following publications that describe the ADSP-BF50x pro-

cessors (and related processors) can be ordered from any

Analog Devices sales office or accessed electronically on our

website:

•Getting Started With Blackfin Processors

•ADSP-BF50x Blackfin Processor Hardware Reference (vol-

umes 1 and 2)

•Blackfin Processor Programming Reference

•ADSP-BF50x Blackfin Processor Anomaly List

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

Lab

site (http:\\www.analog.com\signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. B | Page 22 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

SIGNAL DESCRIPTIONS

Signal definitions for the ADSP-BF50x processors are listed in

Table 11. All pins for the ADC (ADSP-BF506F processor only)

are listed in Table 12.

In order to maintain maximum function and reduce package

size and pin count, some pins have multiple, multiplexed func-

tions. In cases where pin function is reconfigurable, the default

state is shown in plain text, while the alternate functions are

shown in italics.

During and immediately after reset, all processor signals (not

ADC signals) are three-stated with the following exceptions:

EXT_WAKE is driven high and XTAL is driven in conjunction

with CLKIN to create a crystal oscillator circuit. During

hibernate, all signals are three-stated with the following excep-

tions: EXT_WAKE is driven low and XTAL is driven to a solid

logic level.

During and immediately after reset, all I/O pins have their input

buffers disabled until enabled by user software with the excep-

tion of the pins that need pull-ups or pull-downs, as noted in

Table 11.

Adding a parallel termination to CLKOUT may prove useful in

further enhancing signal integrity. Be sure to verify over-

shoot/undershoot and signal integrity specifications on actual

hardware.

Table 11. Processor—Signal Descriptions

Signal Name Type Function

Driver

Type

Port F: GPIO and Multiplexed Peripherals

PF0/TSCLK0/UA0_RX/TMR6/CUD0 I/O GPIO/SPORT0TXSerialCLK/UART0RX/Timer6/Count Up Dir 0 C

PF1/RSCLK0/UA0_TX/TMR5/CDG0 I/O GPIO/SPORT0RX SerialCLK/UART0TX/Timer5/Count Down Dir0 C

PF2/DT0PRI/PWM0_BH/PPI_D8/CZM0 I/O GPIO/SPORT0TXPriData/PWM0Drive B Hi/PPIData8/Counter Zero Marker 0 C

PF3/TFS0/PWM0_BL/PPI_D9/CDG0 I/O GPIO/SPORT0TXFrameSync/PWM0Drive B Lo/PPIData9/Count Down Dir0 C

PF4/RFS0/PWM0_CH/PPI_D10/TACLK0 I/O GPIO/SPORT0RXFrameSync/PWM0Drive C Hi/PPIData10/AltTimerCLK0 C

PF5/DR0PRI/PWM0_CL/PPI_D11/TACLK1 I/O GPIO/SPORT0PriRX Data/PWM0Drive C Lo/PPIData11/AltTimerCLK1 C

PF6/UA1_TX/PWM0_TRIP/PPI_D12 I/O GPIO/UART1TX/PWM0TRIP/PPIData12 C

PF7/UA1_RX/PWM0_SYNC/PPI_D13/TACI3 I/O GPIO/UART1RX/PWM0SYNC/PPIData13/AltCaptureIn3 C

PF8/UA1_RTS/DT0SEC/PPI_D7 I/O GPIO/UART1 RTS/SPORT0 TX Sec Data/PPI Data 7 C

PF9/UA1_CTS/DR0SEC/PPI_D6/CZM0 I/O GPIO/UART1CTS/SPORT0 Sec RX Data/PPIData6/Counter Zero Marker0 C

PF10/SPI0_SCK/TMR2/PPI_D5 I/O GPIO/SPI0SCK/Timer2/PPIData 5 C

PF11/SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2 I/O GPIO/SPI0 MISO/PWM0 TRIP/PPI Data 4/Alt Timer CLK 2 C

PF12/SPI0_MOSI/PWM0_SYNC/PPI_D3 I/O GPIO/SPI0 MOSI/ PWM0 SYNC/PPI Data 3 C

PF13/SPI0_SEL1/TMR3/PPI_D2/SPI0_SS I/O GPIO/SPI0 Slave Select 1/Timer3/PPI Data 2/SPI0 Slave Select In C

PF14/SPI0_SEL2/PWM0_AH/PPI_D1 I/O GPIO/SPI0 Slave Select 2/PWM0 AH/PPI Data 1 C

PF15/SPI0_SEL3/PWM0_AL/PPI_D0 I/O GPIO/SPI0 Slave Select 3/PWM0 AL/PPI Data 0 C

Port G: GPIO and Multiplexed Peripherals

PG0/SPI1_SEL3/TMRCLK/PPI_CLK/UA1_RX/TACI4 I/O GPIO/SPI1 Slave Select 3/Timer CLK/PPI Clock/UART1 RX/Alt Capture In 4 C

PG1/SPI1_SEL2/PPI_FS3/CAN_RX/TACI5 I/O GPIO/SPI1 Slave Select 2/PPI FS3/CAN RX/Alt Capture In 5 C

PG2/SPI1_SEL1/TMR4/CAN_TX/SPI1_SS I/O GPIO/SPI1 Slave Select 1/Timer4/CAN TX/SPI1 Slave Select In C

PG3/HWAIT/SPI1_SCK/DT1SEC/UA1_TX I/O GPIO/HWAIT/SPI1 SCK/SPORT1 TX Sec Data/UART1 TX C

PG4/SPI1_MOSI/DR1SEC/PWM1_SYNC/TACLK6 I/O GPIO/SPI1 MOSI/SPORT1 Sec RX Data/PWM1 SYNC/Alt Timer CLK 6 C

PG5/SPI1_MISO/TMR7/PWM1_TRIP I/O GPIO/SPI1MISO/Timer7/PWM1 TRIP C

PG6/ACM_SGLDIFF/SD_D3/PWM1_AH I/O GPIO/ADCCMSGL DIFF/SDData 3/PWM1Drive A Hi C

PG7/ACM_RANGE/SD_D2/PWM1_AL I/O GPIO/ADC CM RANGE/SD Data 2/PWM1 Drive A Lo C

PG8/DR1SEC/SD_D1/PWM1_BH I/O GPIO/SPORT1 Sec RX Data/SDData1/PWM1Drive B Hi C

PG9/DR1PRI/SD_D0/PWM1_BL I/O GPIO/SPORT1PriRX Data/SDData 0/PWM1Drive B Lo C

PG10/RFS1/SD_CMD/PWM1_CH/TACI6 I/O GPIO/SPORT1RX FrameSync/SDCMD/PWM1 Drive C Hi/AltCaptureIn6 C

PG11/RSCLK1/SD_CLK/PWM1_CL/TACLK7 I/O GPIO/SPORT1 RX Serial CLK/SD CLK/PWM1 Drive C Lo/Alt Timer CLK 7 C

PG12/UA0_RX/SD_D4/PPI_D15/TACI2 I/O GPIO/UART0RX/SDData4/PPIData 15/AltCaptureIn2 C

PG13/UA0_TX/SD_D5/PPI_D14/CZM1 I/O GPIO/UART0TX/SDData5/PPIData14/Counter Zero Marker 1 C

Rev. B | Page 23 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1 I/O GPIO/UART0 RTS/SD Data 6/Timer0/PPI FS1/Count Up Dir 1 C

PG15/UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1 I/O GPIO/UART0 CTS/SD Data 7/Timer1/PPI FS2/Count Down Dir 1 C

Port H: GPIO and Multiplexed Peripherals

PH0/ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP I/O GPIO/ADCCM A2/SPORT1TXPri Data/SPI0SlaveSelect 3/Wake-up Input C

PH1/ACM_A1/TFS1/SPI1_SEL3/TACLK3 I/O GPIO/ADCCMA1/SPORT1TX FrameSync/SPI1SlaveSelect3/AltTimerCLK3 C

PH2/ACM_A0/TSCLK1/SPI1_SEL2/TACI7 I/O GPIO/ADC CM A0/SPORT1 TX Serial CLK/SPI1 Slave Select 2/Alt Capture In 7 C

TWI (2-Wire Interface) Port

SCL I/O

TWI Serial Clock (This signal is an open-drain output and requires a pull-up

resistor. Consult version 2.1 of the I

C specification for the proper resistor

value.)

SDA I/O

TWI Serial Data (This signal is an open-drain output and requires a pull-up

resistor. Consult version 2.1 of the I

C specification for the proper resistor

value.)

JTAG Port

TCK I JTAG CLK

TDO O JTAG Serial Data Out C

TDI I JTAG Serial Data In

TMS I JTAG Mode Select

TRST I JTAG Reset

(This signal should be pulled low if the JTAG port is not used.)

EMU O Emulation Output C

Clock

CLKIN I CLK/Crystal In

XTAL O Crystal Output

EXTCLK O Clock Output B

Mode Controls

RESET IReset

NMI I Nonmaskable Interrupt

(This signal should be pulled high when not used.)

BMODE2–0 I Boot Mode Strap 2-0

ADSP-BF50x Voltage Regulation I/F

EXT_WAKE O Wake up Indication C

PG I Power Good

Power Supplies ALL SUPPLIES MUST BE POWERED

See Operating Conditions on Page 26.

DDEXT

PI/OPowerSupply

DDINT

P Internal Power Supply

DDFLASH

P Flash Memory Power Supply

GND G Ground for All Supplies

Table 11. Processor—Signal Descriptions (Continued)

Signal Name Type Function

Driver

Type

Rev. B | Page 24 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only)

Signal Name Type Function

DGND G Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND

pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be

at the same potential and must not be more than 0.3 V apart, even on a transient basis.

REF SELECT I Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference

is used as the reference source for both ADC A and ADC B. In addition, Pin D

CAP

A and Pin D

CAP

B must be

tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be

supplied to the internal ADC through the D

CAP

A and/or D

CAP

B pins.

P Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the

internal ADC. The AV

and DV

voltages should ideally be at the same potential and must not be more

than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.

CAP

A, D

CAP

B (V

REF

) I Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins

to decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip

reference can be taken from these pins and applied externally to the rest of a system. The range of the

external reference is dependent on the analog input range selected.

AGND G Analog Ground. Ground reference point for all analog circuitry on the internal ADC. All analog input

signals and any external reference signal should be referred to this AGND voltage. All three of these

AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should

be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

to V

I Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differ-

ential analog input channel pairs. See Table 53 (Analog Input Type and Channel Selection).

to V

I Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differ-

ential analog input channel pairs. See Table 53 (Analog Input Type and Channel Selection).

RANGE I Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the

analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to V

REF

. If this pin is

tied to a logic high when CS goes low, the analog input range is 2 × V

REF

. For details, see Table 53 (Analog

Input Type and Channel Selection).

SGL/DIFF I Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single

ended. A logic low selects differential operation while a logic high selects single-ended operation. For

details, see Table 53 (Analog Input Type and Channel Selection).

A0 to A2 I Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultane-

ously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and

so on. The pair of channels selected may be two single-ended channels or two differential pairs. The

logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge

of CS to correctly set up the multiplexer for that conversion. For further details, see Table 53 (Analog

Input Type and Channel Selection).

CS I Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the internal ADC and framing the serial data transfer. When connecting CS to a processor signal that is

three-stated during reset and/or hibernate, adding a pull-up resistor may prove useful to avoid random

ADC operation.

ADSCLK I Serial Clock. Logic input. A serial clock input provides the ADSCLK for accessing the data from the

internal ADC. This clock is also used as the clock source for the conversion process.

Rev. B | Page 25 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

OUT

A, D

OUT

B O Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked

out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data

simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream

consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first.

If CS is held low for 16 ADSCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits

of data. If CS is held low for a further 16 ADSCLK cycles on either D

OUT

A or D

OUT

B, the data from the other

ADC follows on the D

OUT

pin. This allows data from a simultaneous conversion on both ADCs to be

gathered in serial format on either D

OUT

A or D

OUT

B using only one serial port. For more information, see

the ADC—Serial Interface section.

DRIVE

P Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the digital I/O

interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than

that at AV

and DV

but should never exceed either by more than 0.3 V.

P Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the internal

ADC. The DV

and AV

voltages should ideally be at the same potential and must not be more than

0.3 V apart even on a transient basis. This supply should be decoupled to DGND.

Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) (Continued)

Signal Name Type Function

Rev. B | Page 26 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS

Table 13 shows settings for TWI_DT in the NONGPIO_DRIVE

Parameter Conditions Min Nominal Max Unit

DDINT

Internal Supply Voltage Industrial Models 1.14 1.47 V

Internal Supply Voltage Commercial Models 1.10 1.47 V

Internal Supply Voltage Automotive Models 1.33 1.47 V

DDEXT1, 2

Must remain powered (even if the associated function is not used).

1.8 V and 2.5 V I/O are supported only on ADSP-BF504 nonautomotive models. All ADSP-BF50x flash and automotive models support 3.3 V I/O only.

External Supply Voltage 1.8 V I/O, ADSP-BF504, Nonautomotive

and Non Flash Models

1.7 1.8 1.9 V

External Supply Voltage 2.5 V I/O, ADSP-BF504, Nonautomotive

and Non Flash Models

2.25 2.5 2.75 V

External Supply Voltage 3.3 V I/O, ADSP-BF50x, All Models 2.7 3.3 3.6 V

DDFLASH1,

For ADSP-BF504, V

DDFLASH

pins should be connected to GND.

Flash Memory Supply Voltage 1.7 1.8 2.0 V

High Level Input Voltage

4, 5

Parameter value applies to all input and bidirectional pins, except SDA and SCL.

Bidirectional pins (PF15–0, PG15–0, PH15–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF50x processors are 2.5 V

tolerant (always accept up to 2.7 V maximum V

). Voltage compliance (on outputs, V

) is limited by the V

DDEXT

supply voltage.

DDEXT

= 1.90 V 1.2 V

High Level Input Voltage

4, 6

Bidirectional pins (PF15–0, PG15–0, PH2–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF50x processors are 3.3 V tolerant

(always accept up to 3.6 V maximum V

). Voltage compliance (on outputs, V

) is limited by the V

DDEXT

supply voltage.

DDEXT

= 2.75 V 1.7 V

High Level Input Voltage

4, 6

DDEXT

= 3.6 V 2.0 V

IHTWI

High Level Input Voltage

DDEXT

= 1.90 V/2.75 V/3.6 V 0.7 × V

BUSTWI7, 8

The V

IHTWI

min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V

BUSTWI

min and max values in Table 13.

SDA and SCL are pulled up to V

BUSTWI

. See Table 13.

BUSTWI7, 8

Low Level Input Voltage

4, 5

DDEXT

= 1.7 V 0.6 V

Low Level Input Voltage

4, 6

DDEXT

= 2.25 V 0.7 V

Low Level Input Voltage

4, 6

DDEXT

= 3.0 V 0.8 V

ILTWI

Low Level Input Voltage

DDEXT

= minimum 0.3 × V

BUSTWI8

Junction Temperature 88-Lead LFCSP @ T

AMBIENT

= –40°C to +85°C –40 +105 °C

Junction Temperature 88-Lead LFCSP @ T

AMBIENT

= 0°C to +70°C 0 +90 °C

Junction Temperature 120-Lead LQFP @ T

AMBIENT

= –40°C to +85°C –40 +105 °C

Junction Temperature 120-Lead LQFP @ T

AMBIENT

= 0°C to +70°C 0 +90 °C

Junction Temperature 88-Lead LFCSP @ T

AMBIENT

= –40°C to +105°C –40 +125 °C

Table 13. TWI_DT Field Selections and V

DDEXT

BUSTWI

TWI_DT V

DDEXT

Nominal V

BUSTWI

Minimum V

BUSTWI

Nominal V

BUSTWI

Maximum Unit

000 (default) 3.3 2.97 3.3 3.63 V

001 1.8 1.7 1.8 1.98 V

010 2.5 2.97 3.3 3.63 V

011 1.8 2.97 3.3 3.63 V

100 3.3 4.5 5 5.5 V

101 1.8 2.25 2.5 2.75 V

110 2.5 2.25 2.5 2.75 V

111 (reserved)—————

Rev. B | Page 27 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADSP-BF50x Clock Related Operating Conditions

Table 14 describes the core clock timing requirements for the

ADSP-BF50x processors. Take care in selecting MSEL, SSEL,

and CSEL ratios so as not to exceed the maximum core clock

and system clock (see Table 16). Table 15 describes phase-

locked loop operating conditions.

Table 14. Core Clock (CCLK) Requirements—ADSP-BF50x Processors—All Speed Grades

Parameter Min V

DDINT

Nom V

DDINT

Max CCLK

Frequency Unit

CCLK

Core Clock Frequency (All Models) 1.33 V 1.400 V 400 MHz

Core Clock Frequency (Industrial/Commercial Models) 1.16 V 1.225 V 300 MHz

Core Clock Frequency (Industrial Models Only) 1.14 V 1.200 V 200 MHz

Core Clock Frequency (Commercial Models Only) 1.10 V 1.150 V 200 MHz

Table 15. Phase-Locked Loop Operating Conditions

Parameter Min Max Unit

VCO

Voltage Controlled Oscillator (VCO) Frequency

(Commercial/Industrial Models)

72 Instruction Rate

MHz

Voltage Controlled Oscillator (VCO) Frequency

(Automotive Models)

84 Instruction Rate

MHz

For more information, see Ordering Guide on Page 81.

Table 16. Maximum SCLK Conditions for ADSP-BF50x Processors

Parameter V

DDEXT

= 1.8 V/2.5 V/3.3 V Nominal Unit

SCLK

CLKOUT/SCLK Frequency (V

DDINT

 1.16 V) 100 MHz

CLKOUT/SCLK Frequency (V

DDINT

 1.16 V) 80 MHz

Rev. B | Page 28 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typical Max Unit

High Level Output Voltage V

DDEXT

= 1.7 V, I

= –0.5 mA 1.35 V

High Level Output Voltage V

DDEXT

= 2.25 V, I

= –0.5 mA 2.0 V

High Level Output Voltage V

DDEXT

= 3.0 V, I

= –0.5 mA 2.4 V

Low Level Output Voltage V

DDEXT

= 1.7 V/2.25 V/3.0 V,

= 2.0 mA

0.4 V

High Level Input Current

DDEXT

=3.6 V, V

= 3.6 V 10.0 μA

Low Level Input Current

DDEXT

=3.6 V, V

= 0 V 10.0 μA

IHP

High Level Input Current JTAG

DDEXT

= 3.6 V, V

= 3.6 V 75.0 μA

OZH

Three-State Leakage Current

DDEXT

= 3.6 V, V

= 3.6 V 10.0 μA

OZHTWI

Three-State Leakage Current

DDEXT

=3.0 V, V

= 5.5 V 10.0 μA

OZL

Three-State Leakage Current

DDEXT

= 3.6 V, V

= 0 V 10.0 μA

Input Capacitance

5,6

= 1 MHz, T

AMBIENT

= 25°C,

=2.5V

58 pF

INTWI

Input Capacitance

4,6

= 1 MHz, T

AMBIENT

= 25°C,

=2.5V

10 pF

DDDEEPSLEEP7

DDINT

Current in Deep Sleep Mode V

DDINT

= 1.2 V, f

CCLK

= 0 MHz,

SCLK

=0MHz, T

= 25°C,

ASF = 0.00

1.85 mA

DDSLEEP

DDINT

Current in Sleep Mode V

DDINT

= 1.2 V, f

SCLK

= 25 MHz,

= 25°C

2.1 mA

DD-IDLE

DDINT

Current in Idle V

DDINT

= 1.2 V, f

CCLK

= 50 MHz,

= 25°C, ASF = 0.42

18 mA

DD-TYP

DDINT

Current V

DDINT

= 1.40 V, f

CCLK

= 400 MHz,

= 25°C, ASF = 1.00

104 mA

DDINT

Current V

DDINT

= 1.225 V, f

CCLK

= 300 MHz,

= 25°C, ASF = 1.00

69 mA

DDINT

Current V

DDINT

= 1.2 V, f

CCLK

= 200 MHz,

= 25°C, ASF = 1.00

51 mA

DDHIBERNATE8

Hibernate State Current V

DDEXT

=3.30V,

DDFLASH

=1.8 V, T

= 25°C,

CLKIN = 0 MHz (V

DDINT

= 0 V)

40 A

DDSLEEP9

DDINIT

Current in Sleep Mode f

CCLK

= 0 MHz, f

SCLK

 0 MHz Table 18 +

(.16 × V

DDINT

× f

SCLK

)

DDDEEPSLEEP9

DDINT

Current in Deep Sleep Mode f

CCLK

= 0 MHz, f

SCLK

= 0 MHz Table 18 mA

DDINT9

DDINT

Current f

CCLK

 0 MHz, f

SCLK

 0 MHz Table 18 +

(Table 19 × ASF) +

(.16 × V

DDINT

× f

SCLK

)

DDFLASH1

Flash Memory Supply Current 1

— Asynchronous Read (5 MHz

NORCLK

)

10 20 mA

Flash Memory Supply Current 1

— Synchronous Read (50 MHz

NORCLK

)

4 Word 18 20 mA

8 Word 20 22 mA

16 Word 25 27 mA

Continuous 28 30 mA

Rev. B | Page 29 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

DDFLASH2

Flash Memory Supply Current 2

— Reset/Powerdown

15 50 μA

DDFLASH3

Flash Memory Supply Current 3

— Standby

15 50 μA

DDFLASH4

Flash Memory Supply Current 4

— Automatic Standby

15 50 μA

DDFLASH5

Flash Memory Supply Current 5

— Program

15 40 mA

Flash Memory Supply Current 5

— Erase

15 40 mA

DDFLASH6

Flash Memory Supply Current 6

— Dual Operations

Program/Erase in one bank,

asynchronous read in

another bank

25 60 mA

Program/Erase in one bank,

synchronous read in another

bank

43 70 mA

DDFLASH7

Flash Memory Supply Current 7

— Program/Erase Suspended

(Standby)

15 50 μA

Applies to input pins.

Applies to JTAG input pins (TCK, TDI, TMS, TRST).

Applies to three-statable pins.

Applies to bidirectional pins SCL and SDA.

Applies to all signal pins, except SCL and SDA.

Guaranteed, but not tested.

See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

Applies to V

DDEXT

supply only. Clock inputs are tied high or low.

Guaranteed maximum specifications.

Unit for V

DDINT

is V (Volts). Unit for f

SCLK

is MHz. Example: 1.4 V, 75 MHz would be 0.16 × 1.4 × 75 = 16.8 mA adder.

See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of NORCLK.

Parameter Test Conditions Min Typical Max Unit

Rev. B | Page 30 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Total Power Dissipation

Total power dissipation has two components:

1. Static, including leakage current

2. Dynamic, due to transistor switching characteristics

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. Electrical Characteristics on Page 28 shows the

current dissipation for internal circuitry (V

DDINT

). I

DDDEEPSLEEP

specifies static power dissipation as a function of voltage

DDINT

) and temperature (see Table 18), and I

DDINT

specifies the

total power specification for the listed test conditions, including

the dynamic component as a function of voltage (V

DDINT

) and

frequency (Table 19).

There are two parts to the dynamic component. The first part is

due to transistor switching in the core clock (CCLK) domain.

This part is subject to an Activity Scaling Factor (ASF) which

represents application code running on the processor core and

L1 memories (Table 17).

The ASF is combined with the CCLK Frequency and V

DDINT

dependent data in Table 19 to calculate this part. The second

part is due to transistor switching in the system clock (SCLK)

domain, which is included in the I

DDINT

specification equation.

Table 17. Activity Scaling Factors (ASF)

See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors

(EE-297). The power vector information also applies to the ADSP-BF50x

processors.

DDINT

Power Vector Activity Scaling Factor (ASF)

DD-PEAK

1.27

DD-HIGH

1.24

DD-TYP

1.00

DD-APP

0.85

DD-NOP

0.71

DD-IDLE

0.42

Table 18. Static Current—I

DD-DEEPSLEEP

(mA)

(°C)

Voltage (V

DDINT

)

1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V

–40 0.20 0.23 0.26 0.29 0.31 0.34 0.37 0.40 0.43

–20 0.30 0.34 0.38 0.43 0.47 0.51 0.55 0.59 0.63

0 0.50 0.57 0.63 0.70 0.77 0.83 0.90 0.97 1.03

25 0.90 1.03 1.17 1.30 1.43 1.57 1.70 1.83 1.97

40 1.30 1.50 1.70 1.90 2.10 2.30 2.50 2.70 2.90

55 2.00 2.30 2.60 2.90 3.20 3.50 3.80 4.10 4.40

70 3.00 3.47 3.93 4.40 4.87 5.33 5.80 6.27 6.73

85 4.60 5.23 5.87 6.50 7.13 7.77 8.40 9.03 9.67

100 6.80 7.67 8.53 9.40 10.27 11.13 12.00 12.87 13.73

105 7.80 8.77 9.73 10.70 11.67 12.63 13.60 14.57 15.53

125 12.50 14.00 15.50 17.00 18.50 20.00 21.50 23.00 24.50

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 26.

Table 19. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)

CCLK

(MHz)

Voltage (V

DDINT

)

1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V

400 N/A N/A N/A N/A 84.46 88.30 92.39 96.35 100.49

350 N/A N/A N/A N/A 74.30 77.93 81.39 84.94 88.61

300 N/A N/A 58.58 61.46 64.49 67.59 70.71 73.76 77.04

250 43.76 46.22 48.64 51.09 53.61 56.19 58.93 61.56 64.22

200 35.26 37.37 39.29 41.33 43.40 45.54 47.79 49.88 52.18

150 26.71 28.38 29.87 31.46 33.09 34.83 36.56 38.22 39.95

100 18.04 19.20 20.25 21.46 22.61 23.83 25.13 26.39 27.72

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 28.

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 26 and ADSP-BF50x Clock Related Operating Conditions on Page 27.

Rev. B | Page 31 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PROCESSOR—ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 20 may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 22 specifies the maximum total source/sink (I

) cur-

rent for a group of pins. Permanent damage can occur if this

value is exceeded. To understand this specification, if pins PG5,

PG6, PG7, PG8, and PG9 from group 5 in the Total Current Pin

Groups table, each were sourcing or sinking 2 mA each, the

total current for those pins would be 10 mA. This would allow

up to 66 mA total that could be sourced or sunk by the remain-

ing pins in the group without damaging the device. For a list of

all groups and their pins, see the Total Current Pin Groups

table. Note that the V

and V

specifications have separate

per-pin maximum current requirements, see the Electrical

Characteristics table.

Table 20. Absolute Maximum Ratings

Parameter Rating

Internal Supply Voltage (V

DDINT

)–0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)–0.3 V to +3.8 V

Input Voltage

1, 2

Applies to 100% transient duty cycle. For other duty cycles see Table 21.

Applies only when V

DDEXT

is within specifications. When V

DDEXT

is outside speci-

fications, the range is V

DDEXT

± 0.2 V.

–0.5 V to +3.6 V

Input Voltage

1, 2, 3

Applies to pins SCL and SDA.

–0.5 V to +5.5 V

Output Voltage Swing –0.5 V to

DDEXT

+0.5 V

Current per Pin Group

For more information, see description preceding Table 22.

76 mA (max)

Storage Temperature Range –65°C to +150°C

Junction Temperature While Biased

(Nonautomotive Models)

+110°C

Junction Temperature While Biased

(Automotive Models)

+125°C

Table 21. Maximum Duty Cycle for Input Transient Voltage

Applies to all signal pins with the exception of CLKIN, XTAL, EXT_WAKE.

Min (V)

The individual values cannot be combined for analysis of a single instance of

overshoot or undershoot. The worst case observed value must fall within one of

the voltages specified, and the total duration of the overshoot or undershoot

(exceeding the 100% case) must be less than or equal to the corresponding duty

cycle.

Max (V)

Maximum Duty Cycle

Duty cycle refers to the percentage of time the signal exceeds the value for the

100% case. The is equivalent to the measured duration of a single instance of

overshoot or undershoot as a percentage of the period of occurrence.

–0.50 +3.80 100%

–0.70 +4.00 40%

–0.80 +4.10 25%

–0.90 +4.20 15%

–1.00 +4.30 10%

Table 22. Total Current Pin Groups

Group Pins in Group

1PF10, PF11

2 PF12, PF13, PF14, PF15

3PG0

4 PG1, PG2, PG3, PG4

5 PG5, PG6, PG7, PG8, PG9, PG10, PG11

6 PG12, PG13, PG14, PG15, SDA, SCL

7EMU

, EXT_WAKE, PG

8 PF0, PF1, PH0, PH1, PH2

9EXTCLK

10 PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9

Rev. B | Page 32 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ESD SENSITIVITY PACKAGE INFORMATION

The information presented in Figure 9 and Table 23 provides

details about the package branding for the ADSP-BF50x

processors.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary circuitry, damage may occur

on devices subjected to high energy ESD. Therefore,

proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

Figure 9. Product Information on Package

Table 23. Package Brand Information

Nonautomotive only. For branding information specific to Automotive

products, contact Analog Devices Inc.

Brand Key Field Description

ADSP-BF50x Product Name

See product names in the Ordering Guide on Page 81.

t Temperature Range

pp Package Type

Z RoHS Compliant Designation

ccc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliance Designator

yyww Date Code

vvvvvv.x n.n

tppZccc

ADSP-BF50x

#yyww country_of_origin

Rev. B | Page 33 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PROCESSOR—TIMING SPECIFICATIONS

Specifications subject to change without notice.

Clock and Reset Timing

Table 24 and Figure 10 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 14 to

Table 16, combinations of CLKIN and clock multipliers must

not select core/peripheral clocks in excess of the processor’s

speed grade. Table 25 and Figure 11 describe clock out timing.

Table 24. Clock and Reset Timing

Parameter Min Max Unit

Timing Requirements

CKIN

CLKIN Frequency

1, 2, 3, 4

(Commercial/Industrial Models) 12 50 MHz

CLKIN Frequency

1, 2, 3, 4

(Automotive Models) 14 50 MHz

CKINL

CLKIN Low Pulse

10 ns

CKINH

CLKIN High Pulse

10 ns

WRST

RESET Asserted Pulse Width Low

11 × t

CKIN

Switching Characteristic

BUFDLAY

CLKIN to CLKBUF

Delay 11 ns

Applies to PLL bypass mode and PLL non bypass mode.

Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f

VCO

, f

CCLK

, and f

SCLK

settings discussed in Table 14 on Page 27 through

Table 16 on Page 27.

The t

CKIN

period (see Figure 10) equals 1/f

CKIN

If the DF bit in the PLL_CTL register is set, the minimum f

CKIN

specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.

Applies after power-up sequence is complete. See Table 26 and Figure 12 for power-up reset timing.

The ADSP-BF504/ADSP-BF504F/ ADSP-BF506F processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or

CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF.

Figure 10. Clock and Reset Timing

CLKIN

tWRST

tCKIN

tCKINL tCKINH

tBUFDLAY

RESET

CLKBUF

Rev. B | Page 34 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 25. Clock Out Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Switching Characteristics

SCLK

CLKOUT

Period

2,3

10 10 ns

SCLKH

CLKOUT

Width High 44ns

SCLKL

CLKOUT

Width Low 44ns

The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or

CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT.

The t

SCLK

value is the inverse of the f

SCLK

specification. Reduced supply voltages affect the best-case value of 10 ns listed here.

The t

SCLK

value does not account for the effects of jitter.

Figure 11. Clock Out Timing

tSCLKL tSCLKH

tSCLK

CLKOUT

Table 26. Power-Up Reset Timing

Parameter Min Max Unit

Timing Requirement

RST

PWR

RESET Deasserted after the V

DDINT

, V

DDEXT

, V

DDFLASH

, and CLKIN Pins are Stable and

Within Specification

3500 × t

CKIN

In Figure 12, V

DD_SUPPLIES

is V

DDINT

, V

DDEXT

, and V

DDFLASH

Figure 12. Power-Up Reset Timing

RESET

tRST_IN_PWR

CLKIN

VDD_SUPPLIES

Rev. B | Page 35 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Parallel Peripheral Interface Timing

Table 27 and Figure 14 on Page 35, Figure 20 on Page 40, and

Figure 22 on Page 41 describe parallel peripheral interface

operations.

Table 27. Parallel Peripheral Interface Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

PCLKW

PPI_CLK Width

SCLK

–1.5 t

SCLK

–1.5 ns

PCLK

PPI_CLK Period

2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

Timing Requirements—GP Input and Frame Capture Modes

PSUD

External Frame Sync Startup Delay

4 × t

PCLK

4 × t

PCLK

SFSPE

External Frame Sync Setup Before PPI_CLK

(Nonsampling Edge for Rx, Sampling Edge for Tx)

6.7 6.7 ns

HFSPE

External Frame Sync Hold After PPI_CLK 1.5 1.5 ns

SDRPE

Receive Data Setup Before PPI_CLK 4.1 3.5 ns

HDRPE

Receive Data Hold After PPI_CLK 2 1.6 ns

Switching Characteristics—GP Output and Frame Capture Modes

DFSPE

Internal Frame Sync Delay After PPI_CLK 8.7 8.0 ns

HOFSPE

Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns

DDTPE

Transmit Data Delay After PPI_CLK 8.7 8.0 ns

HDTPE

Transmit Data Hold After PPI_CLK 2.3 1.9 ns

PPI_CLK frequency cannot exceed f

SCLK

The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words

guaranteed to be received correctly by the PPI peripheral.

Figure 13. PPI with External Frame Sync Timing

Figure 14. PPI GP Rx Mode with External Frame Sync Timing

PPI_CLK

PPI_FS1/2

tPSUD

tPCLK

tSFSPE

DATA SAMPLED /

FRAME SYNC SAMPLED

DATA SAMPLED /

FRAME SYNC SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tHFSPE

tHDRPE

tSDRPE

tPCLKW

Rev. B | Page 36 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 15. PPI GP Tx Mode with External Frame Sync Timing

Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing

Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing

tHDTPE

tSFSPE

DATA DRIVEN /

FRAME SYNC SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tHFSPE

tDDTPE

tPCLK

tPCLKW

tHDRPE

tSDRPE

tHOFSPE

FRAME SYNC

DRIVEN

DATA

SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tDFSPE

tPCLK

tPCLKW

tHOFSPE

FRAME SYNC

DRIVEN

DATA

DRIVEN

PPI_DATA

PPI_CLK

PPI_FS1/2

tDFSPE

tDDTPE tHDTPE

tPCLK

tPCLKW

DATA

DRIVEN

Rev. B | Page 37 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

RSI Controller Timing

Table 28 and Figure 18 describe RSI Controller Timing.

Table 29 and Figure 19 describe RSI controller (high speed)

timing.

Table 28. RSI Controller Timing

Parameter Min Max Unit

Timing Requirements

ISU

Input Setup Time 5.75 ns

Input Hold Time 2 ns

Switching Characteristics

PP1

Clock Frequency Data Transfer Mode 0 25 MHz

Clock Frequency Identification Mode 100

400 kHz

Clock Low Time 10 ns

Clock High Time 10 ns

TLH

Clock Rise Time 10 ns

THL

Clock Fall Time 10 ns

ODLY

Output Delay Time During Data Transfer Mode 14 ns

ODLY

Output Delay Time During Identification Mode 50 ns

= 1/f

Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

Figure 18. RSI Controller Timing

SD_CLK

INPUT

OUTPUT

tISU

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

tTHL tTLH

tWL tWH

tPP

tIH

tODLY

VOH (MIN)

VOL (MAX)

Rev. B | Page 38 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 29. RSI Controller Timing (High Speed Mode)

Parameter Min Max Unit

Timing Requirements

ISU

Input Setup Time 5.75 ns

Input Hold Time 2 ns

Switching Characteristics

PP1

Clock Frequency Data Transfer Mode 0 50 MHz

Clock Low Time 7 ns

Clock High Time 7 ns

TLH

Clock Rise Time 3ns

THL

Clock Fall Time 3ns

ODLY

Output Delay Time During Data Transfer Mode 2.5 ns

Output Hold Time 2.5 ns

= 1/f

Figure 19. RSI Controller Timing (High-Speed Mode)

SD_CLK

INPUT

OUTPUT

tISU

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

tTHL tTLH

tWL tWH

tPP

tIH

tODLY tOH

VOH (MIN)

VOL (MAX)

Rev. B | Page 39 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Serial Ports

Table 30 through Table 33 on Page 41 and Figure 20 on Page 40

through Figure 22 on Page 41 describe serial port operations.

Table 30. Serial Ports—External Clock

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

SFSE

TFSx/RFSx Setup Before TSCLKx/RSCLKx

3.0 3.0 ns

HFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx

3.0 3.0 ns

SDRE

Receive Data Setup Before RSCLKx

1,2

3.0 3.0 ns

HDRE

Receive Data Hold After RSCLKx

1,2

3.5 3.0 ns

SCLKEW

TSCLKx/RSCLKx Width 4.5 4.5 ns

SCLKE

TSCLKx/RSCLKx Period 2 × t

SCLK

2 × t

SCLK

Switching Characteristics

DFSE

TFSx/RFSx Delay After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)

10.0 10.0 ns

HOFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)

0.0 0.0 ns

DDTE

Transmit Data Delay After TSCLKx

11.0 10.0 ns

HDTE

Transmit Data Hold After TSCLKx

0.0 0.0 ns

Referenced to sample edge.

When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).

Referenced to drive edge.

Table 31. Serial Ports—Internal Clock

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

SFSI

TFSx/RFSx Setup Before TSCLKx/RSCLKx

11.0 9.6 ns

HFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx

–1.5 –1.5 ns

SDRI

Receive Data Setup Before RSCLKx

1,2

11.5 10.0 ns

HDRI

Receive Data Hold After RSCLKx

1,2

–1.5 –1.5 ns

Switching Characteristics

SCLKIW

TSCLKx/RSCLKx Width 7.0 8.0 ns

DFSI

TFSx/RFSx Delay After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)

4.0 3.0 ns

HOFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)

–2.0 –1.0 ns

DDTI

Transmit Data Delay After TSCLKx

4.0 3.0 ns

HDTI

Transmit Data Hold After TSCLKx

–1.8 –1.5 ns

Referenced to sample edge.

When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).

Referenced to drive edge.

Rev. B | Page 40 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 20. Serial Ports

Table 32. Serial Ports—Enable and Three-State

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Switching Characteristics

DTENE

Data Enable Delay from External TSCLKx

0.0 0.0 ns

DDTTE

Data Disable Delay from External TSCLKx

SCLK

+1 t

SCLK

+1 ns

DTENI

Data Enable Delay from Internal TSCLKx

–2.0 –2.0 ns

DDTTI

Data Disable Delay from Internal TSCLKx

SCLK

+1 t

SCLK

+1 ns

Referenced to drive edge.

Figure 21. Serial Ports — Enable and Three-State

tSDRI

RSCLKx

DRx

DRIVE EDGE

tHDRI

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

DATA RECEIVE—INTERNAL CLOCK

tSDRE

DATA RECEIVE—EXTERNAL CLOCK

RSCLKx

DRx

tHDRE

tSFSE tHFSE

tDFSE

tSCLKEW

tHOFSE

tDDTI

tHDTI

TSCLKx

TFSx

(INPUT)

DTx

tSFSI tHFSI

tSCLKIW

tDFSI

tHOFSI

DATA TRANSMIT—INTERNAL CLOCK

tDDTE

tHDTE

TSCLKx

DTx

tSFSE

tDFSE

tSCLKEW

tHOFSE

DATA TRANSMIT—EXTERNAL CLOCK

SAMPLE EDGE

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

DRIVE EDGE SAMPLE EDGE

tSCLKE

tHFSE

TFSx

(OUTPUT)

TFSx

(INPUT)

TFSx

(OUTPUT)

RFSx

(INPUT)

RFSx

(OUTPUT)

RFSx

(INPUT)

RFSx

(OUTPUT)

TSCLKx

DTx

DRIVE EDGE

tDDTTE/I

tDTENE/I

DRIVE EDGE

Rev. B | Page 41 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 33. Serial Ports — External Late Frame Sync

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFSx

or External RFSx in Multi-channel Mode With MFD = 0

1, 2

12.0 10.0 ns

DTENLFSE

Data Enable from External RFSx in Multi-channel Mode With

MFD = 0

1, 2

0.0 0.0 ns

When in multi-channel mode, TFSx enable and TFSx valid follow t

DTENLFSE

and t

DDTLFSE

If external RFSx/TFSx setup to RSCLKx/TSCLKx > t

SCLKE

/2 then t

DDTTE/I

and t

DTENE/I

apply, otherwise t

DDTLFSE

and t

DTENLFSE

apply.

Figure 22. Serial Ports — External Late Frame Sync

RSCLKx

RFSx

DTx

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

EXTERNAL RFSx IN MULTI-CHANNEL MODE

1ST BIT

tDTENLFSE

tDDTLFSE

TSCLKx

TFSx

DTx

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

LATE EXTERNAL TFSx

1ST BIT

tDDTLFSE

Rev. B | Page 42 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Serial Peripheral Interface (SPI) Port—Master Timing

Table 34 and Figure 23 describe SPI port master operations.

Table 34. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SCK Edge (Data Input Setup) 11.6 9.6 ns

HSPIDM

SCK Sampling Edge to Data Input Invalid –1.5 –1.5 ns

Switching Characteristics

SDSCIM

SPISELx low to First SCK Edge 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPICHM

Serial Clock High Period 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPICLM

Serial Clock Low Period 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPICLK

Serial Clock Period 4 × t

SCLK

–1.5 4 × t

SCLK

–1.5 ns

HDSM

Last SCK Edge to SPISELx High 2 × t

SCLK

–2.0 2 × t

SCLK

–1.5 ns

SPITDM

Sequential Transfer Delay 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

DDSPIDM

SCK Edge to Data Out Valid (Data Out Delay) 0606ns

HDSPIDM

SCK Edge to Data Out Invalid (Data Out Hold) –1.0 –1.0 ns

Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing

tSDSCIM tSPICLK tHDSM tSPITDM

tSPICLM tSPICHM

tHDSPIDM

tHSPIDM

tSSPIDM

SPIxSELy

(OUTPUT)

SPIxSCK

(OUTPUT)

SPIxMOSI

(OUTPUT)

SPIxMISO

(INPUT)

SPIxMOSI

(OUTPUT)

SPIxMISO

(INPUT)

CPHA = 1

CPHA = 0

tDDSPIDM

tHSPIDM

tSSPIDM

tHDSPIDM

tDDSPIDM

Rev. B | Page 43 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 35 and Figure 24 describe SPI port slave operations.

Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

SPICHS

Serial Clock High Period 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPICLS

Serial Clock Low Period 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPICLK

Serial Clock Period 4 × t

SCLK

4 × t

SCLK

HDS

Last SCK Edge to SPISS Not Asserted 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SPITDS

Sequential Transfer Delay 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SDSCI

SPISS Assertion to First SCK Edge 2 × t

SCLK

–1.5 2 × t

SCLK

–1.5 ns

SSPID

Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 ns

HSPID

SCK Sampling Edge to Data Input Invalid 2.0 1.6 ns

Switching Characteristics

DSOE

SPISS Assertion to Data Out Active 0 12.0 0 10.3 ns

DSDHI

SPISS Deassertion to Data High Impedance 0 11.0 0 9.0 ns

DDSPID

SCK Edge to Data Out Valid (Data Out Delay) 10 10 ns

HDSPID

SCK Edge to Data Out Invalid (Data Out Hold) 0 0 ns

Figure 24. Serial Peripheral Interface (SPI) Port—Slave Timing

tSPICLK tHDS tSPITDS

tSDSCI tSPICLS tSPICHS

tDSOE tDDSPID

tDDSPID tDSDHI

tHDSPID

tSSPID

tDSDHI

tHDSPID

tDSOE

tHSPID

tSSPID

tDDSPID

SPIxSS

(INPUT)

SPIxSCK

(INPUT)

SPIxMISO

(OUTPUT)

SPIxMOSI

(INPUT)

SPIxMISO

(OUTPUT)

SPIxMOSI

(INPUT)

CPHA = 1

CPHA = 0

tHSPID

Rev. B | Page 44 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

The UART ports receive and transmit operations are described

in the ADSP-BF50x Hardware Reference Manual.

General-Purpose Port Timing

Table 36 and Figure 25 describe general-purpose

port operations.

Table 36. General-Purpose Port Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirement

WFI

General-Purpose Port Pin Input Pulse Width t

SCLK

+ 1 t

SCLK

+ 1 ns

Switching Characteristic

GPOD

General-Purpose Port Pin Output Delay from CLKOUT High 0 11.0 0 8.9 ns

Figure 25. General-Purpose Port Timing

CLKOUT

GPIO OUTPUT

GPIO INPUT

tWFI

tGPOD

Rev. B | Page 45 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Timer Cycle Timing

Table 37 and Figure 26 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (f

SCLK

/2) MHz.

Table 37. Timer Cycle Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

Timer Pulse Width Input Low

(Measured In SCLK Cycles)

1 × t

SCLK

1 × t

SCLK

Timer Pulse Width Input High

(Measured In SCLK Cycles)

1 × t

SCLK

1 × t

SCLK

TIS

Timer Input Setup Time Before CLKOUT Low

10 8 ns

TIH

Timer Input Hold Time After CLKOUT Low

–2 –2 ns

Switching Characteristics

HTO

Timer Pulse Width Output

(Measured In SCLK Cycles)

1 × t

SCLK

– 2.0 (2

–1) × t

SCLK

1 × t

SCLK

– 1.5 (2

–1) × t

SCLK

TOD

Timer Output Update Delay After CLKOUT High 6 6 ns

The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.

Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

Figure 26. Timer Cycle Timing

CLKOUT

TMRx OUTPUT

TMRx INPUT

tTIS tTIH

tWH,tWL

tTOD

tHTO

Rev. B | Page 46 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Timer Clock Timing

Table 38 and Figure 27 describe timer clock timing.

Up/Down Counter/Rotary Encoder Timing

Table 38. Timer Clock Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Switching Characteristic

TODP

Timer Output Update Delay After PPI_CLK High 12.0 12.0 ns

Figure 27. Timer Clock Timing

Table 39. Up/Down Counter/Rotary Encoder Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

WCOUNT

Up/Down Counter/Rotary Encoder Input Pulse Width t

SCLK

+ 1 t

SCLK

+ 1 ns

CIS

Counter Input Setup Time Before CLKOUT High

Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

9.0 7.0 ns

CIH

Counter Input Hold Time After CLKOUT High

00ns

Figure 28. Up/Down Counter/Rotary Encoder Timing

PPI_CLK

TMRx OUTPUT

tTODP

CLKOUT

CUD/CDG/CZM

tCIS

tCIH

tWCOUNT

Rev. B | Page 47 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Pulse Width Modulator (PWM) Timing

Table 40 and Figure 29 describe PWM operations.

Table 40. PWM Timing

Parameter Min Max Unit

Timing Requirement

External Sync Pulse Width 2 × t

SCLK

+ 1 ns

Switching Characteristics

DODIS

Output

Inactive (OFF) After Trip Input 12 ns

DOE

Output

Delay After External Sync

2 × t

SCLK

5 × t

SCLK

+ 13 ns

Output

Delay After Falling Edge of CLKOUT 5 ns

PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.

When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is

asynchronous to the peripheral clock. For more information, see the ADSP-BF50x Blackfin Processor Hardware Reference.

Figure 29. PWM Timing

PWMx_TRIP

PWMx_SYNC

(AS INPUT)

tES

tDOE

OUTPUT

tOD

tDODIS

CLKOUT

Rev. B | Page 48 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC Controller Module (ACM) Timing

Table 41 and Figure 30 describe ACM operations.

Note that the ACM clock (ACLK) frequency in MHz is set by

the following equation (in which ACMCKDIV ranges from

0 to 255).

fACLK

fSCLK

2ACMCKDIV2+

--------------------------------------------------------

tACLK

fACLK

--------------

Table 41. ACM Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

SDR

SPORT DRxPRI/DRxSEC Setup Before ACLK 8.0 7.0 ns

HDR

SPORT DRxPRI/DRxSEC Hold After ACLK 0 0 ns

Switching Characteristics

ACM Controls (ACM_A[2:0], ACM_RANGE, ACM_SGLDIFF) Delay

After Falling Edge of CLKOUT

8.4 8.4 ns

DACLK

ACLK Delay After Falling Edge of CLKOUT 4.5 4.5 ns

DCS

CS Active Edge Delay After Falling Edge of CLKOUT 5.6 5.3 ns

DCSACLK

The Delay Between the Active Edge of CS and the First Edge of

ACLK

– 5 t

ACLK

– 5 ns

Figure 30. ACM Timing

tDCSACLK

ACLK

ACM

CONTROLS

DRxPRI/

DRxSEC

CLKOUT

tDCS

tDACLK

tDO

tSDR tHDR

Rev. B | Page 49 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

JTAG Test And Emulation Port Timing

Table 42 and Figure 31 describe JTAG port operations.

Table 42. JTAG Port Timing

Parameter

DDEXT

= 1.8 V V

DDEXT

= 2.5 V/3.3 V

Min Max Min Max Unit

Timing Requirements

TCK

TCK Period 20 20 ns

STAP

TDI, TMS Setup Before TCK High 4 4 ns

HTAP

TDI, TMS Hold After TCK High 4 4 ns

SSYS

System Inputs Setup Before TCK High

44ns

STWI

TWI System Inputs Setup Before TCK High

n/a 5 ns

HSYS

System Inputs Hold After TCK High

55ns

TRSTW

TRST Pulse Width

(measured in TCK cycles) 4 4 TCK

Switching Characteristics

DTDO

TDO Delay from TCK Low 10 10 ns

DSYS

System Outputs Delay After TCK Low

12 12 ns

Applies to System Inputs = PF15–0, PG15–0, PH2–0, NMI, BMODE3–0, RESET.

Applies to TWI System Inputs = SCL, SDA. For SDA and SCL system inputs, the system design must comply with V

DDEXT

and VBUSTWI voltages specified for the default

TWI_DT (000) setting in Table 13.

50 MHz Maximum.

System Outputs = EXTCLK, SCL, SDA, PF15–0, PG15–0, PH2–0.

Figure 31. JTAG Port Timing

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

tSTWI

Rev. B | Page 50 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PROCESSOR—OUTPUT DRIVE CURRENTS

Figure 32 through Figure 40 show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF50xF

processors.

The curves represent the current drive capability of the output

drivers. See Table 11 on Page 22 for information about which

driver type corresponds to a particular pin.

Figure 32. Driver Type B Current (3.3 V V

DDEXT

)

Figure 33. Driver Type B Current (2.5 V V

DDEXT

)

Figure 34. Driver Type B Current (1.8 V V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

240

120

–240

–120

–40

VOL

VOH

VDDEXT = 3.6V @ – 55

VDDEXT = 3.3V @ 25

–80

–200

160 VDDEXT = 3.0V @ 125

–160

200

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5

160

120

–160

–40

VOL

VOH

VDDEXT = 2.75V @ – 55

VDDEXT = 2.5V @ 25

–80

VDDEXT = 2.25V @ 125

–120

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5

–60

–20

VOL

VOH

VDDEXT = 1.9V @ – 55

VDDEXT = 1.8V @ 25

–40

VDDEXT = 1.7V @ 155

–80

Figure 35. Driver Type C Current (3.3 V V

DDEXT

)

Figure 36. Drive Type C Current (2.5 V V

DDEXT

)

Figure 37. Driver Type C Current (1.8 V V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

100

–100

–60

–20

VOL

VOH

VDDEXT = 3.6V @ – 55

VDDEXT = 3.3V @ 25

–40

–80

80 VDDEXT = 3.0V @ 125

120

–120

2.5

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0

–80

–20

VOL

VOH

VDDEXT = 2.75V @ – 55

VDDEXT = 2.5V @ 25

–40

VDDEXT = 2.25V @ 125

–60

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5

–50

–40

–10

VOL

VOH

VDDEXT = 1.9V @ – 55

VDDEXT = 1.8V @ 25

–20

VDDEXT = 1.7V @ 125

–30

Rev. B | Page 51 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PROCESSOR—TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 41

shows the measurement point for AC measurements (except

output enable/disable). The measurement point V

MEAS

is V

DDEXT

for V

DDEXT

(nominal) = 1.8 V/2.5 V/3.3 V.

Output Enable Time Measurement

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time t

ENA

is the interval from the point when a

reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 42.

The time t

ENA

MEASURED

is the interval, from when the reference sig-

nal switches, to when the output voltage reaches V

TRIP

(high) or

TRIP

(low). For V

DDEXT

(nominal) = 1.8 V, V

TRIP

(high) is 1.05 V,

and V

TRIP

(low) is 0.75 V. For V

DDEXT

(nominal) = 2.5 V, V

TRIP

(high) is 1.5 V and V

TRIP

(low) is 1.0 V. For V

DDEXT

(nominal) =

3.3 V, V

TRIP

(high) is 1.9 V, and V

TRIP

(low) is 1.4 V. Time t

TRIP

the interval from when the output starts driving to when the

output reaches the V

TRIP

(high) or V

TRIP

(low) trip voltage.

Time t

ENA

is calculated as shown in the equation:

If multiple pins are enabled, the measurement value is that of

the first pin to start driving.

Figure 38. Driver Type D Current (3.3 V V

DDEXT

)

Figure 39. Driver Type D Current (2.5 V V

DDEXT

)

Figure 40. Driver Type D Current (1.8 V V

DDEXT

)

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

–40

–10

VOL

VDDEXT = 3.6V @ – 55

VDDEXT = 3.3V @ 25

–20

–30

VDDEXT = 3.0V @ 125

–50

–60

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5

–35

–25

–10

VOL

VDDEXT = 2.75V @ – 55

VDDEXT = 2.5V @ 25

–15

VDDEXT = 2.25V @ 125

–20

–5

–30

SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)

0 0.5 1.0 1.5 2

–16

–12

VOL

VDDEXT = 1.9V @ – 55

VDDEXT = 1.8V @ 25

–14

VDDEXT = 1.7V @ 125

–2

–4

–8

–6

–10

Figure 41. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Figure 42. Output Enable/Disable

INPUT

OUTPUT

MEAS

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

VOH (MEASURED) ⴚ ⌬V

VOL (MEASURED) + ⌬V

tDIS_MEASURED

VOH

(MEASURED)

VOL

(MEASURED)

VTRIP(HIGH)

VOH(MEASURED

)

VOL(MEASURED)

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

tDECAY

tENA_MEASURED

tTRIP

VTRIP(LOW)

tENA tENA_MEASURED tTRIP

–=

Rev. B | Page 52 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Output Disable Time Measurement

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t

DIS

is the

difference between t

DIS

MEASURED

and t

DECAY

as shown on the left side

of Figure 42.

The time for the voltage on the bus to decay by V is dependent

on the capacitive load C

and the load current I

. This decay time

can be approximated by the equation:

The time t

DECAY

is calculated with test loads C

and I

, and with

V equal to 0.25 V for V

DDEXT

(nominal) = 2.5 V/3.3 V and

0.15 V for V

DDEXT

(nominal) = 1.8 V.

The time t

DIS

MEASURED

is the interval from when the reference sig-

nal switches, to when the output voltage decays V from the

measured output high or output low voltage.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t

DECAY

using the equation given above. Choose V

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. C

the total bus capacitance (per data line), and I

is the total leak-

age or three-state current (per data line). The hold time will be

DECAY

plus the various output disable times as specified in the

Processor—Timing Specifications on Page 33.

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 43). V

LOAD

is equal

to (V

DDEXT

) /2. The graphs of Figure 44 through Figure 49 show

how output rise time varies with capacitance. The delay and

hold specifications given should be derated by a factor derived

from these figures. The graphs in these figures may not be linear

outside the ranges shown.

Figure 43. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

tDIS tDIS_MEASURED tDECAY

–=

tDECAY CLVIL

=

ZO = 50:(impedance)

TD = 4.04 r 1.18 ns

2pF

TESTER PIN ELECTRONICS

50:

0.5pF

70:

400:

45:

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

LOAD

DUT

OUTPUT

50:

Figure 44. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8 V V

DDEXT

)

Figure 45. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5 V V

DDEXT

)

Figure 46. Driver Type B Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3 V V

DDEXT

)

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

tRISE

tFALL

tRISE = 1.8V @ 25

tFALL = 1.8V @ 25

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

tRISE

tFALL

tRISE = 2.5V @ 25

tFALL = 2.5V @ 25

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

tRISE

tFALL

tRISE = 3.3V @ 25

tFALL = 3.3V @ 25

Rev. B | Page 53 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

PROCESSOR—ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application

printed circuit board use:

where: T

= junction temperature (°C).

CASE

= case temperature (°C) measured by customer at top cen-

ter of package.



= from Table 43 and Table 44.

= power dissipation (see Total Power Dissipation on Page 30

for the method to calculate P

Values of 

are provided for package comparison and printed

circuit board design considerations. 

can be used for a first

order approximation of T

by the equation:

where T

= ambient temperature (°C).

Values of 

are provided for package comparison and printed

circuit board design considerations when an external heat sink

is required.

Values of 

are provided for package comparison and printed

circuit board design considerations.

In Table 43 and Table 44, airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6, and the junction-to-

board measurement complies with JESD51-8. The junction-to-

case measurement complies with MIL-STD-883 (Method

1012.1). All measurements use a 2S2P JEDEC test board.

Figure 47. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (1.8 V V

DDEXT

)

Figure 48. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (2.5 V V

DDEXT

)

Figure 49. Driver Type C Typical Rise and Fall Times (10%–90%) vs.

Load Capacitance (3.3 V V

DDEXT

)

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

tRISE

tFALL

tRISE = 1.8V @ 25

tFALL = 1.8V @ 25

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

RISE

FALL

RISE

= 2.5V @ 25

FALL

= 2.5V @ 25

RISE AND FALL TIME (ns)

LOAD CAPACITANCE (pF)

0 50 100 150 250

200

tRISE

tFALL

tRISE = 3.3V @ 25

tFALL = 3.3V @ 25

Table 43. Thermal Characteristics (88-Lead LFCSP)

Parameter Condition Typical Unit



0 linear m/s air flow 26.2 °C/W



JMA

1 linear m/s air flow 23.7 °C/W



JMA

2 linear m/s air flow 22.9 °C/W



16.0 °C/W



9.8 °C/W



0 linear m/s air flow 0.21 °C/W



1 linear m/s air flow 0.36 °C/W



2 linear m/s air flow 0.43 °C/W

Table 44. Thermal Characteristics (120-Lead LQFP)

Parameter Condition Typical Unit



0 linear m/s air flow 26.9 °C/W



JMA

1 linear m/s air flow 24.2 °C/W



JMA

2 linear m/s air flow 23.3 °C/W



16.4 °C/W



12.7 °C/W



0 linear m/s air flow 0.50 °C/W



1 linear m/s air flow 0.77 °C/W



2 linear m/s air flow 1.02 °C/W

TJTCASE JT PD

+=

TJTAJA PD

+=

Rev. B | Page 54 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

FLASH—SPECIFICATIONS

Specifications subject to change without notice.

FLASH—PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The program and erase times and the number of program/ erase

cycles per block are shown in Table 45. Exact erase times may

change depending on the memory array condition. The best

case is when all the bits in the block or bank are at ‘0’

(pre programmed). The worst case is when all the bits in the

block or bank are at ‘1’ (not pre programmed). Usually, the

system overhead is negligible with respect to the erase time.

FLASH—ABSOLUTE MAXIMUM RATINGS

Table 46 shows the ADC absolute maximum ratings.

Table 45. Program/Erase Times and Endurance Cycles

Parameter Condition Typical

Typical

After 100k

Write/Erase

Cycles Max Unit

Erase Parameter Block (4K word)

0.31 2.5s

Erase Main Block (32K word)—preprogrammed 0.8 3 4 s

Erase Main Block (32K word)—not preprogrammed 1 4 s

Program

Word 12 12 100 s

Program

Parameter Block (4K word) 40 ms

Program

Main Block (32K word) 300 ms

Suspend Latency Program 5 10 s

Suspend Latency Erase 5 20 s

Program/Erase Cycles (per Block) Main Blocks 100,000 Cycles

Program/Erase Cycles (per Block) Parameter Blocks 100,000 Cycles

The difference between pre programmed and not pre programmed is not significant (< 30 ms).

Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).

Table 46. Flash Absolute Maximum Ratings

Parameter Rating

Junction Temperature While Biased See Table 20 on

Page 31

Storage Temperature Range See Table 20 on

Page 31

Flash Memory Supply Voltage (V

DDFLASH

) –0.2 V to +2.45 V

Rev. B | Page 55 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC—SPECIFICATIONS

Specifications are subject to change without notice.

ADC—OPERATING CONDITIONS

Parameter Conditions Min Nominal Max Unit

DD1

(AV

, DV

, V

DRIVE

)

Throughout the ADC sections of this data sheet, V

refers to both AV

and DV

ADSCLK

= 24 MHz, f

up to 1.5 MSPS,

internal or external reference = 2.5 V ± 1%

unless otherwise noted

2.7 3.6 V

ADSCLK

= 25 MHz, f

up to 1.56 MSPS,

internal or external reference = 2.5 V ± 1%

unless otherwise noted

3.0 3.6 V

ADSCLK

= 32 MHz, f

up to 2.0 MSPS,

internal or external reference = 2.5 V ± 1%

unless otherwise noted

4.75 (AV

, DV

)

2.7 (V

DRIVE

)

5.25 (AV

, DV

)

5.25 (V

DRIVE

)

Junction Temperature 120-Lead LQFP @ T

AMBIENT

= –40°C to +85°C –40 +105 °C

Table 47. Operating Conditions (Analog, Voltage Reference, and Logic I/O)

Parameter Specification Unit Test Conditions/Comments

ANALOG INPUT

Single-Ended Input Range 0 V to V

REF

V RANGE= low

0 V to 2 × V

REF

VRANGE = high

Pseudo Differential Input Range: V

IN+

– V

IN–2

0 V to V

REF

V RANGE = low

2 × V

REF

VRANGE = high

Fully Differential Input Range: V

IN+

and V

IN–

± V

REF

/2 V V

= common-mode voltage

= V

REF

/2, RANGE = low

± V

REF

= V

REF

, RANGE = high

DC Leakage Current ±1 μA max V

to V

, V

to V

Input Capacitance

45 pF typ When in track

10 pF typ When in hold

INTERNAL VOLTAGE REFERENCE (OUTPUT)

Reference Output Voltage 2.5 ± 0.4% V @ 25°C, AV

= 2.7 V to 5.25 V

Long-Term Stability

150 ppm typ For 1000 hours

Output Voltage Thermal Hysteresis

50 ppm typ

CAP

A, D

CAP

B Output Impedance

10  typ

Reference Temperature Coefficient

60 max, 20 typ ppm/°C

REF

Noise

20 μV rms typ

EXTERNAL VOLTAGE REFERENCE (INPUT)

Reference Input Voltage Range

0.1 to AV

V See ADC—Typical Performance Characteristics

DC Leakage Current

±2 μA max

Input Capacitance

25 pF typ

DIGITAL LOGIC INPUTS

Input High Voltage, V

INH

2.8 V min

Input Low Voltage, V

INL

0.4 V max

Input Current, I

±15 nA typ V

= 0 V or V

DRIVE

Input Capacitance, C

IN4

5 pF typ

Rev. B | Page 56 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

DIGITAL LOGIC OUTPUTS

Output High Voltage, V

DRIVE

– 0.2 V min No DC load (I

= 0 mA)

Output Low Voltage, V

0.4 V max No DC load (I

= 0 mA)

Floating State Leakage Current ±1 μA max V

= 0 V or V

DRIVE

Floating State Output Capacitance

7 pF typ

Output Coding

Straight (natural) binary

twos complement

IN–

or V

IN+

must remain within GND/V

IN–

= 0 V for specified performance. For full input range on V

IN–

pin, see Figure 74 and Figure 75.

For full common-mode range, see Figure 70 and Figure 71.

Sample tested during initial release to ensure compliance.

Relates to Pin D

CAP

A or Pin D

CAP

B (V

REF

See ADC—Terminology on Page 61.

External voltage reference applied to Pins D

CAP

A, Pin D

CAP

B (V

REF

See Table 52 and Table 53.

Table 48. Operating Conditions (ADC Performance/Accuracy)

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR) 71 dB min f

= 14 kHz sine wave; differential mode

69 dB min f

= 14 kHz sine wave; single-ended and

pseudo differential modes

Signal-to-(Noise + Distortion) Ratio (SINAD)

70 dB min f

= 14 kHz sine wave; differential mode

68 dB min f

= 14 kHz sine wave; single-ended and

pseudo differential modes

Total Harmonic Distortion (THD)

–77 dB max f

= 14 kHz sine wave; differential mode

–73 dB max f

= 14 kHz sine wave; single-ended and

pseudo differential modes

Spurious-Free Dynamic Range (SFDR)

–75 dB max f

= 50 kHz sine wave

Intermodulation Distortion (IMD)

1,2

= 30 kHz, fb = 50 kHz

Second-Order Terms –88 dB typ

Third-Order Terms –88 dB typ

Channel-to-Channel Isolation –88 dB typ

SAMPLE AND HOLD

Aperture Delay

11 ns max

Aperture Jitter

50 ps typ

Aperture Delay Matching

200 ps max

Full Power Bandwidth 33/26 MHz typ @ 3 dB, AV

, DV

= 5 V/AV

, DV

= 3 V

3.5/3 MHz typ @ 0.1 dB, AV

, DV

= 5 V/AV

, DV

= 3 V

Table 47. Operating Conditions (Analog, Voltage Reference, and Logic I/O) (Continued)

Parameter Specification Unit Test Conditions/Comments

Rev. B | Page 57 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity (INL)

±1 LSB max ±0.7 LSB typ; differential mode

±1.5 LSB max ±0.9 LSB typ; single-ended and pseudo

differential modes

Differential Nonlinearity (DNL)

±0.99 LSB max Differential mode

–0.99/+1.5 LSB max Single-ended and pseudo differential modes

Straight Natural Binary Output Coding

Offset Error

1,2

±7 LSB max

Offset Error Match

1,2

±2 LSB typ

Gain Error

1,2

±2.5 LSB max

Gain Error Match

1,2

±0.5 LSB typ

Twos Complement Output Coding

Positive Gain Error

1,2

±2 LSB max

Positive Gain Error Match

1,2

±0.5 LSB typ

Zero Code Error

1,2

±5 LSB max

Zero Code Error Match

1,2

±1 LSB typ

Negative Gain Error

1,2

±2 LSB max

Negative Gain Error Match

1,2

±0.5 LSB typ

CONVERSION RATE

Conversion Time 14 ADSCLK cycles 437.5 ns with ADSCLK = 32 MHz

Track-and-Hold Acquisition Time

90 ns max Full-scale step input; AV

, DV

= 5 V

110 ns max Full-scale step input; AV

, DV

= 3 V

Throughput Rate 2 MSPS max

See ADC—Terminology on Page 61.

Sample tested during initial release to ensure compliance.

Guaranteed no missed codes to 12 bits.

Table 49. Operating Conditions (Power

)

Parameter Specification Unit Test Conditions/Comments

POWER SUPPLY REQUIREMENTS

2.7/5.25 V min/V max

DRIVE

2.7/5.25 V min/V max

Digital Logic Inputs = 0 V or V

DRIVE

Normal Mode (Static) 2.3 mA max V

= 5.25 V

Operational

= 2 MSPS 6.4 mA max V

= 5.25 V; 5.7 mA typ

= 1.5 MSPS 4 mA max V

= 3.6 V; 3.4 mA typ

Partial Power-Down Mode 500 μA max Static

Full Power-Down Mode (V

)2.8 μA maxStatic

POWER DISSIPATION

Normal Mode (Operational) 33.6 mW max V

= 5.25 V

Partial Power-Down (Static) 2.625 mW max V

= 5.25 V

Full Power-Down (Static) 14.7 μW max V

= 5.25 V

In this table, V

refers to both AV

and DV

Table 48. Operating Conditions (ADC Performance/Accuracy) (Continued)

Parameter Specification Unit Test Conditions/Comments

Rev. B | Page 58 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC—TIMING SPECIFICATIONS

ADC—ABSOLUTE MAXIMUM RATINGS

Stresses above those listed in Table 51 may cause permanent

damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above

those indicated in the operational section of this specification is

not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Table 50. Serial Data Interface

See Figure 87 on Page 72 and Figure 88 on Page 72.

Parameter Specification Unit Test Conditions / Comments

ADSCLK2

Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.

1/32 MHz min/max

CONVERT

14 × t

ADSCLK

ns max t

ADSCLK

= 1/f

ADSCLK

437.5 ns max f

ADSCLK

= 32 MHz, f

SAMPLE

= 2 MSPS; AV

, DV

= 5 V

560.0 ns max f

ADSCLK

= 25 MHz, f

SAMPLE

= 1.56 MSPS; AV

, DV

= 3 V

583.3 ns max f

ADSCLK

= 24 MHz, f

SAMPLE

= 1.5 MSPS; AV

, DV

= 2.7 V

QUIET

30 ns min Minimum time between end of serial read and next falling edge of CS

18/23 ns min CS to ADSCLK setup time; V

= 5 V/3 V

15 ns max Delay from CS until D

OUT

A and D

OUT

B are three-state disabled

The time required for the output to cross 0.4 V or 2.4 V.

27/36 ns max Data access time after ADSCLK falling edge, V

= 5 V/3 V

0.45 t

ADSCLK

ns min ADSCLK low pulse width

0.45 t

ADSCLK

ns min ADSCLK high pulse width

5/10 ns min ADSCLK to data valid hold time, V

= 5 V/3 V

15 ns max CS rising edge to D

OUT

A, D

OUT

B, high impedance

30 ns min CS rising edge to falling edge pulse width

5/35 ns min/max ADSCLK falling edge to D

OUT

A, D

OUT

B, high impedance

Table 51. Absolute Maximum Ratings

Parameter Rating

, DV

to AGND –0.3 V to +7 V

to DGND –0.3 V to +7 V

DRIVE

to DGND –0.3 V to DV

DRIVE

to AGND –0.3 V to AV

to DV

–0.3 V to +0.3 V

AGND to DGND –0.3 V to +0.3 V

Analog Input Voltage to AGND –0.3 V to AV

+ 0.3 V

Digital Input Voltage to DGND –0.3 V to +7 V

Digital Output Voltage to GND –0.3 V to V

DRIVE

+ 0.3 V

REF

to AGND –0.3 V to AV

+ 0.3 V

Input Current to Any ADC Pin

Except Supplies

Transient currents of up to 100 mA will not cause latch up.

±10 mA

Storage Temperature Range See Table 20 on Page 31

Junction Temperature Under Bias See Table 20 on Page 31

Rev. B | Page 59 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC—TYPICAL PERFORMANCE CHARACTERISTICS

= 25°C, unless otherwise noted.

Figure 50. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

Figure 51. Channel-to-Channel Isolation

Figure 52. SINAD vs. Analog Input Frequency for Various Supply Voltages

SUPPLY RIPPLE FREQUENCY (kHz)

20000 200 400 600 800 1000 1200 1400 1600 1800

PSRR (dB)

–60

–70

–80

–90

–100

–110

–120

100mV p-p SINE WAVE ON AVDD

NO DECOUPLING

SINGLE-ENDED MODE

EXTERNAL REFERENCE

INTERNAL REFERENCE

NOISE FREQUENCY (kHz)

10000 100 200 300 400 500 600 800700 900

ISOLATION (dB)

–50

–55

–60

–65

–70

–75

–90

–95

–80

–85

–100

= 5V

INPUT FREQUENCY (kHz)

30000 1000 2000500 1500 2500

SINAD (dB)

VDD = 5V

DIFFERENTIAL MODE

VDD = 3V

DIFFERENTIAL MODE

RANGE = 0 TO VREF

Figure 53. Typical FFT

Figure 54. Typical DNL

Figure 55. Typical INL

FREQUENCY (kHz)

10000 100 200 300 400 500 600 700 800 900

(dB)

–10

–30

–50

–70

–90

–110

4096 POINT FFT

VDD = 5V, VDRIVE = 3V

FSAMPLE = 2MSPS

FIN = 52kHz

SINAD = 71.4dB

THD = –84.42dB

DIFFERENTIAL MODE

CODE

40000 1000 2000 3000 3500500 1500 2500

DNL ERROR (LSB)

1.0

0.6

0.8

0.2

0.4

–0.2

–0.6

–0.8

–0.4

–1.0

VDD = 5V, VDRIVE = 3V

DIFFERENTIAL MODE

CODE

40000 500 1000 1500 2000 2500 3000 3500

INL ERROR (LSB)

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V, V

DRIVE

= 3V

DIFFERENTIAL MODE

Rev. B | Page 60 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 56. Linearity Error vs. V

REF

Figure 57. Effective Number of Bits vs. V

REF

Figure 58. V

REF

vs. Reference Output Current Drive

VREF (V)

2.50 0.5 1.0 1.5 2.0

LINEARITY ERROR (LSB)

1.0

0.6

0.8

0.2

0.4

–0.2

–0.6

–0.4

–1.0

–0.8

VDD = 3V/5V

DIFFERENTIAL MODE

POSITIVE INL

POSITIVE DNL

NEGATIVE DNL

NEGATIVE INL

VREF (V)

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

EFFECTIVE NUMBER OF BITS

12.0

11.0

11.5

10.0

10.5

9.0

9.5

8.0

7.5

8.5

7.0

VDD = 5V

DIFFERENTIAL MODE

VDD = 3V

DIFFERENTIAL MODE

VDD = 3V

SINGLE-ENDED MODE

VDD = 5V

SINGLE-ENDED MODE

CURRENT LOAD (PA)

2000 20 40 60 80 100 120 140 160 180

REF

(V)

2.5010

2.5000

2.5005

2.4995

2.4990

2.4985

2.4980

Figure 59. Histogram of Codes for 10k Samples in Differential Mode

Figure 60. Histogram of Codes for 10k Samples in Single-Ended Mode

Figure 61. CMRR vs. Common-Mode Ripple Frequency

CODE

2046 2047 20492048 2050

NO. OF OCCURRENCES

10000

8000

9000

6000

7000

4000

5000

2000

1000

3000

10000

CODES

DIFFERENTIAL

MODE

INTERNAL

REFERENCE

CODE

2046 2047 2048 2049 2050

NO. OF OCCURRENCES

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

9984

CODES

SINGLE-ENDED

MODE

INTERNAL

REFERENCE

5 CODES 11 CODES

RIPPLE FREQUENCY (kHz)

12000 200 400 600 800 1000

CMRR (dB)

–60

–65

–70

–75

–80

–85

–95

–90

–100

DIFFERENTIAL MODE

VDD = 3V/5V

Rev. B | Page 61 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

ADC—TERMINOLOGY

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the mea-

sured and the ideal 1 LSB change between any two adjacent

codes in the ADC.

Integral Nonlinearity (INL)

Integral nonlinearity is the maximum deviation from a

straight line passing through the endpoints of the ADC trans-

fer function. The endpoints of the transfer function are zero

scale with a single (1) LSB point below the first code transi-

tion, and full scale with a 1 LSB point above the last code

transition.

Offset Error

Offset error applies to straight binary output coding. It is the

deviation of the first code transition (00...000) to

(00 . . . 001) from the ideal (AGND + 1 LSB).

Offset Error Match

Offset error match is the difference in offset error across all 12

channels.

Gain Error

Gain error applies to straight binary output coding. It is the

deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (V

REF

1 LSB) after the offset error

is adjusted out. Gain error does not include reference error.

Gain Error Match

Gain error match is the difference in gain error across all 12

channels.

Positive Gain Error

This applies when using twos complement output coding

with, for example, the 2 × V

REF

input range as –V

REF

to +V

REF

biased about the V

REF

point. It is the deviation of the last code

transition (011…110) to (011…111) from the ideal

(+V

REF

– 1 LSB) after the zero code error is adjusted out.

Positive Gain Error Match

This is the difference in positive gain error across all 12

channels.

Zero Code Error

Zero code error applies when using twos complement output

coding with, for example, the 2 × V

REF

input range as –V

REF

biased about the V

REF

point. It is the deviation of the

mid-scale transition (all 0s to all 1s) from the ideal V

voltage

REF

Zero Code Error Match

Zero code error match refers to the difference in zero code

error across all 12 channels.

Negative Gain Error

This applies when using twos complement output coding

option, in particular the 2 × V

REF

input range as –V

REF

biased about the V

REF

point. It is the deviation of the

first code transition (100…000) to (100…001) from the ideal

(that is, –V

REF

+ 1 LSB) after the zero code error is adjusted

out.

Negative Gain Error Match

This is the difference in negative gain error across all 12

channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode after the

end of conversion. Track-and-hold acquisition time is the

time required for the output of the track-and-hold amplifier

to reach its final value, within ±1/2 LSB, after the end of

conversion.

Signal-to-(Noise + Distortion) Ratio (SINAD)

This ratio is the measured ratio of signal-to-(noise + distor-

tion) at the output of the ADC. The signal is the rms

amplitude of the fundamental. Noise is the sum of all non-

fundamental signals up to half the sampling frequency (f

/2),

excluding dc. The ratio is dependent on the number of quan-

tization levels in the digitalization process; the more levels,

the smaller the quantization noise. The theoretical signal-to-

(noise + distortion) ratio for an ideal N-bit converter with a

sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Therefore, for a 12-bit converter, theoretical SINAD is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of har-

monics to the fundamental. For the ADC, it is defined as:

where:

is the rms amplitude of the fundamental.

, V

, and V

are the rms amplitudes of the second

through the sixth harmonics.

Effective Number of Bits (ENOB)

This is a figure of merit which characterizes the dynamic per-

formance of the ADC at a specified input frequency and

sampling rate. ENOB is expressed in bits. For a full scale sinu-

soidal input, ENOB is defined as:

ENOB = (SINAD – 1.76)/6.02

Peak Harmonic or Spurious Noise (SFDR)

Peak harmonic, or spurious noise, is defined as the ratio of

the rms value of the next largest component in the ADC out-

put spectrum (up to f

/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is

a noise peak.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale (2 × V

REF

when V

= 5 V, V

REF

when V

= 3 V),

10 kHz sine wave signal to all un-selected input channels and

log20)( V

VVVVV

dBTHD 



Rev. B | Page 62 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

determining how much that signal is attenuated in the

selected channel with a 50 kHz signal (0 V to V

REF

). The result

obtained is the worst-case across all 12 channels for the ADC.

Intermodulation Distortion (IMD)

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with non-linearities create distortion

products at sum, and difference frequencies of mfa ± nfb

where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion

terms are those for which neither m nor n are equal to zero.

For example, the second-order terms include (fa + fb) and

(fa fb), while the third-order terms include (2fa + fb),

(2fa fb), (fa + 2fb), and (fa 2fb).

The ADC is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second-order and third-order terms are speci-

fied separately. The calculation of the inter-modulation

distortion is as per the THD specification, where it is the ratio

of the rms sum of the individual distortion products to the

rms amplitude of the sum of the fundamentals expressed in

dBs.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output

at full-scale frequency, f, to the power of a 100 mV p-p sine

wave applied to the common-mode voltage of V

IN+

and V

frequency f

as:

CMRR (dB) = 10 log(Pf/Pf

)

where:

Pf is the power at frequency f in the ADC output.

is the power at frequency f

in the ADC output.

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but

not the converter’s linearity. PSRR is the maximum change in

the full-scale transition point due to a change in power supply

voltage from the nominal value (see Figure 50 (PSRR vs. Sup-

ply Ripple Frequency Without Supply Decoupling).

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum

change of reference output voltage (V

REF

) after the device is

cycled through temperature from either:

T_HYS+ = +25°C to T

MAX

to +25°C

T_HYS = +25°C to T

MIN

to +25°C

It is expressed in ppm by:

where:

REF

(25°C) is V

REF

at 25°C.

REF

(T_HYS) is the maximum change of V

REF

T_HYS+ or T_HYS.

ADC—THEORY OF OPERATION

The following sections describe the ADC theory of operation.

Circuit Information

The ADC is a fast, micropower, dual, 12-bit, single-supply,

ADC that operates from a 2.7 V to a 5.25 V supply. When oper-

ated from a 5 V supply, the ADC is capable of throughput rates

of up to 2 MSPS when provided with a 32 MHz clock, and a

throughput rate of up to 1.5 MSPS at 3 V.

The ADC contains two on-chip, differential track-and-hold

amplifiers, two successive approximation ADCs, and a serial

interface with two separate data output pins.

The serial clock input accesses data from the part but also pro-

vides the clock source for each successive approximation ADC.

The analog input range for the part can be selected to be a 0 V to

REF

input or a 2 × V

REF

input, configured with either single-

ended or differential analog inputs. The ADC has an on-chip

2.5 V reference that can be overdriven when an external refer-

ence is preferred. If the internal reference is to be used elsewhere

in a system, then the output needs to buffered first.

The ADC also features power-down options to allow power sav-

ing between conversions. The power-down feature is

implemented via the standard serial interface, as described in

the ADC—Modes of Operation section.

Converter Operation

The ADC has two successive approximation ADCs, each based

around two capacitive DACs. Figure 62 (ADC Acquisition

Phase) and Figure 63 (ADC Conversion Phase) show simplified

schematics of one of these ADCs in acquisition and conversion

phase, respectively. The ADC is comprised of control logic, a

SAR, and two capacitive DACs. In Figure 62 (ADC Acquisition

Phase) (the acquisition phase), SW3 is closed, SW1 and SW2 are

in Position A, the comparator is held in a balanced condition,

and the sampling capacitor arrays acquire the differential signal

on the input.

)C25(

)_()C25(

)( 







REF

REFREF

HYS V

HYSTVV

ppmV

Figure 62. ADC Acquisition Phase

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

IN+

IN–

REF

Rev. B | Page 63 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

When the ADC starts a conversion (see Figure 63 (ADC Con-

version Phase)), SW3 opens and SW1 and SW2 move to

Position B, causing the comparator to become unbalanced. Both

inputs are disconnected once the conversion begins. The con-

trol logic and the charge redistribution DACs are used to add

and subtract fixed amounts of charge from the sampling capaci-

tor arrays to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

The output impedances of the sources driving the V

IN+

and V

IN–

pins must be matched; otherwise, the two inputs will have dif-

ferent settling times, resulting in errors.

Analog Input Structure

Figure 64 (Equivalent Analog Input Circuit, Conversion

Phase—Switches Open, Track Phase—Switches Closed) shows

the equivalent circuit of the analog input structure of the ADC

in differential/pseudo differential mode. In single-ended mode,

is internally tied to AGND. The four diodes provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signals never exceed the supply rails by

more than 300 mV. This causes these diodes to become for-

ward-biased and starts conducting into the substrate. These

diodes can conduct up to 10 mA without causing irreversible

damage to the part.

The C1 capacitors in Figure 64 (Equivalent Analog Input Cir-

cuit, Conversion Phase—Switches Open, Track Phase—

Switches Closed) are typically 4 pF and can primarily be

attributed to pin capacitance. The resistors are lumped compo-

nents made up of the on resistance of the switches. The value of

these resistors is typically about 100 . The C2 capacitors are

the ADC’s sampling capacitors with a capacitance of 45 pF

typically.

For ac applications, removing high frequency components from

the analog input signal is recommended by the use of an RC

low-pass filter on the relevant analog input pins with optimum

values of 47  and 10 pF. In applications where harmonic dis-

tortion and signal-to-noise ratio are critical, the analog input

should be driven from a low impedance source. Large source

impedances significantly affect the ac performance of the ADC

and may necessitate the use of an input buffer amplifier. The

choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of THD that can be

tolerated.

The THD increases as the source impedance increases and per-

formance degrades. Figure 65 (THD vs. Analog Input

Frequency for Various Source Impedances, Single-Ended Mode

shows a graph of the THD vs. the analog input signal frequency

for different source impedances in single-ended mode, while

Figure 66 (THD vs. Analog Input Frequency for Various Source

Impedances, Differential Mode) shows the THD vs. the analog

input signal frequency for different source impedances in differ-

ential mode.

Figure 67 (THD vs. Analog Input Frequency for Various Supply

Voltages) shows a graph of the THD vs. the analog input fre-

quency for various supplies while sampling at 2 MSPS. In this

case, the source impedance is 47 .

Figure 63. ADC Conversion Phase

Figure 64. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VIN+

VIN–

VREF

IN+

R1 C2

IN–

R1 C2

Figure 65. THD vs. Analog Input Frequency for Various

Source Impedances, Single-Ended Mode

INPUT FREQUENCY (kHz)

6000 200100 400300 500

THD (dB)

–50

–60

–55

–65

–70

–75

–80

–85

–90

FSAMPLE = 1.5MSPS

VDD = 3V

RANGE = 0V TO VREF

RSOURCE = 300

RSOURCE = 0

RSOURCE = 10

RSOURCE = 47

RSOURCE = 100

Rev. B | Page 64 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Analog Inputs

The ADC has a total of 12 analog inputs. Each on-board ADC

has six analog inputs that can be configured as six single-ended

channels, three pseudo differential channels, or three fully dif-

ferential channels. These may be selected as described in the

Analog Input Selection section.

Single-Ended Mode

The ADC can have a total of 12 single-ended analog input chan-

nels. In applications where the signal source has high

impedance, it is recommended to buffer the analog input

before applying it to the ADC. The analog input range can be

programmed to be either 0 to V

REF

or 0 to 2 × V

REF

If the analog input signal to be sampled is bipolar, the internal

reference of the ADC can be used to externally bias up this sig-

nal to make it correctly formatted for the ADC. Figure 68 shows

a typical connection diagram when operating the ADC in sin-

gle-ended mode.

Differential Mode

The ADC can have a total of six differential analog input pairs.

Differential signals have some benefits over single-ended sig-

nals, including noise immunity based on the device’s common-

mode rejection and improvements in distortion performance.

Figure 69 (Differential Input Definition) defines the fully differ-

ential analog input of the ADC.

The amplitude of the differential signal is the difference between

the signals applied to the V

IN+

and V

IN–

pins in each differential

pair (V

IN+

IN–

). V

IN+

and V

IN–

should be simultaneously driven

by two signals each of amplitude V

REF

(or 2 × V

REF

, depending

on the range chosen) that are 180° out of phase. The amplitude

of the differential signal is, therefore (assuming the 0 to V

REF

range is selected) –V

REF

to +V

REF

peak-to-peak (2 × V

REF

regardless of the common mode (CM).

The common mode is the average of the two signals

IN+

+ V

IN–

)/2

and is, therefore, the voltage on which the two inputs are

centered.

This results in the span of each input being CM ± V

REF

/2. This

voltage has to be set up externally and its range varies with the

reference value, V

REF

. As the value of V

REF

increases, the

common-mode range decreases. When driving the inputs with

an amplifier, the actual common-mode range is determined by

the amplifier’s output voltage swing.

Figure 70 (Input Common-Mode Range vs. VREF (0 to VREF

Range, VDD = 5 V)) and Figure 71 (Input Common-Mode

Range vs. VREF (2 × VREF Range, VDD = 5 V)) show how the

common-mode range typically varies with V

REF

for a 5 V power

Figure 66. THD vs. Analog Input Frequency for

Various Source Impedances, Differential Mode

Figure 67. THD vs. Analog Input Frequency for Various Supply Voltages

INPUT FREQUENCY (kHz)

600 700 800 900 10000 200100 400300 500

THD (dB)

–60

–65

–70

–75

–80

–85

–90

SAMPLE

= 1.5MSPS

= 3V

RANGE = 0V TO V

REF

SOURCE

= 300

SOURCE

= 0

SOURCE

= 10

SOURCE

= 47

SOURCE

= 100

INPUT FREQUENCY (kHz)

600 700 800 900 10000 200100 400300 500

THD (dB)

–50

–60

–55

–65

–70

–75

–80

–85

–90

= 3V

SINGLE-ENDED MODE

= 5V

SINGLE-ENDED MODE

= 3V

DIFFERENTIAL MODE

= 5V

DIFFERENTIAL MODE

SAMPLE

= 1.5MSPS/2MSPS

= 3V/5V

RANGE = 0 TO V

REF

Figure 68. Single-Ended Mode Connection Diagram

Figure 69. Differential Input Definition

VIN

+1.25V

–1.25V

VREF

(DCAPA/DCAPB)

VA1 ADC1

VB6

+2.5V

0.47μF

1ADDITIONAL PINS OMITTED FOR CLARITY.

VIN+

ADC1

VIN–

VREF p-p

COMMON

MODE

VOLTAGE

1ADDITIONAL PINS OMITTED FOR CLARITY.

Rev. B | Page 65 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

supply using the 0 to V

REF

range or 2 × V

REF

range, respectively.

The common mode must be in this range to guarantee the func-

tionality of the ADC.

When a conversion takes place, the common mode is rejected,

resulting in a virtually noise free signal of amplitude –V

REF

corresponding to the digital codes of 0 to 4096. If the 2 ×

REF

range is used, then the input signal amplitude extends from

– 2 V

REF

to +2 V

REF

after conversion.

Driving Differential Inputs

Differential operation requires that V

IN+

and V

IN–

be simultane-

ously driven with two equal signals that are 180° out of phase.

The common mode must be set up externally. The common-

mode range is determined by V

REF

, the power supply, and the

particular amplifier used to drive the analog inputs. Differential

modes of operation with either an ac or dc input provide the

best THD performance over a wide frequency range. Because

not all applications have a signal preconditioned for differential

operation, there is often a need to perform single-ended-to-dif-

ferential conversion.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential sig-

nal to one of the analog input pairs of the ADC. The circuit

configurations illustrated in Figure 72 (Dual Op Amp Circuit to

Convert a Single-Ended Unipolar Signal Into a Differential Sig-

nal) and Figure 73 (Dual Op Amp Circuit to Convert a Single-

Ended Bipolar Signal into a Differential Unipolar Signal) show

how a dual op amp can be used to convert a single-ended signal

into a differential signal for both a bipolar and unipolar input

signal, respectively.

The voltage applied to Point A sets up the common-mode volt-

age. In both diagrams, it is connected in some way to the

reference, but any value in the common-mode range can be

input here to set up the common mode. The AD8022 is a suit-

able dual op amp that can be used in this configuration to

provide differential drive to the ADC.

Take care when choosing the op amp; the selection depends on

the required power supply and system performance objectives.

The driver circuits in Figure 72 (Dual Op Amp Circuit to Con-

vert a Single-Ended Unipolar Signal Into a Differential Signal)

and Figure 73 (Dual Op Amp Circuit to Convert a Single-Ended

Bipolar Signal into a Differential Unipolar Signal) are optimized

for dc coupling applications requiring best distortion

performance.

The circuit configuration shown in Figure 72 (Dual Op Amp

Circuit to Convert a Single-Ended Unipolar Signal Into a Differ-

ential Signal) converts a unipolar, single-ended signal into a

differential signal.

The differential op amp driver circuit shown in Figure 73 (Dual

Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a

Differential Unipolar Signal) is configured to convert and level

shift a single-ended, ground-referenced (bipolar) signal to a dif-

ferential signal centered at the V

REF

level of the ADC.

Pseudo Differential Mode

The ADC can have a total of six pseudo differential pairs. In this

mode, V

IN+

is connected to the signal source that must have an

amplitude of V

REF

(or 2 × V

REF

, depending on the range chosen)

Figure 70. Input Common-Mode Range vs. V

REF

(0 to V

REF

Range, V

= 5 V)

Figure 71. Input Common-Mode Range vs. V

REF

(2 × V

REF

Range, V

= 5 V)

REF

(V)

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

COMMON-MODE RANGE (V)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

= 25°C

REF (V)

2.50 0.5 1.0 1.5 2.0

COMMON-MODE RANGE (V)

5.0

4.0

4.5

3.0

3.5

2.0

2.5

0.5

1.0

1.5

TA = 25°C

Figure 72. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

Into a Differential Signal

GND

2 × VREF p–p

27

V+

V–

V+

V–

VREF

2.5V

3.75V

1.25V

2.5V

3.75V

1.25V VREF

(DCAPA/DCAPB)

VIN+ ADC1

VIN–

440

220

0.47μF

1ADDITIONAL PINS OMITTED FOR CLARITY.

220

10k

Rev. B | Page 66 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

to make use of the full dynamic range of the part. A dc input is

applied to the V

IN–

pin. The voltage applied to this input pro-

vides an offset from ground or a pseudo ground for the V

IN+

input. The benefit of pseudo differential inputs is that they sepa-

rate the analog input signal ground from the ADC’s ground

allowing dc common-mode voltages to be cancelled.

The typical voltage range for the V

IN–

pin, while in pseudo dif-

ferential mode, is shown in Figure 74 (V

IN–

Input Voltage Range

vs. V

REF

in Pseudo Differential Mode with V

= 3 V) and

Figure 75 (V

IN–

Input Voltage Range vs. V

REF

in Pseudo Differ-

ential Mode with V

= 5 V). Figure 76 (Pseudo Differential

Mode Connection Diagram) shows a connection diagram for

pseudo differential mode.

Analog Input Selection

The analog inputs of the ADC can be configured as single-

ended or true differential via the SGL/DIFF logic pin, as shown

in Figure 77 (Selecting Differential or Single-Ended Configura-

tion). If this pin is tied to a logic low, the analog input channels

to each on-chip ADC are set up as three true differential pairs. If

this pin is at logic high, the analog input channels to each on-

chip ADC are set up as six single-ended analog inputs. The

required logic level on this pin needs to be established prior to

the acquisition time and remain unchanged during the conver-

sion time until the track-and-hold has returned to track. The

track-and-hold returns to track on the 13

rising edge of

ADSCLK after the CS falling edge (see Figure 87 (Serial Inter-

face Timing Diagram)). If the level on this pin is changed, it will

be recognized by the ADC; therefore, it is necessary to keep the

same logic level during acquisition and conversion to avoid cor-

rupting the conversion in progress.

For example, in Figure 77 (Selecting Differential or Single-

Ended Configuration) the SGL/DIFF pin is set at logic high for

the duration of both the acquisition and conversion times so the

analog inputs are configured as single ended for that conversion

(Sampling Point A). The logic level of the SGL/DIFF changed to

low after the track-and-hold returned to track and prior to the

Figure 73. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal

Figure 74. V

IN–

Input Voltage Range vs. V

REF

Pseudo Differential Mode with V

= 3 V

20k

220k

2 × VREF p–p

27

V+

V–

V+

V–

GND

2.5V

3.75V

1.25V

2.5V

3.75V

1.25V

VIN+ ADC1

VIN–

440

220

0.47μF

1ADDITIONAL PINS OMITTED FOR CLARITY.

220

10k

VREF

(DCAPA/DCAPB)

VREF (V)

3.00 0.5 1.0 1.5 2.0 2.5

VIN– (V)

1.0

0.8

0.4

0.6

0.2

–0.2

–0.4

TA = 25°C

Figure 75. V

IN–

Input Voltage Range vs. V

REF

Pseudo Differential Mode with V

= 5 V

Figure 76. Pseudo Differential Mode Connection Diagram

VREF (V)

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VIN– (V)

2.5

2.0

1.5

1.0

0.5

–0.5

TA = 25°C

DC INPUT

VOLTAGE

VREF

p–p

VREF (DCAPA/DCAPB)

VIN+

ADC1

VIN–

0.47μF

1ADDITIONAL PINS OMITTED FOR CLARITY.

Rev. B | Page 67 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

required acquisition time for the next sampling instant at Point

B; therefore, the analog inputs are configured as differential for

that conversion.

The channels used for simultaneous conversions are selected via

the multiplexer address input pins, A0 to A2. The logic states of

these pins also need to be established prior to the acquisition

time; however, they may change during the conversion time

provided the mode is not changed. If the mode is changed from

fully differential to pseudo differential, for example, then the

acquisition time would start again from this point. The selected

input channels are decoded as shown in Table 53 (Analog Input

Type and Channel Selection).

The analog input range of the ADC can be selected as 0 V to

REF

or 0 V to 2 × V

REF

via the RANGE pin. This selection is

made in a similar fashion to that of the SGL/DIFF pin by setting

the logic state of the RANGE pin a time t

acq

prior to the falling

edge of CS. Subsequent to this, the logic level on this pin can be

altered after the third falling edge of ADSCLK. If this pin is tied

to a logic low, the analog input range selected is 0 V to V

REF

. If

this pin is tied to a logic high, the analog input range selected is

0 V to 2 × V

REF

Output Coding

The ADC output coding is set to either twos complement or

straight binary, depending on which analog input configuration

is selected for a conversion. Table 52 (ADC Output Coding)

shows which output coding scheme is used for each possible

analog input configuration.

Transfer Functions

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB

size is V

REF

/4096 when the 0 V to V

REF

range is used, and the LSB

size is 2 × V

REF

/4096 when the 0 V to 2 × V

REF

range is used. In

differential mode, the LSB size is 2 × V

REF

/4096 when the 0 V to

REF

range is used, and the LSB size is 4 × V

REF

/4096 when the 0

V to 2 × V

REF

range is used. The ideal transfer characteristic for

the ADC when straight binary coding is output is shown in

Figure 78 (Straight Binary Transfer Characteristic), and the

ideal transfer characteristic for the ADC when twos comple-

ment coding is output is shown in Figure 79 (Twos

Complement Transfer Characteristic with VREF ± VREF Input

Range) (this is shown with the 2 × V

REF

range).

Figure 77. Selecting Differential or Single-Ended Configuration

ADSCLK

114 141

SGL/DIFF

tACQ

Table 52. ADC Output Coding

SGL/DIFF RANGE Output Coding

0 (Differential Input) 0 (0 V to V

REF

) Twos complement

0 (Differential Input) 1 (0 V to 2 × V

REF

) Twos complement

1 (Single-Ended Input) 0 (0 V to V

REF

) Straight binary

1 (Single-Ended Input) 1 (0 V to2 × V

REF

) Twos complement

0 (Pseudo-Differential Input) 0 (0 V to V

REF

) Straight binary

0 (Pseudo-Differential Input) 1 (0 V to 2 × V

REF

) Twos complement

Table 53. Analog Input Type and Channel Selection

ADC A ADC B

SGL/DIFF A2 A1 A0 V

IN+

IN–

IN+

IN–

Comment

1000V

AGND V

AGND Single ended

1001V

AGND V

AGND Single ended

1010V

AGND V

AGND Single ended

1011V

AGND V

AGND Single ended

1100V

AGND V

AGND Single ended

1101V

AGND V

AGND Single ended

0000V

Fully differential

0001V

Pseudo differential

0010V

Fully differential

0011V

Pseudo differential

0100V

Fully differential

0101V

Pseudo differential

Rev. B | Page 68 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Serial Interface Voltage Drive

The ADC also has a V

DRIVE

feature to control the voltage at

which the serial interface operates. V

DRIVE

allows the ADC to

easily interface to both 3 V and 5 V processors. For example, if

the ADC was operated with a AV

/DV

of 5 V, the V

DRIVE

could be powered from a 3 V supply, best ADC performance

low voltage digital processors. Therefore, the ADC could be

used with the 2 × V

REF

input range, with a AV

/DV

of 5 V

while still being able to serial interface to 3 V digital I/O parts.

ADC—MODES OF OPERATION

The mode of operation of the ADC is selected by controlling the

(logic) state of the CS signal during a conversion. There are

three possible modes of operation: normal mode, partial power-

down mode, and full power-down mode. After a conversion is

initiated, the point at which CS is pulled high determines which

power-down mode, if any, the device enters. Similarly, if already

in a power-down mode, CS can control whether the device

returns to normal operation or remains in power-down. These

modes of operation are designed to provide flexible power man-

agement options. These options can be chosen to optimize the

power dissipation/throughput rate ratio for differing applica-

tion requirements.

Normal Mode

This mode is intended for applications needing fastest through-

put rates because the user does not have to worry about any

power-up times with the ADC remaining fully powered at all

times. Figure 80 (Normal Mode Operation) shows the general

diagram of the operation of the ADC in this mode.

The conversion is initiated on the falling edge of CS, as

described in the ADC—Serial Interface section. To ensure that

the part remains fully powered up at all times, CS must remain

low until at least 10 ADSCLK falling edges have elapsed after the

falling edge of CS. If CS is brought high any time after the 10

ADSCLK falling edge but before the 14

ADSCLK falling edge,

the part remains powered up, but the conversion is terminated

and D

OUT

A and D

OUT

B go back into three-state. Fourteen serial

clock cycles are required to complete the conversion and access

the conversion result. The D

OUT

line does not return to three-

state after 14 ADSCLK cycles have elapsed, but instead does so

when CS is brought high again. If CS is left low for another 2

ADSCLK cycles (for example, if only a 16 ADSCLK burst is

available), two trailing zeros are clocked out after the data. If CS

is left low for a further 14 (or16) ADSCLK cycles, the result

from the other ADC on board is also accessed on the same D

OUT

line, as shown in Figure 88 (Reading Data from Both ADCs on

One DOUT Line with 32 ADSCLKs). See the ADC—Serial

Interface section.

Once 32 ADSCLK cycles have elapsed, the D

OUT

line returns to

three-state on the 32

ADSCLK falling edge. If CS is brought

high prior to this, the D

OUT

line returns to three-state at that

point. Therefore, CS may idle low after 32 ADSCLK cycles until

it is brought high again sometime prior to the next conversion

(effectively idling CS low), if so desired, because the bus still

returns to three-state upon completion of the dual result read.

Once a data transfer is complete and D

OUT

A and D

OUT

B have

returned to three-state, another conversion can be initiated after

the quiet time, t

QUIET

, has elapsed by bringing CS low again

(assuming the required acquisition time is allowed).

Partial Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be per-

formed at a high throughput rate, and the ADC is then powered

Figure 78. Straight Binary Transfer Characteristic

Figure 79. Twos Complement Transfer Characteristic with

REF

± V

REF

Input Range

000...000

111...111

1LSB = VREF/4096

1LSB VREF – 1LSB

ANALOG INPUT

ADC CODE

000...001

000...010

111...110

111...000

011...111

NOTE

1. VREF IS EITHER VREF OR 2 × VREF.

100...000

011...111

1LSB = 2 uVREF/4096

+VREF – 1 LSB–VREF + 1LSB VREF – 1LSB

ANALOG INPUT

ADC CODE

100...001

100...010

011...110

000...001

000...000

111...111

Figure 80. Normal Mode Operation

ADSCLK

LEADING ZEROS + CONVERSION RESULT

OUT

11410

Rev. B | Page 69 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

down for a relatively long duration between these bursts of sev-

eral conversions. When the ADC is in partial power-down, all

analog circuitry is powered down except for the on-chip refer-

ence and reference buffer.

To enter partial power-down mode, the conversion process

must be interrupted by bringing CS high anywhere after the sec-

ond falling edge of ADSCLK and before the 10

falling edge of

ADSCLK, as shown in Figure 81 (Entering Partial Power-Down

Mode). Once CS is brought high in this window of ADSCLKs,

the part enters partial power-down, the conversion that was ini-

tiated by the falling edge of CS is terminated, and D

OUT

A and

OUT

B go back into three-state. If CS is brought high before the

second ADSCLK falling edge, the part remains in normal mode

and does not power down. This avoids accidental power-down

due to glitches on the CS line.

To exit this mode of operation and power up the ADC again, a

dummy conversion is performed. On the falling edge of CS, the

device begins to power up and continues to power up as long as

CS is held low until after the falling edge of the 10

ADSCLK.

The device is fully powered up after approximately 1 μs has

elapsed, and valid data results from the next conversion, as

shown in Figure 82 (Exiting Partial Power-Down Mode). If CS

is brought high before the second falling edge of ADSCLK, the

ADC again goes into partial power-down. This avoids acciden-

tal power-up due to glitches on the CS line. Although the device

may begin to power up on the falling edge of CS, it powers down

again on the rising edge of CS. If the ADC is already in partial

power-down mode and CS is brought high between the second

and 10

falling edges of ADSCLK, the device enters full power-

down mode.

Full Power-Down Mode

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes substan-

tially longer than that from partial power-down. This mode is

more suited to applications where a series of conversions per-

formed at a relatively high throughput rate are followed by a

long period of inactivity and thus power-down. When the ADC

is in full power-down, all analog circuitry is powered down. Full

power-down is entered in a similar way as partial power-down,

except the timing sequence shown in Figure 81 (Entering Partial

Power-Down Mode) must be executed twice. The conversion

process must be interrupted in a similar fashion by bringing CS

high anywhere after the second falling edge of ADSCLK and

before the 10

falling edge of ADSCLK. The device enters par-

tial power-down at this point. To reach full power-down, the

next conversion cycle must be interrupted in the same way, as

shown in Figure 83 (Entering Full Power-Down Mode). Once

CS is brought high in this window of ADSCLKs, the part com-

pletely powers down.

Note that it is not necessary to complete the 14 ADSCLKs once

CS is brought high to enter a power-down mode.

To exit full power-down and power up the ADC, a dummy con-

version is performed, as when powering up from partial power-

down. On the falling edge of CS, the device begins to power up

and continues to power up, as long as CS is held low until after

the falling edge of the 10

ADSCLK. The required power-up

time must elapse before a conversion can be initiated, as shown

in Figure 84 (Exiting Full Power-Down Mode). See the Power-

Up Times section for the power-up times associated with the

ADC.

Figure 81. Entering Partial Power-Down Mode

ADSCLK

THREE-STATE

OUT

114102

Figure 82. Exiting Partial Power-Down Mode

ADSCLK

OUT

BINVALID DATA VALID DATA

11014 141

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

tPOWER-UP1

Rev. B | Page 70 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Power-Up Times

As described in detail, the ADC has two power-down modes,

partial power-down and full power-down. This section deals

with the power-up time required when coming out of either of

these modes. It should be noted that the power-up times, as

explained in this section, apply with the recommended capaci-

tors in place on the D

CAP

A and D

CAP

B pins.

To power up from full power-down, approximately 1.5 ms

should be allowed from the falling edge of CS, shown as

POWER-UP2

in Figure 84 (Exiting Full Power-Down Mode). Pow-

ering up from partial power-down requires much less time. The

power-up time from partial power-down is typically 1 μs; how-

ever, if using the internal reference, then the ADC must be in

partial power-down for at least 67 μs in order for this power-up

time to apply.

When power supplies are first applied to the ADC, the ADC

may power up in either of the power-down modes or normal

mode. Because of this, it is best to allow a dummy cycle to elapse

to ensure the part is fully powered up before attempting a valid

conversion. Likewise, if it is intended to keep the part in the par-

tial power-down mode immediately after the supplies are

applied, then two dummy cycles must be initiated. The first

dummy cycle must hold CS low until after the 10

ADSCLK

falling edge (see Figure 80 (Normal Mode Operation)); in the

second cycle, CS must be brought high before the 10

ADSCLK

edge but after the second ADSCLK falling edge (see Figure 81

(Entering Partial Power-Down Mode)). Alternatively, if it is

intended to place the part in full power-down mode when the

supplies are applied, then three dummy cycles must be initiated.

The first dummy cycle must hold CS low until after the 10

ADSCLK falling edge (see Figure 80 (Normal Mode Opera-

tion)); the second and third dummy cycles place the part in full

power-down (see Figure 83 (Entering Full Power-Down

Mode)).

Once supplies are applied to the ADC, enough time must be

allowed for any external reference to power up and charge the

various reference buffer decoupling capacitors to their final

values.

Power vs. Throughput Rate

The power consumption of the ADC varies with the throughput

rate. When using very slow throughput rates and as fast an

ADSCLK frequency as possible, the various power-down

options can be used to make significant power savings. How-

ever, the ADC quiescent current is low enough that even

without using the power-down options, there is a noticeable

variation in power consumption with sampling rate. This is true

whether a fixed ADSCLK value is used or if it is scaled with the

sampling rate. Figure 85 (Power vs. Throughput in Normal

Mode with VDD = 3 V) and Figure 86 (Power vs. Throughput

in Normal Mode with VDD = 5 V) show plots of power vs. the

throughput rate when operating in normal mode for a fixed

Figure 83. Entering Full Power-Down Mode

Figure 84. Exiting Full Power-Down Mode

THREE-STATE

110142

ADSCLK

DOUTA

DOUTB

THREE-STATE

110142

INVALID DATAINVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART ENTERS

FULL POWER DOWN.

ADSCLK

DOUTA

DOUTBINVALID DATA VALID DATA

110 14 14

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION.

tPOWER-UP2

Rev. B | Page 71 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

maximum ADSCLK frequency and an ADSCLK frequency that

scales with the sampling rate with V

= 3 V and V

= 5 V,

respectively. In all cases, the internal reference was used.

ADC—SERIAL INTERFACE

Figure 87 (Serial Interface Timing Diagram) shows the detailed

timing diagram for serial interfacing to the ADC. The serial

clock provides the conversion clock and controls the transfer of

information from the ADC during conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode,

at which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 14 ADSCLKs to complete. Once 13

ADSCLK falling edges have elapsed, the track-and-hold goes

back into track on the next ADSCLK rising edge, as shown in

Figure 87 (Serial Interface Timing Diagram) at Point B. If a 16

ADSCLK transfer is used, then two trailing zeros appear after

the final LSB. On the rising edge of CS, the conversion is termi-

nated and D

OUT

A and D

OUT

B go back into three-state. If CS is

not brought high but is instead held low for a further 14 (or 16)

ADSCLK cycles on D

OUT

A, the data from Conversion B is out-

put on D

OUT

A (followed by two trailing zeros).

Likewise, if CS is held low for a further 14 (or 16) ADSCLK

cycles on D

OUT

B, the data from Conversion A is output on

OUT

This is illustrated in Figure 88 (Reading Data from Both ADCs

on One DOUT Line with 32 ADSCLKs) where the case for

OUT

A is shown. In this case, the D

OUT

line in use goes back into

three-state on the 32

ADSCLK falling edge or the rising edge

of CS, whichever occurs first.

A minimum of 14 serial clock cycles are required to perform the

conversion process and to access data from one conversion on

either data line of the ADC. CS going low provides the leading

zero to be read in by the microcontroller or DSP. The remaining

data is then clocked out by subsequent ADSCLK falling edges,

beginning with a second leading zero. Thus, the first falling

clock edge on the serial clock has the leading zero provided and

also clocks out the second leading zero. The 12-bit result then

follows with the final bit in the data transfer valid on the 14

falling edge, having being clocked out on the previous (13

) fall-

ing edge. In applications with a slower ADSCLK, it may be

possible to read in data on each ADSCLK rising edge depending

on the ADSCLK frequency. The first rising edge of ADSCLK

after the CS falling edge would have the second leading zero

provided, and the 13

rising ADSCLK edge would have DB0

provided.

Note that with fast ADSCLK values, and thus short ADSCLK

periods, in order to allow adequately for t

, an ADSCLK rising

edge may occur before the first ADSCLK falling edge. This ris-

ing edge of ADSCLK may be ignored for the purposes of the

timing descriptions in this section. If a falling edge of ADSCLK

is coincident with the falling edge of CS, then this falling edge of

ADSCLK is not acknowledged by the ADC, and the next falling

edge of ADSCLK will be the first registered after the falling edge

of CS.

Figure 85. Power vs. Throughput in Normal Mode with V

= 3 V

Figure 86. Power vs. Throughput in Normal Mode with V

= 5 V

THROUGHPUT (kSPS)

14000 200 400 600 800 1000 1200

POWER (mW)

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

24MHz ADSCLK

VARIABLE ADSCLK

TA = 25°C

THROUGHPUT (kSPS)

20000 200 400 600 800 1000 1200 1400 1600 1800

POWER (mW)

32MHz ADSCLK

VARIABLE ADSCLK

= 25°C

Rev. B | Page 72 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 87. Serial Interface Timing Diagram

Figure 88. Reading Data from Both ADCs on One D

OUT

Line with 32 ADSCLKs

ADSCLK 1513

DOUTA

DOUTB

2 LEADING ZEROS

THREE-

STATE

234

tQUIET

THREE-STATE

DB11 DB10 DB2 DB0

t7t8

0DB1

DB9 DB8

ADSCLK

1515

OUT

ATHREE-

STATE

234 16

THREE-

STATE

ZERO0 ZERO DB11

2 LEADING ZEROS

t10

DB11

2 LEADING

ZEROS

DB10

DB9

ZEROZERO ZERO

2 TRAILING ZEROS

ZERO ZERO

2 TRAILING ZEROS

Rev. B | Page 73 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

120-LEAD LQFP LEAD ASSIGNMENT

Table 54 lists the LQFP leads by signal mnemonic. Table 55 on

Page 74 lists the LQFP leads by lead number.

Table 54. 120-Lead LQFP Lead Assignment (Alphabetical by Signal)

Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No.

A0 100 NC 72 PG11 46 V

A1 98 NMI 11 PG12 47 V

A2 97 PF0 118 PG13 48 V

DDEXT

AGND 73 PF1 119 PG14 49 V

DDEXT

AGND 78 PF2 2 PG15 50 V

DDEXT

AGND 79 PF3 4 PH0 113 V

DDEXT

AGND 82 PF4 3 PH1 115 V

DDEXT

AGND 93 PF5 5 PH2 114 V

DDEXT

AGND 99 PF6 7 RANGE 95 V

DDEXT

76 PF7 8 REF_SELECT 75 V

DDEXT

BMODE0 58 PF8 9 RESET 12 V

DDEXT

BMODE1 57 PF9 10 SCL 55 V

DDEXT

BMODE2 56 PF10 14 ADSCLK 102 V

DDEXT

CLKIN 110 PF11 16 SDA 54 V

DDEXT

CS 101 PF12 18 SGL/DIFF 96 V

DDEXT

CAP

A 77 PF13 19 TCK 34 V

DDEXT

CAP

B 94 PF14 21 TDI 33 V

DDEXT

112

DGND 74 PF15 22 TDO 36 V

DDEXT

116

DGND 104 PG 71 TMS 35 V

DDFLASH

OUT

A 105 PG0 27 TRST 37 V

DDFLASH

OUT

B 103 PG1 28 V

80 V

DDFLASH

107 PG2 29 V

81 V

DDINT

EMU 68 PG3 31 V

83 V

DDINT

EXT_WAKE 70 PG4 32 V

84 V

DDINT

EXTCLK 120 PG5 38 V

85 V

DDINT

GND 13 PG6 39 V

86 V

DDINT

GND 17 PG7 40 V

92 V

DDINT

GND 108 PG8 43 V

91 V

DDINT

117

GND 109 PG9 44 V

90 V

DRIVE

106

NC 60 PG10 45 V

89 XTAL 111

GND 121

AGND 122

* Pin no. 121 is the GND supply (see Figure 89 and Figure 90) for the processor (4.6mm × 6.17mm); this pad must connect to GND.

** Pin no. 122 is the AGND supply (see Figure 89 and Figure 90) for the ADC (2.81mm × 2.81mm); this pad must connect to AGND.

Rev. B | Page 74 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 55. 120-Lead LQFP Lead Assignment (Numerical by Lead Number)

Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal

DDEXT

31 PG3 61 V

DDINT

91 V

2 PF2 32 PG4 62 V

DDEXT

92 V

3PF4 33TDI 63V

DDFLASH

93 AGND

4PF3 34TCK 64V

DDEXT

94 D

CAP

5 PF5 35 TMS 65 V

DDINT

95 RANGE

DDEXT

36 TDO 66 V

DDEXT

96 SGL/DIFF

7PF6 37TRST67 V

DDEXT

97 A2

8 PF7 38 PG5 68 EMU 98 A1

9 PF8 39 PG6 69 V

DDFLASH

99 AGND

10 PF9 40 PG7 70 EXT_WAKE 100 A0

11 NMI 41 V

DDEXT

71 PG 101 CS

12 RESET 42 V

DDINT

72 NC 102 ADSCLK

13 GND 43 PG8 73 AGND 103 D

OUT

14 PF10 44 PG9 74 DGND 104 DGND

15 V

DDEXT

45 PG10 75 REF_SELECT 105 D

OUT

16 PF11 46 PG11 76 AV

106 V

DRIVE

17 GND 47 PG12 77 D

CAP

A107 DV

18 PF12 48 PG13 78 AGND 108 GND

19 PF13 49 PG14 79 AGND 109 GND

20 V

DDEXT

50 PG15 80 V

110 CLKIN

21 PF14 51 V

DDEXT

81 V

111 XTAL

22 PF15 52 V

DDINT

82 AGND 112 V

DDEXT

23 V

DDEXT

53 V

DDINT

83 V

113 PH0

24 V

DDINT

54 SDA 84 V

114 PH2

25 V

DDFLASH

55 SCL 85 V

115 PH1

26 V

DDEXT

56 BMODE2 86 V

116 V

DDEXT

27 PG0 57 BMODE1 87 V

117 V

DDINT

28 PG1 58 BMODE0 88 V

118 PF0

29 PG2 59 V

DDEXT

89 V

119 PF1

30 V

DDEXT

60 NC 90 V

120 EXTCLK

121

GND

122

AGND

* Pin no. 121 is the GND supply (see Figure 89 and Figure 90) for the processor (4.6mm × 6.17mm); this pad must connect to GND.

** Pin no. 122 is the AGND supply (see Figure 89 and Figure 90) for the ADC (2.81mm × 2.81mm); this pad must connect to AGND.

Rev. B | Page 75 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 89 shows the top view of the 120-lead LQFP package lead

configuration.

Figure 90 shows the bottom view of the 120-lead LQFP package

lead configuration.

Figure 89. 120-Lead LQFP Package Lead Configuration (Top View)

PIN 1

PIN 30

PIN 90

PIN 61

PIN 120 PIN 91

PIN 31 PIN 60

PIN 1

120-LEAD LQFP

TOP VIEW

INDICATOR

Figure 90. 120-Lead LQFP Package Lead Configuration (Bottom View)

PIN 30

PIN 1

PIN 61

PIN 90

PIN 31 PIN 60

PIN 120 PIN 91

120-LEAD LQFP

GND

AGND

PAD

(PIN 121)

(PIN 122)

BOTTOM VIEW

Rev. B | Page 76 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

88-LEAD LFCSP LEAD ASSIGNMENT

Table 56 lists the LFCSP leads by signal mnemonic. Table 57 on

Page 77 lists the LFCSP by lead number.

Table 56. 88-Lead LFCSP Lead Assignment (Alphabetical by Signal)

Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No.

BMODE0 51 PF4 82 PG9 34 V

DDEXT

BMODE1 50 PF5 83 PG10 35 V

DDEXT

BMODE2 49 PF6 85 PG11 36 V

DDEXT

CLKIN 68 PF7 86 PG12 37 V

DDEXT

EMU 60 PF8 87 PG13 38 V

DDEXT

EXT_WAKE 62 PF9 88 PG14 39 V

DDEXT

EXTCLK 78 PF10 4 PG15 40 V

DDEXT

GND 3 PF11 6 PH0 71 V

DDEXT

GND 7 PF12 8 PH1 72 V

DDEXT

GND 67 PF13 9 PH2 73 V

DDEXT

NC 45 PF14 11 RESET 2V

DDEXT

NC 46 PF15 12 SCL 44 V

DDEXT

NC 47 PG 63 SDA 43 V

DDFLASH

NC 48 PG0 17 TCK 24 V

DDFLASH

NC 64 PG1 18 TDI 23 V

DDFLASH

NC 65 PG2 19 TDO 27 V

DDINT

NC 66 PG3 21 TMS 25 V

DDINT

NMI 1 PG4 22 TRST 26 V

DDINT

PF0 76 PG5 28 V

DDEXT

DDINT

PF1 77 PG6 29 V

DDEXT

10 V

DDINT

PF2 80 PG7 30 V

DDEXT

13 V

DDINT

PF3 81 PG8 33 V

DDEXT

16 XTAL 69

GND 89

* Pin no. 89 is the GND supply (see Figure 92) for the processor; this pad must connect to GND.

Rev. B | Page 77 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Table 57. 88-Lead LFCSP Lead Assignment (Numerical by Lead Number)

Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal

1NMI

23 TDI 45 NC 67 GND

2RESET

24 TCK 46 NC 68 CLKIN

3 GND 25 TMS 47 NC 69 XTAL

4 PF10 26 TRST 48 NC 70 V

DDEXT

27 TDO 49 BMODE2 71 PH0

6 PF11 28 PG5 50 BMODE1 72 PH1

7 GND 29 PG6 51 BMODE0 73 PH2

8 PF12 30 PG7 52 V

DDEXT

74 V

DDEXT

9 PF13 31 V

DDEXT

53 V

DDINT

75 V

DDINT

10 V

DDEXT

32 V

DDINT

54 V

DDEXT

76 PF0

11 PF14 33 PG8 55 V

DDFLASH

77 PF1

12 PF15 34 PG9 56 V

DDEXT

78 EXTCLK

13 V

DDEXT

35 PG10 57 V

DDINT

79 V

DDEXT

14 V

DDINT

36 PG11 58 V

DDEXT

80 PF2

15 V

DDFLASH

37 PG12 59 V

DDEXT

81 PF3

16 V

DDEXT

38 PG13 60 EMU 82 PF4

17 PG0 39 PG14 61 V

DDFLASH

83 PF5

18 PG1 40 PG15 62 EXT_WAKE 84 V

DDEXT

19 PG2 41 V

DDEXT

63 PG 85 PF6

20 V

DDEXT

42 V

DDINT

64 NC 86 PF7

21 PG3 43 SDA 65 NC 87 PF8

22 PG4 44 SCL 66 NC 88 PF9

GND

* Pin no. 89 is the GND supply (see Figure 92) for the processor; this pad must connect to GND.

Rev. B | Page 78 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 91 shows the top view of the LFCSP pin configuration.

Figure 92 shows the bottom view of the LFCSP lead

configuration.

Figure 91. 88-Lead LFCSP Lead Configuration (Top View)

PIN 1

PIN 22

PIN 66

PIN 45

PIN 88 PIN 67

PIN 23PIN 44

PIN 1

88-LEAD LFCSP

TOP VIEW

INDICATOR

Figure 92. 88-Lead LFCSP Lead Configuration (Bottom View)

PIN 66

PIN 45

PIN 1

PIN 22

PIN 67 PIN 88

PIN 46 PIN 23

PIN 1

88-LEAD LFCSP

GND PAD

(PIN 89)

BOTTOM VIEW

INDICATOR

Rev. B | Page 79 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

OUTLINE DIMENSIONS

Dimensions in Figure 93 (for the 120-lead LQFP) and in

Figure 94 (for the 88-lead LFCSP) are shown in millimeters.

Figure 93. 120-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-120-2)

Dimensions shown in millimeters

For information relating to the SW-120-2 package’s exposed pad, see the table endnote on Page 74.

120

BOTTOM VIEW

(PINS UP)

EXPOSED PAD

EXPOSED

PAD

0.77 REF

2.945 REF

4.60 REF

1.915

2.81 REF

2.41 REF

3.75 REF

1.53

6.17

REF

5.37

REF

COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD

1.45

1.40

1.35

0.15

0.10

0.05

TOP VIEW

(PINS DOWN)

190

120

0.23

0.18

0.13

0.40

BSC

LEAD PITCH

1.60

MAX

16.20

16.00 SQ

15.80 14.10

14.00 SQ

13.90

VIEW A

PIN 1

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90

CCW

SEATING

PLANE

12°

7°

0°

0.20

0.15

0.09

0.75

0.60

0.45

1.00 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Rev. B | Page 80 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Figure 94. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

12 x 12 mm Body, Very Thin Quad

(CP-88-5)

Dimensions shown in millimeters

For information relating to the CP-88-5 package’s exposed pad, see the table endnote on Page 76.

*COMPLIANT TO JEDEC STANDARDS MO-220-VRRD

EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.

0.50

0.40

0.30

0.23

0.18

10.50

REF

0.60 MAX

0.60

MAX

6.70

REF SQ

0.50

BSC

0.138~0.194 REF

12° MAX

SEATING

PLANE

TOP VIEW

EXPOSED PAD

BOTTOM VIEW

0.70

0.65

0.60 0.045

0.025

0.005

PIN 1

INDICATOR

12.10

12.00 SQ

11.90

11.85

11.75 SQ

11.65

PIN 1

INDICATOR

*0.90

0.85

0.75

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

Rev. B | Page 81 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

AUTOMOTIVE PRODUCTS

The ADBF504W model is available with controlled manufactur-

ing to support the quality and reliability requirements of

automotive applications. Note that these automotive models

may have specifications that differ from the commercial models

and designers should review the Specifications section of this

data sheet carefully. Only the automotive grade products shown

in Table 58 are available for use in automotive applications.

Contact your local ADI account representative for specific

product ordering information and to obtain the specific Auto-

motive Reliability reports for these models.

ORDERING GUIDE

Table 58. Automotive Products

Automotive Models

1,2

Temperature

Range

Processor Instruction Rate

(Maximum)

Flash

Memory

Package

Description

Package

Option

ADBF504WYCPZ4XX –40ºC to +105ºC 400 MHz N/A 88-Lead LFCSP_VQ CP-88-5

Z = RoHS compliant part.

The use of xx designates silicon revision.

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 26 for junction temperature (T

)

specification which is the only temperature specification.

Model

1,2

Z = RoHS compliant part.

For feature comparison between ADSP-BF504, ADSP-BF504F, and ADSP-BF506F processors, see the Processor Comparison in Table 1 on Page 3.

Temperature

Range

3,4

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 26 for junction temperature (T

)

specification which is the only temperature specification.

Temperature range 0°C to +70°C is classified as commercial, and temperature range –40°C to +85°C is classified as industrial.

Processor Instruction Rate

(Maximum)

Flash

Memory

Package

Description

Package

Option

ADSP-BF504BCPZ-3F –40°C to +85°C 300 MHz 32M bit 88-Lead LFCSP_VQ CP-88-5

ADSP-BF504BCPZ-4 –40°C to +85°C 400 MHz N/A 88-Lead LFCSP_VQ CP-88-5

ADSP-BF504BCPZ-4F –40°C to +85°C 400 MHz 32M bit 88-Lead LFCSP_VQ CP-88-5

ADSP-BF504KCPZ-3F 0°C to +70°C 300 MHz 32M bit 88-Lead LFCSP_VQ CP-88-5

ADSP-BF504KCPZ-4 0°C to +70°C 400 MHz N/A 88-Lead LFCSP_VQ CP-88-5

ADSP-BF504KCPZ-4F 0°C to +70°C 400 MHz 32M bit 88-Lead LFCSP_VQ CP-88-5

ADSP-BF506BSWZ-3F –40°C to +85°C 300 MHz 32M bit 120-Lead LQFP_EP SW-120-2

ADSP-BF506BSWZ-4F –40°C to +85°C 400 MHz 32M bit 120-Lead LQFP_EP SW-120-2

ADSP-BF506KSWZ-3F 0°C to +70°C 300 MHz 32M bit 120-Lead LQFP_EP SW-120-2

ADSP-BF506KSWZ-4F 0°C to +70°C 400 MHz 32M bit 120-Lead LQFP_EP SW-120-2

Rev. B | Page 82 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Rev. B | Page 83 of 84 | April 2014

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Rev. B | Page 84 of 84 | April 2014

registered trademarks are the property of their respective owners.

D08560-0-4/14(B)

ADSP-BF504/ADSP-BF504F/ADSP-BF506F