025/0251 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features * True Dual-Ported memory cells which allow simultaneous access of the same memory location * 6 Flow-Through/Pipelined devices -- 16K x 16/18 organization (CY7C09269/369) -- 32K x 16/18 organization (CY7C09279/379) * Low operating power -- Active= 195 mA (typical) -- Standby= 0.05 mA (typical) * Fully synchronous interface for easier operation * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise -- 64K x 16/18 organization (CY7C09289/389) * 3 Modes -- Flow-Through -- Pipelined -- Burst * Pipelined output mode on both ports allows fast 100-MHz cycle time * 0.35-micron CMOS for optimum speed/power * High-speed clock to data access 6.5/7.5/9/12 ns (max.) * * * * * * -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and Lower Byte Controls for Bus Matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT709269, IDT70927, and IDT709279 Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL 1 1 0 0 0/1 CE0R CE1R LBR 0/1 OEL OER 0/1 FT/PipeL 1b 0b 1a 0a b 0a 1a 0b 1b a a b 0/1 8/9 [1] FT/PipeR 8/9 I/O8/9L-I/O15/17L [2] [1] I/O8/9R-I/O15/17R I/O Control 8/9 I/O Control 8/9 [2] I/O0L-I/O7/8L [3] A0L-A13/14/15L CLKL ADSL CNTENL CNTRSTL I/O0R-I/O7/8R 14/15/16 14/15/16 Counter/ Address Register Decode Counter/ Address Register Decode True Dual-Ported RAM Array [3] A0R-A13/14/15R CLKR ADSR CNTENR CNTRSTR Notes: 1. I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices. 2. I/O0-I/O7 for x16 devices. I/O0-I/O8 for x18 devices. 3. A0-A13 for 16K; A0-A14 for 32K; A0-A15 for 64K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 23, 1998 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Functional Description A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. The CY7C09269/79/89 and CY7C09369/79/89 are high speed synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/PIPE pin. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's address strobe (ADS). When the port's count enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Pin Configurations A8R A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R [Note 5] A14L 6 70 A14R [Note 5] [Note 6] A15L 7 69 A15R [Note 6] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 CE0L 12 CY7C09289 (64K x 16) CY7C09279 (32K x 16) CY7C09269 (16K x 16) 65 UBR 64 CE0R 63 CE1R 62 CNTRSTR 61 GND CE1L 13 CNTRSTL 14 VCC 15 R/WL 16 60 R/WR OEL 17 59 OER [Note 7] FT/PIPEL 18 58 FT/PIPER [Note 7] GND 19 57 GND I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R Notes: 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pin is NC for CY7C09269. 6. This pin is NC for CY7C09269 and CY7C09279. 7. 2 NC I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 For CY7C09269 and CY7C09279, pin #18 connected to VCC is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-through device. CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Pin Configurations (continued) A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A8R A10L 2 74 A9R A11L 3 73 A10R A12L 4 72 A11R A13L 5 71 A12R [Note 8] A14L 6 70 A13R [Note 9] A15L 7 69 A14R [Note 8] LBL 8 68 A15R [Note 9] UBL 9 67 LBR CE0L 10 66 UBR CE1L 11 65 CE0R CNTRSTL 12 64 CE1R R/WL 13 63 CNTRSTR OEL 14 CY7C09379 (32K x 18) 62 R/WR VCC 15 GND FT/PIPEL 16 CY7C09369 (16K x 18) 61 60 OER I/O17L 17 59 FT/PIPER I/O16L 18 58 I/O17R GND 19 57 GND I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R 1/012L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R CY7C09389 (64K x 18) I/10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C09269/79/89 CY7C09369/79/89 -6 CY7C09269/79/89 CY7C09369/79/89 -7 CY7C09269/79/89 CY7C09369/79/89 -9 CY7C09269/79/89 CY7C09369/79/89 -12 fMAX2 (MHz) (Pipelined) 100 83 67 50 Max Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 9 12 Typical Operating Current ICC (mA) 250 235 215 195 Typical Standby Current for ISB1 (mA) (Both ports TTL Level) 45 40 35 30 Typical Standby Current for ISB3 (mA) (Both ports CMOS level) 0.05 0.05 0.05 0.05 Notes: 8. This pin is NC for CY7C09369. 9. This pin is NC for CY7C09369 and CY7C09379. 3 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Pin Definitions Left Port Right Port Description A0L-A15L A0R-A15R Address Inputs (A0-A14 for 32K, A0-A13 for 16K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L-I/O17L I/O0R-I/O17R Data Bus Input/Output (I/O0-I/O15 for x16 devices). LBL LBR Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0-I/O8 for x18, I/O0-I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBL UBR Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L-I/O15/17L). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >1100V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. -65C to +150C Operating Range Ambient Temperature with Power Applied ..-55C to +125C Supply Voltage to Ground Potential ............... -0.3V to +7.0V Range DC Voltage Applied to Outputs in High Z State ................................. -0.5V to +7.0V Commercial Industrial DC Input Voltage............................................ -0.5V to +7.0V Ambient Temperature VCC 0C to +70C 5V 10% -40C to +85C 5V 10% Shaded area contains advance information. 4 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Electrical Characteristics Over the Operating Range CY7C09269/79/89 CY7C09369/79/89 -6 Symbol -7 -9 -12 Parameter Min Typ Max Min Typ Max Min Typ Max Min VOH Output HIGH Voltage (VCC=Min, IOH=-4.0 mA) 2.4 2.4 2.4 2.4 VOL Output LOW Voltage (VCC=Min, IOH= +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC=Max, IOUT=0 mA) Outputs Disabled ISB1 ISB2 ISB3 ISB4 0.4 0.4 2.2 2.2 -10 Com'l. Indust. Standby Current (Both Com'l. Ports TTL Level)[10] CEL Indust. & CER VIH, f=fMAX 45 Standby Current (One Port TTL Level)[10] CEL | CER VIH, f=fMAX 175 Com'l. 115 235 Indust. Standby Current (Both Com'l. Ports CMOS Level)[10] Indust. CEL & CER VCC - 0.2V, f=0 0.05 0.25 Standby Current (One Com'l. Port CMOS Level)[10] Indust. CEL | CER VIH, f=fMAX 160 200 V 0.8 V V 0.8 10 A 235 420 215 360 195 300 mA 260 445 245 410 225 375 mA 40 105 35 95 30 85 mA 55 120 50 110 45 100 mA 160 220 145 205 125 190 mA 175 235 160 220 140 205 mA -10 450 0.4 2.2 0.8 10 250 V 0.4 2.2 0.8 Typ Max Units 10 -10 10 -10 0.05 0.25 0.05 0.25 0.05 0.25 mA 0.05 0.25 0.05 0.25 0.05 0.25 mA 145 185 130 170 110 150 mA 160 200 145 185 125 165 mA Shaded area contains advance information. Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF AC Test Loads 5V 5V R1 = 893 C = 30 pF RTH = 250 OUTPUT OUTPUT R1 = 893 OUTPUT C = 30 pF R2 = 347 C = 5 pF VTH = 1.4V R2 = 347 (b) Thevenin Equivalent (Load 1) (a) Normal Load (Load 1) ALLINPUTPULSES 3.0V GND 10% 90% 10% 90% (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) 3 ns 3 ns Note: 10. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). 5 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Characteristics Over the Operating Range CY7C09269/79/89 CY7C09369/79/89 -6 Symbol fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ[11,12] tOZ[11,12] tCD1 tCD2 tDC tCKHZ[11,12] tCKLZ[11,12] Parameter Min fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z -7 Max Min 53 100 19 10 6.5 6.5 4 4 -9 Max 45 83 22 12 7.5 7.5 5 5 3 3 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 7 15 6.5 2 2 2 9 4 1 4 1 4 1 4 1 4 1 4 1 4 1 2 2 2 7 18 7.5 9 2 2 2 Units 33 50 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 10 2 1 Max 30 20 12 12 8 8 3 3 9 2 1 Min 40 67 3 3 8 -12 Max 25 15 12 12 6 6 4 0 4 0 4 0 4 0 4 0 4 0 4 0 2 1 Min 7 20 9 9 12 2 1 2 2 2 7 25 12 9 Port to Port Delays tCWDD tCCS Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time 30 9 Notes: 11. Test conditions used are Load 2. 12. This parameter is guaranteed by design, but it is not production tested. 6 35 10 40 15 40 15 ns ns CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = VIL)[13,14,15,16] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Read Cycle for Pipelined Operation (FT/PIPE = VIH)[13,14,15,16] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 An+3 tDC tCD2 Qn Qn+1 tOHZ tCKLZ Qn+2 tOLZ OE tOE Notes: 13. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 14. ADS = VIL, CNTEN and CNTRST = VIH. 15. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 16. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 7 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Bank Select Pipelined Read[17,18] tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tDC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC tSC CE0(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Left Port Write to Flow-Through Right Port Read[19,20,21,22] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD tCD1 DATAOUTR VALID tDC VALID tDC Notes: 17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 18. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 19. The same waveforms apply for a right port write to flow-through left port read. 20. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 21. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 22. It tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. 8 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[16,23,24,25] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Pipelined Read-to-Write-to-Read (OE Controlled)[16,23,24,25] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes: 23. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 24. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 25. During "No operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 9 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = VIL)[14,16,23,24] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn Qn+1 tDC tCKHZ READ tCD1 Qn+3 tCKLZ NO OPERATION WRITE tDC READ Flow-Through Read-to-Write-to-Read (OE Controlled)[14,16,23,24] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN DATAOUT tSD tHA Dn+2 tDC tCD1 tHD Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE 10 READ CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Pipelined Read with Address Counter Advance[26] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn Qn+1 tDC READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Flow-Through Read with Address Counter Advance[26] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 Qn+2 Qn+3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER Note: 26. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. 11 COUNTER HOLD READ WITH COUNTER CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[27,28] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 WRITE WITH COUNTER Notes: 27. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 28. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 12 Dn+4 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[16,28,29,30] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Notes: 29. CE0, UB, and LB = VIL; CE1 = VIH. 30. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 13 Q1 READ ADDRESS n Qn CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Read/Write and Enable Operation[31,32,33] Inputs Outputs CE0 CE1 R/W I/O0-I/O17 X H X X High-Z Deselected[34] X X L X High-Z Deselected[34] X L H L DIN L L H H DOUT Read[34] L H X High-Z Outputs Disabled OE CLK H X Operation Write Address Counter Control Operation[31,35,36,37] Address Previous Address X CLK ADS CNTEN CNTRST I/O Mode X X X L Dout(0) Reset Counter Reset to Address 0 An X L X H Dout(n) Load Address Load into Counter X An H H H Dout(n) Hold External Address Blocked--Counter Disabled X An H L H Dout(n+1) Increment Counter Enabled--Internal Address Generation Notes: 31. "X" = Don't Care, "H" = VIH, "L" = VIL. 32. ADS, CNTEN, CNTRST = Don't Care. 33. OE is an asynchronous input signal. 34. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 35. CE0 and OE = VIL; CE1 and R/W = VIH. 36. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 37. Counter operation is independent of CE0 and CE1. 14 Operation CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09269-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09269-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09269-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09269-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advance information. 32K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09279-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09279-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09279-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09279-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advance information. 64K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09289-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09289-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09289-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09289-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09289-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09289-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09289-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advance information. 15 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY Ordering Information (continued) 16K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09369-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09369-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09369-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09369-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09369-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09369-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09369-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advancd information. 32K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09379-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09379-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09379-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09379-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advance information. 64K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 6.5 CY7C09389-6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.5 CY7C09389-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-7AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09389-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-9AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C09389-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-12AI A100 100-Pin Thin Quad Flat Pack Industrial 9 12 Shaded area contains advance information. Document #: 38-00664-D 16 PRELIMINARY CY7C09269/79/89 CY7C09369/79/89 Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-A (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.