Integrated Device Technology, Inc. CMOS DUAL-PORT RAM 8K (1K x 8-BIT) IDT7130SA/LA IDT7140SA/LA FEATURES * High-speed access Military: 25/30/35/45/55/70/90/100/120ns (max.) Commercial: 20/25/30/35/45/55/70/90/100ns (max.) Low-power operation IDT7130/IDT7140SA Active: 325mW (typ.) Standby: 5mW (typ.) IDT7130/1DT7140LA Active: 325mW (typ.) Standby: 1mW (typ.) MASTER |DT7130 easily expands data bus width to 16-or-more-bits using SLAVE 1DT7140 On-chip port arbitration logic (IDT7130 Only) INT flag for port-to-port communication Fully asynchronous operation from either port Battery backup operation-2V data retention TTL-compatible, single 5V +10% power supply Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-86875 e 8 we we BUSY output flag on IDT7130; BUSY input on IDT7140 DESCRIPTION The 1DT7130/1DT7140 are high speed 1K x 8 dual-port static RAMs. The 1DT7130 is designed to be used as a stand-alone 8-bit dual-port RAM or as a "MASTER" dual- port RAM together with the IDT7140 SLAVE dual-port in 16-bit-or-more word width systems. Using the IDT MAS- TER/SLAVE dual-port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with sepa- rate control, address and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CEMOS high-performance tech- nology, these devices typically operate on only 325mW of power at maximum access times as fast as 20ns. Low- power (LA) versions offer battery backup data retention ca- pability, with each dual-port typically consuming 200,w from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, 48- or 52-pin LCCs, 52-pin PLCCs, and 48-Lead flatpacks. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM RWL CEL OEL Ast ASR ATL . | { A7A VO ft Oor ot -3~{cot {COLUMN COLUMN] [COL]: VO7L JSEL; | {0 VO | [SEL |_- VO7R BUSYL o,______f tg BUSYAM As. 71_ ROW KY MEMORY [ny ROW I Ase Ao. _|?,{ SELECT ARRAY SELECTS] agg Ao. ARBITRATION [72 A%* Aat AND INTERRUPT|* 4R CEL.4 LOGIC CEr RAW + R/Wa INTL? 4 | INTA?) NOTES: 1. 1077130 (MASTER): BUSY is open drain output and requires pullup 2689 drw 01 resistor. 1DT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor. CEMOS is a trademark of integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1990 1990 Integrated Device Technology, inc. DSC-1000/2 qIDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MIUTARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGUARATIONS SJ cE.O1 48 [J Vcc AW C2 47 CEr BUST iH 3 46 (JRWr LLj4 45 R OE. 5 44 B A Ao (6 43 R Aw Q7 42 (Aor Aa Os 41 DIAin Ast 9 p4g-1, 40 LJAzR Aa l10 Gag-1 39 Asa AA? o> a DAs 1 A An 113 48 36 5 Aca Ae (14 35 LIA7R Aoi 15 34 (J Asr Oot [16 33 LJ Aor WOuw (17 32 [J l/O7" Oa O18 31 LJ i/Oer vou 419 30 DOs" VWOa J 20 29 (1 i/O4n vost C21 28 (J 1/Oar Oe. LJ 22 27 D/Oen vOn G23 26 Dl/O1A GND] 24 25 [11/Oor 2689 drw 02 DIP TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) 48-PIN LCC/FLATPACK TOP VIEW 21 22 23 24 25 26 27 26 29 20 31 32 33 Furvevrvervriryrersrervriry gece secdegdd 52-PIN LCC/PLCC TOP VIEW 2889 drw 04 Symbol Rating Commercial | Military Unit VTERM | Terminal Voltage | -0.5to+7.0 [-0.5to+7.0] V with Respect to GND TA Operating 0 to +70 55 to+125 | C Temperature Tatas | Temperature -5 to+125 | -65t0+135 | C Under Bias TstG | Storage -55 fo +125 | -65to+150 | C Temperature louT DC Output 50 50 mA Current NOTE; 2689 bi 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Vec Supply Voltage 45 | 50] 55 GND 0 0 0 VIH Input High Voltage - -0 NOTE: 2680 tI 02 1. Vit (min.) = -3.0V for pulse width less than 20ns. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Ambient Grade Temperature GND Vec Military 85C to +125C ov 5.0v + 10% Commercial 0C to +70C ov .0v + 10% 2689 bi 03 TAIOT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x &-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V +10%) IDT7130SA IDT7130LA IDT7140SA IDT7140LA Symbol Parameter Test Conditions Min. Max. Max. Max. Unit [lu input Leakage Vcc = 5.5V, VIN = OV to Vcc _ 10 _ 5 pA Current |ko{ | Output Leakage CE = VIH, VOUT = OV to Vcc _ 10 5 pA Current VoL Output Low Voltage fo = 4.0mA - 0.4 _ 0.4 Vv (00-107) VoL Open Drain Output {| fot = 16mA 0.5 - 0.5 Vv Low Voltage (BUSY, INT) VoH | Output High Voltage IOH = -4mA 2.4 _ 2.4 _ Vv 2689 ti 04 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE!) (vcc = 5.0V + 10%) 7130 x 2028] 7130 x 259] 7130 x 300] 7130x350] 7130x 45 7140 x 2029)] 7140 x 29 | 7140 x 30] 7140 x 357)! 7140 x 45 Symbol Parameter Test Conditions Version | Typ. Max. | Typ. Max. Typ. Max. | Typ. Max. | Typ. Max. [Unit lec Dynamic Operating | CE = Vii Mil. Pa 7 7 B05 a 2 a 2h * 2a Current (Both Ports | Outputs Open Sh 7 a 550 751951 95 190 mA Active) f = fMax Com't. 5 0 LA| 75 190 180 75155 | 75 145 Isa1 | Standby Current CEL and CEa>Vin [mi SA] ss 25 75 | 25 65 (Both Ports- TTL | f = fuax LA| __ ao Level Inputs) Comi,SA| 25 65 LA| 25 45 25.45 25 45 Isp2__ | Standby Current CEL or CER 2 VIN 40 170) 40 135 (One Port - TTL Active Port Outputs 0 138 40 138 mA Level Inputs) Open, f = fMax') 40.95 | 40. 85 isaa__ | Full Standby Current | Both Ports CEL and 12 35 | 1.0 30 (Both Ports - Ali CER 2 Vcc -0.2V 04 10/02 10 mA CMOS Level Inputs) | VIN 2 Vcc -0.2V or 10 15} 1.0 15 VIN < 0.2V,f = 0! 02 4/4102 4 isp4 | Full Standby Current | One Port CEt or 40 150] 40 125 (One Pont - All CER 2 Vcc -0.2V 35 115] 35 95 CMOS Level Inputs, | Vin > Vcc -0.2V or f= 00) VIN < 0.2V Com 54] 59 160 | 50 150 | 45 137] 40 115] 40 105 |mA Active Port Outputs LA| 46 125 46 115] 42 105 | 35 90 35 80 Open, f = fuax NOTES: 26889 i 06 1. "x" in part numbers indicates power rating (SA or LA). 2. OC to +70C temperature range only. 3. -55C to +125C temperature range only. 4. Att = fwax, address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of 1/tac, and using AC TEST CONDITIONS of input levels of GND to 3V. 5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 6. Not available in DIP packages, see 7030/40 data sheet. 7. DIP packages for 0C to +70C only, see 7030/40 data sheet. 7A 3IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM &K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE! (continued) (Vcc = 5.0V +10%) 7130 x 55 7130 x 70 7130 x 90 | 7130 x 100 [7130 x14 714055 | 7140x70 | 7140x90 | 7140 x 100 17140 x 120% Symbol Parameter Tast Conditions Version | Typ. Max. | Typ. Max. | Typ. Max.| Typ. Max. | Typ. Max. |Unit Icc Dynamic Operating GE = Vi Mil. SA] 65 230] 65 225} 65 200] 65 190] 65 190 LA] 65 185] 65 180] 65 160] 65 155] 65 155 Current (Both Ports Outputs Open SAT 65180 1 65 1801 65 180 | 65 180 mA Acti t = tMax) Com'i. - = ive) tA| 65 140 | 65 135] 65 130| 65 190| \sa1_ | Standby Current CEL and CER>ViH [yi SA] 25 685 | 25 65 [25 65 | 25 65 | 25 65 (Both Ports - TTL { = imax LA| 25 55 25.55 | 25) 45 | 25 45 | 25 45 a Level Inputs) Comi>A| 22 65 | 2 60 [25 55 [25 ss [ P tal 25 45 | 25 40 | 25 35 | 25 35 | GEL or CE SA] 40 1385 | 40 135] 40 125] 40 125] 40 125 Ise (One Port ce rarneennead Mil tal 40 110 | 40 110 | 40 100] 40 100| 40 100], puts m, 4 , SAT 40 115 | 40 110] 40 110] 40 1107 Level Inputs) Open,f=imaxi? |Comlial 40 a5 | 40 85 | 40 75 | 40 75 | Isa | Full Standby Current | Both Ports CEL and | 44, SA] 1.0 30 | 10 30 71.0 30] 1.0 30] 1.0 30 (Both Ports - All CER 2 Vcc -0.2V LAT O2 10 | 02 10402 10 | 02 10]02 10 mA CMOS Level Inputs) | Vin 2 Vcc -0.2V or Com't SA] 1.0 15 10 15 |10 #1 ]10 15687 VIN $ 0.2V, f = 0% talo2 46 |o2 4 |o2 4 f[o2 4[ isaa_| Full Standby Current | One Port CEL or mi. SA] 40 120] 40 115] 40 110] 40 110] 40 110 (One Port - All CEn 2 Vcc -0.2V m 0 CMOS Level Inputs, | VIN 2 Vcc -0.2V or LA] 35 9 35_85 | 35_ 80 | 35 80 | 35 60 f= ot) VIN < 0.2 Com SA} 42 100) 40 100) 40 95 | 40 95 | Ima Active Port Outputs LA] 35 75 35 75 | 35 70 35 7O; Open, f = fax!) NOTES: 2680 i 06 1. *x" in part numbers indicates power rating (SA or LA). 2, 0C to +70C temperature range only. 3, -55C to +125C temperature range only. 4. Atf = fax, address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of 1/tRc, and using AC TEST CONDITIONS of input levels of GND to 3V. 5. f 0 means no address or control lines change. Applies only to inputs at CMOS level standby. DATA RETENTION CHARACTERISTICS (LA Version Only) IDT7130LAIDT7140LA Symbol Parameter Test Conditions Min. Typ. Max. Unit Vor Vcc for Data Retention 2.0 _ 0 Vv kecor Data Retention Current Mil. _ 100 4000 LA Voc = 2.0V, CE 2 Vcc -0.2V | com. 100 1500 pA tepals) Chip Deselect to Data 0 = _ P ; ; VIN > Vec -0.2V or VIN < 0.2V ns Retention Time tala) Operation Recovery tact?) - _ ns Tima NOTES: 2689 bbl 07 1. Vee = 2V, Ta = 425C 2. tac = Read Cycle Time 3. This parameter is guaranteed but not tested. 741IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) DATA RETENTION WAVEFORM MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION MODE ViH AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Referance Levels 1.5V Output Load See Figures 1, 2, 3 and 4 2689 Ibi 08 5V 12500 DATA out " TTSQ. 100pF* (30pF for 20ns 25ns, 30ns, 35ns, and 45ns) Figure 1. Output Load 5V 270Q BUSY or INT 100pF* Figure 3. BUSY and INT Output Load ViH 2089 drw 05 5V 1250Q DATA out 775Q 5pF* Figure 2. Output Load (for txz, tLz, twz, and tow) 2702 BUSY or INT : 30pF* . Figure 4. BUSY and iNT Output Load (for 20ns, 25ns and 30ns versions) * Including scope and jig 2689 drw 06IOT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 6K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5) 7130 x 20(2.6) | 7130 x 25(6) | 7130 x 30( | 7130x357 | 7130 45 7140 x 20(2.6) | 7140 x 25(9) | 7140 x 30/8) | 7140x357) | 7140 x 45 Parameter Min. Max.| Min. Max. | Min. Max. | Min. Max. | Min. Max. 2889 bl 09 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE() (Continued) 7130 x 55 7130 x 70 7130x90 | 7130x100 |7130 x 1206) 7140 x 55 7140 x 70 7140 x90 | 7140x100 |7140 x 1200) Symbol Parameter Min. Max. | Min. Max. | Min. Max. [| Min. Max. | Min. Max. Unit Read Cycle tac Read Cycle Tima 55 _ 70 _ 90 _ 100, 120, ns tAA Address Access Time 55 _ 70 _ 90 100 120 ns tACE Chip Enable Access Time _ 55 _ 70 _ 90 100 120 ns taOE Output Enable Access Time 35 40 40 - 40 60 ns tOH Output Hold From Address Change 0 0 10 _ 10 _ 10 ns tz Output Low Z Time (1.4) 5 5 _ 5 5 5 ns tHZ Output High Z Timet'.4) 30 _ 35 40 40 40 ns tPu Chip Enable to Power Up Time(4) 0 = 0 = 0 _ 0 = 0 = ns tPD Chip Disable to Power Down Time) | 50 | 50 50 50 50 ns NOTES: 2680 thi 10 1, Transiton is measured t500mV from low or high impedance voltage with load (Figures 1, 2, 3 and 4). 2. OC to +70C temperature range only. 3. -55C to +125C temperature range only. 4. This parameter guaranteed but not tested. . "x in part numbers indicates power rating (SA or LA). 6. Not available in DIP packages, see 7030/40 data sheet. 7. DIP packages for 0C to +70C only, see 7030/40 data sheet. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1. 2; 4) i tr >| ADDRESS SY 1AA > } tH I 40H DATAout PREVIOUS DATA VALID DATA VALID XX | 2689 drw 07 7A 6IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (1, 3) {ACE CE * He tAOE ec | # TT uz tHZ DATAouT 7< DATA VALID >_= _____tL2 ______- letPU | + 1PD Icc CURRENT ' 7H 50% 50% SB 2080 dew 08 NOTES: 1. RWis high for Read Cycies. . Device is continuously enabled, CE = Vit. 2 3. Addresses valid prior to or coincident with CE transition low. 4, OE =Vu. vA 7IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (7) 7130 x 20(2.8) | 7130 x 25(8) | 7130 x 30) | 7130 x 3519) | 7130 x 45 7140 x 20'2.8) | 7140 x 258) | 7140 x 300) | 7140 x 35) | 7140 x 45 Parameter Min. Max.| Min. Max.| Min. Max. | Min. Max. | Min. Max. | Unit ns ns ns ns ns ns ns ns ns ns As 2889 bl 11 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE () 7130x55 | 7130x70 | 7130x90 | 7130x100 /7130x 120 7140x55 | 7140x70 | 7140x90 | 7140x100 [7140 x 120 Parameter Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. | Unit twe ns ns tAw ns tas ns twe ns twR ns tow ns tHz , ns {DH as twz ns tow ' ns NOTES: 2680 BI 12 1. Transition is measured +500mV from low or high impedance voltage with load (Figures 1, 2, 3 and 4}. 2, 0C to +70C temperature range only. 3. -58C to +125C temperature range only. 4. This parameter guaranteed but not tested. 5. For MASTER/SLAVE combination, twc = thas + (we. 6. Specified for OE at high (Refer to Timing Waveform of Write Cycle", Note 7) 7. "x" in part numbers indicates power rating (SA or LA). 8. Not available in DIP packages, see 7030/40 data sheet. 9. DIP packages for 0C to +70C only, see 7030/40 data sheet. CAPACITANCE (Ta = +25C, { = 1.0MHz) Symbol Parameter (1) Conditions | Max.] Unit CIN Input Capacitance VIN = OV 11 | pF Cout Output Capacitance VIN = OV 11 | pF NOTE: 2689 tbl 13 1. This parameter is determined by device characterization but is not production tested. 7A 8IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING) (1,2,3,7) ADDRESS 3| DATAouT DATAIN 2680 drw 00 TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING) (1,2,3,5) ADDRESS DATAIN 2689 drw 10 NOTES: . PAW must be high during all address transitions. . Awrite occurs during the overlap (tew or twp) of a low CE and a low R/W. . tWRis measured from the earlier of CE or R/W going high to the end of the write cycle. . During this period, the I/O pins are in the output state and input signals must not be applied. If the CE low transition occurs simultaneously with or after the RW low transition, the outputs remain in the high impedance state. . Transition is measured t500mV from steady state with a 5pF load (including scope and jig). . If OF is low during a RAW controlled write cycle, the write pulse width must be larger of twe or (twz + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If OE is high during an RAW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tw. NOM eono 7A 9IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (8) 7130 x 200,19 17130 x 25419 | 7130 x 30(1) 7190 x 3541 7130 x 45 7140 x 2001917149 x 25(19) | 7140 x 7140 x 354") 7140 x 45 Parameter Min. Max.| Min. Max. | Min. Max. | Min. Max. | Min. Max. 30 ONL to 20 to to to to Write Data Valid to Read Data to to to 2680 ti 14 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (8) 7130 x 55 7130 x 70 7130 x 90 7130 x 100 |7130 x 120(2) 7140 x 55 7140x70 | 7140x90 | 7140x100 |7140 x 120(% Parameter Min. Max.| Min. Max. | Min. Max. | Min. Max. | Min. Max. | Unit to 50 ns to 50 ns to ns ns to ns Write Valid to Read Data ns ns ns ns ns ns topo to ns NOTES: 2680 bi 15 1. 0C to +70C temperature range only. 2. -65C to +125C temperature range only. 3. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Read With BUSY (For Master !1DT7130 only). 4. To ensure that the earlier of the two ports wins. 5. too is a calculated parameter and is the greater of 0, twoo-twe (actual) or toDD-tow (actual). 6. To ensure that the write cycle is inhibited during contention 7. To ensure that a write cycle is completed after contention. 8. *x" in part numbers indicates power rating (SA or LA). 9. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Wavetorm of Read With Port-to-Port Delay (For Slave IDT7140 Only). 10. Not available in DIP packages, see 7030/40 data sheet. 1t. DIP packages for 0C to +70C only, see 7030/40 data sheet. TA 10IDT?7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 6-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ WITH BUSY (1.2.3) (FOR MASTER IDT7130 ONLY) ADDR aR RAWR DATAINR DATAouTL NOTES: 1. To ensure that the eartier of the two ports wins. 2. Write Cycle parameters should be adhered to in order to ensure proper writing. 3. Device is continously enabled for both ports. 4. OE at LO for the reading pon. 2689 drw 11 TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY '':2:3)(FOR SLAVE IDT7140 ONLY) tWC MATCH ADDRR RWa DATAINR ADDRL DATAOUTL VALID 7 NOTES: 1. Assume BUSY input at HI for the writing port, and OE at LO for the reading port. , 2880 drw 12 2. Write Cycle parameters should be adhered to in order to ensure proper writing. 3. Device is continuosly enabled for both ports. TIMING WAVEFORM OF WRITE WITH BUSY INPUT (FOR SLAVE IDT7140 ONLY) twP tWB tWH BUSY 2689 drw 13 7A "1IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF CONTENTION CYCLE NO. 1, CE ARBITRATION CEL VALID FIRST: ADDR ADDRESSES MATCH x LANDR CEL i He {APS CER \ BAC tapc BUSYrR { 1 2689 drw 14 CER VALID FIRST: ADDR ADDRESSES MATCH LANDR Xx X CEn i WH TAPS CEL tBAC [+ tspc BUSYL 2680 drw 15 TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, ADDRESS VALID ARBITRATION) LEFT ADDRESS VALID FIRST: tAc OR two ADDAL ADDRESSES MATCH ADDRESSES DO NOT MATCH x tAPS ADDAR x {BAA [+ tBDA BUSYA 2680 dew 16 RIGHT AODRESS VALID FIRST: tRAc OR two ADDR rR ADDRESSES MATCH ADDRESSES DO NOT MATCH x taps ADDR t ) c {BAA [+--_t BDA BUSYL 2688 drw 17 NOTE: 1, CEL = CEa = ViIDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE () 7130 x 20(1.4) | 7130 x 254) | 7130x 30) | 7130x350) | 7130 45 7140 x 20114) | 7140 x 25 | 7440x390 | 7140x350) | 7140x485 Symbol Parameter Min. Max. | Min. Max. Min. Max. Min. Max. Min. Max. Unit Interrupt Timing tas Address Set-up Time 0 0 _ 0 _ ns twrR Writa Recovery Time 0 0 _ 0 _ ns tiINS Interrupt Set Time _ : _ 35 40 ns tiINR Interrupt Reset Time _ 20 25 30 _ 35 40 ns 2680 bi 16 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE 7130 x 55 7130 x 70 7130 x 90 7130x100 | 7130 x 1202) 7140 x 55 7140 x 70 7140 x 90 7140x100 | 7140 x 120(2) Symbol Parameter Min. Max. | Min. Max, Min. Max. Min. Max. Min. Max. Unit Interrupt Timing tas Address Set-up Tima 0 _ 0 _ 0 _ 0 = Qo _ ns twR Write Recovery Time 0 _ 0 _- 0 _ 0 _ 9 _ ns tINS Interrupt Set Time _ 45 _ 50 _ 55 = 60 70 as tINR Interrupt Reset Time _ 45 50 = 55 = 60 70 ns NOTES: 2680 bi 17 . OC to +70C temperature range only. . 85C to +125C temperature range only. x in part numbers indicates power rating (SA or LA). . Not available in DIP packages, see 7030/40 data sheet. . DIP packages for 0C to +70C only, see 7030/40 data sheet. neon TIMING WAVEFORM OF INTERRUPT MODE "1: 2) LEFT SIDE SETS INTh: jo twc al { ADDRL WRITE 3FF KKK x tAS 1wA RAL TINS INTR 2089 crv 18 RIGHT SIDE CLEAR INTR: tRC > leo twR RRO LLL LLL LLY OFF WN AAAANAANANANANANAR / #tiNR iNTR NOTES: 2088 dew 19 1. CEL =CEr= Vi 2. INTL and INTa are reset (high) during power up. 7.1 131IOT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF INTERRUPT MODE, 2) RIGHT SIDE SETS INTL: he * ! twe * ADDRa x WRITE 3FE MK XK >.< TAS twR R/Wr tINS INTL LEFT SIDE CLEAR INTL: 2680 drw 20 tRC | Pt }+| twr MOLL LLL LLLP 08 WNAAAANAAAAAAAANNG / l*#tINR INTL 2689 drw 21 NOTES: 1, CE. = CEa = Vi 2. INTr and INTL are reset (high) during power up. 16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS LEFT RIGHT RAW RW WW he RAW iotvis0 MASTER BUSY BUSY BUSY BUSY t-AAA, +5V +5V AM RW RW IDT7140 SLAVE BUSY BUSY 2089 drw 22 NOTE: 1. No arbitration in 1077140 (SLAVE). BUSY-IN inhibits write in IDT7140 (SLAVE). 7.1 14IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILUTARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION: The IDT7130/DT?7140 provides two ports with separate control, address and VO pins that permit independent access for reads or writes to any locations in memory. The |DT7130/ 1DT7140 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the ports OE turns on the output drivers when set LOW. Non- contention READ/WRITE conditions are illustrated in Table 1. The interrupt flag (INT) permits communication between Ports or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 3FE (HEX). The left port clears the interrupt by reading address location 3FE. Likewise, the right port interrupt flag (INTRA) is set when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FF. The message (8-bits) at SFE or 3FF is user defined. If the interrupt function is not used, address locations 3FE or 3FF are not used as mailboxes, but as part of the random access memory. Refer to Table 1 for the interrupt operation. ARBITRATION LOGIC FUNCTIONAL DESCRIPTION: The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has access. In all cases, an active BUSY flag will be set for the delayed port. The BUSY flags are provided for the situation when both ports simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has access and sets the delayed ports BUSY flag. BUSY is set at speeds that permit the processor to hold the operation and its respective address data. It is important to note that the operation is invalid for the port that has BUSY set LOW. The delayed port will have access when BUSY goes inactive. Contention occurs when both left and right ports are active and both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are provided: (1) if the addresses match and are valid before CE, on-chip control logic arbitrates between CEL and CEn for access; or (2) if the CEs are low before an address match, on-chip control logic arbitrates between the left and right addresses for access (refer to Table Ill). In either mode of arbitration, the delayed port's BUSY flag is set and will reset when the port granted access completes its operation. DATA BUS WIDTH EXPANSION MASTER/SLAVE DESCRIPTION: Expanding the data bus width to sixteen-or-more-bits in a dual-port RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUSYL while another activates its BUSYR signal. Both sides are now busy and the CPUs will wait indefinitely for their port to become free. To avoid the Busy Lock-Out problem, IDT has developed a MASTER/SLAVE approach where only one arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs which allow an interface to the MASTER with no external components and with a speed advantage over other systems. When expanding dual-port RAMs in width, the writing of the SLAVE RAMs must be delayed, until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUSY to ensure that a write cycle takes place after the contention is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to BUSY from the MASTER. 74 1IOT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BiT) MILUTARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLES TABLE | - NON-CONTENTION READ/WRITE CONTROL(4) RW| CE | OE Do-7 Function CER = CEL = H, Power Down IsB1 or IsB3 on 2689 bl 18 NOTES: 1, AoL-AazAon-Aor 2. It BUSY = L, data is not written 3. If BUSY = L, data may not be valid, see twoo and tooo timing. 4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE TABLE Il - INTERRUPT FLAG: 4) Left Port Port AoL-Ast AoL-Aor Function 3FF x Set a x 3FF Reset a xX 3FE Set Left x xX Reset Left INTL Flag 2680 thi 19 NOTES: 1. Assumes BUSY. = BUSYa = H. 3. If BUSYa = L, then NC. 2. if BUSY. = L, then NC. 4. H= HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE TABLE Ill ARBITRATION (?) Aot-Ast Function Contention L-Port Wins R-Port Wins Arbitration Resolved RLSL = Aor-AoR = Aot-Agt L H R-Port Wins LW5R = AoR-AOR = Aot-Ast. H L Arbitration Resolved LW5R = Aor-AQR = Aot-Agt L H Arbitration Resolved NOTES: 2680 bi 20 1. INT Flags Don't Care. Same = Left and Right Addresses match within Sns of each other. 2. X= DON'T CARE, L = LOW, H = HIGH LLSR = Loft CE = LOW 2 5ns before Right CE. LV5R = Left Address Valid 2 5ns before right address. ALSL = Right CE = LOW 2 5ns before Left CE. RVSL = Right Address Valid 2 5ns before left address. LWSR = Left and Right CE = LOW within 5ns of each other. 7A 16IDT7130SA/LA AND IDT7140SA/LA CMOS DUAL-PORT RAM 8K (1K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range L Commercial (0C ta +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class 8 Plastic DIP Sidebraze DIP (600 mil) Plastic Leaded Chip Carrier 48-Pin Leadless Chip Carrier 52-Pin Leadiess Chip Carrier Flatpack 20 Commercial Only 25 30 36 2 Speed In Nanoseconds 70 90 100 120 Military Only | LA Low Power | SA Standard Power | 7130 8K (1K x 8-Bit) MASTER Dual-Port RAM | 7140 8K (1K x 8-Bit) SLAVE Dual-Port RAM 2689 drw 23 7A v7