DATA SHEET MOS INTEGRATED CIRCUIT PD431008 1M-BIT CMOS FAST STATIC RAM 128K-WORD BY 8-BIT Description The PD431008 is a high speed, low power, 1 048 576 bits (131 072 words by 8 bits) CMOS static RAM. The PD431008 is packed in 32-pin plastic SOJ. Feature 131 072 words by 8 bits organization Fast access time 15, 17, 20 ns (MAX.) Output buffers control: OE Common I/O using three state outputs Fully static operation: no clock or refreshing to operate TTL compatible: all inputs and outputs Single +5 V power supply Ordering Information Access time Part number Package PD431008LE-15 PD431008LE-17 PD431008LE-20 Remark 32-pin plastic SOJ (400 mil) ns (MAX.) Operating Standby supply current supply current mA (MAX.) mA (MAX.) 15 160 17 150 20 140 Quality grade 10 Standard Operating supply current is 120 mA (MAX.) when this product is used at 50ns cycle time. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-3242 (O.D.No. IC-8815) Date Published July 1993 P Printed in Japan (c) 1993 1992 PD431008 Pin Configuration (Marking Side) 32-Pin Plastic SOJ (400 mil) 1 32 A4 A2 2 31 A5 A1 3 30 A6 A0 4 29 A7 CS 5 28 OE I/O1 6 27 I/O8 I/O2 7 26 I/O7 25 GND 24 VCC VCC 8 GND 9 I/O3 10 23 I/O6 I/O4 11 22 I/O5 WE 12 21 A8 A16 13 20 A9 A15 14 19 A10 A14 15 18 A11 A13 16 17 A12 A0 - A16 2 PD431008LE-15 PD431008LE-17 PD431008LE-20 A3 : Address Inputs I/O1 - I/O8 : Data Inputs/Outputs CS : Chip Select WE : Write Enable OE : Output Enable V CC : Power Supply GND : Ground PD431008 Block Diagram A7 1 Address buffer A9 Memory cell array 1 048 576 bits (512x 256x 8) Row decoder 9 8 A16 I/O1 Input data controller I/O8 Output data controller Sense/Switch Column decoder 8 Address buffer 7 1 A0 - A6 A8 CS WE OE VCC GND Truth Table CS OE WE Mode I/O Supply current H Not selected Hi-Z ISB L L H Read DOUT L L Write DIN L H H Output disable Hi-Z Remark ICC : Don't care 3 PD431008 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage V CC - 0.5 Note to +7.0 V Input/Output voltage VT - 0.5 Note to VCC +0.5 V Operating temperature T opt 0 to +70 C Storage temperature T stg - 55 to +125 C Note -3.0 V (MIN.) (Pulse width: 10 ns) Recommended Operating Conditions Parameter Symbol MIN. TYP. MAX. Unit Supply voltage V CC 4.5 5.0 5.5 V High level input voltage VIH 2.2 VCC +0.5 V +0.8 V +70 C Low level input voltage V IL - 0.5 Ambient temperature Ta 0 Note Note -3.0 V (MIN.) (Pulse width: 10 ns) DC Characteristics (Recommended operating conditions unless otherwise noted) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VCC -2 +2 A Output leakage current ILO VI/O = 0 V to VCC , CS = VIH or OE = VIH or WE = V IL -2 +2 A Operating supply current ICC CS = VIL , I I/O = 0 mA Cycle time: 15 ns 160 Cycle time: 17 ns 150 Cycle time: 20 ns 140 Cycle time: 50 ns 120 mA ISB CS = VIH, V IN = VIH or V IL 30 ISB1 VCC - 0.2 V < = CS, < VIN < = 0.2 V or V CC - 0.2 V = VIN 10 High level output voltage VOH I OH = -4.0 mA Low level output voltage V OL I OL = 8 mA Standby supply current Remark 2.4 mA V 0.4 V MAX. Unit V IN : Input voltage Capacitance (Ta = +25 C, f = 1 MHz) Parameter Symbol Test conditions TYP. Input capacitance C IN VIN = 0 V 6 pF Input/Output capacitance CI/O VI/O = 0 V 8 pF Remark 1. VIN : Input voltage 2. These parameters are periodically sampled and not 100 % tested. 4 MIN. PD431008 AC Characteristics (Recommended operating conditions unless otherwise noted) AC Test Conditions Input waveform (Rise/fall time < = 3 ns) 3.0 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V GND Output waveform Output load AC Characteristics directed with the note should be measured with the output load shown in Fig. 1 or Fig. 2. Fig. 1 Fig. 2 (For tAA, tACS, t OE, t OH) (For tCHZ, tCLZ, t OHZ, t OLZ, tWHZ , t OW) +5 V +5 V 480 I/O (Output) I/O (Output) 255 Remark 480 30 pF CL 255 5 pF CL C L includes capacitances of the probe and jig, and stray capacitances. 5 PD431008 Read Cycle Parameter Symbol PD431008LE-15 PD431008LE-17 PD431008LE-20 MIN. MAX. 15 MIN. MAX. 17 MIN. Unit Condition MAX. 20 ns Read cycle time tRC Address access time tAA 15 17 20 ns CS access time tACS 15 17 20 ns OE access time tOE 8 9 10 ns Output hold from address change tOH 5 5 5 ns CS to output in low-Z tCLZ 5 5 5 ns OE to output in low-Z tOLZ 1 1 1 ns CS to output in high-Z tCHZ 7 7 7 ns OE to output in high-Z tOHZ 7 7 7 ns Note 1. Note 2. Note 1. See the output load shown in Fig. 1. 2. See the output load shown in Fig. 2. Read Cycle Timing Chart 1 (Address Access) tRC A0 - A16 (Input) tAA tOH I/O (Output) Previous Data Out Remark 1. In read cycle, WE should be fixed to high level. 2. CS = OE = VIL 6 Data Out PD431008 Read Cycle Timing Chart 2 (CS Access) t RC A0 - A16 (Input) t AA t ACS CS (Input) t CLZ t CHZ OE (Input) t OE t OHZ t OLZ I/O (Output) Hi - Z Data Out Hi - Z Caution Address valid prior to or coincident with CS low level input. Remark In read cycle, WE should be fixed to high level. 7 PD431008 Write Cycle Parameter Symbol PD431008LE-15 PD431008LE-17 PD431008LE-20 MIN. MAX. MIN. MAX. MIN. Unit Write cycle time tWC 15 17 20 ns CS to end of write tCW 10 11 12 ns Address valid to end of write tAW 9 11 12 ns Write pulse width tWP 9 10 10 ns Data valid to end of write tDW 8 9 10 ns Data hold time tDH 0 0 0 ns Address setup time tAS 0 0 0 ns Write recovery time tWR 0 0 0 ns WE to output in high-Z tWHZ Output active from end of write tOW 7 Condition MAX. 7 7 ns Note 3 3 3 ns Note See the output load shown in Fig. 2. Write Cycle Timing Chart 1 (WE Controlled) tWC A0 - A16 (Input) tCW CS (Input) tAW tAS tWP tWR WE (Input) tACS tDW tCLZ tDH Data In I/O (Input) tOH tWHZ tOW Hi - Z I/O (Output) tAA Caution CS or WE should be fixed to high level during address transition. Remark 1. Write operation is done during the overlap time of a low level CS and a low level WE. 2. During tWHZ , I/O pins are in the output state, therefore the input signals of opposite phase to the output must not be applied. 3. When WE is at low level, the I/O pins are always Hi-Z. When WE is at high level, read operation is executed. Therefore OE should be at high level to make the I/O pins Hi-Z. 8 PD431008 Write Cycle Timing Chart 2 (CS Controlled) tWC A0 - A16 (Input) tAS tCW CS (Input) tAW tWP tWR WE (Input) tDW Data In I/O (Input) I/O (Output) tDH Hi - Z Caution CS or WE should be fixed to high level during address transition. Remark Write operation is done during the overlap time of a low level CS and a low level WE. 9 PD431008 Package Drawing 32 PIN PLASTIC SOJ (400 mil) 17 1 16 C 32 D B E H G U J F I T K Q M P N M P32LE-400A NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maxi- mum material condition. ITEM INCHES 21.06 0.2 0.829 0.008 C 10.16 0.400 D 11.18 0.2 0.440 0.008 E 1.005 0.1 0.040 -0.005 F 0.74 0.029 G 3.5 0.2 0.138 0.008 H 2.545 0.2 0.100 0.008 I 0.8 MIN. 0.031 MIN. J 2.6 0.102 K 1.27 (T.P.) 0.050 (T.P.) M 0.40 0.10 0.016 +0.004 -0.005 N 0.12 0.005 P 9.4 0.20 0.370 0.008 Q 0.1 0.004 T R 0.85 U 10 MILLIMETERS B 0.20 +0.10 -0.05 +0.004 R 0.033 0.008+0.004 -0.002 PD431008 RECOMMENDED SOLDERING CONDITIONS Please consult with our sales offices for soldering conditions of the PD431008. TYPE OF SURFACE MOUNT DEVICE PD431008LE: 32-pin plastic SOJ (400 mil) 11 PD431008 [MEMO] 12 PD431008 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 13 PD431008 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6