32-pin plastic
SOJ (400 mil)
µ
PD431008
MOS INTEGRATED CIRCUIT
Description
The
µ
PD431008 is a high speed, low power, 1 048 576 bits (131 072 words by 8 bits) CMOS static RAM.
The
µ
PD431008 is packed in 32-pin plastic SOJ.
Feature
●131 072 words by 8 bits organization
●Fast access time 15, 17, 20 ns (MAX.)
●Output buffers control: OE
●Common I/O using three state outputs
●Fully static operation: no clock or refreshing to operate
●TTL compatible: all inputs and outputs
●Single +5 V power supply
Ordering Information
Operating Standby
Part number Package supply current supply current Quality grade
mA (MAX.) mA (MAX.)
µ
PD431008LE-15 15 160
µ
PD431008LE-17 17 150 10 Standard
µ
PD431008LE-20 20 140
Remark Operating supply current is 120 mA (MAX.) when this product is used at 50ns cycle time.
Document No. IC-3242
(O.D.No. IC-8815)
Date Published July 1993 P
Printed in Japan
The information in this document is subject to change without notice.
1M-BIT CMOS FAST STATIC RAM
128K-WORD BY 8-BIT
© 1992
DATA SHEET
Access time
ns (MAX.)
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
1993
2
µ
PD431008
Pin Configuration (Marking Side)
32-Pin Plastic SOJ (400 mil)
A0 – A16 : Address Inputs
I/O1 – I/O8 : Data Inputs/Outputs
CS : Chip Select
WE : Write Enable
OE : Output Enable
VCC : Power Supply
GND : Ground
µ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
CS
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A16
A15
A14
A13
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A8
A9
A10
A11
A12
PD431008LE-15
PD431008LE-17
PD431008LE-20
µ
µ
3
µ
PD431008
Block Diagram
Truth Table
CS OE WE Mode I/O Supply current
H✕✕ Not selected Hi-Z ISB
L L H Read DOUT
L✕L Write DIN ICC
L H H Output disable Hi-Z
Remark ✕ : Don't care
7 1
1
8
A7
A9
A16
Address
buffer Row
decoder
Memory cell array
1 048 576 bits
(512× 256 8)
Input data
controller Sense/Switch
Column decoder
Address buffer
A0 - A6 A8
I/O1
I/O8
CS
OE
VCC
GND
WE
9
8
Output data
controller
×
4
µ
PD431008
Note –3.0 V (MIN.) (Pulse width: 10 ns)
Note –3.0 V (MIN.) (Pulse width: 10 ns)
Operating supply current ICC mA
CS = VIL,
II/O = 0 mA
Standby supply current ISB1 10
Remark VIN: Input voltage
Remark 1. VIN: Input voltage
2. These parameters are periodically sampled and not 100 % tested.
Output leakage current ILO –2 +2
µ
A
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage VCC –
0.5Note to +7.0 V
Input/Output voltage VT–
0.5 Note to VCC +0.5 V
Operating temperature Topt 0 to +70 °C
Storage temperature Tstg –
55 to +125 °C
Recommended Operating Conditions
Parameter Symbol MIN. TYP. MAX. Unit
Supply voltage VCC 4.5 5.0 5.5 V
High level input voltage VIH 2.2 VCC +0.5 V
Low level input voltage VIL –
0.5Note +0.8 V
Ambient temperature Ta0 +70 °C
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input leakage current ILI VIN = 0 V to VCC –2 +2
µ
A
VI/O = 0 V to VCC, CS = VIH or OE = VIH or
WE = VIL
Cycle time: 15 ns 160
Cycle time: 17 ns 150
Cycle time: 20 ns 140
Cycle time: 50 ns 120
ISB CS = VIH, VIN = VIH or VIL 30
VCC – 0.2 V CS, mA
VIN 0.2 V or VCC – 0.2 V VIN
High level output voltage VOH IOH = –4.0 mA 2.4 V
Low level output voltage VOL IOL = 8 mA 0.4 V
Capacitance (Ta = +25 °C, f = 1 MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input/Output capacitance CI/O VI/O = 0 V 8 pF
<
=
<
=<
=
5
µ
PD431008
AC Characteristics (Recommended operating conditions unless otherwise noted)
AC Test Conditions
Input waveform (Rise/fall time 3 ns)
Output waveform
Output load
AC Characteristics directed with the note should be measured with the output load shown in
Fig. 1 or Fig. 2.
Fig. 1 Fig. 2
(For tAA, tACS, tOE, tOH) (For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
Remark CL includes capacitances of the probe and jig, and stray capacitances.
<
=
+5 V
I/O (Output)
480 Ω
30 pF
CL
255 Ω
+5 V
I/O (Output)
480 Ω
5 pF
CL
255 Ω
1.5 V 1.5 V
Test points
3.0 V
GND
1.5 V 1.5 V
Test points
6
µ
PD431008
Read Cycle
µ
PD431008LE-15
µ
PD431008LE-17
µ
PD431008LE-20
Parameter Symbol Unit Condition
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 15 17 20 ns
Address access time tAA 15 17 20 ns
CS access time tACS 15 17 20 ns
OE access time tOE 8910ns
Output hold from address change tOH 555ns
CS to output in low-Z tCLZ 555ns
OE to output in low-Z tOLZ 111ns
CS to output in high-Z tCHZ 777ns
OE to output in high-Z tOHZ 777ns
Note 1. See the output load shown in Fig. 1.
2. See the output load shown in Fig. 2.
Read Cycle Timing Chart 1 (Address Access)
Remark 1. In read cycle, WE should be fixed to high level.
2. CS = OE = VIL
Note 1.
Note 2.
tOH
tRC
tAA
A0 - A16 (Input)
I/O (Output) Previous Data Out Data Out
7
µ
PD431008
Read Cycle Timing Chart 2 (CS Access)
Caution Address valid prior to or coincident with CS low level input.
Remark In read cycle, WE should be fixed to high level.
A0 - A16 (Input)
t RC
t AA
t OLZ
CS (Input)
I/O (Output) Hi - Z Data Out
t OHZ
Hi - Z
t ACS
OE (Input)
t OE
t CLZ t CHZ
8
µ
PD431008
Write Cycle
µ
PD431008LE-15
µ
PD431008LE-17
µ
PD431008LE-20
Parameter Symbol Unit Condition
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 15 17 20 ns
CS to end of write tCW 10 11 12 ns
Address valid to end of write tAW 91112ns
Write pulse width tWP 91010ns
Data valid to end of write tDW 8910ns
Data hold time tDH 000ns
Address setup time tAS 000ns
Write recovery time tWR 000ns
WE to output in high-Z tWHZ 777ns
Note
Output active from end of write tOW 333ns
Note See the output load shown in Fig. 2.
Write Cycle Timing Chart 1 (WE Controlled)
tWC
tAS tWP
tAW tWR
tDW tDH
Data In
Hi - Z
A0 - A16 (Input)
CS (Input)
WE (Input)
I/O (Input)
I/O (Output)
tCW
tACS
tCLZ
tOH
tAA
tWHZ tOW
Caution CS or WE should be fixed to high level during address transition.
Remark 1. Write operation is done during the overlap time of a low level CS and a low level WE.
2. During tWHZ, I/O pins are in the output state, therefore the input signals of opposite phase to
the output must not be applied.
3. When WE is at low level, the I/O pins are always Hi-Z. When WE is at high level, read operation
is executed. Therefore OE should be at high level to make the I/O pins Hi-Z.
9
µ
PD431008
Write Cycle Timing Chart 2 (CS Controlled)
Caution CS or WE should be fixed to high level during address transition.
Remark Write operation is done during the overlap time of a low level CS and a low level WE.
tWC
tAS tCW
tAW
tWP tWR
tDW tDH
Data In
Hi - Z
A0 - A16 (Input)
CS (Input)
WE (Input)
I/O (Input)
I/O (Output)
10
µ
PD431008
Package Drawing
M
N
K
M
I H
Q
17
16
32
1
F
J
G
E
T
P
U
P32LE-400A
ITEM MILLIMETERS INCHES
B
C
D
E
F
G
H
I
J
K
21.06±0.2
11.18±0.2
1.005±0.1
0.74
3.5±0.2
2.545±0.2
0.8 MIN.
10.16
0.829±0.008
0.440±0.008
0.029
0.138±0.008
0.031 MIN.
0.102
0.400
NOTE
P
Q 0.1
9.4±0.20
0.12
0.40±0.10
1.27 (T.P.)
2.6
0.040+0.004
–0.005
0.050 (T.P.)
0.100±0.008
0.370±0.008
0.004
0.005
0.016
Each lead centerline is located within 0.12 mm
(0.005 inch) of its true position (T.P.) at maxi–
mum material condition.
+0.004
–0.005
M
N
T
U 0.20
R 0.85 R 0.033
0.008
+0.10
–0.05 +0.004
–0.002
32 PIN PLASTIC SOJ (400 mil)
C
D
B
11
µ
PD431008
RECOMMENDED SOLDERING CONDITIONS
Please consult with our sales offices for soldering conditions of the
µ
PD431008.
TYPE OF SURFACE MOUNT DEVICE
µ
PD431008LE: 32-pin plastic SOJ (400 mil)
12
µ
PD431008
[MEMO]
13
µ
PD431008
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.
µ
PD431008
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard:Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
[MEMO]
