ADM11753ARMZR7 - ANALOG DEVICES

16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP

Data Sheet

AD7980

Rev. F Document Feedback

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rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

16-bit resolution with no missing codes

Throughput: 1 MSPS

Low power dissipation

4 mW at 1 MSPS (VDD only)

7 mW at 1 MSPS (total)

70 µW at 10 kSPS

INL: ±0.6 LSB typical, ±1.25 LSB maximum

SINAD: 91.25 dB at 10 kHz

THD: −110 dB at 10 kHz

Pseudo differential analog input range

0 V to VREF with VREF between 2.5 V to 5 V

No pipeline delay

Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V

logic interface

Proprietary serial interface

SPI/QSPI/MICROWIRE™/DSP compatible

Daisy-chain multiple ADCs and busy indicator

10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP,

same space as SOT-23

Wide operating temperature range: −40°C to +125°C

APPLICATIONS

Battery-powered equipment

Communications

Automatic test equipment (ATE)

Data acquisitions

Medical instruments

TYPICAL APPLICATION CIRCUIT

Figure 1.

GENERAL DESCRIPTION

The AD79801 is a 16-bit, successive approximation, analog-to-

digital converter (ADC) that operates from a single power supply,

VDD. It contains a low power, high speed, 16-bit sampling ADC

and a versatile serial interface port. On the CNV rising edge, it

samples an analog input, IN+, between 0 V to REF with respect

to a ground sense, IN−. The reference voltage, REF, is applied

externally and can be set independent of the supply voltage,

VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single,

3-wire bus and provides an optional busy indicator. It is compatible

with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.

The AD7980 is housed in a 10-lead MSOP or a 10-lead LFCSP

with operation specified from −40°C to +125°C.

1 Protected by U.S. Patent 6,703,961.

Table 1. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs and Integrated SAR ADC µModules

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS

µModule Data

Acquisition System

20-Bit AD40201

18-Bit AD7989-11 AD76911 AD40111 AD40031

AD76901 AD40071

AD7989-51 AD79821

AD79841

16-Bit AD7680 AD76851 AD76861 AD40011 ADAQ7980

AD7683 AD76871 AD76881 AD40051 ADAQ7988

AD7684 AD7694 AD76931 AD40001

AD7988-11 AD7988-51 AD40041

AD79161 AD79801

AD40081 AD79831

14-Bit AD7940 AD79421 AD79461

1 Pin for pin compatible.

06392-001

AD7980

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO 5.0V

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

2.5V TO 5V 2.5V

0 TO VREF

AD7980 Data Sheet

Rev. F | Page 2 of 26

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Circuit Information .................................................................... 14

Converter Operation .................................................................. 14

Typical Application Circuit with Multiple Supplies ............... 15

Analog Input ............................................................................... 16

Driver Amplifier Choice ........................................................... 16

Voltage Reference Input ............................................................ 17

Power Supply ............................................................................... 17

Digital Interface .......................................................................... 17

3-Wire CS Mode Without Busy Indicator .............................. 18

3-Wire CS Mode with Busy Indicator ..................................... 19

4-Wire CS Mode Without Busy Indicator .............................. 20

4-Wire CS Mode with Busy Indicator ..................................... 21

Chain Mode Without Busy Indicator ...................................... 22

Chain Mode with Busy Indicator ............................................. 23

Applications Information .............................................................. 24

Layout .......................................................................................... 24

Evaluating the Performance of the AD7980 .............................. 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 26

REVISION HISTORY

10/2017—Rev. E to Rev. F

Changes to Table 1 ............................................................................ 1

Changes to Figure 5 .......................................................................... 8

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

7/2016—Rev. D to Rev. E

Changed VIO = 2.3 V to 5.5 V to VIO = 1.71 V to

5.5 V................................................................................. Throughout

Change to Features Section ............................................................. 1

Changes to Conversion Rate Parameter, Table 2 .......................... 3

Changes to VIO Parameter, Table 3 ............................................... 4

Deleted VIO Range Parameter, Table 3 ......................................... 4

Added Table 5; Renumbered Sequentially .................................... 6

Changes to Table 7 ............................................................................ 8

Changes to Table 9 .......................................................................... 16

Changes to Voltage Reference Input Section .............................. 17

Changes to Figure 32 ...................................................................... 18

Changes to Figure 34 ...................................................................... 19

Changes to Figure 36 ...................................................................... 20

Changes to Figure 38 ...................................................................... 21

Changes to Figure 40 ...................................................................... 22

Changes to Figure 42 ...................................................................... 23

7/2014—Rev. C to Rev. D

Changed QFN (LFCSP) to LFCSP .............................. Throughout

Changes to Features Section and Table 1 ...................................... 1

Added Patent Note, Note 1 .............................................................. 1

Changes to AC Accuracy Parameter, Table 2 ................................ 3

Change to Standby Current Parameter, Table 3 ............................ 4

Changes to Figure 25...................................................................... 13

Changes to Table 8 .......................................................................... 15

Changes to Power Supply Section ................................................ 16

8/2013—Rev. B to Rev. C

Change to Features Section .............................................................. 1

Changes to Table 3 ............................................................................. 4

Change to Figure 5 ............................................................................ 7

Added EPAD Row, Table 6 ............................................................... 7

Changes to Evaluating the Performance of the

AD7980 Section .............................................................................. 23

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 25

6/2009—Rev. A to Rev. B

Changes to Table 5 ............................................................................. 6

Changes to Figure 25...................................................................... 13

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 25

9/2008—Rev. 0 to Rev. A

Deleted QFN Endnote .................................................. Throughout

Changes to Ordering Guide .......................................................... 24

8/2007—Revision 0: Initial Version

Data Sheet AD7980

Rev. F | Page 3 of 26

SPECIFICATIONS

VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.

Table 2.

A Grade B Grade

Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

RESOLUTION 16 16 Bits

ANALOG INPUT

Voltage Range IN+ − IN− 0 VREF 0 VREF V

Absolute Input Voltage IN+ −0.1 VREF + 0.1 −0.1 VREF + 0.1 V

IN− −0.1 +0.1 −0.1 +0.1 V

Analog Input CMRR fIN = 100 kHz 60 60 dB

Leakage Current at 25°C Acquisition phase 1 1 nA

Input Impedance See the

Analog Input section

See the

Analog Input section

ACCURACY

No Missing Codes 16 16 Bits

Differential Linearity Error REF = 5 V −1.0 ±0.5 +2.0 −0.9 ±0.4 +0.9 LSB1

REF = 2.5 V ±0.7 ±0.55 LSB1

Integral Linearity Error REF = 5 V −2.5 ±1.5 +2.5 −1.25 ±0.6 +1.25 LSB1

REF = 2.5 V ±1.65 ±0.65 LSB1

Transition Noise REF = 5 V 0.75 0.6 LSB1

REF = 2.5 V 1.2 1.0 LSB1

Gain Error, TMIN to TMAX 2 ±2 ±2 LSB1

Gain Error Temperature Drift ±0.35 ±0.35 ppm/°C

Zero Error, TMIN to TMAX2 −1.0 ±0.08 +1.0 −0.5 ±0.08 +0.5 mV

Zero Temperature Drift 0.54 0.54 ppm/°C

Power Supply Sensitivity

VDD = 2.5 V

±0.1

LSB

THROUGHPUT

Conversion Rate VIO ≥ 2.3 V up to 85°C, VIO ≥

3.3 V above 85°C up to 125°C

0 1 0 1 MSPS

VIO ≥ 1.71 V, VIO ≤ 3.3 V up

to 125°C

833 833 kSPS

Transient Response Full-scale step 290 290 ns

AC ACCURACY

Dynamic Range VREF = 5 V 91 92 dB3

VREF = 2.5 V 86 87 dB3

Oversampled Dynamic Range fO = 10 kSPS 110 111 dB3

Signal-to-Noise Ratio, SNR fIN = 10 kHz, VREF = 5 V 90.5 90 91.5 dB3

fIN = 10 kHz, VREF = 2.5 V 86.0 87.0 dB3

Spurious-Free Dynamic Range, SFDR fIN = 10 kHz −103.5 −110 dB3

Total Harmonic Distortion, THD fIN = 10 kHz −101 −114 dB3

Signal-to-Noise-and-Distortion Ratio,

SINAD

fIN = 10 kHz, VREF = 5 V 90 91 dB3

fIN = 10 kHz, VREF = 2.5 V 85.5 86.5 dB3

1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.

2 See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.

3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

AD7980 Data Sheet

Rev. F | Page 4 of 26

VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

REFERENCE

Voltage Range 2.4 5.1 V

Load Current 1 MSPS, REF = 5 V 330 µA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 10 MHz

Aperture Delay VDD = 2.5 V 2.0 ns

DIGITAL INPUTS

Logic Levels

VIL VIO > 3V –0.3 0.3 × VIO V

VIH VIO > 3V 0.7 × VIO VIO + 0.3 V

VIL VIO ≤ 3V –0.3 0.1 × VIO

VIH VIO ≤ 3V 0.9 × VIO VIO + 0.3 µA

IIL −1 +1 µA

IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16 bits straight binary

Pipeline Delay Conversion results available immediately

after completed conversion

VOL ISINK = 500 µA 0.4 V

VOH ISOURCE = −500 µA VIO − 0.3 V

POWER SUPPLIES

VDD 2.375 2.5 2.625 V

VIO 1.71 5.5 V

Standby Current1, 2 VDD and VIO = 2.5 V, 25°C 0.35 μA

Power Dissipation VDD = 2.625 V, VREF = 5 V, VIO = 3 V

Total

10 kSPS throughput

µW

1 MSPS throughput, B grade 7.0 9.0 mW

1 MSPS throughput, A grade 7.0 10 mW

VDD Only 4 mW

REF Only 1.7 mW

VIO Only 1.3 mW

Energy per Conversion 7.0 nJ/sample

TEMPERATURE RANGE3

Specified Performance TMIN to TMAX −40 +125 °C

1 With all digital inputs forced to VIO or GND as required.

2 During the acquisition phase.

3 Contact sales for extended temperature range.

Data Sheet AD7980

Rev. F | Page 5 of 26

TIMING SPECIFICATIONS

−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available tCONV 500 710 ns

Acquisition Time tACQ 290 ns

Time Between Conversions tCYC 1000 ns

CNV Pulse Width (CS Mode) tCNVH 10 ns

SCK Period (CS Mode) tSCK ns

VIO Above 4.5 V

10.5

VIO Above 3 V 12 ns

VIO Above 2.7 V 13 ns

VIO Above 2.3 V 15 ns

SCK Period (Chain Mode) tSCK ns

VIO Above 4.5 V 11.5 ns

VIO Above 3 V 13 ns

VIO Above 2.7 V 14 ns

VIO Above 2.3 V 16 ns

SCK Low Time tSCKL 4.5 ns

SCK High Time tSCKH 4.5 ns

SCK Falling Edge to Data Remains Valid

HSDO

SCK Falling Edge to Data Valid Delay tDSDO

VIO Above 4.5 V 9.5 ns

VIO Above 3 V 11 ns

VIO Above 2.7 V 12 ns

VIO Above 2.3 V 14 ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN

VIO Above 3 V 10 ns

VIO Above 2.3 V 15 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns

SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns

SDI Valid Hold Time from CNV Rising Edge (

Mode)

HSDICNV

SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns

SDI High to SDO High (Chain Mode with Busy Indicator)

DSDOSDI

AD7980 Data Sheet

Rev. F | Page 6 of 26

−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 3.3 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.

Table 5.

Parameter Symbol Min Typ Max Unit

Throughput Rate 833 kSPS

Conversion Time: CNV Rising Edge to Data Available tCONV 500 800 ns

Acquisition Time tACQ 290 ns

Time Between Conversions

CYC

1.2

μs

CNV Pulse Width (CS Mode) tCNVH 10 ns

SCK Period (CS Mode) tSCK 22 ns

SCK Period (Chain Mode) tSCK 23 ns

SCK Low Time tSCKL 6 ns

SCK High Time tSCKH 6 ns

SCK Falling Edge to Data Remains Valid tHSDO 3 ns

SCK Falling Edge to Data Valid Delay tDSDO 14 21 ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN 18 40 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns

SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns

SDI Valid Hold Time from CNV Rising Edge (

Mode)

HSDICNV

SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns

SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 22 ns

Timing Diagrams

Figure 2. Load Circuit for Digital Interface Timing

Figure 3. Voltage Levels for Timing

500µA I

1.4V

TO SDO

20pF

06513-002

06392-003

X% VIO

Y% VIO

IH2

IL2

IH2

DELAY

FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.

MINIMUM V

AND MAXIMUM V

USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Data Sheet AD7980

Rev. F | Page 7 of 26

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

IN+,

IN−

to GND

−0.3 V to V

REF

+ 0.3 V or ±130 mA

Supply Voltage

REF, VIO to GND −0.3 V to +6 V

VDD to GND −0.3 V to +3 V

VDD to VIO +3 V to −6 V

Digital Inputs to GND −0.3 V to VIO + 0.3 V

Digital Outputs to GND −0.3 V to VIO + 0.3 V

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Thermal Impedance

(10-Lead MSOP)

θJA 200°C/W

θJC 44°C/W

Lead Temperature

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1 See the Analog Input section.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

AD7980 Data Sheet

Rev. F | Page 8 of 26

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. 10-Lead MSOP Pin Configuration

Figure 5. 10-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Type 1 Description MSOP LFCSP

1 1 REF AI Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND

pin. This pin should be decoupled closely to the pin with a 10 µF capacitor.

2 2 VDD P Power Supply.

3 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, for example, the difference

between IN+ and IN−, is 0 V to VREF.

4 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote

sense ground.

5 5 GND P Power Supply Ground.

6 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the

conversions and selects the interface mode of the device, chain, or CS mode. In CS mode,

it enables the SDO pin when low. In chain mode, the data should be read when CNV is high.

SDO

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

SCK

Serial Data Clock Input. When the device is selected, the conversion result is shifted out

by this clock.

9 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of

the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In

this mode, SDI is used as a data input to daisy-chain the conversion results of two or

more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a

delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In

this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV

is low when the conversion is complete, the busy indicator feature is enabled.

10 10 VIO P Input/Outp

ut Interface Digital Power. Nominally at the same supply as the host interface

(1.8 V, 2.5 V, 3 V, or 5 V).

Not

applicable

EPAD

Not

applicable

Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet

the electrical performances.

1AI = analog input, DI = digital input, DO = digital output, and P = power.

06392-004

REF 1

VDD 2

IN+ 3

IN– 4

VIO

SDI

SCK

SDO

GND 5CNV

AD7980

TOP VIEW

(Not to Scale)

1REF

2VDD

3IN+

4IN–

5GND

10 VIO

9SDI

8SCK

7SDO

6CNV

06392-005

AD7980

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

THIS CONNECTION IS NOT REQUIREDTO

MEET THE ELECTRICAL PERFORMANCES.

Data Sheet AD7980

Rev. F | Page 9 of 26

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line

drawn from negative full scale through positive full scale. The

point used as negative full scale occurs ½ LSB before the first

code transition. Positive full scale is defined as a level 1½ LSB

beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 26).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the

maximum deviation from this ideal value. It is often specified in

terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level ½ LSB above analog

ground (38.1 µV for the 0 V to 5 V range). The offset error is

the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 … 10 to 111 … 11) should occur

for an analog voltage 1½ LSB below the nominal full scale

(4.999886 V for the 0 V to 5 V range). The gain error is the

deviation of the actual level of the last transition from the ideal

level after the offset is adjusted out.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms

amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

input. It is expressed in bits and related to SINAD by the

following formula:

ENOB = (SINADdB − 1.76)/6.02

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which

it is impossible to distinctly resolve individual codes. It is

calculated as

Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)

and is expressed in bits.

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log2(2N/RMS Input Noise)

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic

components to the rms value of a full-scale input signal and is

expressed in dB.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in dB. It is measured

with a signal at −60 dBFS to include all noise sources and DNL

artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in dB.

Signal-to-Noise-and-Distortion Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc. The value for

SINAD is expressed in dB.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It

is the time between the rising edge of the CNV input and when

the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately

acquire its input after a full-scale step function is applied.

AD7980 Data Sheet

Rev. F | Page 10 of 26

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted.

Figure 6. Integral Nonlinearity vs. Code, REF = 5 V

Figure 7. Integral Nonlinearity vs. Code, REF = 2.5 V

Figure 8. FFT Plot, REF = 5 V

Figure 9. Differential Nonlinearity vs. Code, REF = 5 V

Figure 10. Differential Nonlinearity vs. Code, REF = 2.5 V

Figure 11. FFT Plot, REF = 2.5 V

1.25

–1.25

0 65536

06392-036

CODE

INL (LSB)

1.00

0.75

0.50

0.25

–0.25

–0.75

–0.50

–1.00

16384 32768 49152

POSITIVE INL: +0.33 LSB

NEGATIVE INL: –0.39 LSB

1.25

1.00

–1.25

–1.00

0 65536

06392-060

CODE

INL (LSB)

0.75

0.50

0.25

–0.25

–0.75

–0.50

16384 32768 49152

POSITIVE INL: +0.47 LSB

NEGATIVE INL: –0.26 LSB

–180

0500

06392-038

FREQUENCY (kHz)

AMPLITUDE (dB of FULL SCALE)

–20

–40

–60

–80

–100

–120

–140

–160

100 200 300 400

= 1 MSPS

= 10kHz

SNR = 91.27dB

THD = –114.63dB

SFDR = 110.10dB

SINAD = 91.25dB

1.00

–1.00

0 65536

06392-039

CODE

DNL (LSB)

0.75

0.50

0.25

–0.25

–0.75

–0.50

16384 32768 49152

POSITIVE INL: +0.18 LSB

NEGATIVE INL: –0.21 LSB

1.00

–1.00

0 65536

06392-061

CODE

DNL (LSB)

0.75

0.50

0.25

–0.25

–0.75

–0.50

16384 32768 49152

POSITIVE INL: +0.25 LSB

NEGATIVE INL: –0.22 LSB

–180

0500

06392-058

FREQUENCY (kHz)

AMPLITUDE (dB of FULL SCALE)

–20

–40

–60

–80

–100

–120

–140

–160

100 200 300 400

= 1 MSPS

= 10kHz

SNR = 86.8dB

THD = –111.4dB

SFDR = 105.9dB

SINAD = 86.8dB

Data Sheet AD7980

Rev. F | Page 11 of 26

Figure 12. Histogram of a DC Input at the Code Center, REF = 5 V

Figure 13. Histogram of a DC Input at the Code Transition, REF = 5 V

Figure 14. SNR, SINAD, and ENOB vs. Reference Voltage

Figure 15. Histogram of a DC Input at the Code Center, REF = 2.5 V

Figure 16. SNR vs. Input Level

Figure 17. THD, SFDR vs. Reference Voltage

180k

800C 800D 800E 800F80098008 800B800A8003 80058004 80078006

2000

33829

027

01201

06392-042

CODE IN HEX

COUNTS

140k

160k

100k

120k

60k

20k

80k

40k 38751

168591

52710

70k

7FFF 800880018000 80038002 80058004 80078006

150

59691

5428

59404

06392-043

CODE IN HEX

COUNTS

60k

50k

30k

10k

40k

20k

6295

100

2.25 5.25

06392-044

REFERENCE VOLTAGE (V)

SNR, SINAD (dB)

ENOB (BITS)

2.75 3.25 3.75 4.25 4.75

SNR

SINAD

ENOB

60k

7FFA 80067FFC7FFB 7FFE 7FFF7FFD 80018000 8003 8004 80058002

00 00

539

16 14

502

06392-059

CODE IN HEX

COUNTS

50k

30k

10k

40k

20k

32417

52212

31340

7225 6807

–10 0

06392-046

INPUT LEVEL (dB OF FULL SCALE)

SNR (dB)

–9 –8 –7 –6 –5 –4 –3 –2 –1

–

–125

–110

–115

–105

–100

–120

115

100

105

110

2.25 5.25

06392-047

REFERENCE VOLTAGE (V)

THD (dB)

SFDR (dB)

2.75 3.25 3.75 4.25 4.75

THD

SFDR

AD7980 Data Sheet

Rev. F | Page 12 of 26

Figure 18. SINAD vs. Frequency

Figure 19. SNR vs. Temperature

Figure 20. Operating Currents vs. Supply

Figure 21. THD vs. Frequency

Figure 22. THD vs. Temperature

Figure 23. Operating Currents vs. Temperature

100

10 1000

06392-063

FREQUENCY (kHz)

SINAD (dB)

100

–55 125

06392-049

TEMPERATURE (°C)

SNR (dB)

–35 –15 5 25 65 8545 105

06392-050

1.4

1.2

1.0

0.8

0.6

0.4

0.2

CURRENT (mA)

2.425 2.475

VDD VOLTAGE (V)

2.375 2.525 2.575 2.625

VDD

REF

VIO

–

–125

10 1000

06392-064

FREQUENCY (kHz)

THD (dB)

100

–90

–95

–100

–105

–110

–115

–120

06392-052

–

110

–120

THD (dB)

–55 –35 –15 5 25

TEMPERATURE (°C)

45 65 85 105 125

–112

–114

–116

–118

06392-053

1.4

1.2

1.0

0.8

0.6

0.4

0.2

CURRENT (mA)

–55 –35 –15 5 25

TEMPERATURE (°C)

45 65 85 105 125

VDD

REF

VIO

Data Sheet AD7980

Rev. F | Page 13 of 26

Figure 24. Power-Down Currents vs. Temperature

06392-054

CURRENT (µA)

–55 –35 –15 525

TEMPERATURE (°C)

45 65 85 105 125

VDD

+ I

VIO

AD7980 Data Sheet

Rev. F | Page 14 of 26

THEORY OF OPERATION

Figure 25. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7980 is a fast, low power, single-supply, precise 16-bit

ADC that uses a successive approximation architecture.

The AD7980 is capable of converting 1,000,000 samples per

second (1 MSPS) and powers down between conversions. When

operating at 10 kSPS, for example, it consumes 70 µW typically,

ideal for battery-powered applications.

The AD7980 provides the user with on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple multiplexed channel applications.

The AD7980 can be interfaced to any 1.8 V to 5 V digital logic

family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP

that combines space savings and allows flexible configurations.

It is pin-for-pin compatible with the 18-bit AD7982.

CONVERTER OPERATION

The AD7980 is a successive approximation ADC based on a

charge redistribution DAC. Figure 25 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via SW+ and

SW−. All independent switches are connected to the analog inputs.

Therefore, the capacitor arrays are used as sampling capacitors

and acquire the analog signal on the IN+ and IN− inputs. When

the acquisition phase is completed and the CNV input goes high,

a conversion phase is initiated. When the conversion phase begins,

SW+ and SW− are opened first. The two capacitor arrays are then

disconnected from the inputs and connected to the GND input.

Therefore, the differential voltage between the inputs IN+ and

IN− captured at the end of the acquisition phase are applied to

the comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between GND and REF, the comparator input varies by binary

weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The control

logic toggles these switches, starting with the MSB, to bring the

comparator back into a balanced condition. After the completion

of this process, the device returns to the acquisition phase and the

control logic generates the ADC output code and a busy signal

indicator.

Because the AD7980 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

06392-011

COMP

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

CONTROL

LOGIC

SW+LSB

IN+

REF

GND

IN–

MSB

4C 2C

16,384C

32,768C

CC4C 2C16,384C32,768C

Data Sheet AD7980

Rev. F | Page 15 of 26

Transfer Functions

The ideal transfer characteristic for the AD7980 is shown in

Figure 26 and Table 8.

Figure 26. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Analog Input

Description VREF = 5 V Digital Output Code (Hex)

FSR − 1 LSB 4.999924 V FFFF1

Midscale + 1 LSB 2.500076 V 8001

Midscale 2.5 V 8000

Midscale − 1 LSB 2.499924 V 7FFF

−FSR + 1 LSB

76.3 µV

0001

−FSR 0 V 00002

1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).

2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).

TYPICAL APPLICATION CIRCUIT WITH MULTIPLE

SUPPLIES

Figure 27 shows an example of a typical application circuit for

the AD7980 when multiple supplies are available.

Figure 27. Typical Application Circuit with Multiple Supplies

000 ... 000

000 ... 001

000 ... 010

111 ... 101

111 ... 110

111 ... 111

–FSR –FSR + 1LSB

–FSR + 0.5LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

06392-012

ANALOG INPUT

ADC CODE (STRAIGHT BINARY)

06392-013

AD7980

3- OR 4-WIRE INTERFACE

2.5V

V+

20Ω

V+

V–

0TO VREF

1.8V TO 5V

100nF10µF

2.7nF

100nF

REF

IN+

IN–

VDD VIO SDI

CNV

SCK

SDO

GND

REF

SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

SEE THE DRIVER AMPLIFIER CHOICE SECTION.

OPTIONAL FILTER. SEE THE ANALOG INPUT SECTION.

SEE THE DIGITAL INTERFACE FOR THE MOST CONVENIENT INTERFACE MODE.

AD7980 Data Sheet

Rev. F | Page 16 of 26

ANALOG INPUT

Figure 28 shows an equivalent circuit of the input structure of

the AD7980.

The two diodes, D1 and D2, provide ESD protection for the

analog inputs, IN+ and IN−. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more

than 0.3 V, because this causes these diodes to become forward-

biased and start conducting current. These diodes can handle a

forward-biased current of 130 mA maximum. For instance,

these conditions could eventually occur when the supplies of

the input buffer (U1) are different from VDD. In such a case

(for example, an input buffer with a short circuit), the current

limitation can be used to protect the device.

Figure 28. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these

differential inputs, signals common to both inputs are rejected.

During the acquisition phase, the impedance of the analog

inputs (IN+ and IN−) can be modeled as a parallel combination of

capacitor, CPIN, and the network formed by the series connection of

RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

400 Ω and is a lumped component made up of some serial

resistors and the on resistance of the switches. CIN is typically

30 pF and is mainly the ADC sampling capacitor. During the

conversion phase, where the switches are opened, the input

impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass

filter that reduces undesirable aliasing effects and limits the noise.

When the source impedance of the driving circuit is low, the

AD7980 can be driven directly. Large source impedances

significantly affect the ac performance, especially THD. The dc

performances are less sensitive to the input impedance. The

maximum source impedance depends on the amount of THD

that can be tolerated. The THD degrades as a function of the

source impedance and the maximum input frequency.

DRIVER AMPLIFIER CHOICE

Although the AD7980 is easy to drive, the driver amplifier

needs to meet the following requirements:

 The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition

noise performance of the AD7980. The noise coming from

the driver is filtered by the 1-pole, low-pass filter of the

AD7980 analog input circuit made by RIN and CIN or by the

external filter, if one is used. Because the typical noise of the

AD7980 is 47.3 μV rms, the SNR degradation due to the

amplifier is



















3dB

2)(

47.3

log20

LOSS

Nef

SNR

where:

f–3dB is the input bandwidth in MHz of the AD7980

(10 MHz) or the cutoff frequency of the input filter, if

one is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

eN is the equivalent input noise voltage of the op amp,

in nV/√Hz.

 For ac applications, the driver should have a THD

performance commensurate with the AD7980.

 For multichannel multiplexed applications, the driver

amplifier and the AD7980 analog input circuit must settle

for a full-scale step onto the capacitor array at a 16-bit level

(0.0015%, 15 ppm). In the amplifier data sheet, settling at

0.1% to 0.01% is more commonly specified. This can differ

significantly from the settling time at a 16-bit level and

should be verified prior to driver selection.

Table 9. Recommended Driver Amplifiers1

Amplifier Typical Application

ADA4805-1 Low noise, small size, and low power

ADA4807-1 Very low noise and high frequency

ADA4627-1 Precision, low noise, and low input bias current

ADA4522-1 Precision, zero drift, and EMI enhanced

ADA4500-2 Precision, rail-to-rail input/output, and zero input

crossover distortion

1 For the latest recommended drivers, see the product recommendations

listed on the product webpage.

06392-014

REF

IN+

R IN–

GND

D2C

Data Sheet AD7980

Rev. F | Page 17 of 26

VOLTAGE REFERENCE INPUT

The AD7980 voltage reference input, REF, has a dynamic input

impedance and should therefore be driven by a low impedance

source with efficient decoupling between the REF and GND

pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for example,

a reference buffer using the AD8031 or the ADA4805-1, a ceramic

chip capacitor is appropriate for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR435 reference.

If desired, a reference-decoupling capacitor value as small as

2.2 μF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REF

and GND pins.

POWER SUPPLY

The AD7980 uses two power supply pins: a core supply, VDD, and

a digital input/output interface supply, VIO. VIO allows direct

interface with any logic between 1.8 V and 5.0 V. To reduce the

number of supplies needed, VIO and VDD can be tied together.

The AD7980 is independent of power supply sequencing between

VIO and VDD. Additionally, it is very insensitive to power supply

variations over a wide frequency range, as shown in Figure 29.

Figure 29. PSRR vs. Frequency

The AD7980 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate. This makes the device ideal for low sampling

rate (even of a few Hz) and low battery-powered applications.

Figure 30. Operating Currents vs. Sampling Rate

DIGITAL INTERFACE

Though the AD7980 has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7980, when in CS mode, is compatible with SPI, QSPI™,

and digital hosts. This interface can use either a 3-wire or 4-wire

interface. A 3-wire interface using the CNV, SCK, and SDO signals

minimizes wiring connections useful, for instance, in isolated

applications. A 4-wire interface using the SDI, CNV, SCK, and

SDO signals allows CNV, which initiates the conversions, to be

independent of the readback timing (SDI). This is useful in low

jitter sampling or simultaneous sampling applications.

The AD7980, when in chain mode, provides a daisy-chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The mode in which the device operates depends on the SDI level

when the CNV rising edge occurs. The CS mode is selected if

SDI is high, and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, the chain mode is selected.

In either mode, the AD7980 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a busy signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a busy indicator,

the user must time out the maximum conversion time prior to

readback.

The busy indicator feature is enabled in the CS mode if CNV or

SDI is low when the ADC conversion ends (see Figure 34 and

Figure 38). The busy indicator feature is enabled in the chain

mode if SCK is high during the CNV rising edge (see Figure 42).

1 1000

06392-062

FREQUENCY (kHz)

PSRR (dB)

10 100

06392-055

10.000

1.000

0.100

0.010

0.001

OPERATING CURRENTS (mA)

100000

SAMPLING RATE (SPS)

10000 1000000

VDD

VIO

REF

AD7980 Data Sheet

Rev. F | Page 18 of 26

3-WIRE CS MODE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7980 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 31, and the corresponding timing is given in

Figure 32.

With SDI tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance. Once a conversion is initiated, it continues until

completion irrespective of the state of CNV. This can be useful,

for instance, to bring CNV low to select other SPI devices, such

as analog multiplexers; however, CNV must be returned high

before the minimum conversion time elapses and then held

high for the maximum conversion time to avoid the generation

of the busy signal indicator. When the conversion is complete,

the AD7980 enters the acquisition phase and powers down.

When CNV goes low, the MSB is output onto SDO. The

remaining data bits are then clocked by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate provided that it has

an acceptable hold time. After the 16th SCK falling edge or

when CNV goes high, whichever is earlier, SDO returns to high

impedance.

Figure 31. 3-Wire CS Mode Without Busy Indicator

Connection Diagram (SDI High)

Figure 32. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)

06392-015

AD7980

SDOSDI DATA IN

DIGITAL HOST

CONVERT

CLK

VIO

CNV

SCK

06392-016

SDI = 1

CNVH

CONV

CYC

CNV

QUISITION AQUISITION

ACQ

SCK

SCKL

CONVERSION

SCK

SDO D15 D14 D13 D1 D0

HSDO

123 14 1516

DSDO

DIS

SCKH

Data Sheet AD7980

Rev. F | Page 19 of 26

3-WIRE CS MODE WITH BUSY INDICATOR

This mode is usually used when a single AD7980 is connected

to an SPI-compatible digital host having an interrupt input.

The connection diagram is shown in Figure 33, and the

corresponding timing is given in Figure 34.

With SDI tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance. SDO is maintained in high impedance until the

completion of the conversion irrespective of the state of CNV.

Prior to the minimum conversion time, CNV can be used to

select other SPI devices, such as analog multiplexers, but CNV

must be returned low before the minimum conversion time

elapses and then held low for the maximum conversion time to

guarantee the generation of the busy signal indicator. When the

conversion is complete, SDO goes from high impedance to low.

With a pull-up on the SDO line, this transition can be used as an

interrupt signal to initiate the data reading controlled by the

digital host. The AD7980 then enters the acquisition phase and

powers down. The data bits are clocked out, MSB first, by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

rate provided it has an acceptable hold time. After the optional

17th SCK falling edge or when CNV goes high, whichever is

earlier, SDO returns to high impedance.

If multiple AD7980 devices are selected at the same time, the

SDO output pin handles this contention without damage or

induced latch-up. Meanwhile, it is recommended to keep this

contention as short as possible to limit extra power dissipation.

Figure 33. 3-Wire CS Mode with Busy Indicator

Connection Diagram (SDI High)

Figure 34. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)

06392-017

AD7980

SDOSDI DATA IN

IRQ

DIGITAL HOST

CONVERT

CLK

VIO

47kΩ

CNV

SCK

06392-018

CONV

CNVH

CYC

AQUISITION AQUISITION

ACQ

SCK

SCKH

SCKL

CONVERSION

SCK

CNV

SDI = 1

SDO D15 D14 D1 D0

HSDO

1 2 3 15 16 17

DSDO

DIS

AD7980 Data Sheet

Rev. F | Page 20 of 26

4-WIRE CS MODE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7980 devices are

connected to an SPI-compatible digital host.

A connection diagram example using two AD7980 devices is

shown in Figure 35, and the corresponding timing is given in

Figure 36.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI can be

used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time elapses and then held high for the maximum conversion

time to avoid the generation of the busy signal indicator.

When the conversion is complete, the AD7980 enters the

acquisition phase and powers down. Each ADC result can be

read by bringing its SDI input low, which consequently outputs

the MSB onto SDO. The remaining data bits are then clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

rate provided it has an acceptable hold time. After the 16th SCK

falling edge or when SDI goes high, whichever is earlier, SDO

returns to high impedance and another AD7980 can be read.

Figure 35. 4-Wire CS Mode Without Busy Indicator Connection Diagram

Figure 36. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing

06392-019

DIGITAL HOST

CONVERT

CS2

CS1

CLK

DATA IN

AD7980

SDOSDI

CNV

SCK

AD7980

SDOSDI

CNV

SCK

06392-020

tCONV

tCYC

AQUISITION AQUISITION

tACQ

tSCK

tSCKH

tSCKL

CONVERSION

SCK

CNV

tSSDICNV

tHSDICNV

SDO

D15 D13D14 D1 D0 D15 D14 D1 D0

tHSDO

tEN

123 14 15 16 17 18 30 31 32

tDSDO tDIS

SDI(CS1)

SDI(CS2)

Data Sheet AD7980

Rev. F | Page 21 of 26

4-WIRE CS MODE WITH BUSY INDICATOR

This mode is usually used when a single AD7980 is connected

to an SPI-compatible digital host that has an interrupt input,

and it is desired to keep CNV, which is used to sample the analog

input, independent of the signal used to select the data reading.

This requirement is particularly important in applications where

low jitter on CNV is desired.

The connection diagram is shown in Figure 37, and the

corresponding timing is given in Figure 38.

With SDI high, a rising edge on CNV initiates a conversion, selects

the CS mode, and forces SDO to high impedance. In this mode,

CNV must be held high during the conversion phase and the

subsequent data readback (if SDI and CNV are low, SDO is driven

low). Prior to the minimum conversion time, SDI can be used

to select other SPI devices, such as analog multiplexers, but SDI

must be returned low before the minimum conversion time

elapses and then held low for the maximum conversion time to

guarantee the generation of the busy signal indicator. When the

conversion is complete, SDO goes from high impedance to low.

With a pull-up on the SDO line, this transition can be used as

an interrupt signal to initiate the data readback controlled by

the digital host. The AD7980 then enters the acquisition phase

and powers down. The data bits are clocked out, MSB first, by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

rate provided it has an acceptable hold time. After the optional

17th SCK falling edge or SDI going high, whichever is earlier,

the SDO returns to high impedance.

Figure 37. 4-Wire CS Mode with Busy Indicator Connection Diagram

Figure 38. 4-Wire CS Mode with Busy Indicator Serial Interface Timing

06392-021

AD7980

SDOSDI DATA IN

IRQ

DIGITAL HOST

CONVERT

CS1

CLK

VIO

47kΩ

CNV

SCK

06392-022

CONV

CYC

AQUISITION

SSDICNV

AQUISITION

ACQ

SCK

SCKH

SCKL

CONVERSION

SDI

HSDICNV

SCK

CNV

SDO

D15 D14 D1 D0

HSDO

123 15 1617

DSDO

DIS

AD7980 Data Sheet

Rev. F | Page 22 of 26

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can be used to daisy-chain multiple AD7980 devices

on a 3-wire serial interface. This feature is useful for reducing

component count and wiring connections, for example, in

isolated multi-converter applications or for systems with a

limited interfacing capacity. Data readback is analogous to

clocking a shift register.

A connection diagram example using two AD7980s is shown in

Figure 39, and the corresponding timing is given in Figure 40.

When SDI and CNV are low, SDO is driven low. With SCK low,

a rising edge on CNV initiates a conversion, selects the chain

mode, and disables the busy indicator. In this mode, CNV is

held high during the conversion phase and the subsequent data

readback. When the conversion is complete, the MSB is output

onto SDO and the AD7980 enters the acquisition phase and

powers down. The remaining data bits stored in the internal

shift register are clocked by subsequent SCK falling edges. For

each ADC, SDI feeds the input of the internal shift register and

is clocked by the SCK falling edge. Each ADC in the chain

outputs its data MSB first, and 16 × N clocks are required to

readback the N ADCs. The data is valid on both SCK edges.

Although the rising edge can be used to capture the data, a

digital host using the SCK falling edge allows a faster reading

rate and, consequently, more AD7980 devices in the chain,

provided the digital host has an acceptable hold time. The

maximum conversion rate may be reduced due to the total

readback time.

Figure 39. Chain Mode Without Busy Indicator Connection Diagram

Figure 40. Chain Mode Without Busy Indicator Serial Interface Timing

06392-023

DIGITAL HOST

CONVERT

CLK

DATA IN

AD7980

SDOSDI

CNV

SCK

AD7980

SDO

SDI

CNV

SCK

06392-024

CONV

CYC

SSDISCK

SCKL

SCK

HSDISC

ACQ

AQUISITION

SSCKCNV

AQUISITION

SCKH

CONVERSION

SDO

= SDI

HSCKCNV

SCK

CNV

SDI

= 0

SDO

15 D

14 D

15 D

14 D

13 D

1 D

0 D

15 D

14 D

1 D

HSDO

1 2 3 15 16 1714 18 30 31 32

DSDO

Data Sheet AD7980

Rev. F | Page 23 of 26

CHAIN MODE WITH BUSY INDICATOR

This mode can also be used to daisy-chain multiple AD7980

devices on a 3-wire serial interface while providing a busy

indicator. This feature is useful for reducing component count

and wiring connections, for example, in isolated multiconverter

applications or for systems with a limited interfacing capacity.

Data readback is analogous to clocking a shift register.

A connection diagram example using three AD7980 devices is

shown in Figure 41, and the corresponding timing is given in

Figure 42.

When SDI and CNV are low, SDO is driven low. With SCK

high, a rising edge on CNV initiates a conversion, selects the

chain mode, and enables the busy indicator feature. In this

mode, CNV is held high during the conversion phase and the

subsequent data readback. When all ADCs in the chain have

completed their conversions, the SDO pin of the ADC closest to

the digital host (see the AD7980 ADC labeled C in Figure 41) is

driven high. This transition on SDO can be used as a busy

indicator to trigger the data readback controlled by the digital

host. The AD7980 then enters the acquisition phase and powers

down. The data bits stored in the internal shift register are

clocked out, MSB first, by subsequent SCK falling edges. For

each ADC, SDI feeds the input of the internal shift register and

is clocked by the SCK falling edge. Each ADC in the chain

outputs its data MSB first, and 16 × N + 1 clocks are required to

readback the N ADCs. Although the rising edge can be used to

capture the data, a digital host using the SCK falling edge allows a

faster reading rate and, consequently, more AD7980 devices in

the chain, provided the digital host has an acceptable hold time.

Figure 41. Chain Mode with Busy Indicator Connection Diagram

Figure 42. Chain Mode with Busy Indicator Serial Interface Timing

06392-025

AD7980

SDOSDI DATA IN

IRQ

DIGITAL HOST

CONVERT

CLK

CNV

SCK

AD7980

SDOSDI

CNV

SCK

AD7980

SDOSDI

CNV

SCK

06392-026

tCONV

tCYC

tSSDISCK

tSCKH

tSCK

tHSDISC

tACQ

tDSDOSDI

tDSDODSI

AQUISITION

tSSCKCNV

AQUISITION

tSCKL

CONVERSION

tHSCKCNV

SCK

CNV = SDIA

SDOA = SDIB

SDOB = SDIC

SDOC

tEN

DA15 DA14 DA13

DB15 DB14 DB13

DC15 DC14 DC13

DB1 DB0 DA15 DA14 DA1 DA0

DC1 DC0 DB15 DB14 DA0DA1DB0DB1 DA14DA15

DA1 DA0

tHSDO

1 2 3 15 16 17418 19 31 32 33 34 35 47 48 49

tDSDO

tDSDOSDI

AD7980 Data Sheet

Rev. F | Page 24 of 26

APPLICATIONS INFORMATION

LAYOUT

The printed circuit board (PCB) that houses the AD7980

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. The pinout of

the AD7980, with all its analog signals on the left side and all its

digital signals on the right side, eases this task.

Avoid running digital lines under the device because these couple

noise onto the die, unless a ground plane under the AD7980 is

used as a shield. Fast switching signals, such as CNV or clocks,

should never run near analog signal paths. Crossover of digital

and analog signals should be avoided.

At least one ground plane should be used. It can be common or

split between the digital and analog section. In the latter case,

the planes should be joined underneath the AD7980 devices.

The AD7980 voltage reference input REF has a dynamic input

impedance and should be decoupled with minimal parasitic

inductances. This is done by placing the reference decoupling

ceramic capacitor close to, ideally right up against, the REF and

GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies VDD and VIO of the AD7980

should be decoupled with ceramic capacitors, typically 100 nF,

placed close to the AD7980 and connected using short and wide

traces to provide low impedance paths and reduce the effect of

glitches on the power supply lines.

An example of a layout following these rules is shown in

Figure 43 and Figure 44.

EVALUATING THE PERFORMANCE OF THE AD7980

Other recommended layouts for the AD7980 are outlined

in the documentation of the evaluation board for the AD7980

(EVAL-AD7980SDZ). The evaluation board package includes

a fully assembled and tested evaluation board, documentation,

and software for controlling the board from a PC via the

EVAL-SDP-CB1Z.

Figure 43. Example Layout of the AD7980 (Top Layer)

Figure 44. Example Layout of the AD7980 (Bottom Layer)

06392-028

AD7980

06392-027

Data Sheet AD7980

Rev. F | Page 25 of 26

OUTLINE DIMENSIONS

Figure 45.10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Figure 46. 10-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height

(CP-10-9)

Dimensions shown in millimeters

Contact sales for the non-RoHS compliant version of the device.

COMPLIANT TO JEDEC STANDARDS MO-187-BA

091709-A

6°

0°

0.70

0.55

0.40

0.50 BSC

0.30

0.15

1.10 MAX

3.10

3.00

2.90

COPLANARITY

0.10

0.23

0.13

3.10

3.00

2.90

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

2.48

2.38

2.23

0.50

0.40

0.30

0.25

0.20

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.74

1.64

1.49

0.20 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

02-05-2013-C

TOP VIEW BOTTOM VIEW

0.20 MIN

AD7980 Data Sheet

Rev. F | Page 26 of 26

ORDERING GUIDE

Model1, 2, 3

Integral

Nonlinearity Temperature Range Package Description

Package

Option Branding

Ordering

Quantity

AD7980ARMZ ±2.5 LSB max −40°C to +125°C 10-Lead MSOP RM-10 C5X Tube, 50

AD7980ARMZRL7 ±2.5 LSB max −40°C to +125°C 10-Lead MSOP RM-10 C5X Reel, 1,000

AD7980BRMZ ±1.25 LSB max −40°C to +125°C 10-Lead MSOP RM-10 C5D Tube, 50

AD7980BRMZRL7 ±1.25 LSB max −40°C to +125°C 10-Lead MSOP RM-10 C5D Reel, 1,000

AD7980ACPZ-RL ±2.5 LSB max −40°C to +125°C 10-Lead LFCSP CP-10-9 C5X Reel, 5,000

AD7980ACPZ-RL7 ±2.5 LSB max −40°C to +125°C 10-Lead LFCSP CP-10-9 C5X Reel, 1,000

AD7980BCPZ-RL ±1.25 LSB max −40°C to +125°C 10-Lead LFCSP CP-10-9 C5D Reel, 5,000

AD7980BCPZ-RL7 ±1.25 LSB max −40°C to +125°C 10-Lead LFCSP CP-10-9 C5D Reel, 1,000

AD7980BCPZ-R2 ±1.25 LSB max −40°C to +125°C 10-Lead LFCSP CP-10-9 C5D Reel, 1,000

EVAL-AD7980SDZ

Evaluation Board

EVAL-SDP-CB1Z Controller Board

1 Z = RoHS Compliant Part.

2 The EVAL-AD7980SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.

3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.

registered trademarks are the property of their respective owners.

D06392-0-10/17(F)