Advisory
April 2002
DSP16000 Core
In the DSP16000 core, the contents of the internal do
loop cache are also accessible as memory (at loca-
tion 0x1ffc0 in most DSP16000 devices) in order to
facilitate saving and restoring of the cache contents
on a subroutine call or context switch.
It is accessible in both the X and Y address space, pri-
marily in order to allow the use of the block move
pipelin ed ins truction for faster loadin g/s aving.
It has been determined that while both X and Y
accesses to this area work correctly, a simultaneous
access of both X and Y to this area does not work.
The bank-conflict wait-state does not get sequenced
properly in this case, and the X-side data is returned
undefined. For example, if the following instruction:
nop y=*r0++ x=*pt0++
is executed with both r0 and pt0 pointing to the inter-
nal cache area, the value returned to the x register will
be undefined.
Since the only reason to access this area is for the
purpose of saving and restoring the cache contents, a
simultaneous read of this area should not be required.
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright © 2002 Agere Systems Inc.
All Rights Reserved
April 2002
AY02-020WINF (Must accompany DA02-001WINF, DA01-003WINF, DS02-037WINF, DS02-020WMA,
DS01-152WMA, DS01-070WTEC, and DS98-032WTEC)
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Tel. (852) 3129-2000, FAX (852) 3129-2020
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Advance Data Sheet
April 2002
DSP16411 Digital Signal Processor
1 Features
Twin DSP16000 dual-M AC cores perform up to
960 million MACs per second at 240 MHz
Low power:
—1.0 V internal supply for power efficiency
—3.3 V I/O pin supply for compatibility
322K x 16 on-chip RAM
Centralized direct memory access unit (DMAU):
—T ransparent peripheral-to-memory and memory-
to-memory transfers
—Better utilization of DSP MIPS
—Simplifies man agem ent of system data flow
16-bit parallel interface unit (PIU) with dir ect mem-
ory access (DMA) provides host a ccess to all DSP
memory
Two enhanced s erial I/O units (SIU0 and SIU1)
with DMA:
—Compat ible with TDM highways such as T1/E1
and ST-bus
—Hardware support for µ-law and A-law com-
panding
Core messaging units (MGU0 and MGU1) for inter-
processor comm uni cation
On-chip, programmable, PLL clock synthesizer
elim inates need for high-spee d clock input
Two 7-bit control I/O interfaces (BIOs) for
increased flexibility and lower system costs
32-bit system and external memory interface
(SEMI) supports 16-bit or 32-bit synchronous or
asynchronous memories
Two
IEEE
® 1149.1 test ports (JTAG boundary
scan)
Full-spee d, in-circuit emulation hardware for each
core with eight address and two data watchpoint
units for efficient application development
Supp orted by DSP16411 so ftware and hardware
development tools
208-ball PBGA package (17 mm x 17 mm; 1.0 mm
ball pitch) for small foot print
2 Description
The DSP16411 is a digital signal processor ( DSP)
optimized for communi c ations infrastruc ture applica-
tions. Large, on-chip memory enables it to be pro-
gramme d to perform numerous fixed-point signal
processing func tions, including equali zation, chan-
nel coding, compres sion, and speech coding . The
DSP16411 features twin DSP16000 dual-MAC DSP
cores and enhanced DM A capabi lities. Together,
these features deliver the performance required for
second- and third-generat ion infrastruct ure equip-
ment.
The DSP16411 extends the performance of the
DSP16410C with a higher maximum clock rate and
additional on-chip RAM, while maintaining low power
consumption, efficient software code densit y, and
small physical size. The DSP16411 is board des ign,
pinout, and code compatible with the DSP16410C to
protect investments in hardware and software devel-
opment.
Note: This data sheet contains advance information
that i s preliminary and subject to change.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
Table of Contents
Contents Page
2A gere System s— P rop rietary Agere Systems Inc.
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any instructions
➤1 Features...........................................................................................................................................................1
➤2 Description.......................................................................................................................................................1
➤3 Notation Conventions ....................................................................................................................................14
➤4 Hardwar e Ar ch i te c tur e........ ..... ....... .............. ..... .............. ..... ....... .............. ..... ....... .............. ....... ........ ...........1 4
➤4.1 DSP1 6411 Archi tectural Overview.......................................................................................................14
➤4.1.1 DSP16000 Cores ....................................................................................................................17
➤4.1.2 Clock Synthesizer (PLL)..........................................................................................................17
➤4.1.3 Triport RAMs (TPRA M〈0—1〉).................................................................................................17
➤4.1.4 Shared Local Memory (SLM)..................................................................................................17
➤4.1.5 Internal Boot ROMs (IROM〈0—1〉) .........................................................................................17
➤4.1.6 Messaging Units (MGU〈0—1〉) ...............................................................................................17
➤4.1.7 System and External Memory Interface (SEMI)......................................................................18
➤4.1.8 Bit Input/Output Units (BIO〈0—1〉)..........................................................................................18
➤4.1.9 Timer Units (TIMER0_〈0—1〉 and TIMER1_〈0—1〉)...............................................................18
➤4.1.10 Direct Memory Access Unit (DMAU).......................................................................................18
➤4.1.11 Interrupt Multiplexers (IMUX〈0—1〉)........................................................................................18
➤4.1.12 Parallel Interface Unit (PIU) ....................................................................................................18
➤4.1.13 Serial Interface Unit s (SIU〈0—1〉)...........................................................................................18
➤4. 1. 1 4 Test Access Po rts (JTAG〈0—1〉)............................................................................................18
➤4.1.15 Hardware Developmen t Systems (HDS〈0—1〉)......................................................................18
➤4.2 DSP1 6000 Core Architect ural Overview..............................................................................................19
➤4.2.1 System Control and Cache (SYS) ...........................................................................................19
➤4.2.2 Data Arithmetic Unit (DAU).....................................................................................................19
➤4.2.3 Y-Memory Space Address Arithmetic Unit (YAAU).................................................................20
➤4.2.4 X-Memory Space Address Arithmetic Unit (XAAU).................................................................20
➤4.2.5 Core Block Diagram................................................................................................................21
➤4.3 Device Reset........................................................................................................................................23
➤4.3.1 Reset After Powerup or Power Interruption ............................................................................23
➤4.3.2 RSTN Pin Reset......................................................................................................................23
➤4.3.3 JTAG Controller Reset............................................................................................................24
➤4.4 In te r r u p ts a nd Trap s..... ....... ....... ....... ....... ....... ....... ....... ........ ....... ....... .............. ..... .............. ....... ....... ..25
➤4.4.1 Hardware Interrupt Logic .........................................................................................................25
➤4.4.2 Hardware Interrupt Multiplexing..............................................................................................28
➤4.4.3 Clearing Core Interrupt Requests ............. ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ..30
➤4.4.4 Host Interrupt Output...............................................................................................................30
➤4.4.5 Globally Enabling and Disabling Hardware Interrupts.......................... .. ....... ....... .......... .. .......30
➤4.4.6 Individually Enabling, Disabling, and Prioritizing Hardware Interrupts....................................31
➤4.4.7 Hardware Interrupt Status.......................................................................................................32
➤4.4.8 Interrupt and Trap Vector Table..............................................................................................32
➤4.4.9 Software Interrupts..................................................................................................................34
➤4.4.10 INT[3:0] and TRAP Pins..........................................................................................................34
➤4.4.11 Nesting Interrupts....................................................................................................................35
➤4. 4.12 Int e rr u p ts a nd Cac he Usag e..... .............. ..... ....... .............. ..... .............. ..... ....... .............. .........37
➤4. 4.13 Int e rr u p t Po ll ing........... .... ....... ............... .... ....... ............... .... ............... .... ....... ............... ....... ....37
➤4.5 Memory Maps ......................................................................................................................................38
➤4.5.1 Private Internal Memory..........................................................................................................39
➤4.5.2 Shared Internal I/O..................................................................................................................39
➤4.5.3 Shared External I/O and Memory............................................................................................39
➤4. 5.4 X- Me mor y Map.. .............. ..... ....... .............. ..... ....... .............. ..... ....... .............. ..... .............. .......40
➤4. 5.5 Y- Me mor y Map s....... ....... ....... ....... ........ .............. ..... ....... .............. ..... .............. .... ........ ....... ....41
➤4.5.6 Z-Memory Maps......................................................................................................................42
Table of Contents (continued)
Contents Page
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Syst e ms Inc. Agere S ystems—Prop rietary 3
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➤4.5.7 Internal I/O Detailed Memory Map..........................................................................................43
➤4.6 Triport Random-Access Memory (TPRAM) .........................................................................................44
➤4.7 Shared Local Memory (SLM)...............................................................................................................45
➤4.8 Interprocessor Communication............................................................................................................46
➤4.8.1 Core-to-Core Interrupts and Traps..........................................................................................47
➤4.8.2 Message Buffer Data Exchang e .............................................................................................47
➤4.8.2.1 Mess age B uffer Write Protocol ...............................................................................48
➤4.8.2.2 Mess age B uffer Read Protocol...............................................................................48
➤4.8.3 DMAU Data Transfer...............................................................................................................49
➤4.9 Bit Input/Output Units (BIO 〈0—1〉).......................................................................................................50
➤4.10 Timer Units (TIMER0_〈0—1〉 and TIMER1_〈0—1〉) ...........................................................................53
➤4.11 Hardware Development System (HDS〈0—1〉).....................................................................................56
➤4.12 JTAG Test Port (JTAG〈0—1〉).............................................................................................................57
➤4.12.1 Port Identification ....................................................................................................................57
➤4.12.2 Emulation Interface Signals to the DSP16411........................................................................58
➤4.12 .2.1 TCS 14- Pin Header...... ............... .... ....... ............... .... ....... ............... .... ....... .............58
➤4.12.2.2 JCS 20-Pin Header.................................................................................................59
➤4.12.2.3 HDS 9-Pin, D-Type Connector................................................................................60
➤4.12 .3 Multiproc e ssor JTAG Con necti ons......... ....... ....... ....... ....... ....... ....... ............... .... ....... .............61
➤4.12.4 Boundary Scan........................................................................................................................62
➤4.13 Direct Memory Access Unit (DMAU)....................................................................................................64
➤4.13.1 Overview .................................................................................................................................64
➤4.13.2 Registers.................................................................................................................................67
➤4.13 .3 Data Stru ctur e s....... ....... ....... ....... ....... ........ ....... ....... ....... ....... .............. ..... ....... .............. ....... .83
➤4.13.3.1 One-Dim ension al Data Structure (SWT Channels) . ...............................................83
➤4.13.3.2 Two-Dimens ion al Data Structure (SWT Channels) . ...............................................84
➤4.13.3.3 Memory-to-Memory Block T ransfers (MMT Channels).. .. ....... .......... ....... .. .......... ...86
➤4.13.4 The PIU Addressing Bypass Channel.................... ................... .............. ................... .............86
➤4.13.5 Single-Word Transfer Channels (S W T) ..................................................................................87
➤4.13.6 Memory-to-Memory Transfer Channels (MMT).......................................................................90
➤4.13 .7 Inte r r u p ts a nd Priority Res olu tion...... ....... ....... ....... ....... ........ ....... .............. ..... ....... .............. ...92
➤4.13.8 Error Reporting and Recovery ................................................................................................94
➤4.13 .9 Progra mming Exa mples... ........ ....... ....... ....... ....... .............. ..... ....... .............. ..... ....... .............. .95
➤4.13.9.1 SWT Example 1: A Two-Dimensi onal Array ...........................................................95
➤4.13.9.2 SWT Example 2: A One-Dimen sional Array ...........................................................97
➤4.13.9.3 MMT Example.........................................................................................................99
➤4.14 System and External Memory Interface (SEMI).................................................................................100
➤4.14 .1 Exter n a l Inter fa ce.... ....... ....... ....... ....... ............... .... ....... ............... .... ....... ............... ....... ....... .101
➤4.14.1.1 Configuration.........................................................................................................102
➤4.14.1.2 Asy nchronous Me mory Bus Arbitr ation . ................................................................1 03
➤4.14.1.3 Enables and Strobes........................................................ ................... ..................104
➤4.14.1.4 External Clock.......................................................................................................1 05
➤4.14.1.5 Address and Data .................................................................................................1 06
➤4.14.1.6 Address and Data .................................................................................................1 08
➤4.14.2 16-Bit External Bus Accesses...............................................................................................109
➤4.14.3 32-Bit External Bus Accesses...............................................................................................109
➤4.14.4 Registers...............................................................................................................................110
➤4.14.4.1 ECON0 Register. ..... ....... .............. ..... ....... .............. ..... .............. ..... ....... .............. .111
➤4.14.4.2 ECON1 Register. ..... ....... .............. ..... ....... .............. ..... .............. ..... ....... .............. .112
➤4.14.4.3 Segment Registers ...............................................................................................1 14
➤4.14 .5 Asyn ch r o nous Memor y .. ....... ....... ....... ........ ....... ....... .............. ..... ....... .............. ..... ....... ....... .116
Table of Contents (continued)
Contents Page
4Agere S ystems—Prop rietary Agere Syste ms Inc.
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p
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any instructions
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
➤4.14.5.1 Func tional Timi ng ..................................................................................................1 16
➤4.14.5.2 Extending Access Time Via the ERDY Pin...........................................................1 20
➤4.14 .5.3 Interf a cing Exampl e s .. ....... ....... ....... ........ ....... ....... ....... .............. ..... ....... ..............122
➤4.14.6 Synchronous Memory................. ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... .. .......... .......124
➤4.14.6.1 Func tional Timi ng ..................................................................................................1 24
➤4.14 .6.2 Interf a cing Exampl e s .. ....... ....... ....... ........ ....... ....... ....... .............. ..... ....... ..............126
➤4.14.7 Performance..........................................................................................................................128
➤4.14.7.1 System Bus...........................................................................................................128
➤4.14.7.2 External Memory, Asynchronous Interface...........................................................1 29
➤4.14.7.3 External Memory, Synchronous In terface. ............................................................131
➤4.14.7.4 Summary of Access Times...................................................................................1 33
➤4.14.8 Priority...................................................................................................................................134
➤4.15 Parallel Interface Unit (PIU) ...............................................................................................................135
➤4.15.1 Registers...............................................................................................................................135
➤4.15.2 Hardware Interface................................................................................................................139
➤4.15.2.1 Enables and Strobes.................................... .............. ................... ................... .....140
➤4.15.2.2 Address and Data Pins.........................................................................................1 41
➤4.15.2.3 Flags, Interrupt, and Ready Pins ..... .......... ....... ....... .. .......... ....... .. ....... .......... .......142
➤4.15.3 Hos t Data Read and Write Cycles ........................................................................................1 43
➤4.15.4 Hos t Register Read and Write Cycles...................................................................................1 45
➤4.15.5 Hos t Comm ands ...................................................................................................................147
➤4.15.5.1 Status/Control/ Addres s Register Read Comma nds..............................................1 48
➤4.15.5.2 Status/Control/ Addres s Register Write Commands..............................................1 48
➤4.15.5.3 Memory Read Commands.... .... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... .....149
➤4.15.5.4 Flow Control for Memory Read Comma nds..........................................................150
➤4.15.5.5 Memory Write Commands..................................................... .............. .................151
➤4.15.5.6 Flow Control for Control/Status/Address Register and Memory Write
Commands ........................................................................................................151
➤4.15.6 Hos t Comm and Example s ....................................................................................................152
➤4.15.6.1 Do wnload of Program or Data . .............................................................................1 52
➤4.15.6.2 Up load of Data.. ................................. ...................................................................152
➤4.15.7 PIU In terrupts........................................................................................................................153
➤4.16 Serial Interface Unit (SIU)..................................................................................................................154
➤4.16.1 Hardware Interface................................................................................................................156
➤4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic , and Frame Sync Select ion Logic...........157
➤4.16.3 Basic Input Processing........... ................... ................... .............. ................... ................. .......159
➤4.16.4 Basic Output Processing.......................................................................................................160
➤4.16.5 Clock and Frame Sync Generation.... .............. ................... ................... .............. .................161
➤4.16.6 ST-Bus Timing Examples......................................................................................................166
➤4.16.7 S IU Loopbac k. .......................................................................................................................168
➤4.16.8 Basic Frame Structure ..........................................................................................................168
➤4.16.9 A ssigning SIU Logica l Channels to DMAU Channels...........................................................1 69
➤4.16.10 Frame Error Detection and Reporting...................................................................................170
➤4.16.11 Frame Mode..........................................................................................................................170
➤4.16.12 Channel Mode—32 Channels or Less in Two Subframe s or Less .......................................1 71
➤4.16.13 Channel Mode—Up t o 128 Channels in a Maximum of Eight Subframes . ...........................1 77
➤4.16.14 SIU Examples .......................................................................................................................1 80
➤4.16.14.1 Single-Chann el I/O ................................................................................................1 80
➤4.16.14.2 ST-Bus Interface...................................................................................................1 81
➤4.16.15 Registers...............................................................................................................................184
➤4.17 Internal Clock Selection .....................................................................................................................200
Table of Contents (continued)
Contents Page
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Syst e ms Inc. Agere S ystems—Prop rietary 5
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➤4.18 Clo ck Syn th e sis... ........ ....... .............. ..... ....... .............. ..... .............. ..... ....... .............. ......... ....... ........ ...201
➤4.18.1 PLL Operating Frequency............................... .............. ................... ................... ..................201
➤4.18.2 PLL LOCK Flag Generation..................................................................................................201
➤4.18 .3 PLL Regi ster s. ....... ....... ....... ....... ....... ....... .............. ..... ....... .............. ..... ....... .............. ........ ...202
➤4.18.4 PLL Programming Example..................................................................................................203
➤4.18.5 Powering Down the PLL ........................................................................................................203
➤4.18.6 Phase-Lock Loop (PLL) Frequency Accuracy and Jitter.... .............. ................... ..................203
➤4.19 External Clock Selection....................................................................................................................2 04
➤4.20 Power Man age men t........ ....... ....... ........ ....... ....... .............. ..... ....... .............. ..... ....... ................ ........ ...205
➤5 Process or Boot-Up and Memory Download.................................................................................................208
➤5.1 IROM Boot Routine and Host Download Via PIU ..............................................................................208
➤5.2 EROM Boot Routine and DMAU Downl oad.......................................................................................2 09
➤6 Soft w are Archite c tur e ... ........ .... .............. ..... ....... ............... .... ....... ............... .... .............. ........ ....... .............. .210
➤6.1 Instruction Set Quick Reference ........................................................................................................2 10
➤6.1.1 Condi tions Based on the State of Flags................................................................................226
➤6.2 Registers............................................................................................................................................227
➤6.2.1 Directly Program-Accessible (Register-Mapped) Registers.... .. ....... ....... .......... .. ....... .......... .227
➤6.2.2 Memory-M apped Regi sters...................................................................................................231
➤6.2.3 Re g i ste r En co d ing s... ..... ....... ..... ....... .............. ..... ....... .............. ..... ....... .............. ..... .......... ...235
➤6.2.4 Re se t State s..... ....... ....... ....... ....... ....... ........ ....... ....... ....... .............. ..... .............. ..... ......... ......249
➤6.2.5 RB Field Encoding ................................................................................................................252
➤7 Ball Grid Array Information ..........................................................................................................................2 53
➤7.1 208-Ball PBGA Package.................................. ................... ................... .............. ..............................253
➤8 Signal Descriptions......................................................................................................................................2 56
➤8.1 Sy ste m Inte r fac e........... ..... ....... .............. ..... .............. ..... ....... .............. ..... ....... .............. ....... ....... ......257
➤8.2 BIO Inter fa ce..... ....... ..... ....... .............. ..... ....... .............. ..... .............. ..... ....... .............. ....... ....... ........ ...257
➤8.3 System and Exte rnal Memory Interface.............................................................................................257
➤8.4 SIU0 Interface....................................................................................................................................260
➤8.5 SIU1 Interface....................................................................................................................................261
➤8.6 PIU Interface......................................................................................................................................2 62
➤8.7 JTAG0 Test Interface.........................................................................................................................263
➤8.8 JTAG1 Test Interface.........................................................................................................................263
➤8.9 Power and Ground................. ....... .......... .. ....... .......... .. ....... ....... .......... .. ....... ....... ..... ....... ..................264
➤9 Device Charac te r istics.......... .... ....... ............... .... ....... ............... .... ............... .... ....... ................. ....... ....... ......265
➤9.1 Absolute Maximum Rati ngs . ..... ....... .............. ..... ....... .............. ..... .............. ..... ....... .............. ....... ......265
➤9.2 Handling Precau tions.........................................................................................................................265
➤9.3 Recom me nded Operating Condit ions.. ..............................................................................................265
➤9.3.1 Packa ge Thermal Considerations.........................................................................................2 66
➤10 Electrical Characteristics and Require ments...............................................................................................267
➤10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs...............................268
➤10.1.1 Maintenance of Valid Logic Lev els on the SEMI Interface...................... ................... ...........268
➤10.1.2 Maintenance of Valid Logic Lev els on the PIU Interface.... .............. ................... ..................269
➤10.2 Analog Power Supply Decoupling......................................................................................................270
➤10.3 Power Dissipation .. ....... ....... ....... ....... ....... ....... ........ .............. .... ........ .............. .... ................... ........ ...271
➤10.3.1 Internal Power Dissipation ....................................................................................................271
➤10.3.2 I/O Power Dissipation............................................................................................................2 72
➤10.4 Power Supply Sequencing Issues......................................................................................................273
➤10.4.1 Powerup Sequenc e.................................................. .............................................................273
➤10.4.2 Powerdown Sequenc e ..........................................................................................................273
➤11 Timing Charact eristics and Requiremen ts...................................................................................................274
➤11.1 Phase - L o ck L oop..... ..... .............. ..... ....... .............. ..... ....... .............. ..... .............. ..... ....... . ...... ....... ......275
Table of Contents (continued)
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6Agere S ystems—Prop rietary Agere Syste ms Inc.
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DSP16411 Digital Signal Processor April 2002
➤11.2 Wake-Up Latency...............................................................................................................................276
➤11.3 DSP Clock Generation.......................................................................................................................277
➤11.4 Reset Circu it... .............. .... ........ .............. .... ........ .............. ..... ....... .............. ..... .................. ........ .........278
➤11.5 Reset Syn ch r o n izati o n... ....... ....... ....... ............... .... ....... ............... .... ....... ............... .... ............ ....... .....279
➤11.6 JTAG..................................................................................................................................................280
➤11.7 Interrupt and Trap..............................................................................................................................2 81
➤11.8 Bit I/O.................................................................................................................................................2 82
➤11.9 System and External Memory Interface.............................................................................................283
➤11.9 .1 Asyn ch r o nous In te rface ..... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... .............. ..... .........284
➤11.9.2 Synchr onous Interface.............................. ................... .............. ................... ........................287
➤11.9.3 ERDY Interface.....................................................................................................................289
➤11.10PIU.....................................................................................................................................................290
➤11.11SIU.....................................................................................................................................................294
➤12 Appendix—Naming Inconsistencies............................................................................................................304
➤13 Outline Diagram— 208-B all PBGA...............................................................................................................305
➤14 Index............................................................................................................................................................306
List of Figures
Figure Page
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April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. Agere Systems—Prop ri etary 7
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➤Figure 1. DSP16411 B lock Diagram.................................................................................................................15
➤Figure 2. DSP16000 Core Bloc k Diagram........................................................................................................21
➤Figure 3. CORE0 and CORE1 In terrupt Logic Block Diagram .........................................................................26
➤Figure 4. IMUX Block Diagram.........................................................................................................................29
➤Figure 5. Functiona l Timing for INT[3:0] and TRAP..................................................... .....................................34
➤Figu r e 6. X- Memo r y Map.... ....... ....... ....... ....... ....... ....... ........ .............. .... ........ .............. .... ........ . ............. ..... .....40
➤Figu r e 7. Y- Memo r y Map s.... .............. ..... .............. ..... ....... .............. ..... ....... .............. ..... .............. ....... ..... ....... .41
➤Figure 8. Z-Memory Maps ................................................................................................................................42
➤Figu r e 9. I nt e rn a l I/O Memory Map..... ....... ..... .............. ..... ....... .............. ..... ....... .............. ..... ........ ...... ........ .....43
➤Figure 10. Interleaved Internal TPRAM..............................................................................................................44
➤Figure 11. Example Memory Arrangement....... ..... ....... .. .......... ....... ....... .. .......... ....... .. ....... .......... ....... ...............44
➤Figure 12. Interprocessor Communication Logic in MGU0 and MGU1 ..............................................................46
➤Figure 13. Timer Block Diagram.........................................................................................................................54
➤Figure 14. TCS 14-Pin Connector ......................................................................................................................58
➤Figure 15. JCS 20-Pin Connector. ......................................................................................................................59
➤Figure 16. HDS 9-Pin Connector........................................................................................................................60
➤Figure 17. Typical Multiprocessor JTAG Connection with Single Scan Chain ...................................................61
➤Figure 18. DMAU Interconnections and Channels .......................... ....... .. .......... ....... ....... .. .......... ....... .. .............65
➤Figure 19. DMAU Block Diagram ........................................................................................................................66
➤Figure 20. One-Dimensional Data Structure for Buffe ring
n
Channels...................... .. ....... .......... ....... .. .......... ...83
➤Figure 21. Two-Dimensional Data Structure for Double-Buffering
n
Channels..................................................84
➤Figure 22. Memory-to-Memory Block Transfer...................................................................................................86
➤Figure 23. Example of a Two-Dimensional Double-Buffered Data Structure ..... .. ....... ....... .......... .. ....... .......... .. .95
➤Figure 24. Example of One-Dimen sional Data Structure....................................................................................97
➤Figure 25. Memory-to-Memory Block Transfer...................................................................................................99
➤Figure 26. SEMI Interface Block Diagram ........................................................................................................1 00
➤Figu r e 27. Asynch ro nou s Me mor y Cycles... ........ .............. ..... ....... .............. ..... .............. .... ........ ................... ...117
➤Figure 28. Asynchronous Memory Cycles (RSETUP = 1, WSETUP = 1) ........................................................1 18
➤Figure 29. Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1) ............................................................1 19
➤Figure 30. Use of ER DY Pin to Extend Asynchronous Accesses. ....................................................................120
➤Figure 31. Example of Using the ERDY Pin.....................................................................................................1 21
➤Figure 32. 32-Bit External Interface with 16-Bit Asynchronous SRAMs ... .......... .. ....... ....... ..... ....... ....... .......... .123
➤Figure 33. 16-Bit External Interface with 16-Bit Asynchronous SRAMs ... .......... .. ....... ....... ..... ....... ....... .......... .123
➤Figure 34. Synchronous Memory Cycles..... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ..... .............125
➤Figure 35. 16-Bit External Interface with 16-Bit Pipelined, Synchronous
ZBT
SRAMs .... ..... ....... ..... ....... ........126
➤Figure 36. 32-Bit External Interface with 32-Bit Pipelined, Synchronous
ZBT
SRAMs .... ..... ....... ..... ....... ........127
➤Figure 37. 32-Bit PA Regi ster Host and Core Access......... ....... ....... ............... .... ....... ............... .... ....... ...........138
➤Figure 38. PIU Functional Timing for a Data Read and Write Operation. .........................................................1 44
➤Figure 39. PIU Functional Timing for a Register Read and Write Operation....................................................146
➤Figure 40. SIU Block Diagram..........................................................................................................................1 55
➤Figure 41. Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync S elect ion Logic .....................1 58
➤Figure 42. Default Serial Input Functional Timing....................... ....... ....... ..... ....... ....... ..... ....... ....... ..................159
➤Figure 43. Default Serial Output Functional Timing..........................................................................................1 60
➤Figure 44. Frame Sync to Data Delay Timing...................................................................................................1 63
➤Figure 45. Clock and Frame Sync Generation with External Clo ck and Synchronizat ion
(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires No Resynchronization)..................1 66
➤Figure 46. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = A GS YNC = IFSA = IFSK = 1 and Timing Requ ires Resynchroni zation)........................1 67
➤Figure 47. Basic Frame Structure.....................................................................................................................1 68
➤Figure 48. Basic Frame Structure with Idle Time ..............................................................................................169
➤Figure 49. Channel Mode on a 128-Channel Frame. .......................................................................................171
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➤Figure 50. S ubframe and Chann el Selection in Channel Mode ........................................................................176
➤Figure 51. Genera ting Interrupts on Subframe Boundaries..............................................................................178
➤Figu r e 52. ST-Bus Si n gle - R a te Clock..... .... .............. ..... .............. ..... ....... .............. ..... .............. ..... ....... ....... .....183
➤Figure 53. ST-Bus Double-Rate Clock .............................................................................................................183
➤Figure 54. Internal Clock Selection Logic.........................................................................................................200
➤Figure 55. Clock Synthesizer (P LL) Block Diagram ..........................................................................................2 01
➤Figure 56. P ower Mana gem ent and Clock Distribution ....................................................................................206
➤Figure 57. Interpretation of the Instruction Set Summary Table.......................................................................211
➤Figure 58. DS P1 6411 Program-Ac cess ible Registers for Each Core...............................................................228
➤Figure 59. Example Memory-Mapped Registers................ ....... .. .......... ....... ....... .. .......... ....... .. ....... .......... .......231
➤Figure 60. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View)... ....... ..... ....... .....253
➤Figure 61. DS P1 6411 Pinout by Interface........................................................................................................256
➤Figure 62. Analog Supply Dec oupl ing ........................ ......................................................................................270
➤Figure 63. Reference Voltag e Level for Timing Characteristics and Requ irements fo r Inputs and Outputs ....274
➤Figure 64. I/O Clock Timing Diagram...............................................................................................................2 77
➤Figure 65. P owerup and Device Reset Timing D iagram . .................................................................................278
➤Figure 66. Reset Synchronization Timing.........................................................................................................279
➤Figure 67. JTAG I/O Timing Diagram ..............................................................................................................2 80
➤Figure 68. Interrupt and Trap Timing Diagram.................................................................................................2 81
➤Figure 69. Write Out put s Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics...2 82
➤Figure 70. Enable and Write Strobe Transiti on Timing. ....................................................................................283
➤Figure 71. Timing Diagram for EREQN and EACKN........................................................................................2 84
➤Figure 72. A synchrono us Read Timing Diagram (RHOLD = 0 and RSET UP = 0)...........................................285
➤Figure 73. Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0)................................................286
➤Figure 74. Synchronous Read Timing Diagram (Read-Read-Write Sequence).... ..... ....... ....... ....... ..... ....... .....287
➤Figure 75. Synchronous Write Timing Diagram...... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ............288
➤Figure 76. ERDY Pin Timing Diagram..............................................................................................................2 89
➤Figure 77. Host Data Write to PDI Timing Diagram..........................................................................................290
➤Figure 78. Host Data Read from PDO Timing Diagram...... ....... .. .......... ....... .. ....... .......... ....... .. ....... .......... .. .....291
➤Figure 79. Hos t Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram.....................................292
➤Figure 80. Hos t Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram .....................................293
➤Figure 81. SIU Passive Frame and Channel Mode Input Timing Diagram.......................................................294
➤Figure 82. S IU Passive Frame Mode Out put Timing Diag ram . ........................................................................295
➤Figure 83. S IU Passive Channel Mode Out put Timing Diagram ......................................................................2 96
➤Figure 84. SCK External Clock Source Input Timing Diagram.........................................................................297
➤Figure 85. S IU Active Frame and Channe l Mode Input Timing Diagram ... .......................................................298
➤Figure 86. SIU Active Frame Mode Output Timing Diagram............................................................................300
➤Figure 87. S IU Active Channel Mode Output Timing Diagram.........................................................................301
➤Figure 88. ST-Bus 2x Input Timing Diagram ....................................................................................................302
➤Figure 89. ST-Bus 2x Output Timing Diagram..................................................................................................303
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➤Table 1. DSP16411 B lock Diagram Legend................................................................................................... 16
➤Table 2. DSP16000 Core Bloc k Diagram Legend. . ..................................................................................... .. . 22
➤Table 3. State of Device Output and Bidirectional Pins During and After Reset . ........................................... 24
➤Table 4. Hardware Interrupts.......................................................................................................................... 27
➤Table 5. imux (Interrupt Multiplex Control) Register...................................................................................... 28
➤Table 6. Global Disabling and Enabling of Hardware Interrupts ..................................................................... 30
➤Table 7. inc0 and inc1 (Interrupt Control) Registers 0 and 1 .... ..................................................................... 31
➤Table 8. ins (Interrupt Status) Register.......................................................................................................... 32
➤Table 9. Interrupt and Trap Vector Table ....................................................................................................... 33
➤Table 10. psw1 (Processor Status Word 1) Register....................................................................................... 35
➤Table 11. DSP16411 Me mory Component s..................................................................................................... 38
➤Table 12. signal Register................................................................................................................................. 47
➤Table 13. Full-Duplex Data Transfer Code Through Core-to-Core Message Buffer. ....................................... 48
➤Table 14. DMAU MMT Channel Interrupts....................................................................................................... 49
➤Table 15. DMA Intracore and Intercore Transfers Example............................................................................. 49
➤Table 16. sbit (BIO Status/Control) Register ................................................................................................... 50
➤Table 17. cbit (BIO Contro l) Register............................................................................................................... 51
➤Tabl e 18. BIO Oper a tions...... ....... ....... ....... ............... .... ........ .............. .... ........ .............. .... ............................... 52
➤Table 19. BIO Flags.......................................................................................................................................... 52
➤Table 20. timer〈0,1〉c (T IMER〈0,1〉 Control) Register..................................................................................... 55
➤Table 21. timer〈0,1〉 (TIMER〈0,1〉 Running Count) Register........................................................................... 56
➤Table 22. ID (JTAG Identification) Reg ister...................................................................................................... 57
➤Table 23. TCS 14-Pin Socket Pinout................................................................................................................ 58
➤Table 24. JCS 20-Pin Sock et Pinout.................................................. .............................................................. 59
➤Table 25. HDS 9-Pin, Subminiature, D-Type Plug Pinout................................................................................ 6 0
➤Table 26. JTAG0 Boundary-Scan Register ...................................................................................................... 62
➤Table 27. JTAG1 Boundary-Scan Register ...................................................................................................... 63
➤Table 28. DM AU Chann el Assign ment.. ........................................................................................................... 64
➤Table 29. DM AU M emo ry-Mappe d Registers ................................................................................................... 67
➤Table 30. DSTAT (DMAU Status) Register....................................................................................................... 69
➤Table 31. DMCON0 (DMAU Master Control 0) Register.................................................................................. 71
➤Table 32. DMCON1 (DMAU Master Control 1) Register.................................................................................. 72
➤Table 33. Collective Designations Used in Table 34........................................................................................ 73
➤Table 34. CTL〈0—3〉 (SWT〈0—3〉 Control) Registers...................................................................................... 74
➤Table 35. Collective Designations Used in Table 36........................................................................................ 76
➤Table 36. CTL〈4—5〉 (MMT〈4—5〉 Control) Registers ..................................................................................... 76
➤Table 37. SADD〈0—5〉 and DADD〈0—5〉 (Channels 0—5 Source and Destination Address) Register s........ 77
➤Table 38. SCNT〈0—3〉 (SWT〈0—3〉 Source Counter) Registe rs..................................................................... 78
➤Table 39. SCNT〈4—5〉 (MMT〈4—5〉 Source Counter) Registers..................................................................... 78
➤Table 40. DCNT〈0—3〉 (SWT〈0—3〉 Destination Counter) Registers .............................................................. 79
➤Table 41. DCNT〈4—5〉 (MMT〈4—5〉 Destination Counter) Registers.............................................................. 79
➤Table 42. LIM〈0—3〉 (SWT〈0—3〉 Limit) Registers .......................................................................................... 80
➤Table 43. LIM〈4—5〉 (MMT〈4—5〉 Limit) Registers.......................................................................................... 80
➤Table 44. SBAS〈0—3〉 (SWT〈0—3〉 Source Base Address) Registers ........................................................... 81
➤Table 45. DBAS〈0—3〉 (SWT〈0—3〉 Destination Base Address) Registers..................................................... 81
➤Table 46. STR〈0—3〉 (SWT〈0—3〉 Stride) Registers........................................................................................ 82
➤Table 47. RI〈0—3〉 (SWT〈0—3〉 Reindex) Registers....................................................................................... 82
➤Table 48. S WT-S pecific Memory-Ma pped Regist ers ...................................................................................... . 88
➤Table 49. MM T -Spe cific Memory-Mapped Registers.................................................................................... ... 91
➤Table 50. DMAU Interrupts............................................................................................................................... 92
➤Table 51. Overview of SEMI Pins....................................................................................................... ....... ..... 101
List of Tables (continued)
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➤Table 52. Configuration Pins for the SEMI External Interface....................................................................... . 102
➤Table 53. Asynchronous Memory Bus Arbitration Pins.................................................................................. 103
➤Table 54. Enable and Strobe Pins for the SEMI External Interface... ................................. ............................ 10 4
➤Table 55. ECKO Output Clock Pin Configuration....................................................................................... .... 105
➤Table 56. Address and Data Bus Pins for the SEMI External Interface ......................................................... 106
➤Table 57. 16-Bit External Bus Configuration .......................................................................................... ....... . 109
➤Table 58. 32-Bit External Bus Configuration .......................................................................................... ....... . 109
➤Table 59. SEMI Memory-Mapped Registers .................................................................................................. 110
➤Table 60. ECON0 (External Control 0) Register............................................................................................. 111
➤Table 61. ECON1 (External Control 1) Register............................................................................................. 112
➤Table 62. ECKO Output Clock Pin Configuration....................................................................................... .... 113
➤Table 63. EXSEG0 (CORE0 External X Segment Address Extension) Register........................................... 114
➤Table 64. EXSEG1 (CORE1 External X Segment Address Extension) Register........................................... 114
➤Table 65. EYSEG0 (CORE0 External Y Segment Address Extension) Register........................................... 115
➤Table 66. EYSEG1 (CORE1 External Y Segment Address Extension) Register........................................... 115
➤Table 67. System Bus Minimum Access Times ......................................................................................... .... 128
➤Table 68. A ccess Time Pe r SEMI Transaction, Async hronous Interface, 32-Bit Data Bus............................ 133
➤Table 69. A ccess Time Pe r SEMI Transaction, Async hronous Interface, 16-Bit Data Bus............................ 133
➤Table 70. A ccess Time Pe r SEMI Transaction, Synchronous Interface, 32-Bit Data Bus . ............................. 133
➤Table 71. A ccess Time Pe r SEMI Transaction, Synchronous Interface, 16-Bit Data Bus . ............................. 133
➤Table 72. E xampl e Average Acce ss Time Per SEMI Transaction, 32-Bit Data Bus...................................... 134
➤Table 73. E xampl e Average Acce ss Time Per SEMI Transaction, 16-Bit Data Bus...................................... 134
➤Table 74. PIU Registers ...................................................................................................................... ..... ...... 135
➤Table 75. PCON (PIU Control) Register......................................................................................................... 136
➤Table 76. PDI (PIU Data In) Register......................................................................................................... .... 137
➤Table 77. PDO (PIU Data Out) Register......................................................................................................... 137
➤Table 78. HSCRATCH (Host Scratch) Register............................................................................................. 137
➤Table 79. DSCRATCH (DSP Scratch) Register............................................................................................. 137
➤Table 80. PA (Parallel Address) Register....................................................................................................... 138
➤Table 81. PIU External Interface .................................................................................................... ........ ....... . 139
➤Table 82. Enable and Strobe Pins... .......................................................................................... ........ ....... ...... 140
➤Table 83. Address and Data Pins........................................................................................................ ....... .... 141
➤Table 84. Fla gs, Interrupt, and Ready Pins.............................................................................................. ...... 142
➤Table 85. S ummary of Host Commands .................................................................................................. ...... 147
➤Table 86. Status/Control/Address Register Read Commands ... .......... ....... .. ....... .......... ....... .. ....... .......... .. .... 148
➤Table 87. S tatus/Co ntrol/Address Regist er Write Commands ....................................................................... 148
➤Table 88. Me mory Read Com ma nds. ..................................................................................................... ....... . 149
➤Table 89. Memory Write Commands ...................................................................................................... ....... . 151
➤Table 90. SIU External Interface .................................................................................................... ........ ....... . 156
➤Table 91. Cont rol Register Fields for Pin Conditioning, Bit Clock Selection , and Frame Sync Selection ...... 157
➤Table 92. A Summary of Bit Clock and Frame Sync Control Register Fields................................................. 164
➤Table 93. Examples of Bit Clock and Frame Sync Control Register Fields.................................................... 165
➤Table 94. Subframe Definition................................................................................................................ .... .... 172
➤Table 95. Loc ation of Control Fields Used in Channel Mode......................................................................... 174
➤Table 96. Des cription of Control Fields Used in Channel Mode..................................................................... 174
➤Table 97. Subframe Selection............................................................................................................. ........... 175
➤Table 98. Channel Activation Within a Selec ted Subfram e............................................................................ 175
➤Table 99. Channel Masking Wi thin a Selected Su bframe.................................................. ............................ 175
➤Table 100. Control Register and Field Configuration for ST-Bus Interface ...................... ....... .. ....... .......... .. .... 181
➤Table 101. Control Register and Fields That Are Configured as Required for ST-B us Interface..................... 182
➤Table 102. SIU Registers ................................................................................................................. ........ ....... . 184
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➤Table 103. SCON0 (SIU Input/Output General Control) Register.................................................................... 1 85
➤Table 104. SCON1 (SIU Input Frame Control) Registe r .................................................................................. 186
➤Table 105. SCON2 (SIU Output Frame Control) Register................................................................................ 187
➤Table 106. SCON3 (SIU Input/Output Subframe Control) Register ................................................................. 188
➤Table 107. SCON4 (SIU Input Even Subframe Valid Vector Control) Register................................................ 189
➤Table 108. SCON5 (SIU Input Odd Subframe Valid Vector Control) Register................................................. 189
➤Table 109. SCON6 (SIU Output Even Subframe Valid Vector Control) Register............................................. 190
➤Table 110. SCON7 (SIU Output Odd Subframe Valid Vector Control) Register.............................................. 190
➤Table 111. SCON8 (SIU Output Even Subframe Mask Vector Control) Register............................................ 190
➤Table 112. SCON9 (SIU Output Odd Subframe Mask Vector Control) Register.............................................. 190
➤Table 113. SCON10 (SIU Input/Output General Control) Register.................................................................. 191
➤Table 114. SCON11 (SIU Input/Output Active Clock Control) Register ........................................................... 194
➤Table 115. SCON12 (SIU Input/Output Active Frame Sync Control) Register................................................. 195
➤Table 116. SIDR (SIU Input Data) Register...................................................................................................... 1 96
➤Table 117. SODR (SIU Output Data) Register................................................................................................. 196
➤Table 118. STAT (SIU Input/Output General Status) Register......................................................................... 197
➤Table 119. FSTAT (SIU Input/Output Frame Status) Regist er ................ ....... ....... ..... ....... ....... ....... ..... ....... ..... 197
➤Table 120. OCIX〈0—1〉 and ICIX〈0—1〉 (SIU Output and Input Channel Index) Registers ................. ....... ..... 198
➤Table 121. OCIX〈0—1〉 (SIU Output Channel Index) Registers......... ................... .............. ................... .......... 198
➤Table 122. ICIX〈0—1〉 (SIU Input Channel Index) Registers ............. ....... .......... .. ....... ....... ..... ....... ....... .......... 199
➤Table 123. Sourc e Clock Selection .. ...................................................................................................... ........ .. 200
➤Table 124. pllcon (Phase-Lock Loop Control) Register................................................................................... 202
➤Table 125. pllfrq (Phase-Lo ck Loop Frequenc y Control) Register.................................................................. 202
➤Table 126. pllfrq1 (Phase- Lock Loop Fr equency Control 1) Register .................. .............. ................... .......... 202
➤Table 127. plldly (Phase-Lock Loop Delay Control) Register... .. ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ..... 202
➤Table 128. ECKO Output Clock Pin Configuration.................................................................................... ....... 204
➤Table 129. Wake-Up Latenc y and Powe r Consumption for Low-Power Standby Mode .................................. 2 07
➤Table 130. Core Boot-Up After Reset. ............................................................................................. ....... ........ .. 208
➤Table 131. Content s of IROM0 and IRO M 1 Boot ROM s.................................................................................. 208
➤Table 132. DSP1 6411 Instruction Groups................................................................................................... ..... 210
➤Table 133. Instruction Set Summary ............................................................................................... ....... ........ .. 212
➤Table 134. Notation Conventions for Instruction Set Descripti ons............ .......... .. ....... ....... ..... ....... ....... .......... 218
➤Table 135. Overall Replacement Table.............................................. ................... .............. ................. ....... ..... 219
➤Table 136. F1 Ins truction Syntax.................... ............................................................................. .... ....... ..... ..... 222
➤Table 137. F1E Funct ion Sta tement Synt ax.......................................................................... ............... ....... ..... 224
➤Table 138. DSP1 6411 Condi tional Mnemon ics................................................................................................ 226
➤Table 139. Program-Ac cess ible (Register-Mapped) Regist ers by Type, Listed Alphabetically. ....................... 229
➤Table 140. DM AU Memo ry-Mappe d Registers ............................................................................................ ..... 232
➤Table 141. SEMI Memory-Mapped Registers ....................................................... .............. ................... ..... ..... 233
➤Table 142. PIU Registers ................................................................................................................ ............... .. 234
➤Table 143. SIU Memory-M apped Regi sters..................................................................................................... 234
➤Table 144. alf (AWAIT Low-Power and Flag) Register.................................................................................... 235
➤Table 145. auc0 (Arithmetic Unit Control 0) Register....................................................................................... 236
➤Table 146. auc 1 (Arithmetic Unit Control 1) Register....................................................................................... 237
➤Table 147. cbit (BIO Control) Register........................................................................................................... .. 238
➤Table 148. cloop (Cache Loop) Regist e r..... ........ ....... ....... .............. ..... ....... .............. ..... ....... .............. ..... ....... 239
➤Table 149. csave (Cache Save) Register........................................................................................................ 239
➤Table 150. cstate (Cache State) Register........................................................................................................ 239
➤Table 151. imux (Interrupt Multiplex Control) Register.................................................................................... 240
➤Table 152. ID (JTAG〈0—1〉 Identification) Registers........................................................................................ 241
➤Table 153. inc0 and inc1 (Interrupt Control) Registers 0 and 1. ...................................................................... 241
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➤Table 154. ins (Interrupt Status) Register.................................................................................................... .... 242
➤Table 155. mgi (Core-to-Core Message Input) Register............ .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... ..... .... ..... ..... .. .... 242
➤Table 156. mgo (Core-to-Core Message Output) Register.............................................................................. 242
➤Table 157. pid (Processor Identification) Register........................................................................................... 242
➤Table 158. pllcon (Phase-Lock Loop Control) Register................................................................................... 243
➤Table 159. pllfrq (Phase-Lo ck Loop Frequenc y Control) Register.................................................................. 243
➤Table 160. pllfrq1 (Phase- Lock Loop Fr equency Control 1) Register ... ......... ................... .............. ................ 243
➤Table 161. plldly (Phase-Lock Loop Delay Control) Register................ ....... ....... .. .......... ....... .. ....... .......... ...... 243
➤Table 162. psw0 (Processor Status Word 0) Register ..................................................................................... 244
➤Table 163. psw1 (Processor Status Word 1) Register..................................................................................... 245
➤Table 164. sbit (BIO Status/Control) Register ................................................................................................. 246
➤Table 165. signal (Core-to-Core Signal) Register ........................................................................................... 246
➤Table 166. timer0c and timer1c (TIMER〈0,1〉 Control) Registers................................................................... 247
➤Table 167. timer0 and timer1 (TIMER〈0,1〉 Running Count) Registers .......................................................... 248
➤Table 168. vsw (Viterbi Support Word) Register.............................................................................................. 248
➤Table 169. Core Register States After Reset—40-Bit Registers...................................................................... 249
➤Table 170. Core Register States After Reset—32-Bit Registers...................................................................... 249
➤Table 171. Core Register States After Reset—20-Bit Registers...................................................................... 250
➤Table 172. Core Register States After Reset—16-Bit Registers...................................................................... 250
➤Table 173. Of f-Core (Peripheral) Register Reset Values................................................................................. 250
➤Table 174. Memory-M apped Regi s ter Reset Values—32-Bit Registers . ......................................................... 2 51
➤Table 175. Memory-M apped Regi s ter Reset Values—20-Bit Registers . ......................................................... 2 51
➤Table 176. Memory-M apped Regi s ter Reset Values—16-Bit Registers . ......................................................... 2 51
➤Table 177. RB Field............................................................................................................... ....... .... ............... . 252
➤Table 178. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol.............................. ................ 254
➤Table 179. Absolute Maximum Ratings............ .. ....... .......... .. ....... .......... ....... .. ....... .......... .. ....... ....... ........ ....... . 265
➤Table 180. Minimum ESD Voltage Thresholds............................. ................... ................... .............. ................ 265
➤Table 181. Recom me nded Operat ing Conditions ............................................................................................ 265
➤Table 182. P ackage Therm al Consideration s ................................ .......................................................... .... .... 266
➤Table 183. Electrical Characteristics and Requirements..... .. ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... .......... . 267
➤Table 184. Effect of EYMOD E Pin and BHE DIS Field ..................................................................................... 268
➤Table 185. Typical Internal Power Dissipation at 1.0 V and 240 MHz.............................................................. 271
➤Table 186. Typical I/O Power Dissipation at 3.3 V and 240 MHz............. ....... ..... ....... ....... ....... ..... ....... ....... .... 272
➤Table 187. Referenc e Voltag e Level for Timing Characteristics and Requ irements fo r Inputs and Outputs ... 274
➤Table 188. PLL Requirem ents........................................................................................................ ....... ....... .... 275
➤Table 189. Wake-Up Latenc y....................................................................................................... ....... ....... ...... 276
➤Table 190. Timing Requirements for Input Clock...... .......... ....... .. .......... ....... ....... .. .......... ....... .. ....... ........ ....... . 277
➤Table 191. Timing Characteristics for Output Clock....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ....... .... 277
➤Table 192. Timing Requirements for Powerup and Device Reset..... ....... ..... ....... ....... ....... ..... ....... .. .......... ...... 278
➤Table 193. Timing Characteri stics for Device Reset .................. .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ..... ....... .... 278
➤Table 194. Timing Requirements for Reset Synchronization Timing ....... ..... ....... .. .......... ....... ....... .. .......... ...... 279
➤Table 195. Timing Requirements for JTAG I/O......... ..... ....... ....... .......... .. ....... ....... ..... ....... ....... ....... ........ ....... . 280
➤Table 196. Timing Characteristics for JTAG I/O........ ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ............ ...... 280
➤Table 197. Timin g Requirements for Interrupt and Trap .................................................................................. 281
➤Table 198. Timin g Requirements for BIO Input Read . ..................................................................................... 282
➤Table 199. Timing Characteristics for BIO Output............... ....... .. .......... ....... ....... .. .......... ....... .. ....... .......... ...... 282
➤Table 200. Timing Characteristics for
ERWN
and Memory En ables.... ....... ....... ....... ....... ....... ....... .............. .... 283
➤Table 201. Timin g Requirements for EREQN .......................................................................................... ........ 284
➤Table 202. Timing Characteristics for EACKN and SEMI Bus Disable .... ....... ..... ....... ....... ..... ....... ....... ....... .... 284
➤Table 203. Timin g Requirements for Asynchronous Me mory Read Operation s.............................................. 285
➤Table 204. Timin g Characteristics for Asynchronous M emo ry Read Operations............................................. 2 85
List of Tables (continued)
Table Page
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➤Table 205. Timin g Characteristics for Asynchronous M emo ry Write Operations............................................. 286
➤Table 206. Timin g Requirements for Synchronous Read Op erations.............................................................. 287
➤Table 207. Timing Characteristics for Synchronous Read Operations...... .......... ....... ....... .. .......... ....... .. .......... 287
➤Table 208. Timing Characteristics for Synchronous Write Operations.... ....... ....... ..... ....... ....... ....... ..... ....... ..... 288
➤Table 209. Timin g Requirements for ERDY Pin.. ........................................................................................ ..... 289
➤Table 210. Timin g Requirements for PIU Data Write Operations.. ................................................................... 290
➤Table 211. Timing Characteri stics for PIU Data Write Operations . .... ..... .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... ..... 290
➤Table 212. Timin g Requirements for PIU Data Read Operations .................................................................... 291
➤Table 213. Timing Characteristics for PIU Data Read Operations............ ..... ....... ....... ..... ....... ....... ....... ..... ..... 291
➤Table 214. Timin g Requirements for PIU Register Write Operations............................................................... 292
➤Table 215. Timing Characteristics for PIU Register Write Operations ........... ....... ....... ....... ..... ....... ....... ..... ..... 292
➤Table 216. Timin g Requirements for PIU Register Read Operations............................................................... 293
➤Table 217. Timing Characteristics for PIU Register Read Operations.................. ....... ..... ....... ....... ....... ..... ..... 293
➤Table 218. Timing Requirements for SIU Passive Frame Mode Input.... ....... ....... ..... ....... ....... ....... ..... ....... ..... 294
➤Table 219. Timing Requirements for SIU Passive Channel Mode Input ........ ....... ..... ....... .. .......... ....... ....... ..... 294
➤Table 220. Timing Requirements for SIU Passive Frame Mode Output .................... ....... ....... ....... ..... ....... ..... 295
➤Table 221. Timing Characteristics for SIU Passive Frame Mode Output....... ....... ..... ....... .. .......... ....... ....... ..... 295
➤Table 222. Timing Requirements for SIU Passive Channel Mode Output ........................ ....... ....... ..... ....... ..... 296
➤Table 223. Timing Characteristics for SIU Passive Channel Mode Output........... ....... ..... ....... ....... ..... ....... ..... 296
➤Table 224. Timing Requirements for SCK External Clock Sour ce............ .......... ....... .. ....... .......... ....... .. .......... 297
➤Table 225. Timing Requirements for SIU Active Frame Mode Input.............. ....... ....... ..... ....... ....... ....... ..... ..... 298
➤Table 226. Timing Characteristics for SIU Active Frame Mode Input...... .. .......... .. ....... ....... .......... .. ....... .......... 298
➤Table 227. Timing Requirements for SIU Active Channel Mode Input................ ....... .. ....... .......... .. ....... .......... 299
➤Table 228. Timing Characteristics for SIU Active Channel Mode Input... .. .......... ....... .. ....... .......... ....... .. .......... 299
➤Table 229. Timing Requirements for SIU Active Frame Mode Output ...... .......... .. ....... ....... .......... .. ....... .......... 300
➤Table 230. Timing Characteristics for SIU Active Frame Mode Output..... .......... .. ....... ....... ..... ....... ....... .......... 300
➤Table 231. Timing Requirements for SIU Active Channel Mode Output ........ ....... ....... ..... ....... ....... ..... ....... ..... 301
➤Table 232. Timing Characteristics for SIU Active Channel Mode Output..................... ....... .......... .. ....... .......... 301
➤Table 233. S T-Bus 2x Input Timing Requirem ent s...................................................................................... ..... 302
➤Table 234. S T-Bus 2x Output Tim ing Requireme nts. .................................................................................. ..... 303
➤Table 235. ST-Bus 2x Output Timing Characteristics .................................................................................... .. 303
➤Table 236. Pin Name Inconsist encies ................................................................................................ .... ........ .. 304
➤Table 237. Register Name Inconsistencies.............. ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... ....... ........ .. 304
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3 Notation Conventions
The following notation conventions apply to this data
sheet. Table 134 on page 218 specifies the notation
conventions for the DSP16000 instruction set.
lower-case Registers that are directly writable or
readable by DSP16411 core instruc-
tions are lower-case.
UPPER-CASE Device flags, I/O pins, control register
fields, and registers that are not directly
writable or readable by DSP16411 core
instructions are upper-case.
boldface Register name s and DSP16411 core
instructions are printed in boldface
when used in text des criptions.
italics
Document ation variables that are
replaced are printed in italics.
courier DSP16411 program exampl es or
C-language representati ons are printed
in courier font.
[ ] Square brackets enclose a range of
numbers that represents multiple bits in
a single register or bus. The range of
numbers is delimited by a colon. F or
example, imux[11:10] are bits 11 and
10 of the program-accessible imux reg-
ister.
〈〉 Angle brackets enclose a list of items
delimited by commas or a range of
items delimited by a dash (—), one of
which is selected if used in an
instruction. For example, SADD〈0—3〉
represents the four memory-mapped
registers SADD0, SADD1, SADD2,
and SADD3, and the general instruc-
tion aTE〈h,l〉=RB can be replaced
with a 0 h = time r0.
4 Hardware Architecture
4.1 DSP16411 Arc hitectural Overview
The DSP16 411 device is a 16-bit fixed -point program-
mable digital signal processor (DSP). The DSP16411
consi sts of two DSP16000 cores together with on-chip
memory and peripherals. Advanced ar chitectural fea-
tures with an expanded instruction set deliver a dra-
matic increase in per formance compar ed to traditional
DSP architectures for signal coding algorithms . This
increase in per formance, together wit h an effici ent
design implementation, results in an extremely cost-
efficient and power-efficient solution for wireless and
multimedia applications.
Figure 1 on page 15 shows a block diagram of the
DSP16411.
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4 Hardware Architecture (continued)
4.1 DSP16411 Architectural Overview (continued)
DSP16411B Block Diagram
Figure 1. DSP 16411 Block Diagra m
YDB YAB XDB XAB
YDB YAB XDB XAB
IDB
XAB0
XDB0
YAB0
YDB0
YAB1
YDB1 32 20 32 32 20 32 20
CORE0
SAB
SDB
ZEAB
ZEDB
ZIDB ZIAB
SDB SAB
ZEDB
ZEAB
SDB SAB
32 20
TPRAM0
IROM0
PAB DPI
27 16
PIU SIU0
DMAU DSI0
DSI1
IMUX0
imux
32 MGU0
signal
jiob
BOUNDARY SCAN
JTAG0
TIMER0_0
TIMER1_0
TIMER0_1
TIMER1_1
32
BIO0
pid 16
16
HDS0
cbit
PD[15:0] PODS PCSNPIDS
PADD[3:0] PRWN
PRDYMD
POBE PIBF PRDY PINT
SDB
SAB
SIU1
SICK0
SID0
SIFS0
SOCK0
SOD0
SOFS0
SCK0
SICK1
SID1
SIFS1
SOCK1
SOD1
SOFS1
SCK1
ED[31:0]
EA[18:0]
ERAMN
EROMN
EION
ERWN[1:0]
ECKO
EREQN
EACKN
ERDY
EXM
ERTYPE
ESIZE
INT[3:0]
TCK0
TMS0
TDO0
TDI0
TRST0N
CKI
RSTN
TRAP
IO0BIT[6:0] IO1BIT[6:0]
TCK1
TMS1
TDO1
TDI1
TRST1N
INT[3:0]
SEMI
CLK
DDO
DDO DDODSI
DSI
DDO
XABXDBYABYDB
IDB
CORE1
(160K x 16)
MGU1 IMUX1
imux
CLOCK/CONTROL
pllcon
20
XAB1
XDB1
ZSEGZSEG 4
YDB YAB XDB XAB
ZIDB ZIAB
TPRAM1
(160K x 16)
IROM1
SLM
(2K x 16)
32 20
SDB SAB
32 20
PAB DPI
32
ESEG[3:0]
16 16
20
32
16
16
BIO1
SDB SAB
32 20
TO IMUX1
TO HDS1/MGU1 TRAP
ZIABZIDB
sbit cbit
timer1
timer1c timer1
timer1c
timer0
timer0c timer0
timer0c
mgi
mgo mgo
mgi
signal
pid
20
32
ID
pllfrq
plldly
jiob
BOUNDARY SCAN
JTAG1
HDS1
ID
KEY: OFF-CORE REGISTER-MAPPED REGISTERS
ACCESSIBLE BY CORE0
sbit
OFF-CORE REGISTE R-MAPPED REGISTERS
ACCESSIBLE BY CORE1
pllfrq1
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4 Hardware Architecture (continued)
4.1 DSP16411 Architectural Overview (continued)
Table 1. DSP16411 Block Diagra m Legend
Symbol Description
BIO〈0—1〉Bit I/O Units. On e for each cor e .
cbit 16-Bit BIO Cont rol Regist er.
CLK Internal Clock Signal.
CORE0 DSP160 00 Core—System Master.
CORE1 DSP160 00 Core—System Sla ve.
DDO DMA Data Out. (For transferri ng data from DMAU to PIU, SIU0, and SIU1.)
DMAU Direct Memory Access Unit.
DPI DMA Parallel In. (For transferring 16-bit data from PIU to DMAU.)
DSI0 DMA Serial Data In Zero. (For transferring data from SIU0 to DMAU.)
DSI1 DMA Seri al Data In One. (For tr ansferring data fr om SIU1 to DMAU.)
HDS〈0—1〉Hardware Development Systems. One for each core.
ID JTAG Port Identif ication Register Accessible Via the JTAG Port. One for each of the two JTAG〈0—1〉
ports.
IDB Internal Data Bus. One for each core.
imux 16-Bit IMUX Cont rol Register.
IMUX〈0—1〉I nterrupt Multiplexers. One for each cor e; se lects ten interr upts from DM AU, SIU0 , SIU1, PIU, I NT[3: 0],
TIMER〈0—1〉, and MGU.
IROM〈0—1〉I nternal Read- O nly Memories (one for each cor e) fo r Boot and HDS Code.
jiob 32-Bit JTAG Test Register.
JTAG〈0—1〉JTAG Test Ports. One for each core .
mgi 16-Bit Core-to- Core M essage Inp ut Regi ster.
mgo 16-Bi t Core-to-Core Message Ou tput Register.
MGU〈0—1〉Cor e-t o-Core Messagi ng Unit. One for each core.
PAB 27-Bi t Par all el Address Bus. (For DMAU/PIU comm unications.)
pid 16-Bit Processor ID Register (CORE0: 0x0 000; CORE1: 0x0001).
PIU Parallel Inter face Unit. (16-bit par allel host inter face.)
pllcon 16-Bit Phase-Lock Loop Contro l Regi ster.
pllfrq 16-Bit Phase-Lock Loop Fr equency Control Regi ster.
pllfrq1 16-Bi t Phase-Lock Loop Frequency Control 1 Register.
plldly 16-Bit Phas e-Lock Loop Delay Contro l Regi ster.
SAB 20-Bit System Address Bus. A ddress for system bus (S-bus ) accesses.
sbit 16-Bit BIO Status/Control Register.
SDB 32-Bit System Data Bus. Data for system bus (S-bus) accesses.
SEMI Sys tem and External Memory Interfac e.
signal 16- Bit Signal Register for Core- to-Core Commun ication.
SIU0 Serial Input/Output Unit Zero.
SIU1 Serial Input/Output Unit One.
SLM 2 Kword Shared Local Memory.
timer0 16-Bit Timer Running Count Register for TIMER0.
TI ME R0 _0 Pr o g r a m ma bl e Ti m e r 0 fo r CO R E 0.
TI ME R0 _1 Pr o g r a m ma bl e Ti m e r 0 fo r CO R E 1.
timer0c 16-Bit Timer Control Register for TIMER0.
timer1 16-Bit Timer Running Count Register for TIMER1.
TI ME R1 _0 Pr o g r a m ma bl e Ti m e r 1 fo r CO R E 0.
TI ME R1 _1 Pr o g r a m ma bl e Ti m e r 1 fo r CO R E 1.
Table 1. DSP16411 Block Diagra m Legend (continued)
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4 Hardware Architecture (continued)
4.1 DSP16411 Architectural Overview (continued)
4.1.1 DSP16000 Cores
The two DSP16000 cores (CORE0 and CORE 1) are
the signal-processing engi nes of the DSP16411 . The
DSP16000 is a modified Ha rvard architecture with sep-
arate sets of buses for the instruction /coefficient
(X-memory) and data (Y-memory) spaces. Each set of
buses has 20 bits of address and 32 bits of data. The
core contains data and address arithmet ic units and
control for on-chip memory and periphe rals.
4.1.2 Clock Synthesizer (PLL)
The DSP16411 powers up with an input clock (CKI) as
the source for the processor clock (CLK). An on-chip
clock synthesizer (PLL) that runs at a frequency multi-
ple of CKI can also be used to generate CLK. T he
clock synthesizer is deselected and power ed down on
reset. The select ion of the clock source is under soft-
ware control of CORE0. See S ection 4 .17, begin ning
on page 200, for details.
4.1.3 Triport RAMs (TPRAM〈0—1〉)
Each core has a priva te block of TPRAM consisting of
160 banks (banks 0—159 ) of zero wait-state memory.
Each bank consists of 1K 16-bit words and has three
separate address and data ports: one port to the core’s
instruction/coefficient (X-m emor y) space, a second
port to the core’s data (Y-memory) space, and a third
port to the DMA (Z-memory ) space. TPRAM0 is
accessible by CORE0, TPRAM1 is accessible by
CORE1, and both TPRAM0 and TPRAM1 are accessi-
ble by the DMAU. TP RA M is organized into even and
odd interleaved ban ks for which each even/odd
address pair is a 32-bit wide module (see Section 4.6
on page 44 for details). The TPRAMs support single-
word, aligned double -word, and misaligned double -
word accesses.
4.1.4 Shared Local Memory (S LM )
The SLM consists of two banks of memory. Each bank
consi sts of 1K 16-bit words. The SL M can be
accessed by both cores and by the DMAU and PIU
over the system bus (SAB, SDB). The SLM supports
single-word (16-bit) and aligned double-word (32-bit)
accesses. Misali gned doub le-word accesses are not
supported. An ac ce ss to the SLM take s mult iple clock
cycles to complete, and a core access to the SLM
causes the core to incur wait-states. See
Section 4.14.7.1 on page 128 for det ails on syste m bus
performance.
4.1.5 Internal Boot ROMs (IRO M 〈0—1〉)
Each core has its own boot ROM that contains a single
boot routine and software to suppo rt the Agere hard-
ware development system (HDS). The code in IROM0
and IROM1 is identical. See Section 5 on page 208 for
details.
4.1.6 Mes saging Units (MGU〈0—1〉)
The DSP16411 provides an MGU for each core: MGU0
for CORE0 and MGU1 for CORE1. The MGUs provide
interprocessor (cor e-to-core) communication and inter-
rupt generation. S ee Section 4.8 on page 46 for
details.
timer1c 16-Bit Timer Control Register for TIMER1.
TPRAM〈0—1〉160 Kword Three-Port Random-Acces s Memor ies (one for each core). Private code (X), data (Y), and
DMA (Z).
XAB〈0—1〉20-Bit X-Memor y Space Addres s Bus. One for each core.
XDB〈0—1〉32-Bit X-Memory Space Data Bus. One for eac h core.
YAB〈0—1〉20-Bit Y-M em ory Space Addr ess Bus. One for each core.
YDB〈0—1〉32-Bit Y-Memory Space Data Bus. One for each core.
ZEAB 20-Bit Extern al Z- M emory Space Address Bus. Interf aces DMAU to SEMI.
ZEDB 32-Bi t Ext ernal Z-Memory Space Data Bus. Interfac es DMAU to SEMI.
ZIAB 20-Bit Internal Z-Memory Space Address Bus. Interfaces DMAU to TPRAM0 and TPRAM1.
ZIDB 32-Bit Internal Z-Memory Space Data Bus. Inte rfaces DMAU to TPRAM0 and TPRAM1.
ZSEG External Segment Address Bits Associated with ZEAB. Interfaces DMAU to SEMI.
Symbol Description
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4 Hardware Architecture (continued)
4.1 DSP16411 Architectural
Overview (continued)
4.1.7 System and External Memory Interface
(SEMI)
The SEMI interfaces both cores and the DMAU to
external memory and I/O devices. It interfaces directly
to pipelined synchronou s
ZBT
™
SRA Ms and asyn-
chronous SRAMs. The SEMI also interfac es the cores
and the DMAU to the internal SLM and to memory-
mapped registers in the DMAU, PIU, SIU0, and SIU1
via the internal system bus or S-bus (SAB and
SDB). See Section 4. 14, beginning on page 10 0, for
details.
4.1.8 Bit Input/Output Units (BIO〈0—1〉)
The DSP1641 1 provides a BIO unit for each core: BIO0
for CORE0 and BIO1 for CORE1. Each BIO unit pro-
vides convenient and ef ficient monitoring and control of
seven individually configurable pin s. If configured as
outputs, the pins can be individually set, cleared, or
toggled. If configu re d as inputs, individual pins or com-
binations of pins can be tested for patterns. Fl ags
returned by the BIO can be tested by conditional
instructions. See Section 4.9 on page 50 for details.
4.1.9 Timer Units (TIMER0_〈0—1〉 and
TIMER1_〈0—1〉)
The DSP16411 provides two timer units for each core:
TIMER0_0 and TIMER1_0 fo r CORE0, and TIMER0_1
and TIMER1_1 for CORE1. Each timer can be used to
provide an interrupt, either single or repetitive, at the
expiration of a programmed interval. M ore than nine
orders of magnitude of interval selection are provided.
See Sec tion 4.10 on page 53 for more information.
4.1.10 Direct Memory Access Unit (DMAU)
The direct memory access unit (DMAU) manages data
transfers in the DSP1 6411 me mory space. Dat a can
be moved between DSP16411 memory and peripher-
als and between different memory spaces in the
DSP16411. Once initiated, DMAU transfers occur with-
out core intervention. T he DM AU support s concurrent
core execution and I/O processing. See Section 4.13,
beginning on page 64, for details.
4.1.1 1 Interrupt Multiplexers (IMUX〈0—1〉)
The DSP16411 provides an interrupt multiplexer unit
for each core: IMUX0 for CORE0 and IMUX1 for
CORE1. Each IMUX multiplexes the 26 hardware
interrupts into the 20 available hardware interrupt
reques ts for each core. See Sec ti o n 4.4.2 on p age 28
for details.
4.1.12 Pa rallel Interface Unit (PIU)
The parallel interface unit (PIU) is a 16-bit parallel port
that provides a host processor direct access to the
entire DSP16411 m emo ry system (including memory -
mapped peripheral registers). See Section 4.15,
beginning on page 135, for details.
4.1.13 Se rial Interface Units (SIU 〈0—1〉)
The DSP164 11 provides two identical SIUs. Each S IU
is a full-duplex, double-buffered serial port with in de-
pendent input and output frame and bit clock control.
Clock and frame signa ls can be generated exte rnally
(passive) or by on-chip clock and frame generation
hardware (active). T he SIU features multiple-chann el
TDM mode for ST-bus (1x and 2x co mpa tible) and
T1/E1 com patibility. Each S IU is provided a DMAU
interface for data transfer to memory (TPRAM0,
TPRAM1, SLM, memory-mapped registers, or external
memory) without c ore intervention. See Section 4.16,
beginning on page 154, for details.
4.1.14 Test Access Ports (JTAG〈0—1〉)
The DSP16411 provides a JTAG unit for each core:
JTAG 0 for CORE0 and JTAG1 for CORE1. See
Section 4.12 on page 57 for deta ils.
4.1.15 Ha rdw are Devel op ment S ystem s
(HDS〈0—1〉)
The DSP16 411 provides an HDS unit for each core:
HDS0 for CORE0 and HDS1 for CORE1. Each HDS i s
an on-chip har dware module available for debugging
assem bly-lan guage program s that execu te on the
DSP16000 core in real-time. The main capability of the
HDS is in allowing controlled visibility into the core’s
state during program execution. The HDS is enhanced
with powerful debugging capabi lities such as complex
breakp ointing condition s, multiple data /address watc h-
point registers, and an intelligent trace mechanism for
recording discontinuities. See Section 4.1 1 on page 56
for details.
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4 Hardware Architecture (continued)
4.2 DSP16000 Core A rchitectural Overview
The DSP16411 cont ains two identi cal DSP1600 0
cores. As shown in F igure 2 on page 21, each core
consists of four major blocks : syst em c ontrol and cache
(SYS), data arithmetic unit (DAU), Y-memo ry space
address arithmetic unit (YAAU), and X-memory space
address arithmetic unit (XAAU). Bits within the auc0
and auc1 registers configure the DAU mode-controlled
operations. S ee t he
D SP160 00 D igital Signal Proces-
sor Core
Information Manual for a complete description
of the DSP16000 core.
4.2.1 System Control and Cache (SYS)
This section consists of the control block and the
cache.
The control block provides overall system coordination
that is most ly invisible to the user. The cont rol block
includes an instructi on decoder and sequencer, a
pseudorandom sequence generator (PSG), an inter-
rupt and trap handler, a wait-state generator , and low-
power standby mode control logic. An interrupt and trap
handler provides a user-locatable vecto r table and
three le vels of user-assigned interrupt priority.
SYS contains the alf register, which is a 16-bit register
that contains AWAIT, a power-saving standby mode
bit, and peripheral flags. The inc0 and inc1 registers
are 20-bit interrupt control registers, and ins is a 20-bit
interrupt sta tus register.
Programs use the instruction cache to store and exe-
cute repetitive operations such as those found in an
FIR or IIR filter section. The cache can contain up to
thirty-one 16-bit and 32-bit instructions. The code in the
cache can repeat up to 216 – 1 times without looping
overhead. Operations in the cac he that require a coeffi-
cient access ex ecute at twice the normal rate because
th e XAAU and i ts as so ciated bus are not needed for
fetching instructions. The cache greatly reduces the
need for writing in-line repetitive code and, therefore,
reduces instruction/coeff icient memory size require-
ments. In addition, the use of cache reduces power
consum ption becaus e it eliminates memo ry accesse s
for instruction fetches.
The cache provides a convenient, low-overhead loop-
ing structure that is interruptible, savable, and restor-
able. The cache is addressable in both the X and Y
memory spaces . An interrupt or trap handling routine
can save and restore cloop, cstate, csave, and the
contents of the cache. The cloop register controls the
cache loop count. The cstate register contains the cur -
rent state of the cache. The 32-bit csave register holds
the opcode of the instruction following the loop instruc-
tion in program memory.
4.2.2 Data Arithmetic Unit (DAU)
The DAU is a power-effici ent, dual-MAC (multiply/accu-
mulate), parallel-pipelined structure that is tailored to
comm unicat ions appli cations . It can perform two dou-
ble-word (32-bit) fetches, two multiplications, and two
accumulations in a single instruction cycle. The dual -
MAC parallel pipeline begins with two 32-bit registers,
xand y. The pipeline treats the 32-bit registers as four
16-b it signed registers if used as input to two signed
16-bit x 16-bit multipliers. Each multiplier produces a
full 32-bit result stored into registers p0 and p1. The
DAU can direct the output of each multiplie r to a 40-bit
ALU or a 40-bit 3-input ADDER. The ALU and ADDER
results are each stored in one of eight 40-bit accumula-
tors, a0 through a7. Both the ALU and ADDER include
an ACS (add/compare/select) function for Viterbi
decoding. The DAU can direct the output of each accu-
mulator to the ALU/ACS, the ADDER/ AC S, or a 40-bit
BMU (bit manipulation unit) .
The ALU implement s 2-input addition, subtraction, and
various logical operations. The ADD ER implements
2-input or 3-input addition and subtraction. To support
Viterbi decoding, the ALU and ADDER have a split
mode in which two simul taneous 16-bit additions or
subtractions are performed. This mode, available in
speci alized dual-MA C instructions, is used to compute
the distance between a received symbol and its esti-
mate.
The ACS provides the add/compare/ select function
required for Viterbi decoding. This unit provides flags to
the traceb ack encoder for implemen ting mode-con-
trolled side-eff ects for ACS operations. The source
operands for th e ACS are any two accumulators, and
results are written back to one of the source accumula-
tors.
The BMU implements barrel-shift, bit-fi eld insertion, bit-
field extraction, exponent extraction, normalization, and
accum ulator shuffling operat ions. ar0 through ar3 are
auxiliary registers whose main function is to control
BMU operations.
The user can enab le overflow saturation to affe ct the
multipl ier output and the results of the three arithm etic
units. Overflow saturation can also af fect an accumula-
tor value as it is transferred to memory or other
register . These features accommodate various speech
coding standa rd s such as GSM-FR, GSM-HR, and
GSM- EFR. Shifting in the arithmetic pipeline occu rs at
several stages to accommodate various standa rds for
mixed-precision and double-precision multiplications.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.2 DSP16000 Core Architectural
Overview (continued)
4.2.2 Data Arithmetic Unit (DAU) (continued)
The DAU contains control and status registers auc0,
auc1, psw0, psw1, vsw, and c0—c2.
The arithmetic unit control registers auc0 and auc1
select or deselect vario us modes of DAU operation.
These modes include scaling of products, saturation on
overflow, feedback to the x and y registe rs from accu-
mu lators a6 and a7, simultaneous loading of x and y
registers with the same value (used for single-cycle
squaring), and clearing the low half of registers when
loading the high half to facili tate fixed-point operations.
The processor status word registers psw0 and ps w1
contain f l ags set by ALU/ACS, ADDER, or BMU opera-
tions. They also include information on the current sta-
tus of the interrupt controller.
The vsw register is the Viterbi support word associated
with the traceback encoder . The traceback encoder is a
specialized block for accelerating Viterbi decoding. The
vsw cont rols side-effects for three compare functions:
cmp0( ), cmp1( ), and cmp2( ). These instructions are
part of the MAC group that utilizes the traceback
encoder. The side-effects allow the DAU to store, with
no overhead, state information necessary for traceback
decoding. Side-effects use the c1 counter, the ar0 and
ar1 auxiliary regis ters, and bits 1 and 0 of vsw.
The c1 and c0 counters are 16-bit signed registers
used to count events such as the numbe r of times the
program has executed a sequence of code. The c2
register is a holding register for counter c1. Conditional
instructions control these counters and provide a con-
venient method of program loo ping.
4.2.3 Y-M emor y Space Add ress Arithmeti c Unit
(YAAU)
The YAAU supports high-speed, register-indirect, data
memory addressing with postincremen t of the a ddress
register. Eig ht 20-bit pointer registers (r0—r7) store
read or wri te addresses for the data (Y-memory) space.
Two s ets of 20-bit registers (rb0 and re0; rb1 and re1)
define t he upper and lower boundaries of two zero-
overhead circular buffers fo r efficient filter implement a-
ti o n s . T h e j and k registers are two 20-bit sign ed regis-
ters that are used to hold user-defined post increm ent
values for r0—r7. Fixed increm ents of +1, –1, 0, +2,
and –2 are also available. (Posti ncrement options 0
and –2 are not available for some specialized transfers.
See the
DSP16000 Digital Signal Processor Core
Infor-
mat ion Manual for details.)
The YAA U includes a 20-bit stack pointer (sp). The
data mov e group includes a set of stack instructions
that consists of push, pop, stack-relative, and pipelined
stack- relative operations. The addressing mode used
for the stack-relative instructions is register-plus-dis-
placem ent ind irect addressing (the displacem ent is
optional). The displacement is specified as either an
immediate value as part of the instruction or a value
stored in j or k. The YAAU c om putes the address by
adding the displacement to sp and leaves the contents
of sp unchanged. The data move group also includes
instructions with regis ter-plus-displacement indirect
addressing for the pointer registers r0—r6 in addition
to sp.
The dat a move group of instructions includes instruc-
tions for loading and storing any YAAU register from or
to memory or another core register. It also includes
instructions for loading any YAAU register with an
immedia te value stored with the ins truction. The
pointer arithmetic group of instructions allows adding of
an immediate value or the contents of the j or k register
to any YAAU pointer register and storing the resu lt to
any YAAU regist er.
4.2.4 X-Memory Space Address Arithmetic Unit
(XAAU)
The XAAU contains registers and an adder that control
the sequencing of instructions in th e processor. Th e
program count er (PC) automatically increm ents
through the instruction space. The interrupt return reg-
ister pi, the subroutine return register pr, and the trap
return register ptrap are automatically loaded with the
return address of an interrupt service routine, subrou-
tine, and trap service routine, respectively . High-speed,
register-indirect, read-only memory address ing with
postincrem enting is done with the pt0 and pt1 regis-
ters. The signed registers h and i are used to hold a
user-define d signed posti ncremen t value. Fixed post in-
crem ent values of 0, +1, –1, +2, and –2 are also avail-
able. (Postincrement options 0 and –2 are available
only if the target of the data transfer is an accumulator .
See the DSP16000 Digital Signal Processor Core
Infor-
mat ion Manual f or details.)
The dat a move group include s instructions for loading
and storing any XAAU registe r from or to memory or
another core register. It also includes instructions for
loading any XAAU register with an immediate value
stored with the instruction.
vbase is the 20-bit vector base offset register . T he user
programs this register with the base address of the
interrupt and trap vector table.
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4 Hardware Architecture (continued)
4.2 DSP16000 Core A rchitectural Overview (continued)
4.2.5 Core Block Diagram
DSP16000 Core Block Diagram
Figure 2. DSP16000 Core Block Diagram
pr (20)
ptrap(20)
DAU
+
XAAU
SINGLE
–1, 0, 1
MUX
+
YAAU
MUXCOMPARE
SYS
cstate (16)
csave (32 )
CACHE CONTROL
(32)
IMMEDIATE
OFF-
CORE
SHIFT(2, 1, 0, –2)/SAT.
16
×
16 MULTIPLY 16
×
16 MULTIPLY
SPLIT /MUX
SAT.
ALU/ACS ADDER/ACS BMU
MUX MUX
MUX/EXTRACT
ENCODER
TRACEBACK
SHIF T(0, –1) SHIF T(0, –1)
SWAP MUX
SHIFT(0, –1)
SHIFT
(0, –14)
SAT.
SHIFT(0, –15, –16)
SAT. SAT.
SHIF T(2, 1, 0, –2)/SAT .
KEY:
PROGRAM-ACCESSIBLE REGISTERS
MODE-CONTROLLED OPTIONS
PSG
BUSES
VALUE
‡
SAT.SAT. SAT.
ar0 ( 16)
ar1 ( 16)
ar2 ( 16)
ar3 ( 16)
c0 (16)
c1 (16)
c2 (16)
vsw (16 )
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
y (32) x (32)
p0 (32) p1 (32)
a0 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
a7 (40)
a1 (40)
ins (20)
inc0 (20)
inc1 (20)
cloop (16)
PC (20)
pt0 (20)
pt1 (20)
pi (20)
vbase (20)
(20) (20)
XDB (32)
IDB
(32)
YAB YAB
(20) (20)
re0 (20)
re1 (20) rb0 ( 20)
rb1 ( 20)
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
sp (20)
k (20)
j (20)
DOUBLE
–2, 0, 2
31 INSTRUCTIONS
alf (16)
(32)
XDB
IDB
(32)
SINGLE
–1, 0, 1
MUX
IMMEDIATE
VALUE
†
i (20)
h (20) DOUBLE
–2, 0, 2
† Associated with
PC
-relative branch addressing.
XAB
(20)
YAB
(20)
TO
MEMORY
FROM
MEMORY
TO/FROM
MEMORY
TO
MEMORY
(32)
IDB
(32)
TO
PERIPH-
ERAL
XDB
YDB
XABXAB
‡ Associated with register-plus-displacement indirect addressing.
MUX
k (20)
j (20)
re0 (20)
re1 (20) rb0 ( 20)
rb1 ( 20)
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
sp (20)
ar0 ( 16)
ar1 ( 16)
ar2 ( 16)
ar3 ( 16)
c0 (16)
c1 (16)
c2 (16)
vsw (16 )
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
y (32) x (32)
p0 (32) p1 (32)
a0 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
a7 (40)
a1 (40)
SHIFT(2, 1, 0, –2)/SAT.
SAT.
SAT.
SAT. SAT.
SHIF T(2, 1, 0, –2)/SAT .
SAT.SAT. SAT.
pr (20)
ptrap(20)
cstate (16)
csave (32 )
ins (20)
inc0 (20)
inc1 (20)
cloop (16)
pt0 (20)
pt1 (20)
pi (20)
vbase (20)
alf (16)
i (20)
h (20)
MUX
DEMUX
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4 Hardware Architecture (continued)
4.2 DSP16000 Core A rchitectural Overview (continued)
4.2.5 Core Block Diagram (continued)
Table 2. DSP16000 Core Block Diagram Le gend
Symbol Name
16 x 16 MULTIPLY 16-Bit x 16-Bit Multi plier.
a0—a7 40-Bit Accumulators 0—7.
ADDER/ACS 3-Input 40-Bit Adder/Subtractor and Add/Compare/Select Function . Used in Viterbi decodi ng.
alf 16-Bit AWAIT Low-Power and Flags Register.
ALU/ACS 40-Bit Ari thmetic Logi c Unit and Add/Compare/Select Functi on. Used in Viterbi dec oding.
ar0—ar3 16-Bit Auxi li ary Registers 0—3.
auc0, auc1 16-Bit Arithmetic Unit Control Regis ters.
BMU 40-Bit Manipulation Unit.
c0, c1 16-Bit Counters 0 and 1.
c2 16-Bit Counter Holdi ng Regis ter.
cloop 16-Bit Cache Loop Count Register.
COMPARE Compar ator. Used f or ci rcul ar buffer a ddressing.
csave 32-Bit Cache Save Register.
cstate 16- Bit Cache State Register.
DAU Data Arithmetic Unit.
h20-Bit Pointer Postincrement Register for the X-Memory Space.
i20-Bit Pointer Postincrement Register for the X-Memory Space.
IDB 32-Bit Internal Data Bus.
inc0, inc1 20-Bit Int errupt Contr ol Registe rs 0 and 1.
ins 20- Bit Interrupt Status Regi ster.
j20-Bit Poin ter Postinc rement/ Offset Regi ster for the Y-Memory Space.
k20-Bit Poin ter Postinc rement/ Offset Regi ster for the Y-Memory Space.
MUX Multiplexer.
p0, p1 32-Bit Product Registers 0 and 1.
PC 20-Bit Program Counter.
pi 20-Bit Progr am Int errupt Retur n Register.
pr 20-Bit Program Return Register.
PSG Pseudorandom Sequence Generator.
psw0, psw1 16-Bit Processor Status W ord Registers 0 and 1.
pt0, pt1 20-Bit Poin ters 0 and 1 to X-Memory Space.
ptrap 20-Bit Program Trap Return Register.
r0—r7 20-Bit Pointers 0—7 to Y- Me mory Space.
rb0, rb1 20-Bit Circular Buffer Pointers 0 and 1 (begin address).
re0, re1 20-Bit Circular Buffer Pointers 0 and 1 (end address).
SAT Saturation.
SHIFT Shifting Operation.
sp 20-Bit Stack Pointer.
SP LIT/ M UX Split/Mult iplexer. Routes the appr opriate ALU/ACS, BMU, and ADDER/ACS outputs to the appropriate
accumulator.
SWAP MUX Swap Multi plexer. Route s the appropri ate data to the appropriate multiplier input .
SYS System Control and Cache.
vbase 20-Bit Vector Base Offset Register.
vsw 16-Bit Vite rbi Support Word. Associated with the traceback encoder.
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4 Hardware Architecture (continued)
4.2 DSP16000 Core A rchitectural Overview (continued)
Table 2. DSP16000 Core Block Diagram Le gend (continued)
4.2.5 Core Block Diagram (continued)
4.3 Device Reset
The DSP16411 has three negative-a ssertion external
reset input pins: RSTN, TRST0N, and TRST1N. RSTN
is used to reset bot h CORE0 and CORE1. The primary
function of TRST0N and TRST1N is t o reset the JTAG0
and JTAG1 controllers.
4.3.1 Reset After Powerup or Power Interru ption
At initial pow erup or if power is interrupted, a reset is
required and RSTN, TRST0N, and TRST1N must all
be asserted (low) simultaneously for at l east seven CKI
cycles (see Section 11.4 on page 278 for details). The
TRST0 N and TRS T1N pins mus t be asserted even if
the JTAG controllers are not used by the application.
Failure to pr operly reset the device on powerup or after
a power interruption can lead to a loss of communica-
tion wit h the DSP16411 pins.
4.3.2 RSTN Pin Reset
The device is properly reset by asserting RSTN (low)
for at least seven CKI cycles and then deasserting
RSTN. Reset initiali zes the st ate of user registers, syn-
chroniz es the internal clocks, and initiates code execu-
tion. See Secti on 6.2.4, beginning on page 249, for the
values of t he user registers after reset.
After RSTN is deasserted, there is a delay of several
CKI cycles before the DSP16000 cores begin execut-
ing instructions (see Section 11.5 on page 279 for
details). The state of the EXM pin on the rising edge of
RSTN controls the boot program address for both
cores, as described in Section 5 on page 208.
x32-Bit Multiplier Input Register.
XAAU X-Memory Space Address Arithmet ic Unit.
XAB X-Memory Space Address Bus.
XDB X-Memory Space Dat a Bus.
y32-Bit Multiplier Input Register.
YAAU Y-Memo ry Space Address Ari thmetic Unit.
YAB Y-Memo ry Space Address Bus.
YDB Y-Memory Space Data Bus.
Symbol Name
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4 Hardware Architecture (continued)
4.3 Device Reset (continued)
4.3.2 RSTN Pin Reset (continued)
Table 3 defines the states of th e output and bidirection al pins both during and after reset. It does not include the
TDO0 and TDO1 output pins because their state is not affected by RSTN. The state of TDO0 and TDO1 are
affected only by the JTAG0 and JTAG1 cont rollers.
4.3.3 JTAG Contr oller Reset
The recommended m etho d of re setting the JTAG controllers is to assert RSTN, TRS T0N, and TRST1N low simul-
taneously. An alternate method is to clock TCK〈0,1〉 through at least five cycles with TMS〈0,1〉 held high. Both
methods ensure that the user has control of the device pins. JTAG controller reset places it in the test logic reset
(TLR) state and does not initialize user registers, synchronize internal clocks, or initiate code execution unless
RSTN is also asserted (see Section 6.2 .4 on page 249).
Table 3. State of Device Output and Bidirectional Pins During and After Reset
Type Pin Condition State of Pin
During Reset (RSTN = 0) Initial State of Pin
After Reset (RSTN = 1)
Output PIBF, PINT — logic low logic low
PRDY PRDYMD = 0 logi c l ow logi c low
PRDYMD = 1 logic high logic high
EACKN, EION, ERAMN,
EROMN, ERWN0, ERWN1 INT 0 = 0
(deasserted) logic high ini tial inactive state
INT 0 = 1
(asserted) 3-state
POBE — logic high logic high
SOD0, SOD1 — 3-state 3-state
ECKO INT0 = 0
(deasserted) logi c low CKI/2
INT 0 = 1
(asserted) 3-state
EA[18:0]†
† The output/bidirectional pins EA[18:0], ESEG[3:0], ED[31:0], and PD[15:0] include bus hold circuits. If BHEDIS (ECON1[12]—Table 61 on
page 112) = 0, the bus hold circuits on EA[18:0], ESEG[3:0], and ED[31:0] are activated. If BHPDIS (ECON1[13]) = 0, the bus hold circuits on
PD[15:0] are activated. The bus hold circuits are enabled and activated (BHEDIS = BHPDIS = 0) during and after reset. Activated bus hold c ir-
cuits affect the electrical characteristics of the associated pins. See Section 10.1, beginning on page 268, and Table 18 3 on page 267 for
details.
INT 0 = 0
(deasserted) logi c low initia l i nactiv e state
INT 0 = 1
(asserted) 3-state
ESEG[3:0]†INT 0 = 0
(deasserted) logi c low logic low
INT 0 = 1
(asserted) 3-state
Bidirectional
(Input/Output) IO0BIT[6:0], IO1BIT[6:0],
PD[15:0]†, SICK0, SICK1,
SIFS0, SIFS1, SOCK0,
SOCK1, SOFS0, SOFS1,
TRAP
— 3-state configured as input
ED[31:0]†EYMODE = 0 3-state 3-state
EYMODE = 1 output output
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps
Each core in the DSP16411 supports the following
interrupts and traps:
26 hardware interrupts with three levels of user-
assign ed priority:
— 1 core-to-core interrupt.
— 10 general DMAU interrupts.
— 1 D MAU interrupt under control of the o ther core.
— 4 SIU interrupts.
— 3 PIU interrupts.
— 1 MGU interrupt.
—2 timer interrupts.
— 4 external interrupt pins.
64 software interrupts for each core, generated by
the executi on of an ic al l IM6 instructi on .
The TRA P pin.
The core-to-core trap.
Because the DSP16000 core support s a maximum of
20 hardware interrupts and the D SP164 11 provides
26 hardware interrupts, each core has an associated
programma ble interrupt multiplexer (IMUX〈0,1〉).
The interrupt and trap vectors are in contiguous loca-
tions in memory, and the base (starting) address of the
vectors is configurab le in the core’s vbase register.
Each interrupt and trap source is preassigned to a
unique vector offset that differentiates its service rou-
tine.
The core must reach an interruptible or trappable state
(completion of an interruptible or trappa ble instruction)
before it services an interrupt or trap. If the core ser-
vices a n inte rru pt or trap, it saves the contents of it s
program counter (PC) and begins executing instruc-
tions at the corresponding location in its vector ta ble.
Fo r i n terr u p ts, th e co r e saves its PC in its program
interrupt (pi) register. For traps, the core saves its PC
in its program trap (ptrap) register. After servicing the
interrupt or trap, the servicing routine must return to the
interrupted or trapped program by executing an ireturn
or treturn instruction.
The core’s ins register (see Table 8 on page 32) con-
tains a 1-bit status field for eac h of its hardware inter-
rupts. If a hardware interrupt occurs, the core sets the
corresponding ins f ield to indicate that the interrupt is
pending. If the core services that interrupt, it clears the
corresponding ins field. The psw1 register (see
Table 10 on page 35) includes control and status bits
for the core’s hardware inter rupt logic.
If a hardware interrupt is disabled, the core does not
service it. If a ha rdware interrupt is e nabled , the core
services it according to i ts priority. Device reset glo-
bally disables hardware interrupts. A n application can
globall y enable or disable hardware interrupts and can
individually enable or disable each hardware interrupt.
An appl ication globally enables hardware interrupt s by
executing the ei (enable interrupts) instruction and glo-
bally disables th em by executing the di (disable inter-
rupts) instruction. (Wit hin an interrupt service ro utine
(ISR) , the execution of an ireturn instruction also glo-
bally enable s hardware interrupts.) An application can
individually enable a hardware interrupt at an assigned
priority or individu ally disable a hardware interrupt by
configu ring the inc0 or inc1 register (see Table 7 on
page 31).
Software interrupts emulate hardware interrupts. The
core services softwar e interrupts even if hardware
interrupts are globally disabled.
A trap is similar to an interrupt but has the highest pos-
sible priority. An app lication cannot disable traps by
executing a di instruction or by any other means. Traps
do not nest, i.e., a trap service routine (TSR) cannot be
interrupted or trapped. A trap does not affec t the state
of the psw1 register.
The
DSP16000 Digital Signal Processor Core
Informa-
tion Manual provides an extensive discussion of inter-
rupts and traps. T he rem ainder of Section 4.4
describ es the interrupts and trap s for the DSP164 11.
4.4. 1 Hardware Int erru pt Lo gi c
Figure 3 on page 26 illust r at e s th e p ath of eac h in ter-
rupt from its generating peripheral or pin to the interrupt
logic of CORE0 and CORE1. S ome of the interrupts
conn ect directly to the cores, and others connect via
the IMUX〈0,1〉 block. Som e of the interrupts are spe-
cific to a core, and some are commo n to both cores.
The program me r can configure IMUX〈0,1〉 using the
corresponding imux register. T he program m er can
divide proces sing of the multiplexed interru pts PIBF,
POBE, S〈O,I〉INT〈0,1〉, DSINT[3:0], DDINT[3:0],
DMINT[5:4], and INT[3:2] between CORE0 and
CORE 1, or cause some of these interrupts to be com-
mon to both cores by defining the fields in each core’s
imux register. See Section 4.4.2 on page 28 for
details on interrupt multiplexing.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.1 H ardwar e Interrup t Logi c (continued)
Interrupt Block Diagram
† Th ese inte rrupts are specific to a core, no t common to both cores.
‡ Each of the MXI[9:0] interrupts can be either specific to a core or common to both cores, determined by how each interrupt is con fig ur e d in
imux (see Table 5 on page 28).
Figure 3. CORE0 and CORE1 Interrupt Logic Block Diagram
TIMER0_0
IMUX0
MGU0
PIUDMAU
CORE0 CORE1
IMUX1
MGU1
TIMER1_0 TIMER0_1 TIMER1_1
PIBF (PIU)
POBE (PIU)
INT[3:2]
DSINT[3:0], DDINT[3:0], DMINT[5:4]
S〈O,I〉INT〈0,1〉
10
4
XIO†
MXI[9:0]‡XIO†
10 10
MGIBF†SIGINT†
INT[1:0]
PHINT MXI[9:0]‡MGIBF†
SIGINT†DMINT[5:4]PHINT
TIME0†TIME1†TIME0†TIME1†INT[1:0]
DMINT[5:4]
2
2
INT[1:0]
(SIU〈0,1〉)
inc0
imux
KEY: PROGRAM-ACCESSIBLE REGISTER
S
2
inc1
ins
inc0
inc1
ins
imux
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.1 H ardwar e Interrup t Logi c (continued)
Table 4 summarizes each hardware interrupt in the DSP16411, including whether it is internal or external, which
module generates it, and a brief description. For details on the operation of each internal interrupt, see the section
that describes the correspondi ng block.
Table 4. H ardw are In terrupts
Interrupt Type Name Description
DSINT0 Internal DMAU Source Inter rupt for SWT0 (for SIU0) Channel SWT0† source ( output) int errupt request.
DDINT0 Internal DMAU Des ti nation Inter rupt for SWT0 (for SIU0) C hannel SWT0† desti natio n (i nput) interrupt r equest.
DSINT1 Internal DMAU Source Inter rupt for SWT1 (for SIU0) Channel SWT1† source (output) interrupt request.
DDINT1 Internal DMAU Des ti nation Inter rupt for SWT1 (for SIU0) C hannel SWT1† desti natio n (i nput) interrupt r equest.
DSINT2 Internal DMAU Source Inter rupt for SWT2 (for SIU1) Channel SWT2† source (output) interrupt request.
DDINT2 Internal DMAU Des ti nation Inter rupt for SWT2 (for SIU1) C hannel SWT2† desti natio n (i nput) interrupt r equest.
DSINT3 Internal DMAU Source Inter rupt for SWT3 (for SIU1) Channel SWT3† source (output) interrupt request.
DDINT3 Internal DMAU Des ti nation Inter rupt for SWT3 (for SIU1) C hannel SWT3† desti natio n (i nput) interrupt r equest.
DMINT4 Internal DMAU Interrupt for MMT4 Channel MMT4‡ in terrupt request.
DMINT5 Internal DMAU Interrupt for MMT5 Channel MMT5‡ in terrupt request.
INT[3:0] External External Int errupt Requests An external device ha s request ed service by assertin g
the corresponding INT[3:0] pin (0-to-1 transition).
MGIBF Int ernal MGU Input Buffer Ful l The MGU input buffer (mgi) is full.
PHINT Inter nal PIU Host I nterrupt The host sets the HINT field (PCON[4]).
PIBF Internal PIU Input Buffer Full PDI cont ains dat a from a previou s host write operat ion.
POBE Internal PIU Output Buffer Empty The data in PDO has been re ad by the host.
SIGINT Int ernal Signal Inter rupt (Co re-to-Core) The other cor e sets its signal[0] field.
SIINT0 Internal SIU0 Input Interrupt Based on the II NTSEL[1:0] field (SCON10[12:1 1]),
asserted if:
Input frame sync detected.
Input subframe trans fer complete.
Input channe l t ransfer com plete.
Input error occurs.
SIINT1 Internal SI U1 Input Interrupt
SOINT0 Internal SIU0 Output In terrupt Based on the OINTSEL[1:0] f ield (SCON10[14:13]):
Out put frame sync detect ed.
Output subframe transfer complete.
Output channel transfer complete.
Output error occurs.
SOINT 1 Int ernal SI U1 Ou tput Interrupt
TIME0 Internal TIMER0 Delay/Interval Reached TIMER0 has reached zero count.
TIME1 Internal TIMER1 Delay/Interval Reached TIMER1 has reached zero count.
XIO Inter nal Core-to- Core DMAU Int errupt Based on the other cor e’s XIOC[1:0] fiel d:
Zero (l ogic low).
DMINT4 (MMT4 transfer complete).
DMINT5 (MMT5 transfer complete).
† An SWT channel is a single-word transfer channel used for both input and output by an SIU. It transfers single words (16 bits).
‡ A n M MT cha nn el is a mem or y-t o-m emo r y chan ne l us ed by the core s t o co py a bloc k f rom an y a rea o f me mo ry to an y othe r are a of me mory . It
tra nsfers single words (16 bits) or double words (32 bi ts).
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.2 Hardware Interrupt Multiplexing
The total number of DSP16411 hardware interrupt sources (26) exceeds the number of interrupt requests sup-
ported by the DSP16000 core (20). Therefore, each core includes an interrupt multiplexer block (IMUX ) and asso-
ciated control register (imux) to permit the 26 interrupts to be multiplexed into the 20 available hardware interrupt
requests. Each core supports ten dedicated interrupt requests. Each core’s IMUX block multiplexes the remaining
16 hardware requests into the ten remaining hardware interrupt reques t lines.
Table 5 describes the imux registe r and Figure 4 on page 29 ill u stra tes the IMUX block.
Table 5. im ux (Interrupt Multiplex Cont rol) Register
15—14 13—12 11—10 9—8 76543210
XIOC[1:0]†Reserved IMUX9[1:0] IMUX8[1:0] IMUX7 IMUX6 IMUX5 IMUX4 IMUX3 IMUX2 IMUX1 IMUX0
Bit Field Controls
Multiplexed
Interrupt
Value Interrupt
Selected Description R/W Reset
Value
15—14 XIOC[1:0]†XIO 00 0 (logic low) —R/W00
01 DMINT4 DMAU interrupt for MMT4.
10 DMINT5 DMAU interrupt for MMT5.
11 Reserved Reserved.
13—12 Reserved — 0 — Reserved—write with zero. R/W 0
11—10 IMUX9[1:0] MXI9 00 INT3 Pin. R/W 00
01 POBE PIU output buffer empty.
10 PIBF PIU input buffer full.
11 Reserved Reserved.
9—8 IMUX8[1:0] MXI8 00 INT2 Pin. R/W 00
01 POBE PIU output buffer empty.
10 PIBF PIU input buffer full.
11 Reserved Reserved.
7 IMUX7 MXI 7 0 SIINT1 SIU1 input int err upt. R/W 0
1 DDINT2 DMAU destination int err upt for SWT2 (SIU1).
6 IMUX6 MXI 6 0 SOINT1 SIU1 output int err upt. R/W 0
1 DSINT2 DMAU sour ce interrupt for SWT2 (SIU 1).
5 IMUX5 MXI 5 0 SIINT0 SIU0 input int err upt. R/W 0
1 DDINT0 DMAU destination int err upt for SWT0 (SIU0).
4 IMUX4 MXI 4 0 SOINT0 SIU0 output int err upt. R/W 0
1 DSINT0 DMAU sour ce interrupt for SWT0 (SIU 0).
3 IMUX3 MXI3 0 DDINT2 DMAU destination interrupt for SWT2 (SIU1). R/W 0
1 DDINT3 DMAU destination int err upt for SWT3 (SIU1).
2 IMUX2 MXI2 0 DSINT2 DMAU source interrupt for SWT2 (SIU1). R/W 0
1 DSINT3 DMAU sour ce interrupt for SWT3 (SIU 1).
1 IMUX1 MXI1 0 DDINT0 DMAU destination interrupt for SWT0 (SIU0). R/W 0
1 DDINT1 DMAU destination int err upt for SWT1 (SIU0).
0 IMUX0 MXI0 0 DSINT0 DMAU source interrupt for SWT0 (SIU0). R/W 0
1 DSINT1 DMAU sour ce interrupt for SWT1 (SIU 0).
† The XIOC[1:0] field controls the XIO interrupt for the other core.
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.2 Hardware Interrupt Multiplexing (continued)
IMUX Block Diagram
Figure 4. IMUX Block Diagram
MUX
MXI0
DSINT0
DSINT1
I
MUX0 (imux[0])
XIO (TO OTHER CORE)
0
DMINT4
DMINT5
XIOC[1:0] (imux[15:14])
MXI8
INT2
POBE
PIBF
IMUX8[1:0] (imux[9:8])
MXI9
INT3
POBE
PIBF
IMUX9[1:0] (imu x[11:10])
MXI1
DDINT0
DDINT1
IMUX1 (imux[1])
MXI2
DSINT2
DSINT3
IMUX2 (imux[2])
MXI3
DDINT2
DDINT3
IMUX3 (imux[3])
MXI4
SOINT0 DSINT0
IMUX4 (imux[4])
MXI5
SIINT0 DDINT0
IMUX5 (imux[5])
MXI6
SOINT1 DSINT2
IMUX6 (imux[6])
MXI7
SIINT1 DDINT2
IMUX7 (imux[7])
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
IMUX
〈
0,1
〉
2
2
2
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.3 Clearing Core Interrupt Reque sts
Internal hardware interrupt signals are pulses that the core latches into its ins register (see Section 4.4.7 on
page 32). Therefore, the user software need not clear the interrupt request. However, in the case of the PIU host
interrupt, PH INT, the user softwa re must clear the HINT field (PCON[4] ) to allow the host to request a subsequent
interrupt. See Sec tion 4.15.7 on page 153 for details.
4.4.4 H ost Interrupt Ou t put
The DSP16411 provides an interrupt output pin, PINT, that can interrupt a host processor connected to the PIU. A
core can assert this pin by setting the PINT field (PCON[3]). The host must clear the PINT field to allow a core to
request a subseque nt interrupt. See Section 4.15.7 on page 153 for details.
4.4.5 Glob a lly En a bli ng and Disabl in g Ha rd ware Interrupts
A device reset globally disables interrupts, i.e., the core does not service interrupts by default after reset. The
application must execute an ei instruction to globally enable interrupts, i.e ., to caus e the core to service interrupts
that are individually enabled. S ection 4.4.6 on page 31 describes individ ually enabling and disabl ing
interrupts. Ex ecuting the di instruction globally disables interrupts.
The core automatically globally disables interrupts if it begins ser vicing an interrupt, i.e., interrupt nesting is dis-
abled by default. When the ireturn instruction that the programmer must place at the end of the ISR is executed,
the core automatically globally re-enables interrupts. Therefore, the programmer does not need to explicitly re-
enable interrupts by executing an ei instruction before exiting the ISR. An interrupt service routine (ISR ) can allow
nesting, i.e., c an be i nterrupted by a hi gher-pri ority interrupt, if it globally enables interrupts in the correct sequence
as descri bed in Section 4.4.11 on page 35, Nesting Interrupts.
The one-bit IEN field (psw1[ 14]—see Table 10 on page 35) is cleared if hardware interrupts are globally
disabled. T he IEN field is set if interrupts are globally enabled .
Table 6 s ummarizes global disabling and enabling of hardware interrupts.
Table 6. G lobal Disablin g and Enabling of Hardw are Interru pts
Condition Caused By Indicated By Effect
Ha rd w a re in te rr u p ts
globally† disabl ed
Device re se t
Execution of a di instruction
The core begins to service an inte rrupt
IEN (psw1[14]) = 0 Core does not ser vice
interrupts.
Ha rd w a re in te rr u p ts
globally† enabled
Execution of an ei instruction
Execution of an ireturn instruct ion
IEN (psw1[14]) = 1 Core services individually
enabled interrupts.
† With the exce ption of device reset, CORE0 an d CORE1 are independent with respect to global disabli ng and enabling of hardware interrupts.
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.6 I ndi vi dually En abl i ng , Disabl ing, an d P rio ri tizi ng H ardware Inter rupts
An application can individually disabl e a hardware interrupt by clearing both bits of its correspondi ng 2-bit field in
the inc0 or inc1 register (see Table 7). Reset clears t he inc0 and inc1 registers, individually disabling all hardware
interrupts by default . An application can individually enable a hardware interrupt at one of three priority levels by
setting one or both bits of its correspond ing 2-bit field in the inc0 or inc1 register.
The following are the advantages of interrupt prioritization:
An ISR can service concurrent interrupts according to their pr iority.
Interrupt nesting is supported, i.e., an interrupt can interrupt a lower-priority ISR. See Section 4.4.11 on page 35
for details on interrupt nesting.
If mul tiple concurrent interrupts with the same assi gned priority occur, the core first se rvices the interrupt tha t has
its status fie ld in the relative least sig nificant bit location of the ins register (see Table 8 on page 32), i.e., the core
first services the interrupt with the lowest vector address (see Table 9 on page 33).
Note: If interrupts are globally enabled (see Section 4.4.5 on page 30), an application must not change inc〈0—1〉,
because doing so can cause a potential race condition between the detection of the interrupts and the deter-
mination of their relative priorities. Prior to changing inc〈0—1〉, the applicati on must globally disable inter-
rupts by executing a di instruction. After changing inc〈0—1〉, the application can globally re-enable interrupts
by executing an ei ins truction.
The following code segment is an example of properly changing inc〈0—1〉:
di // Globally disable interrupts (default after reset).
inc1=0x00001 // Enable MGIBF at level 1 priority.
ei // OK to globally re-enable interrupts.
di // Before changing inc1, first globally disable interrupts.
inc1=0x00006 // Change MGIBF priority to level 2...
// Enable SIGINT at level 1 priority.
ei // OK to globally re-enable interrupts.
Table 7. inc 0 and inc1 (Interrupt Control) Register s 0 and 1
19—18 17—16 15—14 13—12 11—10 9—8 7—6 5—4 3—2 1—0
inc0 INT1[1:0] INT0[1:0] DMINT5[1:0] DMINT4[1:0] MXI3[1:0] MXI2[1:0] MXI1[1:0] MXI0[1:0] TIME1[1:0] TIME0[1:0]
inc1 MXI9[1:0] MXI8[1:0] MXI7[1:0] MXI6[1:0] MXI5[1:0] MXI4[1:0] PHINT[1:0] XIO[1:0] SIGINT[1:0] MGIBF[1:0]
Field Value Description R/W Reset
Value
INT〈0—1〉[1:0]
DMINT〈4—5〉[1:0]
MXI〈0—9〉[1:0]†
TIME〈0—1〉[1:0]
PHINT[1:0]
XIO[1:0]
SIGINT[1:0]
MGIBF[1:0]
00 Di sable the selected interrupt (no priority). R/W 00
01 Enable the sele cted interrup t at priority 1 (lowest) .
10 Enable the sele cted interrup t at priority 2.
11 Enable the sele cted interrup t at priority 3 (highest).
†See Table 5 on page 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.7 Hardwar e Interrupt Status
If a hardware interrupt occurs, the core sets the corre-
sponding bit in the ins register ( Table 8) to indica te t hat
the interrupt is pending. If the core services the inter-
rupt, it clears the ins bit. Alternatively , if the application
uses interrupt polling (Section 4.4.13 on page 37), the
application program m ust explicitly clear the ins bit b y
writing a 1 to that b it and a 0 to every other ins bit.
Writing a 0 to an ins bit leaves that bit unchanged. A
reset clears the ins register, indicating that no inter-
rupts are pending.
If a hardware interrupt occurs, the core sets its ins bit
(i.e., latches the interrupt as pending) regardless of
whether the interrupt is enabled or disabled. If a hard-
ware interrupt occurs while it is disabled and the inter-
rupt is later enabled, the core services the inte rrupt
after servicing any other pending interrupts of equal or
higher priority.
Note: The DSP16000 core globally disables interrupts
when it begins executing instructions in the vec-
tor table. If the ISR does not globally enable
interrupts by following t he procedure specif ied in
Section 4.4.11 on page 35, Nesti n g Interrupts,
and the same interrupt reocc ur s while the core is
executing t he ISR, the interrupt is not latched
in to ins and is theref ore not recognized by the
core.
4.4.8 Interrupt and Trap V ector Table
The interrupt and trap vectors for a core are in contigu -
ous locations in memory. The base (starting) address
of the vectors is configurable in the core’s vbase
register. Each interrupt and trap source is pre-
assig ned to a unique vector offset within a 352-word
vector table (see Table 9 on page 33). T he program -
mer can place at the vector location an instruction that
branches to an interrupt servic e routine (ISR) or trap
service routine (TSR). A fter servicing the interrupt or
trap, the ISR or TSR must return to the interrupted or
trapped program by executing an ireturn or treturn
instruct ion. Al ternatively, the programme r can place at
the vector location up to four words of instructions that
service the interrupt or trap, the last of whic h must be
an ireturn or treturn.
Table 8. ins (Interrupt Status) Regi ster
19 18 17 16 15 14 13 12 11 10
MXI9 MXI8 MXI7 MXI6 MXI5 MXI4 PHINT XIO SIGINT MGIBF
9 8765432 1 0
INT1 INT0 DMINT5 DMINT4 MXI3 MXI2 MXI1 MXI0 TIME1 TIME0
Field Value Description R/W Reset Value
MXI〈0—9〉†
PHINT
XIO
SIGINT
MGIBF
INT〈0—1〉
DMINT〈4—5〉
TIME〈0—1〉
0 Read—corresponding interrupt not pending.
Wr ite—no effect. R/Clear 0
1 Read—corresponding interrupt is pending.
Wr it e—clears bit and changes correspondi ng interrupt status to not
pending.
†See Ta ble 5 on page 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.8 Interrupt and Trap Ve ctor Table (continued)
Table 9. Interrup t and Trap Vector Table
Vector Description Vector Address†Priority
Hexadecimal Decimal
Reserved vbase + 0x0 vbase + 0 —
PTRAP‡vbase + 0x4 vbase + 4 6 (Highest)
UTRAP§vbase + 0x8 vbase + 8 5
Reserved vbase + 0xC vbase + 12 —
TIME0 vbase + 0x10 vbase + 16 0—3††
TIME1 vbase + 0x14 vbase + 20 0—3††
MXI0 (DSINT0 or DSINT1‡‡)vbase + 0x18 vbase + 24 0—3††
MXI1 (DDINT0 or DDINT1‡‡)vbase + 0x1C vbase + 28 0—3††
MXI2 (DSINT2 or DSINT3‡‡)vbase + 0x20 vbase + 32 0—3††
MXI3 (DDINT2 or DDINT3‡‡)vbase + 0x24 vbase + 36 0—3††
DMINT4 vbase + 0x28 vbase + 40 0—3††
DMINT5 vbase + 0x2C vbase + 44 0—3††
INT0 vbase + 0x30 vbase + 48 0—3††
INT1 vbase + 0x34 vbase + 52 0—3††
MGIBF vbase + 0x38 vbase + 56 0—3††
SIGINT vbase + 0x3C vbase + 60 0—3††
XIO vbase + 0x40 vbase + 64 0—3††
PHINT vbase + 0x44 vbase + 68 0—3††
MXI4 (SOINT0 or DSINT0‡‡)vbase + 0x48 vbase + 72 0—3††
MXI5 (SIINT0 or DDINT0‡‡)vbase + 0x4C vbase + 76 0—3††
MXI6 (SOINT1 or DSINT2‡‡)vbase + 0x50 vbase + 80 0—3††
MXI7 (SIINT1 or DDINT2‡‡)vbase + 0x54 vbase + 84 0—3††
MXI8 (INT2, POBE, or PIBF ‡‡)vbase + 0x58 vbase + 88 0—3††
MXI9 (INT3, POBE, or PIBF ‡‡)vbase + 0x5C vbase + 92 0—3††
ica ll 0 §§ vbase + 0x60 vbase + 96 —
icall 1 vbase + 0x64 vbase + 1 00 —
—
icall 62 vbase + 0x158 vbase + 344 —
icall 63 vbase + 0x15C vbase + 3 48 —
†vbase cont ai ns the base addres s of th e 352-word vector tabl e.
‡ Driven by TRAP pin (see Section 4.4.10 on page 34) or core-t o-core trap (see Section 4.8.1 on page 47 ).
§ Reserved for HDS.
†† The programmer specifies the relative priority levels 0—3 for hardware interrupts via inc0 and inc1 (see Table 7 on pa ge 31 ). Level 0 indicates a dis-
abled interrupt. If multiple concurrent interrupts with the same assigned priority occur, the core first services the interrupt that ha s i t s status fi eld i n the
r elati ve l e ast si gni fi cant bit loc ati on o f the ins regi st er (s ee Table 8 on page 32); i.e., the core first services the interrupt with the lowest vector address.
‡‡ The choice of interrupt is selected by the imux register (see Table 5 on page 2 8).
§§ Re served for system servi ces.
…
…
…
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.9 Software Interrupts
Software interrupts emulate hardware interrupts. A
software interrupt is always enable d and has no
assigned priority and no corresponding field in the ins
register. A program causes a software interrupt by exe-
cuting an icall IM6 instruction, where IM6 is replaced
with 0—63. When a software interrupt is serviced, the
core saves th e contents of PC in th e pi register a nd
transfers control to the interrupt vecto r defined in
Table 9 on page 33.
CAUTION: If a software interrupt is inserted into an
ISR, it is explicitly nested in the ISR and
therefore the ISR must be structured for
nesting. See Section 4.4.11 on page 35
and the
D SP160 00 Digital Signal Pro-
cessor Core
Inform at io n Manua l for
more information about nesting .
4.4.10 INT[3:0] and TRAP Pins
The DSP16 411 provides four positive-assertion edge-
detected interrupt pins (INT[3:0]) and a bidirectional
positive-assertion edge-d etected trap pin (TRAP).
The TRA P pin is used by an application to gain con trol
of both processors for asynchronous event handling,
typically for catastrophic error recovery. It is a 3-state
bidirectional pin that connects to both cores and both
HDS blocks. TRAP is connected directly to both cores
via the PTRAP signal. After reset, TRAP is configured
as an input; it can be configured as an output under
JTAG control to suppor t HDS multiple-device debug-
ging.
Figure 5 is a functional timi ng diagram for the INT[3:0]
and TRAP pins. A low-to-high transition of one of these
pins asserts the corresponding interrupt or trap.
INT[3: 0] or TRAP must be held high for a minimu m of
two CLK cycles and must be he ld low for at least two
CLK cycles before being reasserted. I f INT[3:0] or
TRAP is as serted and stays high, the core services the
interrupt or trap only once.
A minim um of four cycle s1 after INT[3:0] or PTRAP is
asserted, the c ore services the interrupt or trap by exe-
cuting instruc tions starting at the vector location as
defined in Table 9 on page 33. In the case of PTRAP, a
maximum of three instructions are allowed to execute
before the core services the trap.
Functional Timing for INT[3:0] and TRAP
Fi gure 5. Func tion al Timing for INT [3:0] and TRAP
1. The number of cycles depends on the number of wait-states incurred by the interrupted or trapped instruction.
ECKO
†
AB
INT[3:0]/TRAP
‡
† ECKO is programmed to be the internal clock CLK (the ECKOB[1:0] field (ECON1[3:2]—see Table 6 1 on page 112) i s programmed to 00 an d
the E CKO A[1:0] field (ECON1[1:0]) is programmed to 01).
‡ The INT[3:0] or TRAP pin must be held high for a minimum of two CLK cycles and must be held low for a minimum of two CLK cycles be fore
being reasserted.
Notes:
A. The DSP16411 synchronizes INT[ 3:0] or TRAP on the falling ed ge of the inter nal clock CLK.
B. A minimum four-cycle delay before the core services the interrupt or trap (executes instructions starting at the vector location). For a trap, the
core executes a maxi mum of th ree instructions before it se rvice s the trap.
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.11 Nesti ng Interrupts
The psw1 register (see Table 10) contains the IPLC[ 1: 0] and IPLP[1:0 ] fields that are used for interrupt
nesting. See the
DSP16000 Digital Signal Process or Core
Information M anual for details on these fields.
Table 10. psw1 (Processor Status Word 1) Register
15 14 13—12 11—10 9—7 6 5—0
Reserved IEN IPLC[1:0] IPLP[1:0] Reserved EPAR a[7:2]V
Bit Field Value Description R/W Reset
Value†
15 Reserved 0 Reserved—write with zero. R/W 0
14 IEN‡0 Ha rdware inter rupts are gl obally disabled. R 0
1 Ha rdware inter rupts are gl obally enabled.
13—12 IPLC[1:0] 0 0 Current hardware int errup t priori ty l evel is 0; core handles pending int errupts of
priorit y 1, 2, or 3. R/W 00
01 Current hardware int errup t priori ty l evel is 1; core handles pending int errupts of
priority 2 or 3.
10 Current hardware int errup t priori ty l evel is 2; core handles pending int errupts of
priority 3 only.
11 Current hardware int errup t priori ty l evel is 3; core does not handle any pending
interrupts.
11—10 IPLP[1:0] 00 Previous hardware interrupt priority level§ was 0. R/W XX
01 Previous hardware interrupt priority level§ was 1.
10 Previous hardware interrupt priority level§ was 2.
11 Previous hardware interrupt priority level§ was 3.
9—7 Reserved 0 Reserved—write with zero. R/W X
6 EPAR 0 Mos t re cent BMU or special function shift resu lt has odd parity. R/W X
1 Mos t re cent BMU or speci al f unction shift result has even parity.
5 a7V 0 The current contents of a7 are not mathematically overflowed. R/W X
1 The current contents of a7 are mathematically overflowed.††
4 a6V 0 The current contents of a6 are not mathematically overflowed. R/W X
1 The current contents of a6 are mathemat ically overflowed.††
3 a5V 0 The current contents of a5 are not mathematically overflowed. R/W X
1 The current contents of a5 are mathemat ically overflowed.††
2 a4V 0 The current contents of a4 are not mathematically overflowed. R/W X
1 The current contents of a4 are mathemat ically overflowed.††
1 a3V 0 The current contents of a3 are not mathematically overflowed. R/W X
1 The current contents of a3 are mathemat ically overflowed.††
0 a2V 0 The current contents of a2 are not mathematically overflowed. R/W X
1 The current contents of a2 are mathemat ically overflowed.††
† In this co l um n, X indi cates unkn own on po werup reset and unaffected on subsequ ent reset.
‡ The user clears this bit by executing a di instructio n and sets it by ex ecuting an ei or ireturn instruction. The core clears this bit whenever it begins to
service an interrupt.
§ Previous int errup t priority level is th e priority level of the int errupt m ost recentl y servi ced pr i or to the curr ent interrupt. This f i el d i s use d for int errupt
nesting.
†† The most recen t D AU result that was wri tten t o that accum ul ator result ed i n m athe m at i cal overflow (LMV ) wi th FS AT = 0.
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.11 Nesti ng Interrupts (continued)
Caution: The procedure for nesting interrupts described below is different than that described in
S e c t ion 5.4.9 o f t h e
DSP16000 Di gital Signal Processo r Core
Information Manua l. The DSP16411
contains version 2 of the DSP16000 core, and the manual describes version 1 of the core. See the
DSP16K V2 Core Nested Interrupt Design Exception
Advisory (AY01-033WINF) for details.
The DSP16000 core automatically globally disables interrupt s when it begins servicing an interrupt, disabling inter-
rupt nesting by d efault. To allow interrupt nesting, the interrupt service routine (ISR) must perform the steps spec i-
fied in the following ISR code example. The code segment highlighted in bold globally enables interrupts in the
proper sequence. This code se gme nt replaces the ei instruction in the ISR code example described in
Section 5.4.11 of the
DSP16000 Digital Signal Processor Core
Information Manual. (The code example in
Section 5.4. 11 of the information manual cont ains additiona l instructions needed if the main body of the ISR use s
cache loops. These instructions hav e been om itted from the following exam ple for simplicity.)
// Save Context:
ISR: push pi // Save pi to stack - needed for nesting.
push psw1 // Save psw1 to stack - needed for nesting.
push cstate // Save cstate to stack - needed for nesting.
cstate=0 // Clear cstate - needed for nesting.
// (The cstate register must be saved and cleared so that, if this ISR has interrupted
// a cache loop and this ISR is interrupted by a higher-priority interrupt, the ireturn
// in the higher-priority ISR returns to this ISR and not to the cache loop.)
// Save (push) any other registers to stack that will be used in BODY below.
// If required, execute noninterruptible user code here.
// Globally enable interrupts -- replaces ei instruction and is needed for nesting.
push psw1 // Save current state of IPLC and IPLP.
pi=JMP // Set jump location for ireturn.
psw1=0x3C00 // Set IPLC=IPLP=3 (set core to highest priority level) so that
// no interrupts will be accepted until psw1 is restored.
ireturn // Globally enable interrupts and goto pi (JMP).
JMP: pop psw1 // Restore psw1 -- restore core to correct priority level.
////////////////////////////////////////////////////////////////////////////////////
// BODY -- Main body of ISR that services the interrupt. Can be interrupted //
// by an interrupt of higher priority. //
////////////////////////////////////////////////////////////////////////////////////
di // Globally disable interrupts for restoring state.
// If required, execute noninterruptible user code here.
// Restore (pop) any other registers from stack that have been saved (pushed).
pop cstate // Restore cstate from stack.
pop psw1 // Restore psw1 from stack.
pop pi // Restore pi from stack.
ireturn // Return from interrupt and globally enable interrupts.
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4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.12 Interrupts an d Cache Usage
If an ISR or TSR uses cache (do or redo) loops, then it must first save the state of the ca che and then restore it
before returning to normal program execution. This is necessary because the interrupt or trap can occur during the
execution of a cache loop. See Section 3.5.2.7 and Section 5.4.11 of the
DSP16000 Digital Signal Processor Core
Information Man ual for details on saving and restoring the state of the cache.
4.4.13 Interrupt Polling
If a core disables an interrupt and tests its ins field, it can poll that interrupt ins tead of automatically servicing
it. This proced ure, however, costs in the amoun t of code that must be written and executed to replace what the
DSP16000 core does by design.
The programmer can poll an interrupt source by checking its pending status in ins. The program can clear an inter-
rupt and change its status from pending to not pending by writing a 1 to its corresponding ins f i eld. This clears the
field and leaves the remaining fields of ins unchanged. The example code segment below polls the MGU input
buff er full (MGIBF):
poll: a0=ins // Copy ins register contents to a0.
a0=a0&0x00000400 // Mask out all but bit 10.
if eq goto poll // If bit 10 is zero, then MGIBF not pending.
... // Interrupt is now pending -- service it.
ins=0x00400 // Clear MGIBF; don’t change other interrupts.
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4 Hardware Architecture (continued)
4.5 Memory Maps
The DSP16000 core is a modified Harvard architecture with sep arate program and data mem ory spaces
(X-memory space and Y-memory spac e). Th e core differentiates between the X- and Y-memory spaces by the
addressing unit used for the access (XAAU vs. YAAU) and not by the physical memory accessed. The core
accesses its X-memory space via its 20-bit X address bus (XAB) and 32-bit X data bus (XDB) . The core accesses
its Y-memory space via its 20-bit Y address bus (YAB) and 32-bit Y data bus (YDB).
The DMAU accesses pr ivat e intern a l memory (TPRAM〈0—1〉) via its 20-bit internal Z address bus (ZIAB) an d
32-bit internal Z data bus (ZIDB) and shared external memory1 (EIO and ERAM) via its 20-bit external Z address
bus (ZEAB) and 32-bit external Z data bus (ZED B).
Although DSP16 411 memory is 16-bit word-addressable, data or instruction widths can be either 16 bits or 32 bits
and applications can access the memorie s 32 bits at a time.
Table 11 summarizes the componen ts of the DSP16411 mem ory. The table specifies the name and size of each
component , whether it is internal or external, whether it is private to a core or shared by both cores, an d in which
memory space(s) i t resides. The five memor y spaces are CORE0’s X -memory space, CORE0’s Y-memory space,
CORE1’s X-memory space, COR E1’s Y-m em ory space, and the DMAU’s Z-memory space.
Table 11. DSP16411 Memory Compo nen ts
The remainder of this section consi sts of the following:
Sect ion 4.5 .1, Privat e Internal Memory, on page 39.
Sect ion 4.5 .2, Shared Internal I/O, on page 39.
Sect ion 4.5 .3, Shared External I/O and Memo ry, on page 39.
Section 4.5.4, X-Memory Map, on page 40.
Section 4.5.5, Y-Memory Maps, on page 41.
Sect ion 4.5 .6, Z -M emo ry Maps, on page 42.
Section 4.5.7, Internal I/O Detailed Memory Map, on page 43 .
1. ZEAB and ZEDB connect to EI O and ER AM through the SEMI.
Type Memory
Component Size CORE0 CORE1 DMAU
X-Memory
Space Y-Memory
Space†X-Memory
Space Y-Memory
Space†Z-Memory
Space†
Private Int ernal TPRAM0 160 Kwords ✓ ✓ ✓
CACHE0 62 words ✓ ✓
IROM0 4 Kwords ✓
TPRAM1 160 Kwords ✓ ✓ ✓
CACHE1 62 words ✓ ✓
IROM1 4 Kwords ✓
Shared Int ernal Internal I/O‡128 Kwords ✓ ✓ ✓
Shared External EIO 128 Kwords ✓ ✓ ✓
ERAM 512 Kwords ✓ ✓ ✓
EROM 512 Kwords ✓ ✓
† Assumes that WEROM is 0 for normal operation. If WEROM is 1, ERAM is replaced by EROM in the memory space, allowing the normally
read-only EROM section to be written. WEROM is discussed in detail in Sectio n 4.5.3 on page 39.
‡ The internal I/O section consists of 2 Kwords of SLM and memory-mapped registers in the SEMI, DMAU, PIU, SIU0, and SIU1 blocks. Only a
s m all portion of the 128 Kwords reserv ed for internal I/O is actually popu lated wit h memory or registers.
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4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.1 Private Internal Memo ry
Each core has its own private internal memories for
program and dat a storage. CORE0 has IROM0,
CACHE0, and TPRAM0. CORE1 has IRO M1,
CACHE1, and TPRAM1. A core cannot directly access
the other core’s private memory. However, the DMAU
can access both TPRAM0 and TPRAM1 and can move
data between these two memories to facilitate core-to-
core communication (see Section 4.8 on page 46).
TPRAM is described in more de tail in Section 4.6 on
page 44. Cache memory is described in detail in the
DSP16000 Digital Signal Processor Core
Information
Manual. IROM contains boot and HDS code and is
described in Section 5 on page 208 .
4.5.2 Shared Interna l I/O
The 128 Kword internal I/O mem ory component is
accessible by both cores in their Y-memory spaces and
by the DMAU in its Z-memory space. Any access to
this memory component is made over the system bus
and is arbitrated by the SEMI. T he internal shared I/O
memory component consists of:
2 Kwords of shared local memory (SLM). SLM can
be used for core-to-core communication (see
Section 4.8 on page 46). SLM is described in
Sect ion 4.1 .4 on page 17.
Mem ory-map ped control and data registers within
the following peripherals:
—DMAU
—SEMI
—PIU
—SIU0
—SIU1
Only a small portion of the 128 Kwords reserved for
internal I/O is actua lly populated with memory or regis-
ters. Any access to the internal I/O memo ry compo-
nent takes multiple cycles to complete. DSP core or
DMAU writes take a minimum of two CLK cycles to
comple te. DSP core or DMAU reads take a minim um
of five CLK cycles to complete.
4.5.3 Shared External I/O and Memory
External I /O and memory consists of three shared com-
ponents: EIO, ERAM, and EROM. EIO and ERAM are
accessible in the Y- memory spaces of both cores and
also in the DMAU’s Z-memory space. EROM is nor-
mally read-only and accessible only in the X-memory
spaces of both cores. If the programmer sets the
WEROM field in the memory-mapped ECON1 register
(see Table 61 on page 112), EROM takes the place of
ERAM in the Y-memory spaces of both cores and in
the DMAU’s Z-memory space (see Secti on 4.5.5 on
page 41 and Section 4.5.6 on page 42 for details).
This allows the EROM compone nt to be written for pro-
gram downl oads to external X memory.
The phys ical size of the EIO, ERAM, and ERO M com -
ponent s can be expanded from the sizes defined in
Table 11 on page 38 by employing the ESEG[3: 0]
pins. The external memory system can use ESEG[3:0]
in eith er of the following ways:
1. ESEG[3:0 ] can be interpreted by the external mem-
ory system as four separate decoded add ress
enable signal s. Each ESEG[3:0 ] pin individually
select s one of four segments for each memory
component. This results in four glueless 512 Kword
(1 Mbyte) ERAM segments, four glueless 512 Kword
(1 M byte) EROM segments, and four glueless
128 Kword (256 KB) EIO segment s.
2. ESEG[3:0 ] can be interpreted by the external mem-
ory system as an extension of the address bus, i.e.,
the ESEG[3:0] pins can be concatenated with the
EAB[18:0] pins to form a 23- bit address. This results
in one glueless 8 Mword (16 Mbytes) ERAM seg-
ment, one glueless 8 Mword (16 Mbytes) EROM
segment, and one glueless 2 Mword (4 Mbytes) EIO
segment.
See Section 4.14.1.5 on page 106 for details on config-
uring the ESEG [3:0] pins.
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4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.4 X-Memo ry M ap
Fi gur e 6. X-Mem or y Ma p
INTERNAL
EXTERNAL
0x00000
0x30FFF IROM
n
(PRIVATE†)
4 Kw ords
.................... ...
0x31000
0x80000
0x2FFFF
XMAP
.......................................
0x7FFFF
16 bits
0xFFFFF
..................................................
EROM (SHARED)‡
0x3FFFE
CACHE
n
(PRIVATE†)
RESERVED
RESERVED
0x27FFF 0x28000
0x3FFBF
62 words
†
n
is 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0
c annot be accessed di rect ly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed direct ly by CORE0. Both TPRAM0 an d
TPRAM 1 can be accessed by the DMAU and PIU.
‡EROM can be configured as four glueless 512 Kw ord (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. See Section 4.14.4.3 begin-
ning on page 11 4 for details. EROM is sh are d, i.e., is access ible by b oth CO RE0 and CORE1, and is also accessible by the DMAU and the
PIU.
RESERVED
TPRAM
n
(PRIVATE†)
160 Kwords
0x30000
0x3FFC0
0x3FFFD
.......
0x3FFBF
0x28000
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4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.5 Y-M em o ry Map s
Figure 7. Y -Memory Maps
†
n
is 0 f or COR E0 or 1 fo r CORE1 . Pr iv ate me mo ry can be a cce ssed by th e co re wit h wh ic h it is asso ci at ed. TPR AM0, CACHE 0 , and I RO M0
cannot be accessed direct ly by CORE1. TPRAM1, CACHE1, and IROM 1 cannot be accessed dire ctly by CO RE0. Both TPR AM0 and
TPRAM1 c an be acce ssed by the DMAU and PIU.
‡ Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See Section 4.5 .7 on pa ge 43 for details.
§ A shared memory space is access ible by both CORE0 and CORE1, and is also accessible by the DMAU and t he PIU.
†† EROM and E RAM can each be configured as four gluel ess 512 K word (1 Mbyte) segments or one 8 Mword (16 Mb ytes) segment. EIO can
be configured as four gluele ss 128 Kword ( 256 Mbyt es) segm ents or one glueless 2 Mword (4 Mbyt es) segm ent. (S ee Section 4.14.4.3 on
page 114.)
CACHE
n
(P RIVATE
†
)
62 words
...................
0x3FFFE
0x3FFFF
RESERVED
0x3FFBF
YMAP
(WER OM = 0)
RESERVED
..............
0x7FFFF
16 bits
EIO
††
(SHARED
§
)
0xFFFFF
...........................................
0x60000
INTERNAL I/O
‡
(SHARED
§
)
ERAM
††
(SHARED
§
)
128 Kwords
TPRAM
n
(PRIVATE
†
)
160 Kwords
..............
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
...................
0x3FFC0
0x3FFFD
0x5FFFF
INTERNAL
EXTERNAL
CACHE
n
(P R IVA T E
†
)
62 words
...................
0x3FFFE
0x3FFFF
RESERVED
0x3FFBF
YMAP
(WER OM = 1)
RESERVED
..............
0x7FFFF
16 bits
EIO
††
(SHARED
§
)
0xFFFFF
...........................................
0x60000
INTERNAL I /O
‡
(SHARED
§
)
EROM
††
(SHARED
§
)
12 8 K w ords
TPRAM
n
(PRIVATE
†
)
160 Kwords
..............
0x40000
0x28000
12 8 K w ords
0x27FFF
0x80000
0x00000
...................
0x3FFC0
0x3FFFD
0x5FFFF
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4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.6 Z-Memory Maps
Figure 8. Z-Memory Maps
INTERNAL
EXTERNAL
† T he CMP[2:0] field in the DMAU addr ess register (SADD〈0—5〉 or DADD〈0—5〉—Table 37 on page 77) or in the parallel address register
(PA—Table 8 0 on page 1 38) selects either TPRAM0 or TPRAM1.
‡ Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See Section 4.5 .7 on pa ge 43 for details.
§ A shared memory space is access ible by both CORE0 and CORE1, and is also accessible by the DMAU and t he PIU.
†† EROM and E RAM can each be configured as four gluel ess 512 K word (1 Mbyte) segments or one 8 Mword (16 Mb ytes) segment. EIO can
be configured as four gluele ss 128 Kword ( 256 Mbyt es) segm ents or one glueless 2 Mword (4 Mbyt es) segm ent. (S ee Section 4.14.1.3 on
page 104.)
...................
0x3FFFF
RESERVED
ZMAP
(WE ROM = 0)
..............
0x7FFFF
16 bits
EIO
††
(SHARED
§
)
0xFFFFF
...........................................
0x60000
INTER NA L I/O
‡
(SHARED
§
)
ERAM
††
(SHARED
§
)
128 Kwords
..............
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
.............................
0x5FFFF
TPRAM0† (160 Kwords)
TPRAM1† (160 Kwords)
or
0x28000
...................
0x3FFFF
RESERVED
ZMAP
(WER OM = 1)
..............
0x7FFFF
16 bits
EIO
††
(SHARED
§
)
0xFFFFF
...........................................
0x60000
INTERNAL I /O
‡
(SHARED
§
)
EROM
††
(SHARED
§
)
12 8 K w ords
..............
0x40000
0x28000
12 8 K w ords
0x27FFF
0x80000
0x00000
.............................
0x5FFFF
TPRAM0† (160 Kw ords )
TPRAM1† (160 Kw ords )
or
0x28000
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4 Hardware Architecture (continued)
4.5 Memory Maps (continued)
4.5.7 Internal I/O Detailed Memory Map
Figure 9 is a detai led view of the 128 Kword internal I/O memory component shown in Figures 7 and 8. It consists
of a 4 Kwo rd block for the memory-mapped registers of each peripheral and a 2 Kword block for the SLM. The
internal I/O memory component is directly accessible by both cores and by the DMAU and PIU. The SEMI controls
access to the internal I/O memory com ponent, which is subject to wait-state and con tention penalties. The SEMI
permits only 16-bit and aligned 32-bit accesses to the internal I/O memory component. The SEMI does not per m i t
misaligned 32-bit accesses (double-word acces ses with an o dd address) for the internal I/O memory component
because they produ ce undefined resu lts. An acces s to the internal I/O memory componen t takes multiple clock
cycles to complete and a core access to the internal I/O memory component causes that core to incur wait-
states. See Section 4.14.7.1 on page 128 for details on system bus performance.
Figure 9. Internal I/O Memory Map
The memory-mapped registers located in their associated peripherals are each mapped to an even address. The
sizes of these registers are 16 bits, 20 bits, or 32 bits. A register that is 20 bits or 32 bits must be accessed as an
aligned double word. A register that is 16 bits can be accessed as a single word with an even address or as an
aligned double word. If a register that is 16 bits or 20 bits is accessed as a double word, the contents of the register
are right-justified. S ection 6 .2.2 on page 231 details the memory-mapp ed registers.
0x40000
0x40FFF
......
16 bits
SEMI REGIST ERS
†Although 4 Kwords are reserved for the memory-mapped registers of each peripheral, not all of the 4 Kwords are actually used.
PIU REGISTERS
DMAU REGISTERS
SIU0 REGISTERS
SIU1 REGISTERS
SLM (2 Kwords)
0x42000
0x42FFF
......
0x44000
0x44FFF
......
0x45800
0x5FFFF
...........................
0x41000
0x41FFF
......
0x43000
0x43FFF
......
0x45000
0x457FF
(4 Kwords†)
(4 Kwords†)
(4 Kwords†)
(4 Kwords†)
(4 Kwords†)
RESERVED
(106 Kwords)
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4 Hardware Architecture (continued)
4.6 Tripo rt Random -A ccess Memor y (TPR AM)
Each core has a priva te block TPRAM (TPRAM 0 and TPRAM1) c onsisting of 160 banks (banks 0—159) of zero
wait-state memory. Eac h bank cons ists of 1K 1 6-bit words and has three separate address and data ports: one
port to the core’ s instruction/coefficient (X-memory) space, a second port to the core’s data (Y-memory) space, and
a third port to the DMAU’s (Z-memory) space. TPRAM is organized int o even and odd interleaved banks for which
each even/odd addres s pair is a 32-bit wide mod ule as illustrated in Figure 10. T he co re’s data buses (XDB and
YDB) and the DMAU’s data bus (ZIDB) are each 32 bits wide, and therefore 32-bit data in the TPRAM with an
aligned (even) address can be accessed in a single cycle. Typi cally, a misaligned double word is accessed in two
cycles.
Figure 10. Interleaved Internal TPRAM
Figure 11 illust rates an example arrangement of single words (16 bits) and double words (32 bits) in memory. It
also illustrates an aligned double word and a misaligned double word. See the
DSP16000 Digital Signal Processor
Core
Information Manual for details on word alignment and misalignm ent wait-states.
Example Memory Ar rangement
Figure 11. Example Memory Arrangement
0x000
0x003
0x001
0x002
0x7FF0x7FE
11 LSBs
16 bits 16 bits
32 bits
EVEN BANK ODD BANK
OF
ADDRESS
11 LSBs
OF
ADDRESS
TPRA M MODUL E
1K x 32 bits
(2 Kwords)
LESS SIGNIFICANT WORDMORE SIGNIFICANT WORD
SINGLE WORDSINGLE WORD0
3
1
5
2
SINGLE WORD
7
4
6LESS SIG NIF ICANT WORD SI NGLE WORD
ADDRESS ADDRESS
ALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
MISALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
KEY:
16 bits
32 bits
EVEN BANK ODD BANK
LEAST SIGNIFICANT WORDMOST SIGNIFICANT WORD2
5MOST SIGNIFICANT WORD
LEAST SIGNIFICANT WORD
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4 Hardware Architecture (continued)
4.6 Tripo rt Random -A ccess Memor y
(TPRAM) (continued)
The core’s X and Y ports and the DMAU ’s Z port can
access separate mod ules within a TPR AM simu lta-
neously with no wait-st ates incurred by the core. If the
same module of TPRAM is accessed from multiple
ports simultaneously, the TPRAM automatically
sequences the accesses in the follo wing priority order:
X port (instruction/coeffi cient), Y port (data), then Z
port (DMAU). This sequencing can cause the core to
incu r a con flict wai t-state. Be caus e the co re must com-
plete any consecuti ve accesses to a module of TPRAM
before the DMAU can access that module , the DMAU
can be blocked from accessing that module for a signif -
ican t n umb er of cycles.
4.7 Shared Local Memory (SLM)
Each core, the DMAU, and the PIU can access SLM
(shared local memory) through the SEM I and the sys-
tem buse s (SAB and SDB). SLM is a 2 K word block
located in the internal I/O memory component . S LM
supp orts both 16-bit and aligned 32-bit accesses, but
not 32-bit misaligned accesses .
The SEMI controls access to the SLM, which is subject
to wait-state and contention penalties; see
Sect ion 4. 14.7.1 on page 128 for details. Bec ause
access to the SLM is subject to wait-state and conten-
tion pena lties, it is not an efficient method for transfer-
ring large blocks of data between the cores. (An
efficient method is to use the DMAU memory -to-mem-
ory (MMT) channel .)
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4 Hardware Architecture (continued)
4.8 Interprocessor Communication
Effective interprocessor (core-to-core) communication
requires synchronizat ion and acce ss to required data.
The following hardware mechanism s suppo rt access
synchronization:
The MGU provides core-to-core interrupts and traps.
The MGU provides message buffer interrupts and
flags.
DMAU interrupts.
The following mechani sms sup port data access:
The MGU can control the occur rence of a synchro-
nizing event (interrupt/trap) for information/s tatus
transfer.
The MGU provides data transfer through its full-
duplex mess age buffers (mgi and mgo).
The DMAU can copy data from one core’s TPRAM to
the other core’s TPRAM.
Cores can directly sh are data in external memory
(ERAM, EROM , or EIO spaces).
Cores can directly sh are data in the SLM.
Figure 12 illus trates the interprocessor communicat ion
logic provided by MGU0 and MGU1.
Inter-Processor Communication Logic in MGU0 and MGU1
Figure 12. Interprocessor Communication Logic in MGU0 and MGU1
CORE0
MGU0
mgi
mgo
signal
pid
PTRAPMGOBF MGIBE MGIBF
FLAGS
DMINT[5:4]
(INTERRUPTS
FROM DMAU)
INTERRUPTS
SIGINTXIO
MUX
BIT 1 BIT 0
TRAP
16
16
CORE1
MGU1
mgi
mgo
signal
pid
PTRAP MGOBFMGIBEMGIBF
FLAGS
INTERRUPTS
SIGINT XIO
BIT 1BIT 0
2
imux
0
2 2
MUX
2
0
IMUX0 IMUX1
KEY: PROGRAM-ACCESSIBLE REGISTERS
imux
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4 Hardware Architecture (continued)
4.8 Interprocessor Communication (continued)
Note: Sharing data directly through external memory
(ERAM, EROM , or EIO spaces) or the SLM is
the least efficient means of interprocessor com-
munication involving large blocks of data. It is
more efficient to perform block memory-to-mem-
ory moves using a DMAU MMT channel. See
Section 4.7 on page 45 for details on SLM and
Section 4.5.3 on page 39 for details on ERAM,
EROM, or EIO.
4.8.1 Core-to-Core Interrupts and Traps
Software executing on one core can interrupt the other
core by writing a 1 to its own MGU signal r egister bit 0
(Table 12). This causes the assertion of the other
core’s SIGINT interrupt sig nal.
The code seg men t below illustrates the code running
on one core to assert the SIGINT interrupt of the other
core:
signal=1 // interrupt other core
Software executing on one core can trap the other core
by writing a 1 to its own signal register bit 1. This
causes th e assertion of the other core’s PTRAP. As
shown in Figure 12 on page 46, the signal register bit 1
is logically ORed with the TRAP pin and the resul t is
input to the other core’s PTRAP signal. (See
Section 4.4.10 on page 34 f or more information on
PTRAP). See the code segment below:
signal=2 // trap other core
To ensure corre ct operation, the execut ion of the
signal register write instruction must be followed by the
execution of any instruction other than another signal
register write in struction.
Table 12. signal Register
4.8.2 Messag e Buffer Data Exchan ge
Each core can use its MGU message buffers to transmit and receive status information to and from the other core.
A core can send a message to another core by writing to its own 16-bit output message register mgo. A core can
receive a message from anot her core by reading its own 16-bit input message register mgi.
If the transmitting core writes mgo, the following steps occur:
1. After t wo instruction cycles of latency, the transmitting core’s message output buffer full (MGOBF) condition flag
is set.
2. After an additional two instruction cycles of latency:
The DSP16411 copies the contents of the transmitting core’s mgo to the receiving core’s input message reg-
ister mgi.
The DSP16411 clears the receiving core’ s mes sage input buffer empty (MGIBE) condition flag.
The DSP16 411 asserts the receiving core’s mes sage input buffer full (MGIBF) interrupt.
15—11 1 0
Reserved SIGTRAP SIGINT
Bit Field Value Description R/W Reset
Value
1 5—11 Reser ved 0 Reserved—wr ite wi th zero. W 0
1 SIGTRAP 0 No effect . W 0
1 T rap the other core by asse rt ing its PTRAP signal.
0 SIGINT 0 No effect. W 0
1 Interr upt the other core by asse rt ing its SIGINT interr upt.
Note: If the pro gram set s the SIGT RAP or SIGINT field, the M GU autom atic al l y clea rs the fiel d after assertin g the trap or int errupt. Th erefore, the pro-
gram must not explicitly clear the field.
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4 Hardware Architecture (continued)
4.8 Interprocessor Communication (continued)
4.8.2 Messag e Buffer Data Exchan ge (continued)
The receiving core can use interrupts or polling to
detect the presence of an incoming message. When
the receiving core reads mgi, t he foll owing steps occur:
1. After o ne in structi on cycle of latency, the DSP1 6411
set s the recei ving core’s MGIBE flag.
2. After an addit ional instruction cycle of latency, the
DSP16411 clears the transmitting core’ s MGOBF
flag.
4.8.2.1 Message Buffer Write Protocol
To ensure an older message has been processed by
the receiving core, the transmitting core must not writ e
a new message to mgo until i ts MGOBF flag is c leared.
The example code segm ent below is executed by the
transmitting core :
if mgobf goto . // Wait for old message
// to be read.
mgo=*r0++ // Write new message.
4.8.2.2 M essa ge Buffer Read Protocol
The receiving core can detect an incoming message by
enabling the MGIBF interrupt in the inc1 register
(Table 153 on page 241). The following is an example
of a simple interrupt service routine for the receiving
core:
ISR: a0h=mgi
*r0++=a0h // Read new message and
// clear MGIBF.
ireturn
As an alt ernati ve to the interrupt- directed message
buffer re ad protocol describe d above, the receiving
core can poll its MGIBE flag for the arrival of a new
mess age. The exam ple code segm ent below is exe-
cuted by the receiving core:
if mgibe goto . // Wait for new
// message.
a0h=mgi
*r0++=a0h // Read new message.
The DSP16 411 can operate a full-duplex commu nica-
tion channel between CORE0 and CORE1, with each
core using its own mgi and mgo reg isters and its own
MGO B F and MGIBE flags. Table 13 illustrates two
code segments for a full-duplex data exchange of
N
words between CORE0 and CO RE1 . Th is segment
exchan ges two words (one input, one out put) between
the two cores every 18 CLK cycles.
Table 13. Full -Duplex Data Transfer Code Through Core -to-Core Messag e Buffer
CORE0 Message Buf fer Transfer Code CORE1 Message Buffer Transf er Code
c0=1-N
xfer: if mgobf goto .
mgo=* r0 ++ //W rit e me ssag e to
//CORE 1 an d set MG OBF .
//4 cycles latency
//unti l CO RE1’ s MG IBE
//is cleared.
if mgibe goto . //Wait for CORE1
//message to arrive.
a0h=mgi
*r1++=a0h //Rea d CORE1 message
//and cl ea r CORE 1’ s
//MGOBF.
if c0lt goto xfer
c0=1-N
xfer: if mgobf goto .
mgo=*r0++ //Write message to
//CORE0 and set MGOBF.
//4 cycles latency
//until CORE0’s MGIBE
//is cl ea red.
if mgibe goto . //Wait for CORE0
//message to arrive.
a0h=mgi
*r0++=a0h //Read CORE0 message
//and clear CORE0’s
//MGOBF.
if c0lt goto xfer
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4 Hardware Architecture (continued)
4.8 Interprocessor Communication (continued)
4.8.3 DMAU Data Transfer
The most effic ient mechani sm for synchronous ly trans-
ferring large data blocks between the two cores is
through the two DMA U memory-to-mem ory (MMT)
channels, MMT4 and MMT5, described in detail in
Section 4.13.6, beginning on page 90. For example,
one core uses one MMT chan nel to transfer data and
the other core uses the other channel . In this way, a
transmitting core writes a message block via its MMT
channel and an interrupt notifies the receiving core
after the DMA transfer is complete. Table 14 summa-
rizes the MMT interrupts, DMINT4 and DMINT5, used
to synchronize DMAU transfers. Both cores can moni-
tor both DMINT4 and DMINT5.
Table 14. DMAU MMT Channel Interrupts
If an MMT channel is dedicated to intercore transfers
and not used for intracore transfers, the transmi tting
and receiving cores can use the DMINT4 and DMINT5
interrupts directly to synchronize transfers. For exam-
ple, MMT4 ca n be dedicated to CORE0-to-CORE1
transfers and MMT5 can be dedicated to CORE1-to-
CORE0 transfers. In this case, DMINT4 interrupts
CORE1 if a message bloc k from CORE0 is in memory,
and likewise, DMINT5 interrupts CORE0 if a message
block from CORE1 is in memory.
If an MMT channel is used for both intracore and inter-
core transfers, DMINT4 or DMINT5 is used for synchro-
nizing intraco re transfers and the XIO interrupt is used
for synchronizing intercore transfers. Each core pro-
grams the XIO interrupt for the other core via its
imux register (Table 5 on page 28). The XIOC[1:0]
field (imux[15:14]) selects XIO for the other core as
either zero (XIOC[1:0] = 0), DMINT4 (XIOC[1:0] = 1),
or DMINT5 (XIOC[1:0] = 2).
Table 15 illustrates an examp le configurati on for intrac-
ore and intercore transfers via DMA. This example
assig ns CORE0 to MMT4 and COR E1 to MMT5.
Table 15. DMA Intracore and Intercore Transfers Example
If a core uses an M MT c hannel for i ntr acore t ransfers, i. e., not for tr ansfers with t he other core, i t m ust first program
its XIOC[1:0] field (imux[15:14]) to zero. This prevents t he MMT interrupt from disturbing the other core via its XIO
interrupt. Th e core must enable the corresponding MM T interrupt (DMINT4 or DMINT5) in its inc0 register
(Table 153 on page 241 ).
If a core uses its MMT channel for int ercore transfers, i .e., f or tr ansmitting to the ot her core, it m ust first program it s
XIOC[1:0 ] fiel d (imux[15:14]) to either 1 or 2 (DMINT4 or DMINT5). The receiving core must enable its XIO inter-
rupt in its inc1 register (Table 153 on page 241). The transmitting core must disable the corresponding MMT inter-
rupt (DMINT4 or DMINT5) in it s own inc0 register.
DMAU
Channel Interrupt
Name Description
MMT4 DMINT4 MMT4 transfer complete.
MMT5 DMINT5 MMT5 transfer complete.
DMAU
Channel Int racore Intercore (Core-to-Core)
Transmitting Receiving
Core Interrupt imux[XIOC[1:0]] Core imux[XIOC[1:0]] Core Interrupt
MMT4 CORE0 DMINT4 0
(CORE1’s XIO = 0) CORE0 1
(CORE1’s XIO = DMINT4) CORE1 XIO (DMINT4)
MMT5 CORE1 DMINT5 0
(CORE0’s XIO = 0) CORE1 2
(CORE0’s XIO = DMINT5) CORE0 XIO (DMINT5)
Advance Data Sheet
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4 Hardware Architecture (continued)
4.9 Bit Input/Output Units (BIO〈0—1〉)
The DSP16411 has two bit I/O units, BIO0 for CORE0
and BIO1 for CORE1. Each BIO unit connects to
seven bidirectional pins, IO0BIT[6:0] for BIO0 and
IO1BIT[6:0] for BIO1. User software running in CORE0
controls and monitors BIO0 via its sbit and cbit regis-
ters. User software running in CORE1 controls and
monitors BIO1 via its sbit and cbit registers. The soft-
ware can:
■Individ ually configure each pin as an input or output.
■Read the current state of the pins.
■Test the combined state of input pins.
■Individ ually set, clear, or toggle output pins.
The DIREC[6:0] fiel d (sbit[14:8]—see Table 16) con-
trols the direction of the corresponding IO〈0,1〉BIT[6:0]
pin; a logic 0 configures the pin as an input or a logic 1
configures it as an output. Reset clears the
DIREC[6:0] field, configuring all BIO pins as inputs by
default. T he read-only VALUE [ 6:0] field (sbit[6:0])
contains the current state of the corresponding pin,
regardless of whether the pin is configured as an input
or output.
The cbit register (Table 17 on page 51) contains two
7-bit fields, MO DE[6:0]/MA SK[6: 0] and
DATA[6:0]/PAT[6: 0]. The meanin g of the individual
bits in these fi elds, MODE[
n
]/MASK[
n
] and
DATA[
n
]/PAT[
n
], is based on whether the correspond-
ing IO〈0,1〉BIT[
n
] pin is configured as an input or an
output. If IO〈0,1〉BIT[
n
] is configured as an input, the
fields are MASK[
n
] and PAT[
n
]. If IO〈0,1〉BIT[
n
] is
configu red as an output, the field s are MODE[
n
] and
DATA[
n
]. Table 18 on page 52 summarizes the func-
tion of the MODE[6:0]/MAS K[6:0] and
DATA[6:0]/PAT[6:0] fields.
If the software configures an IO〈0,1〉BIT[
n
] pin as an
output and:
■If the software clears MODE[
n
] and clears DATA[
n
],
the BIO〈0,1〉 drives the pin low.
■If the software clears MODE[
n
] and sets DATA[
n
], the
BIO〈0,1〉 drives the pin high.
■If the software sets MODE[
n
] and clears DA T A[
n
], the
BIO does not change the state of the pin.
■If the software sets MODE[
n
] and sets DATA[
n
], the
BIO〈0,1〉 toggles (inverts) the state of the pin.
If an IO〈0,1〉BIT[
n
] pin is configured as an input a nd
the software sets MASK[
n
], the BIO〈0,1〉 tests the
state of the pin by compa ring it to the PAT[
n
] (pattern)
field. B IO〈0,1〉 sets or clears its flags based on the
result of the compariso n of all its tested inputs:
■ALLT (all tru e) is set if all of the tested inputs match
the test pattern.
■ALLF ( all false) is set if all of the tested inputs do not
match the test pattern.
■SOMET (some true) is set if some or all of t he tested
inputs match the test pattern.
■SOMEF (some false) i s set if some or all of the
tested inputs do not match the test pattern.
Table 16. s bit (BIO Status/Control ) Register
15 14—8 7 6—0
Reserved DIREC[6:0] Reserved VALUE[6:0]
Bit Field Value Description R/W Reset
Value†
15 Reserved X Reserved—writing to this field has no functional effect. R/W 0
14—8 DIREC[6:0]
(Con trols dir ec-
tion of pins)
0Configure the corresponding IO〈0,1〉BIT[6:0] pin as an input. R/W 0
1Configure the corresponding IO〈0,1〉BIT[6:0] pin as an output.
7 Reserved X Reserved—value is read-only and is undefined. R 0
6—0 VALUE[6:0]‡
(Current value of
pins)
0The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 0. RP
§
1The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 1.
† For this column, X indicates unknow n on poweru p reset and unaffected on subseq uent reset .
‡ This field is read-only; writing the VALUE[6:0] field of sbit has no ef fect. If the user software toggle s a bit in the D IREC [6:0] field, there is a
latency of one cycle un til the VALUE[6: 0] field reflects t he current s tate of the corresponding I O〈0,1〉BIT[6:0] pin. If an IO〈0,1〉BIT[6:0] pin is
c o nfig u red as an output (DIREC[6:0] = 1) an d the use r softwa re writes cbit to change the st ate o f the pin, ther e is a latency of two cy cles until
the VALUE[6:0] field reflects the current state of the corresponding IO〈0,1〉B IT[6:0] ou tput pi n.
§ The IO〈0,1〉BIT[6:0] pins are configured as inputs after reset. If external circuitry does not drive an IO〈0,1〉BIT[
n
] pin, the VALUE[
n
] field is
undefined after reset.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.9 Bit Input/Output Units (BIO〈0—1〉)(continued)
Table 17. cbit (BIO Control) Register
If all the IO〈0,1〉BIT[6:0] pins are configured as outputs
or if the MASK[
n
] field is cleared for all pins that are
configured as inputs, the BIO〈0,1〉 sets the ALLT and
ALLF flags and clears the SOMET and SOMEF flags.
Table 19 on page 52 summarizes the BIO flags, which
software can test with conditional instructions ( see
Table 138 on page 226 ) . So ft ware can te st, save, or
restore the stat e of the flags by reading or writing the
alf register (see Table 144 on page 235). As illustrated
in Table 19 on page 52, ALLT is the logical inverse of
SOMEF and ALLF is the logical inverse of SOMET.
If an IO〈0,1〉BIT[
n
] pin is configured as an input and
the soft ware writes cbit to change the MASK[
n
] or
PAT[
n
] field , there is a late n cy of tw o cycle s until the
DSP16411 updates the BIO flags to reflect t he change.
The following code segment illustrates this latency by
the use of the two nop instructions:
sbit=0 // All pins are inputs.
cbit=0 // Test no inputs.
...
cbit=0x0302 // Test IOBIT[1:0].
2*nop // Any 2 instructions.
if allt goto OK // Branch if IOBIT1...
// is 1 and IOBIT0 is 0.
15 14—8 76—0
Reserved MODE[6:0]/MASK[6:0] Reserved DATA[6:0]/PAT[6:0]
Bit Field Value Description R/W Reset
Value
15 Reserved 0 Reserved—write with zero. R/W 0
14—8 MODE[6:0]
(outputs†)
†An IO〈0,1〉BI T [6:0] p i n i s c onfigured as an output if the cor respo nding DI REC[6:0] field (sbit[14:8]) has be en set by t he us er softwar e. An
IO〈0,1〉BIT[6:0] pin i s confi gured as an input if the corres ponding DI REC[ 6:0] field has been cleared by t he user sof t ware or by device reset.
0 The BIO drives the corresponding IO〈0,1〉BIT[6:0] output pin to the corre-
sponding value in DATA[6:0]. R/W 0
1■If the corr espo nding DATA[6: 0] fiel d is 0, the BIO does not change the st ate
of the corresponding IO〈0,1〉BIT[6:0] output pin.
■If the corres ponding DATA[ 6:0] fi eld is 1, the BIO toggles ( inverts) the state
of the corresponding IO〈0,1〉BIT[6:0] output pin.
MASK[6:0]
(inputs†)0 The BIO does not test t he stat e of t he co rrespon ding IO〈0,1〉BIT[6: 0] i nput pi n
to determine the state of the BIO flags‡.
‡ The BI O flags are ALLT, ALLF, SO M ET, and SOM E F. See Table 19 on page 52 for d etails o n BIO flags.
1 The BIO compares th e state of the corr espon ding IO〈0,1〉BIT[6:0] i nput pin to
the corr espondi ng value in the P AT[6:0] f ield to deter mine the state of the BIO
flags‡; t rue if pin mat ches or false if pin doesn’ t match.
7 Reserved 0 Reserved—write with zero. R/W 0
6—0 DATA[6:0]
(outputs†)0■If the corr espondi ng MODE[6:0] field i s 0, the BIO drives the correspondi ng
IO〈0,1〉BIT[6:0] output pin to logic 0.
■If the corresponding MO DE[6:0] fi eld is 1, the BIO does not change the
state of the corresponding IO〈0,1〉BIT[6:0] output pin.
R/W 0
1■If the correspondi ng MODE[6:0] field is 0, the BIO drives the correspondi ng
IO〈0,1〉BIT[6:0] output pin to logic 1.
■If the corresponding MO DE[6:0] fi eld is 1, the BIO toggl es (i nvert s) t he
state of the corresponding IO〈0,1〉BIT[6:0] output pin.
PAT[6:0]
(inputs†)0 If the correspo nding MASK[6:0] field i s 1, the BIO tests the state of the corre-
sponding IO〈0,1〉BIT[6:0] input pin to determine the state of t he BIO fl ags ‡;
true i f pi n is l ogic 0 or fal se if pin is logi c 1.
1 If the corr espondi ng MASK[6:0] fie ld i s 1, the BIO tests the state of the corre-
sponding IO〈0,1〉BIT[6:0] input pin to determine the state of t he BIO fl ags ‡;
true i f pi n is l ogic 1 or fal se if pin is logi c 0.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.9 Bit Input/Output Units
(BIO〈0—1〉)(continued)
If an IO〈0,1〉BIT[
n
] pin is configured as an output and
the soft ware writes cbit to change the state of the pin,
there is a latency of one cycle until the DSP1641 1
changes the state of the pin and a latency of an addi-
tional cycle until the VALUE[
n
] field (sbit[6:0]) reflects
the change. The use of two nop inst ru c tions in th e fol-
lowing code segment illustrates this latency:
sbit=0x1000 // IOBIT4 is an output.
cbit=0x0010 // Drive IOBIT4 high.
nop // IOBIT4 goes high.
nop // VALUE4 is updated.
a0h=sbit // Bit 4 of a0h is 1.
If the software writes sbit to change an IO 〈0,1〉BIT[
n
]
pin from an input to an output or from an output to an
input, there is a latency of one cycle before the
VALUE[
n
] field of sbit is updated to refl ect the state of
the pin. If the soft ware writes sbit to change an
IO〈0,1〉BIT[
n
] pin from an output to an input and back
to an output, the BI O drives the pin with its origin al out-
put value.
The following code segment illustrates the latency
describ ed in the previous paragraph:
sbit=0x0F00 // IOBIT[3:0] - output.
cbit=0x000A // IOBIT[3:0] = 1010
// ...after 1 cycle.
cbit=0x0101 // Toggle IOBIT0...
// IOBIT[3:0] = 1011
// ...after 1 cycle.
sbit=0 // IOBIT[3:0] - input.
sbit=0x0F00 // IOBIT[3:0] - output.
// IOBIT[3:0] = 1011
// ...after 0 cycles.
nop // Any instruction.
a0h=sbit // a0h[3:0] = 1011.
Table 18. BIO Operations
..
Table 19. B IO Flags
DIREC[
n
]†
†0 ≤ n ≤ 6.
MODE[
n
]/
MASK[
n
]†DATA[
n
]/
PAT[
n
]†BIO Action
1
(Output) 00
Clear IO〈0,1〉BIT[
n
].
1Se t IO 〈0,1〉BIT[
n
].
10
Do not change
IO〈0,1〉BIT[
n
].
1Toggle IO〈0,1〉BIT[
n
].
0
(Input) 0X
Do not test ‡
IO〈0,1〉BIT[
n
].
‡ The BIO tests the state of inpu t pins t o determine the states of the
BIO flags. See Table 19 for details on the BIO flags.
10
Test‡ IO 〈0,1〉BIT[
n
]
fo r logic zero.
1Test‡ IO 〈0,1〉BIT[
n
]
for l ogic one.
Condition ALLT
(alf[0]) ALLF
(alf[1]) SOMET
(alf[2]) SOMEF
(alf[3])
All or some of the
IO〈0,1〉BIT[ 6:0] pins are
configured as input s.†
† For at least one pin IO〈0,1〉BIT[
n
], DIREC[
n
]=0.
All tested inputs match the pattern.‡
‡ For every pin IO〈0,1〉BIT[
n
] with DIREC[
n
] = 0 an d MA S K [
n
]=1, IO〈0,1〉BIT[
n
]=PAT[
n
].
101 0
All tested inputs do not match the pattern.§
§ For every pin IO〈0,1〉BIT[
n
] with DIREC[
n
] = 0 an d MA S K [
n
]=1, IO〈0,1〉BIT[
n
]≠PAT[
n
].
010 1
Some (but not all) of the tested input s match the pattern.††
†† For at least one pin IO〈0,1〉BIT[
n
] with DIREC[
n
] = 0 and MASK[
n
]= 1, IO〈0,1〉BIT[
n
]=PAT[
n
], and for at least one pin IO〈0,1〉BIT[
n
] with
DIREC[
n
] = 0 and MASK[
n
] = 1, IO〈0,1〉BIT[
n
]≠PAT[
n
].
001 1
All of the in puts are not tested.‡‡
‡‡ For all pins IO〈0,1〉BIT[
n
] with DIREC[
n
]= 0, MASK[
n
]=0.
110 0
All IO〈0,1〉BIT[ 6:0] pins are configured as outputs.§§
§§ DIRE C[6:0 ] ar e all on es .
110 0
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4 Hardware Architecture (continued)
4.10 Timer Units (TIMER0_〈0—1〉 and
TIMER1_〈0—1〉)
The DSP16411 provides two timer units for each core:
TIMER0_0 and TIMER1_0 for CORE0 and TIMER0_1
and TIMER1_1 for CORE1. Each TIM ER provides a
programmable single interval interrupt or a programma-
ble periodic interrupt. Figure 13 on page 54 is a block
diagram of a TIMER that contains:
■A 16-bit control register timer〈0,1〉c (see Tabl e 20
on page 55).
■A running count register timer〈0,1〉 (see Table 21 on
page 56) consisting of a 16-bit down counter and a
16-b it period register.
■A prescaler that divides the internal clock (CLK) by
one of 16 programmed values in the range 2 to
65536. The presc aler output clock decre ments the
timer〈0,1〉 down counter. The program me d pres-
cale value and the value written to timer〈0,1〉 deter-
mine the interrupt interval or period.
By default after dev ice reset1, the DSP16411 clears
timer〈0,1〉c and powers up the TIMER. To save power
if the TIMER is not in use, the software can set the
PWR_DWN field (timer〈0,1〉c[6]). Until the user soft-
ware writes to timer〈0,1〉c and timer〈0,1〉, the TIMER
does not oper ate or generate interrupts.
Note: The software can read or write timer〈0,1〉 only if
the TIMER is powered up (PWR_DWN = 0).
If the software reads timer〈0,1〉, the value read is the
output of the down counter. If the software writes
timer〈0,1〉, the TIMER loads the write value into the
down counter and into the period register simulta-
neously.
The prescaler consists of a 16-bit up counter and a
multiplexer controlled by the PRESCALE[ 3:0] field
(timer〈0,1〉c[3:0]). PRESCALE[3:0] contains a
value N that selects the period of the prescaler output
clock a s:
where fCLK is the frequenc y of the internal clock (see
Section 4.17 on page 200 ).
To operate the TIMER (i. e., for the prescaler to decre-
ment the timer〈0,1〉 down counter), the user software
must perform the follow ing steps.
■Write timer〈0,1〉c to program its fields as follows:
—Write 0 to the PWR_DWN field.
— Write 0 t o the RELOAD fiel d (timer〈0,1〉c[5 ]) for a
single interval interrupt or write 1 to the RELOAD
field for periodic interrupts.
— W rite 1 to the COUNT field (timer〈0,1〉c[4]) to
enable the prescaler output clock.
— P rogram the PRE SCALE[ 3:0] field to configure
the frequenc y of the prescaler output clock.
■Write a nonzero value to timer〈0,1〉 to enable the
down counter input clock.
The software ca n perform the above steps in either
order, and the TIMER starts after the second s tep.
If the TIMER is operating and the timer〈0,1〉 down
counter reaches zero, the TIMER asserts its interrupt
reques t pulse TIME〈0,1〉 (see Section 4.4, beginning
on page 25, f or details on interrupts). The i nterval from
starting the TIMER to the occurrence of the first inter-
rupt is the following:
If the down counter reaches zero and RELOAD is 0,
the TIMER disables the input clock to the down
coun ter, causing the down counter to hold its current
value of zero. T he user software can restart the
TIME R by writing a nonzero va lue to timer〈0,1〉.
If the down counter reaches zero and RELOAD is 1, a
prescale period elapses and the TIMER reloads the
down counter from the timer〈0,1〉 period register .
Another presc ale period elapses and the prescaler
decrem ents the down counter. Therefo re, the subse-
quent interval between periodic interrupts is the follow-
ing:
Software can read or write timer〈0,1〉 while the tim er is
running. If the software writes timer〈0,1〉, the TIMER
loads the write value into the down counter and period
register and initializes the prescaler by clearing the
16-bit up counter. B ecaus e the TIMER initializes the
prescaler if the software writes timer〈0,1〉, the interval
from writing timer〈0,1〉 to decrementing the down
counter is one complete prescale period.
Clearing COUNT disables the clock to the prescaler,
causi ng the down counter to hold its current val ue and
the prescaler to retain its current state. If the TIMER
remains powered up (PWR_DWN = 0), software can
stop and restart the TIMER at any time by clearing and
setting COUNT.
1. After device reset, the DSP16411 clears the down counter of timer〈0,1〉 and lea v es the period register of timer〈0,1〉 un ch an ged.
2N1+
fCLK
-------------
timer〈0,1〉2N1+
×
fCLK
-------------------------------------------------
timer〈0,1〉1+()2N1+
×
fCLK
---------------------------------------------------------------
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4 Hardware Architecture (continued)
4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)
Figure 13. Timer Block Diagram
15—7 6 5 4 3—0
RESERVED PWR_DWN RELOAD COUNT PRESCALE[3:0]
4
16-bit RELOAD VALUE
16-bit DOWN COUNTER
16
16
16
16
timer〈0,1〉c
timer〈0,1〉
10
LD
LD
(PERIOD) REGISTER
LD
15
14
0
16-bit
UP
COUNTER
15
14
0
MUX
CLR
MUX
16
CLK
PRESCALER
COUNTER = 0 (LEVEL)
16
N
CLK
N1+
2
-------------
LOAD
timer〈0,1〉
REGISTER
TIME
〈0,1〉
INTERRUPT
PULSE
IDB[15:0]
TO CORE
KEY: PROGRAM-ACCESSIBLE
REGISTER
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4 Hardware Architecture (continued)
4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)
Table 20. timer〈0,1〉c (TIMER〈0,1〉 Control) Register
15—7 6 5 4 3—0
Reserved PWR_DWN RELOAD COUNT PRESCALE[3:0]
Bit Field Value Description R/W Reset
Value
15—7 Reserved 0 Reserved—write wit h zero. R/W 0
6 PWR_DWN 0 Power up the t imer. R/W 0
1 Power down the timer†.
5 RELOAD 0 Stop decrementing the down counter after i t reaches zero. R/W 0
1 Automatically rel oad the down coun ter from the period regi ster after
the counter reaches zero and continue decrementing the counter
indefinitely.
4 COUNT 0 Hold the down counter at its current value, i.e. , st op the time r. R/W 0
1 Decrement the down counter, i.e., run the timer.
3—0 PRESCALE[3:0] 0000 Control s the counter prescaler to determ ine the fre-
quency of the timer, i.e., the frequency of the clock
appli ed to the timer down counter. This frequency is a
ratio of the internal clock frequency fCLK.
fCLK/2 R/W 0000
0001 fCLK/4
0010 fCLK/8
0011 fCLK/16
0100 fCLK/32
0101 fCLK/64
0110 fCLK/128
0111 fCLK/256
1000 fCLK/512
1001 fCLK/1024
1010 fCLK/2048
1011 fCLK/4096
1100 fCLK/8192
1101 fCLK/16384
1110 fCLK/32768
1111 fCLK/65536
† If TIMER〈0,1〉 is powered down, timer〈0,1〉 cannot be read or written. While the timer is powered down, the state of the down counter and
peri od register re main unch anged.
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4 Hardware Architecture (continued)
4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)
Table 21. timer〈0,1〉 (TIMER〈0,1〉 Running Count) Register
4.11 Hardware Development System
(HDS〈0—1〉)
The DSP16411 provides an on-chip hardware develop-
ment module for each of the two cores (HDS〈0—1〉).
Each HDS is available for debugging assembly-
language programs that execute on the DSP16000
core at the core’s rated speed. The main capability of
the HDS is allowing controlled visibility into the core’s
state during program executio n.
The fundament al steps in debugging an appl ication
using the HDS include the following:
1. S etup : Download program code and data into the
correct memory regions and set breakpointing con-
ditions.
2. Run: Start execution or single step from a desired
starting point (i.e., allow device to run under simu-
lated or real-time conditions).
3. Break: Break program execution on satisfying break-
pointing conditions; upload and allow user accessi-
bility to internal state of the device and its pins.
4. Res um e: Res um e exec ution (normally or single
step) after hitting a breakpoint and finally upload
internal state at the end of execution.
A power ful deb ugging capab ilit y of the HDS is the abil-
ity to brea k program executi on on comple x breakpoint-
ing conditions . A complex breakpoin t condition, for
example, can be an instruction that executes from a
particular instruction-address location (or from a partic-
ular instruction-address range suc h as a su broutine)
and accesses a coefficient/data element from a spe-
cific memory location (or from a memory region such
as inside an array or outside an array). Complex condi-
tions can also be chained to form more complex break-
point conditions. For example, a complex breakpoint
condit ion can be defined as the back-to-back execution
of two different subroutines.
The HDS also provides a debugging feature that allows
a number of complex breakpoin ts to be ignored. Th e
number of breakpoints ignored is programmable by t he
user.
An intelligent trace mechanism for recording disconti -
nuity poin ts during program executio n is also available
in the HDS. T his mechanis m allows unambiguous
reconstr uction of program flow involving discontinuit y
points such as gotos, calls, returns, and interrupts. The
trace mechanism compres ses single-level (non-
nested) loops and records them as a single discontinu-
ity. This feature prev ents single-level loops from filling
up the trace buffers. Also, cache loops do not get reg-
istered as discontinuit ies in the trace buffers. The re-
fore, two-level loops with inner cache loops are
registered as a single discontinuity.
The HDS provides a 32-bit cycle counter for accurate
code profiling during program development. The cycle
counter records processor CLK cycles between a user-
defin ed start point and end point. The cy cle counter
can optionally be used to break program execution
after a user-specified number of clock cycles.
15—0
TIMER〈0,1〉 Down Count er
TIMER〈0,1〉 Period Register
Bit Field†Description R/W‡Reset
Value§
15—0 Down Counter If the COUNT field (timer〈0,1〉c[4]) is set, TIMER〈0,1〉 decrements this portion
of the timer〈0,1〉 register every prescale period. When the down counter
reaches zero, TIMER〈0,1〉 generates an interrupt.
R/W 0
15—0 Peri od Register If the COUNT field (timer〈0,1〉c[4]) and the RELOAD field (timer〈0,1〉c[5]) are
both set and the down counter contains zero, TIMER〈0,1〉 reloads the down
counter with the contents of this portion of the timer〈0,1〉 register.
WX
† If the user program writes to the timer〈0,1〉 register, TIMER〈0,1〉 loads the 16-bit write value into the down counter and into the period register
simultaneously. If the user program reads the timer〈0,1〉 register, TIMER〈0,1〉 returns the current 16-bit value from the down counter.
‡ To read or write the timer〈0,1〉 register, TIMER〈0,1〉 must be powered up, i.e., the PWR_DWN field (timer〈0,1〉c[6]) must be cleared.
§ For this column, X indicates unknow n on poweru p reset and unaffected on subseq uent reset .
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)
The DSP16411 provide s an on-chip
IEEE
1149.1 com-
pliant JTAG port for each of the two cores
(JTAG〈0—1〉). JTAG is an on-chip hardware module
that controls the HDS. All communication between the
HDS softwar e, running on the host computer, and the
on-chip HDS is in a bit-serial manner through the JTAG
port. Th e JTAG port pins con sis t of test data input ,
TDI〈0—1〉, test data output, TDO〈0—1〉, test mode
select , TM S〈0—1〉,
test clock, TCK〈0—1〉, a n d test
reset, TRST〈0—1〉N.
The set of test registers includes the JTAG identifica-
tion register (ID), the boundary-scan register, and the
scanna ble periphe ral registers.
4.12.1 Port Identification
Each JTA G port has a read-only identification regist er,
ID, as defined in Table 22. As specified in the table, the
contents of the ID register for JTAG0 is 0x1C81532 1
and the cont ents of the ID register for JTAG1 is
0x0C 815321.
Table 22. ID (JTAG Identification) Register
31—28 27—19 18—12 11—1 0
DEVICE OPTIONS ROMCODE PART ID AGERE ID One
Bit Field Value Description R/W Reset Value
31—28 DEVICE OPTIONS 0x1 JTAG0—device options. R 0x1
0x0 JTAG1—d evice options. 0x0
27—19 ROMCODE 0x190 ROMCODE of device. 0x1 90
18—12 PART ID 0x15 Pa rt ID—DSP16411. 0x15
11—1 AGERE ID 0x190 Agere identif ication . 0x190
0 On e 1 Logic one. 1
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)(continued)
4.12.2 Emulation Interface Signals to the DSP16411
For in-circuit emulation and application software
debugging, the Agere
TargetView
™ Commu nicat ion
System (TCS) provides communication between a host
PC and one or more DSP16411 devices. Users of the
TCS hardware have the option of u sing one of three
connectors to interface this tool with DSP16411
devices on the target application. The pinouts for these
connectors are described in the following th ree sec-
tions.
4.12.2.1TCS 14-Pin Header
The TCS interface pod provides a 14-pin, dual-row
(0.10 in. x 0.1 0 in.) socket (female ) for connection to
the user’s target ha rdware. Figure 14 illustr a t es the
pinout of this connector. Table 23 describe s the signal
names and their relationship to the DSP16411 signals.
Figu re 14. TCS 14 -P in Co nnect or
5-7333 (F)
PIN 1 PIN 13
PIN 2 PIN 14
Table 23. TCS 14-Pin Socke t Pinout
TCS Pin
Number TCS Signal
Name Description TCS
I/O DSP16411
Pin Number DSP16411
Signal Name DSP16411
I/O
1 TCK Test cl ock O F4 and L13 TCK0 and TCK1 I
2 NC No connect NA NA NA NA
3 Ground System ground G See Section 7 on page 253 VSS G
4 Ground System ground G See Section 7 on page 253 VSS G
5 TMS Test mode select O G2 and K15 TMS0 and TMS1 I
6V
TARG Target I/O voltage I See Section 7 on page 253 VDD2P
7 NC No connect NA NA NA NA
8 NC No connect NA NA NA NA
9 TDO Test data output I F1 or L16 (not both) TDO0 or TDO1 (not both) O
10 TDI Test data input O G1 or K16 (not both) TDI0 or TDI1 (not both) I
11 Ground System gro und G See Section 7 on page 253 VSS G
12 Ground System gro und G See Section 7 on page 253 VSS G
13 NC No connect NA NA NA NA
14 NC No connect NA NA NA NA
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)(continued)
4.12.2 Emulation Interface Signals to the
DSP16411 (continued)
4.12.2.2 JCS 20-Pin Header
The TCS tools provide an interface adapter to convert
the 14-pin interface pod to a 20-pin dual-row
(0.05 in. x 0.10 in.) socket (female,
3M
® part number
82020-6 006) for connection to the user ’s target hard-
ware. Figure 15 illu strat es the pinout of this
connector. Table 24 describes the signal names and
their relationship to the DSP16411 signa ls. This con-
nector is also compatible with the Agere JTA G commu-
nications system (JCS) tools.
Figure 15. JCS 20-Pin Connector
5-7334 (F)
PIN 19
PIN 20
PIN 1
PIN 2
Table 24. JCS 20-Pin Socket Pinout
JCS Pin
Number JCS Signal
Name Description JCS I/O DSP16411
Pin Number DSP16411
Signal Name DSP16411 I/O
1 NC No connect NA NA NA NA
2 Ground System ground G See Section 7 on page 253 VSS G
3 NC No connect NA NA NA NA
4 NC No connect NA NA NA NA
5 NC No connect NA NA NA NA
6 TMS Test mode select O G2 and K15 T MS0 and TMS1 I
7 Ground System ground G See Section 7 on page 253 VSS G
8V
TARG Target I/O voltage I See Section 7 on page 253 VDD2P
9 NC No connect NA NA NA NA
10 Ground System ground G See Section 7 on page 253 VSS G
11 NC No connect NA NA NA NA
12 TDI Test data i nput O G1 or K16 (not both) TDI0 or TDI1 (no t bot h) I
13 Ground System ground G See Section 7 on page 253 VSS G
14 TCK Test clock O F4 and L13 TCK0 and TCK1 I
15 Ground System ground G See Section 7 on page 253 VSS G
16 TDO Test dat a output I F1 or L16 (not both) TDO0 or TDO1 (not both) O
17 NC No connect NA NA NA NA
18 Ground System ground G See Section 7 on page 253 VSS G
19 NC No connect NA NA NA NA
20 NC No connect NA NA NA NA
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)(continued)
4.12.2 Emulation Interface Signals to the
DSP16411 (continued)
4.12.2.3 HDS 9-Pin, D-Type Connector
The TCS tools also provide an inter face adapter to con-
vert the 14-pin interface pod to a 9-pin, subminiature,
D-type plug (male) for connection to the user’s target
hardware. Figure 16 illustrates the pinout of this
connector. Table 25 describes th e signal nam es and
their relationship to the DSP16411 signa ls. This con-
nector is also compatible with the Agere JTA G commu-
nications system (JCS) and hardware developme nt
system (HDS) tools.
Figu re 1 6. H D S 9- Pi n Connector
5-7335 (F)
PIN 5
PI N 9
PIN 1
PIN 6
Table 25. HDS 9-Pin, Subminiature, D-Type Plug Pinout
HDS Pin
Number HDS Signal
Name Description HDS I/O DSP16411
Pin Number DSP16411
Signal Name DSP16411
I/O
1 Ground System ground G See Sect ion 7 on page 253 VSS G
2 TCK Test cl ock O F4 and L13 TCK0 and TCK1 I
3 NC No connect NA NA NA N A
4 TMS Test mode select O G2 and K15 TMS0 and TMS1 I
5 Ground System ground G See Section 7 on page 253 VSS G
6 TDO Test data out put I F1 or L 16 (not both) TDO0 or TDO1
(not bot h) O
7 TDI Test data input O G1 or K16 (not both) TDI0 or TDI1
(not bot h) I
8V
TARG Target I/O volt age I See Section 7 on page 253 VDD2P
9 NC No connect NA NA NA N A
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)(continued)
4.12.3 Multiprocessor JTAG Connections
The DSP16411 has two JTA G ports, one for each
DSP16000 core. The user can daisy chain these ports
onto the same scan chain, potenti ally with other
DSP16411 devices, or i nterface to each JTAG port indi-
vidually for debuggin g. If multiple JTAG ports are inter-
faced together on the same scan chain, TMS and TCK
are broadcast to all DS Ps in t he scan chain. TDI of the
first JTAG port in the chain is then conne cted to TDI of
the TCS connector on the user’s board, TDO of the first
JTAG port is connected to TDI of the next JTAG port in
the chain, and so on. TDO of the last JTAG port in the
chain is then tied to TDO of the TCS connector. If
more than six JTAG ports are in the same scan chain ,
TMS and TCK must be buffered to ensure compatibility
with t155 and t156 (See Table 195 on page 280). In
the typica l application, the user’s board tie s the
DSP1641 1 JTAG reset signals, TRST0N and TRST1N,
to the device reset, RSTN. Figure 17 illustrates a typi-
cal daisy-chain connection between the TCS hardware
and the two cores of a single DSP16411.
Note : CORE0 is DSP1 on the scan chain an d CORE1 is DSP2 on t he scan chain. For mu ltiple DSP16411 devi ces on a si ngle scan chain,
maintain the CORE0-to-CORE1 daisy-chain.
Figur e 17 . Typica l Multiprocess or JTAG Connecti on with Single Scan Chain
JCS/TCS
TDOTCK TMS TDI
TCK0 TMS0 TDI0 TDO0 TCK1 TMS1 TDI1 TDO1
CORE1CORE0
RESET
TRST0N
TRST1N
RSTN DSP16411
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉)(continued)
4.12.4 Boundary Scan
JTAG0 cont ains a full boundary-scan register as described in Table 26 and JTAG1 contains a single-bit boundary-
scan register as described in Table 27 on page 63. As described in Section 4.12.3 on page 61 , JTAG0 and JTAG1
of multiple DSP16411 devices can be chained together with full boundary-scan capabilities.
Table 26. J TAG0 Boundary -Sca n Register
Cell Type†Sign al Name/
Function Control
Cell Cell Type†Signal Name/
Function Control
Cell
0 I ERTYPE — 87 DC IO1BIT [1] direct ion control —
1 I EXM — 88 I/O IO1BIT[1] 87
2 I ESIZE — 89 DC IO1BIT[2] direction control —
3 I EREQN — 90 I/O IO1BIT[2] 89
4 I ERDY — 91 DC IO1BIT [3] dir ection contro l —
20—5 I/O ED[15:0] 21 92 I/O IO1BIT[3] 91
21 DC ED[15:0] direction control — 93 DC IO1BIT[4] direction control —
37—22 I/O ED[31:16] 38 94 I/O IO1BIT[4] 93
38 DC ED[31:16] di rection control — 95 DC IO1BIT[5] dir ection contro l —
39 O EACKN 65 96 I/O IO1BIT[5] 95
41—40 O ERWN[1:0] 45 97 DC I O 1BIT[6] dir ection contro l —
42 O EROMN 45 98 I/O IO1BIT[6] 97
43 O ERAMN 45 99 DC IO1BIT[7] direction control ‡ —
44 O EION 45 100 I/O IO1BIT[7]‡99
45 OE EION, ERAMN, EROMN,
ERWN[1:0] 3-state control — 104—101 I PADD[3:0] —
64—46 O EA[18:0] 65 105 I PCSN —
65 OE EA[18:0] 3-s tate contr ol — 106 I PRWN —
69—66 O ESEG[3:0] 70 107 I PIDS —
70 OE ESEG[3:0] 3-state control — 108 I PODS —
71 OE ECKO and EACKN
3-state con trol — 109 I PRDYMD —
72 O ECKO 71 110 O PINT 114
73 OE SOD1 3-state cont rol — 111 O PRDY 114
74 O SOD1 73 112 O PIBF 114
75 I SID1 — 113 O POBE 114
76 I SCK1 — 114 OE PINT, PRDY, PIBF,
POBE 3-state control —
77 DC SOFS1 direction control — 130—115 I/O PD[15:0] 131
78 I/O SOFS1 77 131 DC PD[15:0] di rection cont rol —
79 DC SOCK1 direction control — 132 I EYMODE —
80 I/O SOCK1 79 133 DC IO 0BIT[0] dir ecti on control —
81 DC SIFS1 direction control — 134 I/O IO0BIT[0] 132
82 I/O SIFS1 81 135 DC IO0BIT[1] direct ion cont rol —
83 DC SICK1 direction control — 136 I/O IO0BIT[1] 134
84 I/O SICK1 83 137 DC IO0BIT[2] direct ion cont rol —
85 DC IO1BIT[0] directi on contr ol — 138 I/O IO0BIT[ 2] 136
86 I/O I O 1BIT[0] 85 139 DC IO0BIT [3] dir ecti on control —
† Key to this column: I = input; O E = 3-state control cell; O = outpu t; DC = bi direc tiona l control cell ; I/ O = input/output.
‡ There is n o pin asso ciated with thi s signal.This is a pad only and is not connected in the package.
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4 Hardware Architecture (continued)
4.12 JTAG Test Port ( JTAG〈0—1〉) (continued)
4.12.4 Boundary Scan (continued)
140 I/O IO0BIT[3] 138 153 DC SOFS0 direction control —
141 DC IO0BIT[4] di rection contr ol — 154 I/O SOFS0 152
142 I/O IO0BIT[4] 140 155 DC SO CK0 direction control —
143 DC IO0BIT[5] di rection contr ol — 156 I/O SO CK0 154
144 I/O I O 0BIT[5] 142 157 DC SIFS0 direct ion control —
145 DC IO0BIT[6] di rection contr ol — 158 I/O SIFS0 156
146 I/O I O 0BIT[6] 144 159 DC SICK0 direction cont rol —
147 DC IO0BIT[7] direction control‡— 160 I/O SICK0 158
148 I/O IO0BIT[7]‡146 164—161 I INT[3:0] —
149 OE SOD0 3-state cont rol — 165 DC TRAP directi on control —
150 O SOD0 148 166 I/O TRAP 164
151 I SID0 — 167 I RSTN —
152 I SCK0 — 168 I CKI —
Table 27. JTAG1 Boundary -Sca n Register
Cell Function Control Cell
0 Internal Cell —
Table 26. JTAG0 Boundary -Sca n Register (continued)
Cell Type†Sign al Name/
Function Control
Cell Cell Type†Signal Name/
Function Control
Cell
† Key to this column: I = input; O E = 3-state control cell; O = outpu t; DC = bi direc tiona l control cell ; I/ O = input/output.
‡ There is n o pin asso ciated with thi s signal.This is a pad only and is not connected in the package.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU)
The DMAU (direc t memory access unit) manages
movemen t of data to or from the DSP16411 internal or
extern al memor y w ith mi ni ma l cor e inte r vention:
The DMAU can move data between memory and the
I/O uni ts:
— The DMAU provides four single-word tra nsfer
(SWT) channels for moving data between memory
and SIU〈0—1〉. A core initially defines the data
structure and the DMAU provides address genera-
tion, compare, and update functions. Two-dimen-
sional array capability facilitates applications such
as TDM channel multiplexing/demultiplexing.
Each SWT channel allows an SIU to access mem-
ory one word (16 bits) at a time.
— The DMAU provides a single addressing bypass
channel for moving data between memory and the
PIU. Unlike the SWT channels, the bypass chan-
nel does not provide address generation, com -
pare, and update functions. The bypass channel
allows a host to address and access memory one
word (16 bi ts) at a time.
The DMAU can move data between two blocks of
memory. It provides two memory-to-memory (MMT)
chan nels for which a core initia lly defines the data
structure. The DMAU provides address generation,
compare, and update functions for each channel.
The DMAU c an perform a block transfer either a sin-
gle word (16 bits) at a time or a double word ( 32 bits)
at a time.
4.13.1 Overview
The DMAU has six independent channels and an
addressing bypass channel as deta iled in Table 28.
These chann els can access any DSP16411 me mory
component, including TPRAM0, TPRAM1, and external
memory.
Figure 18 on page 65 is a functional overview of the
DMAU channels and their interconnecti ons to the
peripherals and m emo ry buses. T he DMAU arbitrate s
among the seven channels for access to the memory.
For an SWT channel, a core can define a data struc-
ture (array) in DSP16411 memory by programming
DMAU memory-mapped registers. The DMAU can
then perform source or destination transfers. A source
transfer is defined as a series of read operations from
the memory array to an SIU. A destination transfer is
defined as a series of write operations to the memory
array from an SIU. A transfer consists of a series of
transactions in response to SIU requests. A source
transaction is defined as reading a word (16 bits) from
the array, writing the word to the SIU output data re gis-
ter (SODR), and updating the appropriate DMAU
registers. A destinat ion transaction is defined as
reading a word from the SIU input data register ( SIDR),
writing the word to the array , and updating the appropri-
ate DMAU registers. See Section 4.13.5, beginning on
page 87, f or details on SWT transactions .
The DMAU also provides two channels for memory-to-
memory transfers (MMT). These channels allow a
user-defined block of data to be transfer red between
any two DSP1641 1 memory blocks, including external
memory. Each MMT channel transfers data between a
source block and a des t i na tion block. The DMAU
can perform a block transfer either a single word
(16 bits) at a time or a double word (32 bits) at a
time. See Section 4.13.6, beginning on page 90, for
details on memory-to-memory block transfers.
Finally, the DMAU provides an addressing by pass
chan nel that is dedicat ed to the PIU. This channel
bypasses the DMAU address generation, compare,
and update processes. The DMAU relies on the PIU to
provide the memo ry address for each PIU transaction
(data transfer between a host and the DSP16411).
The address ing bypass channel provides a hos t with
fast access to any DSP16411 memory space. See
Section 4.13.4 on page 86 for more details.
Table 28. DMAU Cha nnel Assignment
DMAU Channel Descript ion Associated With
SWT0 Single-word (16-bit ) transfer s SIU0
SWT1 Single-word (16-bit ) transfer s
SWT2 Single-word (16-bit ) transfer s SIU1
SWT3 Single-word (16-bit ) transfer s
MMT4 Single-word (16-bit) or double-word (32-bit) transfers Memory
MMT5 Single-word (16-bit) or double-word (32-bit) transfers
Bypass Singl e-word (16-bi t) transf ers PIU
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.1 Overview (continued)
DMAU Channels
Figure 18. DMAU Interconnections and Channels
Figure 19 is a block diagram of the DMAU. The DMAU include s 55 memory-mapped registers that it uses in p ro-
cessing source transfers, destination transfers, and memory-to-mem ory block transfers. Thes e registers are con-
figured by programs running in the cores that access the registers. The registers control the DMAU and contain its
current status. See Section 4.13.2, beginning on page 67, for details on these registers. Although the DMAU reg-
isters are memory-mapped, they are physically located in the DMAU and are accessible by either core via the
SEMI and the SDB (system data bus).
TPRAM0
TPRAM1
SEMI
ZEDB
ZIDB
Z-BUS
ARBITER
SWT0
SWT1
SWT2
SWT3
PIU
CHANNEL
CHANNEL
CHANNEL
CHANNEL
16
32
32
DMAU
DESTINATION
DATA
16
SOURCE
DATA
16
DESTINATION
DATA
16
SOURCE
DATA
BYPASS
CHANNEL
16
DATA
16/32
DESTINATION
DATA
16/32
SOURCE
DATA
16/32
DESTINATION
DATA
16/32
SOURCE
DATA
SIU1
SIU0
MMT4
CHANNEL
MMT5
CHANNEL
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.1 Overview (continued)
DMAU Block Diagram
Figure 19. DMAU Block Diagram
DMAU
SAB SDB ZSEG ZEAB ZEDB
DPI
PAB
DDO
DSI0
8 CONTROL REGISTERS
DMCON
〈
0—1
〉
16 bits
CTL
〈
0—5
〉
4 STRIDE REGISTERS
16 bits
STR
〈
0—3
〉
4 REINDEX REGISTERS
RI
〈
0—3
〉
20 bits
8 BASE REGISTERS
SBAS
〈
0—3
〉
DBAS
〈
0—3
〉
20 bits
6 LIMIT REGISTERS
LIM〈0—5〉
20 bits
12 COUNTER REGISTERS
SCNT〈0—5〉
DCNT〈0—5〉
20 bits
12 ADDRESS REGISTERS
32 bits
SADD〈0—5〉
DADD〈0—5〉
ADDRESS
COMPARE
&
UPDATE
DSINT[3:0], DDINT[3:0], DMINT[5:4]
10
20 420
32 32
16
16
32
16
SEMI TPRAM〈0,1〉SEMI
1 STATUS REGISTER
32 bits
DSTAT
DDO PIU
SIU0
DDO
DSI1
SIU1
16
27
16
27
20
20
20
20
20
20
14
(TO CORES)
PIU ADDRESSING
BYPASS CHANNEL
SOCIX1
SICIX1
SOCIX0
SICIX0
REQUEST
ZIAB ZIDB
3220
MMT
SOURCE
LOOK-AHEAD
BUFFER
(6 x 32 FIFO)
Z-BUS
ARBITER
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers
Table 29 lists the DMAU memory-mapped regist ers in functional order, not in address order. Section 6.2.2 on
page 231 des cribes addres sing of memory -map ped registers. The DMAU contains a status register and two mas-
ter control registers for all SWT and MMT channels: DMCON0, DMCON1, and DSTAT. Every DMAU channel has
a corresponding control register CTL〈0—5〉, source and destination address register (SADD〈0—5〉 and
DADD〈0—5〉), source and destination count er register (SCNT〈0—5〉 and DCNT〈0—5〉), and limit register
(LIM〈0—5〉). In addition, each SWT channel has a corresponding source and destination base address register
(SBAS〈0—3〉 and DBAS〈0—3〉), reindex register (RI〈0—3〉), and stride register (STR〈0—3〉).
Table 29. DMAU Memory -Mapped Registers
Type Register
Name Channel Address Size
(Bits) R/W Type Signed/
Unsigned Reset
Value†
DMAU Status DSTAT All 0x4206C 32 R status unsigned X
DMAU Master Control 0 DMCON0 All 0x4205C 16 R/W control unsigned 0
DMAU Master Control 1 DMCON1 All 0x4205E
Channel Cont rol CTL0 SWT0 0x42060 16 R/W control unsigned X
CTL1 SWT1 0x42062
CTL2 SWT2 0x42064
CTL3 SWT3 0x42066
CTL4 MMT4 0x42068
CTL5 MMT5 0x4206A
Source Address SADD0 SWT0 0x42000 32 R/W address unsigned X
Destination Addr ess DADD0 0x42002
Source Address SADD1 SWT1 0x42004
Destination Addr ess DADD1 0x42006
Source Address SADD2 SWT2 0x42008
Destination Addr ess DADD2 0x4200A
Source Address SADD3 SWT3 0x4200C
Destination Addr ess DADD3 0x4200E
Source Address SADD4 MMT4 0x42010
Destination Addr ess DADD4 0x42012
Source Address SADD5 MMT5 0x42014
Destination Addr ess DADD5 0x42016
Source Count SCNT0 SWT0 0x42020 20 R/W data unsigned X
Destination Count DCNT0 0x42022
Source Count SCNT1 SWT1 0x42024
Destination Count DCNT1 0x42026
Source Count SCNT2 SWT2 0x42028
Destination Count DCNT2 0x4202A
Source Count SCNT3 SWT3 0x4202C
Destination Count DCNT3 0x4202E
Source Count SCNT4 MMT4 0x42030
Destination Count DCNT4 0x42032
Source Count SCNT5 MMT5 0x42034
Destination Count DCNT5 0x42036
† For this colum n, X ind i cates unkn own on po werup reset and unaff ected on su bsequent reset. Any reserv ed fields wit hi n the re gi ster are reset to zero.
‡ The reindex regist ers are i n sign-magnitud e fo rmat.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
Table 29. D MAU Mem ory -Mapped Registers (continued)
4.13.2 Reg ist ers (continued)
Note: The remainder of Section 4.13.2 describes the detailed encoding for each register.
Limit LIM0 SWT0 0x42050 20 R/W data unsigned X
LIM1 SWT1 0x42052
LIM2 SWT2 0x42054
LIM3 SWT3 0x42056
LIM4 MMT4 0x42058
LIM5 MMT5 0x4205A
Source Base SBAS0 SWT0 0x42040 20 R/W address unsigned X
Destination Base DBAS0 0x42042
Source Base SBAS1 SWT1 0x42044
Destination Base DBAS1 0x42046
Source Base SBAS2 SWT2 0x42048
Destination Base DBAS2 0x4204A
Source Base SBAS3 SWT3 0x4204C
Destination Base DBAS3 0x4204E
Stride STR0 SWT0 0x42018 16 R/W data unsigned X
STR1 SWT1 0x4201A
STR2 SWT2 0x4201C
STR3 SWT3 0x4201E
Reindex RI0 SWT0 0x42038 20 R/W data signed‡X
RI1 SWT1 0x4203A
RI2 SWT2 0x4203C
RI3 SWT3 0x4203E
Type Register
Name Channel Address Size
(Bits) R/W Type Signed/
Unsigned Reset
Value†
† For this colum n, X ind i cates unkn own on po werup reset and unaff ected on su bsequent reset. Any reserv ed fields wit hi n the re gi ster are reset to zero.
‡ The reindex regist ers are i n sign-magnitud e fo rmat.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
The DMAU status register (DSTAT) reports curren t DMAU channel activity for bo th source and destination opera-
tions and reports cha nnel errors. T his register can be rea d by the user software executing in either core to deter-
mine if a specific DMAU channel is already in use , or if an error has occurred that may result in data corruption.
The ERR[5:0] fields of the DSTAT register reflect DMAU protocol errors. See S ection 4.13. 8 on page 94 for infor-
mation on error reporting and recove ry.
Table 30. DSTAT (DMAU Status) Register
The memory address for this register is 0x4206C.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBSY5 RBSY4 SBSY5 DBSY5 SRDY5 DRDY5 ERR5 SBSY4 DBSY4 SRDY4 DRDY4 ERR4 SBSY3 DBSY3 SRDY3 DRDY3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR3 SBSY2 DBSY2 SRDY2 DRDY2 ERR2 SBSY1 DBSY1 SRDY1 DRDY1 ERR1 SBSY0 DBSY0 SRDY0 DRDY0 ERR0
Bits Field Value Description R/W Reset
Value†
31 RBSY5 1 MMT 5 is busy completing a reset operation‡.RX
0 MM T5 is not completing a reset operation.
30 RBSY4 1 MMT 4 is busy completing a res et operati on‡.RX
0 MM T4 is not completing a reset operation.
29 SBSY5 1 MMT 5 is reading memory. R X
0 MM T5 is not reading memory.
28 DBSY5 1 MMT5 is writing memory. R X
0 MM T5 is not writing memory.
27 SRDY5 1 MMT5 has a source transaction pendin g. R X
0 MM T5 does not have a source transaction pending.
26 DRDY5 1 MMT5 has a destination transaction pending. R X
0 MM T5 does not have a destination transaction pending.
25 ERR5 1 MMT 5 has dete cted a protocol error (source or des tination). Error report i s cle ared by
writing a 1 to this bit. R/Clear X
0MMT5—no errors.
24 SBSY4 1 MMT 4 is reading memory. R X
0 MM T4 is not reading memory.
23 DBSY4 1 MMT4 is writing memory. R X
0 MM T4 is not writing memory.
22 SRDY4 1 MMT4 has a source transaction pendin g. R X
0 MM T4 does not have a source transaction pending.
21 DRDY4 1 MMT4 has a destination transaction pending. R X
0 MM T4 does not have a destination transaction pending.
20 ERR4 1 MMT 4 has dete cted a protocol error (source or des tination). Error report i s cle ared by
writing a 1 to this bit. R/Clear X
0 MM T4—no errors.
19 SBSY3 1 SWT3 is re ading memory. R X
0 SW T3 is not reading memory.
18 DBSY3 1 SWT3 is writing memory. R X
0 SW T3 is not writing memory.
† For this column, X ind i cates unknown on po werup reset and unaffected on subsequ ent reset.
‡ A core re sets MM T 5 by sett i ng the RESET5 f i el d (DMCON1[5]—Table 32 on page 72) and res ets MMT 4 by sett i ng th e RESE T 4 field ( DMCON1[4]).
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
Table 30. DSTAT (DMAU Status) Register (continued)
4.13.2 Reg ist ers (continued)
17 SRDY3 1 SWT3 has a source transaction pending. R X
0 SW T3 does not have a source transaction pending.
16 DRDY3 1 SWT3 has a destination transaction pending. R X
0 SW T3 does not have a destination transaction pending.
15 ERR3 1 SWT 3 has detec ted a pro tocol error (sour ce or des ti nati on). Error report is cleared by
writing a 1 to this bit. R/Clear X
0SWT3—no errors.
14 SBSY2 1 SWT2 is re ading memory. R X
0 SW T2 is not reading memory.
13 DBSY2 1 SWT2 is writing memory. R X
0 SW T2 is not writing memory.
12 SRDY2 1 SWT2 has a source transaction pending. R X
0 SW T2 does not have a source transaction pending.
11 DRDY2 1 SWT2 has a destination transaction pending. R X
0 SW T2 does not have a destination transaction pending.
10 ERR2 1 SWT 2 has detec ted a protocol e rr or (source or des tination). Error report i s cleared by
writing a 1 to this bit. R/Clear X
0 SW T2—no errors.
9 SBSY1 1 SWT1 is re ading memory. R X
0 SW T1 is not reading memory.
8 DBSY1 1 SW T1 is writing memory. R X
0 SW T1 is not writing memory.
7 SRDY1 1 SW T1 has a source transaction pending. R X
0 SW T1 does not have a source transaction pending.
6 DRDY1 1 SWT1 has a destination transaction pending. R X
0 SW T1 does not have a destination transaction pending.
5 ERR1 1 SWT 1 has detec ted a protocol error (source o r destination). Error report is cleared by
writing a 1 to this bit. R/Clear X
0 SW T1—no errors.
4 SBSY0 1 SWT0 is re ading memory. R X
0 SW T0 is not reading memory.
3 DBSY0 1 SW T0 is writing memory. R X
0 SW T0 is not writing memory.
2 SRDY0 1 SW T0 has a source transaction pending. R X
0 SW T0 does not have a source transaction pending.
1 DRDY0 1 SWT0 has a destination transaction pending. R X
0 SW T0 does not have a destination transaction pending.
0 ERR0 1 SWT 0 has detec ted a protocol error (source o r destination). Error report is cleared by
writing a 1 to this bit. R/Clear X
0 SW T0—no errors.
Bits Field Value Description R/W Reset
Value†
† For this column, X ind i cates unknown on po werup reset and unaffected on subsequ ent reset.
‡ A core re sets MM T 5 by sett i ng the RESET5 f i el d (DMCON1[5]—Table 32 on page 72) and resets MMT4 by setting the RESET4 field (DMCON1[4]).
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
The DMAU master control registers, DMCON0 and DMCON1, control the reset, enable, or disable of individual
DMAU channel s. DMCON0 also controls the enabling of the source look-ahead buffer for pipelined MMT reads of
a source block.
Table 31. DMCON0 (DMAU Master Control 0) Register
The memory address for this register is 0x4205C.
15 14 13 12 11 10 9 8 7—4 3—0
HPRIM MINT XSIZE5 XSIZE4 TRIGGER5 TRIGGER4 SLKA5 SLKA4 DRUN[3:0] SRUN[3:0]
Bits Field Value Definition R/W Reset
Value
15 HPRIM 0 If MMT channel int erruption is enabled (if MINT is set), thi s bit indic ates MMT4 is
the higher-priority channel. R/W 0
1 If MMT cha nnel interrupti on is enabled (if MINT is set ), this bi t in dicates MMT5 i s
the higher-priority channel.
14 M INT 0 If the DMAU has b egun process ing an MMT c hanne l, it trans fer s all t he d ata fo r that
MMT channel wit hout interrup ti on by the othe r MMT cha nnel. Any SWT or PIU
bypa ss channel requests interrupt the active MMT channel.
R/W 0
1 The higher-p ri ority MMT channel indicated by HPRIM can preempt the lower-prior-
ity MMT channel. If the DMAU has begun proc essing the higher-priority MMT
channel, it transfer s all the data for that MMT channel withou t interru ption by the
lower-priority MMT channel. Any SWT or PIU bypass channel requests interrupt
the active MMT channel.
13 XSIZE5 0 MMT5 transf ers sing le wor ds (16-bit values). R/W 0
1 MMT5 transfers aligned double words (32-bit values)†.
12 XSIZE4 0 MMT4 transf ers sing le wor ds (16-bit values). R/W 0
1 MMT4 transfers aligned double words (32-bit values)†.
11 TRIGGER5 0 If the DMAU beg ins a bloc k transfer usi ng MMT5 , it autom atically clea rs t his bit . I f a
core wri tes a 0 to this bit position, it has no ef fect and does not change the DMAU
acti vity. Th e cores can cause the DMAU to terminat e chann el acti vity by setti ng the
RESET5 field (DMCON1[5]—Tabl e 32 on page 72).
R/W 0
1 Set by core softw are to r equest the DMAU to begin a block tra nsfer using M MT 5.
10 TRIGGER4 0 If the DMAU beg ins a bloc k transfer usi ng MMT4 , it autom atically clea rs t his bit . I f a
core wri tes a 0 to this bit position, it has no ef fect and does not change the DMAU
acti vity. Th e cores can cause the DMAU to terminat e chann el acti vity by setti ng the
RESET4 field (DMCON1[4]—Tabl e 32 on page 72).
R/W 0
1 Set by core softw are to r equest the DMAU to begin a block tra nsfer using M MT 4.
9 SLKA5 0 For ce source and des ti nati on accesses f or MM T5 to occur in order (source look-
ahead disabled). R/W 0
1 Permit source reads for MMT5 to be launched before older destination writes
(source look-ahead enab led). This maximizes block transfer throughput.
8 SLKA4 0 For ce source and des ti nati on accesses f or MM T4 to occur in order (source look-
ahead disabled). R/W 0
1 Permit source reads for MMT4 to be launched before older destination writes
(source look-ahead enab led). This maximizes block transfer throughput.
† The corresponding source and destination addresses must be even.
‡ Each bit of DRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, DRUN3 corresponds to SWT3.
§ Each bit of SRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, SRUN2 corresponds to SWT2.
4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
Table 31. DMCON0 (DMAU M aster Control 0) Register (continued)
4.13.2 Reg ist ers (continued)
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Table 32. DMCO N1 (DMAU M aster Con trol 1) Register
7—4 DRUN[3:0] 0 The DMAU clea rs t his field if i t has completed a destination transfer and the corre-
sponding AUTOLOAD fi eld (CTL〈0—3〉[0]—Table 34 on page 74) is cleared. If a
core wri tes a 0 to this bit position, it has no ef fect and does not change the DMAU
acti vity. Th e cores can cause the DMAU to terminat e chann el acti vity by setti ng the
corresponding RESET[3:0] field (DMCON1[3:0]—Table 32 on page 72).
R/
Set 0
1 The software r unning in a core set s this field to cause th e DMAU to ini tiate a new
destination transfer for th e corr esponding SWT channel‡.
3—0 SRUN[3:0] 0 The DMAU clears t his field if it has completed a source t ransfer and the corre-
sponding AUTOLOAD fi eld (CTL〈0—3〉[0]—Table 34 on page 74) is cleared. If a
core wri tes a 0 to this bit position, it has no ef fect and does not change the DMAU
acti vity. Th e cores can cause the DMAU to terminat e chann el acti vity by setti ng the
corresponding RESET[3:0] field (DMCON1[3:0]—Table 32 on page 72).
R/
Set 0
1 The software r unning in a core set s this field to cause th e DMAU to ini tiate a new
source transfer for the corresponding SWT channel§.
The memory address for this register is 0x4205E .
15—7 6 5—4 3—0
Reserved PIUDIS RESET[5:4] RESET[3:0]
Bits Field Value Definition R/W Reset
Value
15—7 Reserved 0 Reserv ed—write with zero. R/W 0
6 PIUDIS 0 The DMAU processe s PIU req uests. R/W 0
1 The DMAU ignores PIU requ ests.
5—4 RESET[5:4] 0 The corresponding MMT channel† is unaffect ed.
† RESET5 corresp o nds t o MMT5 a n d RESET 4 co r resp o nds t o MMT4 . Setting RESET[5: 4] doe s no t a ffe ct t he state of any DMAU reg i ste r s. RESET[5:4]
is typicall y used f or error recover y—see S ecti on 4.13.8 on pa ge 94 fo r details.
R/W 0
1 The software running in a core set s this field to cause t he DMAU to uncondi-
tionally terminate all channel activity for the corresponding MMT channel †.
3—0 RESET[3:0] 0 The corresponding SWT channel‡ is unaff ected.
‡ Each bi t of RESET[3: 0] corr esponds to o ne of the SWT〈0—3〉 channels. For example, RESET3 corresponds to SWT3. Setting a RESET[3:0] field does
not affect the s tate of any DMA U registers , including the st ate of t he S RUN[3: 0]/DRUN[3:0] fiel ds (DMCON0[7:0]—Table 31). RE SE T [ 3:0] i s t ypically
used for error rec over y—see Section 4.13. 8 on page 94 for deta ils .
R/W 0
1 The software running in a core set s this field to cause t he DMAU to uncondi-
tionally terminate all channel activity for the corresponding SWT channel‡.
Bits Field Value Definition R/W Reset
Value
† The corresponding source and destination addresses must be even.
‡ Each bit of DRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, DRUN3 corresponds to SWT3.
§ Each bit of SRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, SRUN2 corresponds to SWT2.
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 34 on page 74 describes the SWT〈0—3〉 cont rol
registers, CTL〈0—3〉. Each of the CTL〈0—3〉 registers
controls the behavior of the corresponding SWT chan-
nel and determines the following:
1. Whet her the access takes place in row-major (two-
dimensional array) or column-major (one-dimen-
sional array) order.
2. Whether the autoload featur e is enabled or disabled.
If enabled, this feature causes the DMAU to auto-
matically reload the address registers with the con-
tents of the base register after an entire array has
been proc essed .
3. T he point in the operation when a DMAU interrupt
reques t is generated.
The control register for a specific SWT chann el deter-
mines these attributes for both the source and destina-
tion transfers for th at channel. Therefore, if the SWT
channel is used for bidirectional transfers, the source
and destination data must have the same array size
and structure. As a result, each SWT channel has only
one stride (STR〈0—3〉) and one reindex (RI〈0—3〉)
register. Therefore, references to fields in Table 34 are
common to both SWT source and destination tr ansfers
and are given as common references. Table 33 maps
the common ref erences used in Table 34 to their spe-
cific attribute.
Table 33. Collective Designations Used in Tab le 34
Collective
Designation Descri ption Register or Register Fie ld See
RUN Source Channel Enable f or SWT 〈3—0〉SRUN[3:0] (DMCON0[3:0]) Table 31 on page 71
Desti nation Channel Enable for SWT〈3—0〉DRUN[3:0] (DMCON0[7:4])
ADD Source Address SADD〈0—3〉Table 37 on page 77
Destination Address DADD〈0—3〉
ROW Source Row Counter SROW[12:0 ] (SCNT〈0—3〉[19:7]) Table 38 on page 78
Destination Row Counter DROW [12:0] (DCNT〈0—3〉[19:7]) Table 40 on page 79
COL Source Column Counter S C O L [6 :0 ] ( SCNT〈0—3〉[6:0]) Table 38 on page 78
Destination Column Counter DCOL[6:0] (DCNT〈0—3〉[6:0]) Table 40 on page 79
LASTROW Row Limit LAST ROW [12:0] (LIM〈0—3〉[19:7]) Table 42 on page 80
LASTCOL Column Limit LASTCOL[6:0] (LIM〈0—3〉[6:0])
BAS Source Base Register SBAS〈0—3〉Table 44 on page 81
Destination Base Register DBAS〈0—3〉Table 45 on page 81
STR Stride Regi ster STR〈0—3〉Table 46 on page 82
RI Reindex Register RI〈0—3〉Table 47 on page 82
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 34. C TL〈0—3〉 (SWT〈0—3〉 Control) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
15—6 5—4 3—1 0
Reserved POSTMOD[1:0] SIGCON[2:0] AUTOLOAD
Bit Field Value Definition R/W Reset
Value†
15—6 Reserved 0 Reserved—write with zero. R/W 0
5—4 POSTMOD [1: 0] 00 The DMAU perform s no pointer or counter updat e operat ions. R/W XX
01 Select two-dimensional array accesses. After every transaction:
If the column counter has not expired, the DMAU increments it by one
and increment s the address by the contents of the stride regis ter.
(If C O L≠LASTCOL, then COL=COL+1 and ADD=ADD+STR.)
If t he row counter has not ex pired and the column counter has expired,
the DMAU increments the row cou nter by one, clears the column
counter, and in crements the addres s by t he contents of the sign -magni-
tude r eindex re giste r . (If ROW≠LASTROW a nd COL=LASTCOL, then
ROW=ROW+1, COL=0, and ADD=ADD+RI.)
If both the row counter and the column counter have expired and the
AUTO LOAD field is se t, the DMAU clears th e row and col umn counter s
and rel oads the addres s with the bas e value. (If ROW=LASTROW and
COL=LASTCOL and AUTOLOAD=1, then ROW=0, COL=0, and
ADD=BAS.)
If both the row counter and the column counter have expired and the
AUTO LO AD fie ld i s cleare d, t he DMAU deac ti vates t he channel.
(If ROW=LASTROW and COL=LASTCOL and AUTOLOA D=0, then
RUN=0.)
10 Select one- dimensi onal array accesses. After every transaction:
If the row counter has not expired, the DMAU increments the counter
and the address. (If ROW≠LASTROW, then ROW=ROW+1 and
ADD=ADD+1.)
If t he row counter has expir ed and t he col um n counte r has not expired,
the DMAU clears the row counter and incr em ents the co lumn counte r
and the address. (If ROW=LASTROW and COL≠LASTCOL, th en
ROW=0, COL=COL+1, and ADD=ADD+1.)
If both the row counter and the column counter have expired and the
AUTO LOAD field is se t, the DMAU clears th e row and col umn counter s
and rel oads the addres s with the base valu e. (If ROW=LASTROW and
COL=LASTCOL and AUTO LOAD=1, then ROW=0, COL=0, and
ADD=BAS.)
If both the row counter and the column counter have expired and the
AUTO LO AD fie ld i s cleared, t he DMAU clears the row and col umn
counter s, relo ads the address with the base val ue, and deacti vates the
channel. (If ROW=LASTROW and COL=LASTCOL and
AUTOLOAD=0, then ROW=0, COL=0, ADD=BAS, and RUN=0.)
11 Reserved.
† For this column, X ind i cates unknown on po werup reset and unaffected on subsequ ent reset.
‡ The DMAU hardware performs the division as a one-bit right shift. Therefore, the least significant bit is truncated for odd values of LASTROW or LAST-
COL.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
Table 34. CTL〈0—3〉 (SWT〈0—3〉 Control) Registers (continued)
4.13.2 Reg ist ers (continued)
MMT block transfers are unidirectional only, but are listed as comm on references for consistency with the SWT
channels. Each of the CTL〈4—5〉 registers described in Table 36 on page 76 contro ls the behavior of the corre-
sponding MMT channel. The control register of a specific MMT channel determines the point in the block transfer
when a DMAU interrupt request is generated. Table 35 on page 76 maps the common references used in Table 36
on page 76 to their sp ecific attribute.
3—1 SIGCON[2:0] 000 The DMAU generates an interrupt request after each single word has
been transferred . R/W XXX
001 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with ROW equal to LASTROW/2‡.
010 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with COL equal to LASTCOL.
011 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with COL equal to LASTCOL and ROW equal to LASTROW/2‡.
100 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with ROW equal to LASTROW.
101 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with COL equal to LASTCOL and ROW equal to LASTROW.
110 The DMAU gene rates an i nterr upt reques t followi ng compl etion of a tr ans-
fer with COL equal to LASTCOL/2‡ and ROW equal to LASTROW.
111 Reserved.
0 AUTOLOAD 0 After th e DMAU transfers an entire arr ay, it deactivates the channel.
(If ROW=LASTROW and COL=LASTCOL, then RUN=0.) The software
can reactivate the channel by setting the RUN field.
R/W X
1After the DMAU transfers an entire array, it reloads the channel’s counter
and address registers with their base values and initiates another array
transfer wi thout core in ter vention. (If ROW=LASTROW and
COL=LASTCOL, then ROW=0, COL=0, and ADD=BAS.)
Bit Field Value Definition R/W Reset
Value†
† For this column, X ind i cates unknown on po werup reset and unaffected on subsequ ent reset.
‡ The DMAU hardware performs the division as a one-bit right shift. Therefore, the least significant bit is truncated for odd values of LASTROW or LAST-
COL.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 35. C ollective Design ations Used in Table 36
Table 36. C TL〈4—5〉 (MMT〈4—5〉 Con trol) R egisters
Collective
Designation Description Register or Register Fie ld See
XSIZE Transfer Size for MMT4 XSI ZE4 (DMCON0[12])
(0 for 16 bits or 1 for 32 bits) Table 31 on page 71
Transfer Size for MMT5 XSI ZE5 (DMCON0[13])
(0 for 16 bits or 1 for 32 bits)
ADD Source Address SADD〈4—5〉Table 37 on page 77
Desti nation Address DADD〈4—5〉
ROW Source Row Counter SROW[12:0] (SCNT〈4—5〉[19:7]) Table 39 on page 78
Destination Row Counter DROW[12:0] (DCNT〈4—5〉[19:7]) Table 41 on page 79
LASTROW Row Limit LASTROW[12:0 ] (LIM〈4—5〉[19:7]) Table 43 on page 80
See Table 29, starting on page 67, for the memory addresses of these registers.
15—6 5—4 3—1 0
Reserved POSTMOD[1:0] SIGCON[2:0] Reserved
Bit Field Value Definition R/W Reset
Value†
15—6 Res erved 0 Reserved—write with zero. R/W 0
5—4 POSTMOD[1:0] 00 The DMAU performs no poi nter or counter upd ate operati ons. R/W XX
01 Reserved.
10 After every transaction:
If t he row counter has not expired, the DMAU increments it and i ncre-
ments the address by the el ement size‡. (If ROW≠LASTROW, then
ROW=ROW+1 and ADD=ADD+1+XSIZE.)
If the row c ounter has expired, the DMAU clear s the row counter, incre-
ments the address by the el ement size‡, and deacti vates the channel.
(If ROW=LASTROW, then RO W=0 and ADD=ADD+1+XSIZE.)
11 Reserved.
3—1 SIGCON[2:0] 000 The DMAU generates an interrupt request after each element‡ has been
transferred. R/W XXX
001 The channel genera tes an interr upt requ est following complet ion of a
transfer with ROW equal to LASTROW/2.
01X Reserved.
100 The channel genera tes an interr upt requ est following complet ion of a
transfer with ROW equal to LASTROW.
101 Reserved.
11X Reserved.
0 Reserved 0 Reserved—write with zer o. R/W 0
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
‡ The element si ze is 1 for single-w ord tr ansactions (XSIZE = 0 ) or 2 for double-word transactio ns (XSI ZE = 1).
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 37. SADD〈0—5〉 and DADD〈0—5〉 (Channels 0—5 Source and Destination Address) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
31—27 26—23 22—20 19—0
Reserved ESEG[3:0] CMP[2:0] ADD[19:0]
Bit Field Value Description R/W Reset
Value†
31—27 Reser ved 0 Reser ved—writ e wit h zero. R/W 0
26—23 ESEG[3:0] 0x0
to
0xF
External memory address extension. If the DMAU accesses external
memory (CMP[2:0] = 100), it cau ses the SEMI to place the value in t his
field onto the ESEG[3:0] pins.
R/W X
22—20 CMP[2:0] 000 The select ed m em ory component is TPRAM0. R/W XXX
001 The select ed m em ory component is TPRAM1. R/W
01X Reserved. R/W
100 The select ed m em ory component is ERAM‡, EIO, or internal I/O. R/W
101 Reserved. R/W
11X Reserved. R/W
19—0 ADD[19:0] 0x00000
to
0xFFFFF
The addres s wi thin the se lec ted memo ry component . For an MMT〈4—5〉
channel, if the corresponding XSIZE[5:4] field (DMCON0[13:12]—see
Table 31 on page 71) is se t, this value must be even.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
‡ If the WE ROM fiel d (ECON1[11]—Table 61 on page 1 12 ) is set, EROM is selected in place of ERAM.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 38. SCNT〈0—3〉 (SWT〈0—3〉 Source Counter) Reg isters
Table 39. SCNT〈4—5〉 (MMT〈4—5〉 Source Counter) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6—0
SROW[12:0] SCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 SROW [12:0] The row counter of the one-dimensional or two-dimensional source array for
the corresponding SWT channel (read dat a). The DMAU updates this field
as the tr ansfer proceeds and automatically clears it upon t he com pletion of
the tr ansfer.
R/W X
6—0 SCOL[6:0] The column counter of the one-dimens ional or two-d imensional sour ce arra y
for t he corres ponding SWT channel (read data). The DMAU updates this
fie ld as the transf er pr oceeds and aut omat ically cl ear s it upon the com pletion
of the t ransfe r.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset . SCNT〈0—3〉 are not cle ared by a reset of the DMA U
channel via the DMCON1 register (Table 32 on page 72). B ef ore an S WT chan nel can be used, the pro gram mu st clear t he correspo ndi ng
SCNT〈0—3〉 regist er after a DSP 16411 device reset. Otherwis e, the value of this regi st er is undefi ned.
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6—0
SROW[12:0] SCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 SROW [12:0] The row counter of the source block for the corresponding MMT channel
(read data). The DMAU increment s this field as the transfer proceeds and
automati cally clears it upon the completion of the tran sfer.
R/W X
6—0 SCOL[6:0] The column count er of the source block for t he corres ponding MMT channel
(read data). Typ ically, the user has progra mmed the LASTCOL[6:0] fiel d
(LIM〈4—5〉[6:0]—Table 43 on page 80) with zero, and therefore, the DMAU
does not update thi s fi eld.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset . SCNT〈4—5〉 are not cle ared by a reset of the DMA U
channel via the DMCON1 register (Table 32 on page 72). B ef ore an MM T chann el can be used, the prog ram mus t cl ear the corr espon di ng
SCNT〈4—5〉 regist er after a DSP 16411 device reset. Otherwis e, the value of this regi st er is undefi ned.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 40. DCNT〈0—3〉 (SWT 〈0—3〉 Destination Counter) Registers
Table 41. DCNT〈4—5〉 (MMT〈4—5〉 Destination Counter) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6—0
DROW[12:0] DCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 DROW[12: 0] The row coun ter of t he one-di mensi onal or t wo-di mensi onal dest inat ion arr ay
for t he corres ponding SWT channel (write data). The DMAU updates this
fie ld as the transf er pr oceeds and aut omat ically cl ear s it upon the com pletion
of the t ransfe r.
R/W X
6—0 DCOL[ 6:0] The column count er of the one-dimensional or two-dimensional des ti nation
array for the cor responding SWT chann el ( w ri te data). The DMAU upd ates
this field as the transfer proceeds and automatically clears it upon the com-
pletion of th e transfer.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset . DCNT〈0—3〉 are not cleared by a reset of the DMAU
channel via the DMCON1 register (Table 32 on page 72). Before an SWT chan nel can be used, the pro gram mu st clear t he correspo ndi ng
DCNT〈0—3〉 regi ster after a DSP1 6411 devi ce reset . Othe rwise, the v al ue of this regis ter is undefined.
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6:0
DROW[12:0] DCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 DROW[12: 0] The row c ounter of the destina ti on bloc k for the corr espondi ng M M T channel
(write data) . The DMAU increments this f iel d as the transfer proceeds and
automati cally clears it upon the completion of the tran sfer.
R/W X
6—0 DCOL[6:0] The column counter of the destination block for the corresponding MMT
channel (wr it e data). Typical ly, the user has programmed the LASTCOL[6:0]
fi eld (LIM〈4—5〉[6:0]—Table 43 on page 80) with zero, and therefore, the
DMAU does not update this field.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset . DCNT〈4—5〉 are not cleared by a reset of the DMAU
channel via the DMCON1 register (Table 32 on page 72). Before an MMT chann el can be used, the prog ram must cl ear the corr espon di ng
DCNT〈4—5〉 regi ster after a DSP1 6411 devi ce reset . Othe rwise, the v al ue of this regis ter is undefined.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 42. L IM〈0—3〉 (SWT〈0—3〉 Limit) Re gisters
Table 43. LIM〈4—5〉 (MMT〈4—5〉 Limit) Re gi st ers
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6—0
LASTROW[12:0] LASTCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 LASTROW[12:0] The last row count for both the source and destination arrays for the corre-
sponding SWT channel. The sou rce and destination arrays are either one-
dimension al or two-dimensional. For a single-buff ered array, t his field is pro -
gramm ed wit h the n umber of ro ws i n each si ngle buffer minus one (
r
–1). For
a double-buffer ed two-dimensional array, this field is program m ed wit h two
times the number of ro ws in each single buffer minus one ((2 ×
r
)–1).
R/W X
6—0 LASTCOL[6:0] The last col um n count for both t he source and des tination arrays for the cor-
respondi ng SWT cha nnel. The sour ce and destination arrays are eit her one-
dimensional or two-dimensional. This field is programmed with the number
of columns minus one (
n
–1).
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
See Table 29, starting on page 67, for the memory addresses of these registers.
19—7 6—0
LASTROW[12:0] LASTCOL[6:0]
Bit Field Description R/W Reset
Value†
19—7 LASTROW[12:0] The last row count for both the source and destination blocks for the corre-
sponding MMT channel. This field is typically programm ed with the number
of rows‡ in t he block minu s o ne (
r
–1).
R/W X
6—0 LASTCOL[6:0] The last col um n count for both t he source and des tination blocks for the cor-
respondi ng MMT channel. The user typically pro grams thi s fi eld with zero§.R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
‡ Each row contains one el ement. The elem ent si ze is eit her 16 bit s or 32 bits, based on the p rogra m m in g of the XSIZE4 or XSI Z E5 field
(DMCON0[13:12]—Table 31 on pa ge 71).
§ This document assumes that the LASTCOL[6:0] field is programmed with zero.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 44. SBAS〈0—3〉 (S WT〈0—3〉 Source Base Address) Registers
Table 45. DBAS〈0—3〉 (SWT〈0—3〉 Destination Base Address) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
19—0
Source Base Address
Bit Field Description R/W Reset
Value†
19—0 Source Base
Address The program must initialize t he SBAS〈0—3〉 register with the starting address of the
one-dimensional or two-dimensional source array for the corresponding channel
(read data). I f the corresponding AUTOLOAD f ield (CTL〈0—3〉[0]) is set, the DMAU
copies the con tents of SBAS〈0—3〉 to t he corresp onding SADD〈0—3〉 register after
the transfer of an ent ire array is com plete. The DMAU doe s not modi fy SBAS〈0—3〉.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
See Table 29, starting on page 67, for the memory addresses of these registers.
19—0
Destination Base Address
Bit Field Description R/W Reset
Value†
19—0 Destination
Base Address The program must initiali ze the DBAS〈0—3〉 register with the starting address of the
one-dimensi onal or two-dimens ional desti nation array for the correspondi ng channel
(write data). If the corresponding AUTOLOAD field (CTL〈0—3〉[0]) is set, the DMAU
copies the con tents of DBAS〈0—3〉 to th e corresp onding DADD〈0—3〉 regi ster after
the tran sfer of an entire array is complete. The DMAU does not modi fy DBAS〈0—3〉.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Reg ist ers (continued)
Table 46. STR〈0—3〉 (SWT〈0—3〉 Stride) Registers
Table 47. RI〈0—3〉 (SWT〈0—3〉 Reindex) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
15—14 13—0
Reserved Stride
Bit Field Value Description R/W Reset
Value†
15—14 Res erved 0 Reserved—write with zero. R/W 0
13—0 Stride ≤16,383 If the corresponding SWT channel is programmed for one-dimensional array
access es (i f the POSTMOD[1: 0] field (CTL〈0—3〉[5:4]) is 0x2), this field is ignored.
If the corresponding SWT channel is programmed for two-dimensional array
accesses (i f t he POST MOD[ 1:0] fiel d (CTL〈0—3〉[5: 4]) is 0x1), the DMAU adds
the contents of this regi ster to the cor respond ing source and desti nati on addres s
registers (SADD〈0—3〉 and DADD〈0—3〉) until it processes the last column i n the
array. The program mu st initi alize thi s register with the numbe r of memory loca-
tions between corresponding ro ws (el em ents) of consecutive colum ns (buffers).
T y pical ly, the col umns (buf f ers) are bac k-to- back (cont iguous ) in memor y, and this
register i s programmed wit h the number of rows per column .
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
See Table 29, starting on page 67, for the memory addresses of these registers.
19 18—0
Sign Bit Magnitude
Bit Fie ld Value Descr ipt ion R/W Reset
Value†
19 Si gn Bit 1 If the corresponding SWT channel is programmed for one-dimensional
array acc esses (if the POSTMOD[1:0] fi eld (CTL〈0—3〉[5:4]) is 0x2), this
field is ignored.
If t he corresp onding SWT channel is program med for two-dimensi onal
array acc esses (if the POSTMOD[1:0] fi eld (CTL〈0—3〉[5:4]) is 0x1), this
bit must be set. This causes the reindex value to be negative and the
DMAU to subtract the reindex magnitude from SADD〈0—3〉 and
DADD〈0—3〉.
R/W X
18—0 Magnitude ≤262,143 If the corresp onding SWT channel is program m ed for one-dimens ional
array acc esses (if the POSTMOD[1:0] fi eld (CTL〈0—3〉[5:4]) is 0x2), this
field is ignored.
If t he corresp onding SWT channel is program med for two-dimensi onal
array acces ses (if the POSTMO D[1: 0] field (CTL〈0—3〉[5:4]) is 0x1), the
DMAU subtracts thi s value from the corresponding address register
(SADD〈0—3〉 or DADD〈0—3〉) after acce ssing th e last column in t he
array. For a single-buffered array of
r
rows and
n
columns (
n
> 1), the
magn itude of the r eindex value is (
r
×(
n
– 1)) – 1. For a double-buffered
arra y of
r
rows and
n
column s (
n
> 1), the magni tude of the rein dex value
is (2
r
×(
n
–1))–1.
R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.3 Data Structures
The DMAU moves data in one-dimensional array , two-dimensional array , and block transfer patterns. The following
sections outline these three types of data structures and the methods for programming the DMA U registers to
establish them.
4.13.3.1 One-Dimensional Data Structure (SWT Channels)
Figure 20 illustrates the structure of a one-dimensional array for an SWT channel. The array consists of
n
columns
(buff ers), each containing
r
rows (element s). The columns must be contiguous (back-to-back ) in memory. See
Section 4.13.5, beginning on page 87, for more information about SWT channels. See S ec tion 4.13.9.2, beginning
on page 97, for an example of a transfer using a one-dimensional array.
A One-D imensional Data St ructure for Buffer ing
n
Input Channels
Fi gure 20. One-D i m ensiona l Da t a St ruc tu re for Buffer ing
n
Channe ls
One-dimensional data structures for data transfers use
the address, base, limit, counter, and control registers
associated with the SWT channel carrying the data
between an SIU and memory.
CTL〈0—3〉:The user software must initialize the cor-
responding control register with the POSTMOD[1:0]
field programme d to 0x2 to enable one-dimensiona l
array accesses, the SIGCON[2:0] field programmed to
a value that defines when interrupts are generated, and
the AUTOLOAD field set to one so that no further core
interaction is needed.
DADD〈0—3〉 and SADD〈0—3〉:The user software
must initialize the corresponding destination and
source address registers to the top of th e input (desti-
nation) and output (source) arrays located in memory.
The DMAU automatically increments these registers as
the transfer proceeds.
DBAS〈0—3〉 and SBAS〈0—3〉:The us er software
must also initialize the corresponding destination and
source base regis ters to the top of the input (destina-
tion ) a nd output (sour ce) arr ay s lo ca ted in
memory. These registers are used with the autoload
feature of the associated SW T channe l.
LIM〈0—3〉:The user software must initialize the cor-
respon ding limit register with the dimensio ns of the
array. The number of rows (or elements) is
r
; therefore,
the LAST ROW [12 :0] field is programmed to
r
– 1. The
numbe r of column s,
n
, is the same as the number of
buffers; therefore, LASTCOL[6:0] field is programmed
to
n
–1.
DCNT〈0—3〉 and SCNT〈0—3〉:The corresponding
destinati on and source count registers contain the row
and column counters for one-dimensional array
accesses. The user software must initially clear these
registers. The DMAU automatically clears these regis-
ters upon the completion of an SWT tr ansfer, and incre-
ments the row and column counter fields of these
registers as the transfer proceeds.
DMCON0: The user software must set the corre-
sponding SRUN[3:0] and DRUN[3:0] fields in DMCON0
to enable source and destination tran sfers.
SOURCE
BUFFER
COMPLETE
SBAS〈0—3〉
AUTOLOAD
OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY
ROW=0
ROW=1
ROW=
r
–1
ROW=0
ROW=1
ROW=
r
–1
COL=0COL=
n
–1
SOURCE
BUFFER
COMPLETE
DESTINATION
BUFFER
COMPLETE
DBAS〈0—3〉
AUTOLOAD
ROW=0
ROW=1
ROW=
r
–1
ROW=0
ROW=1
ROW=
r
–1
COL=0COL=
n
–1
DESTINATION
BUFFER
COMPLETE
Advance Data Sheet
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.3 Data Structures (continued)
4.13.3.2 Tw o-Dimensional Data Structure (SWT Channels)
Figure 21 illu strates the structure of a two-dimens ional double-buffered array for an SWT channel. This structure i s
useful for TDM channel multiplexing and demultiplexing. The array c onsists of
n
columns (double buffers), each
containing 2
r
rows (elements). The co lumns are typically contiguous (back-to-back) in memory, but this is not
required. S ee Section 4. 13. 5, beginning on page 87 , for more information about SW T channel s. See
Section 4.13. 9. 1, beginning on page 95, for an example of a transfer using a two-dimens io nal array.
A Two-Dimensional Data Structure for Double-Buffering
n
Channels
Figure 21. Two-Dimensional Data Structure for Double-Buffering
n
Channels
Two-dimensional data structures for data transfers use
address, base, limit , counter, stride, reindex, and con-
trol registers associated with the SWT channel carrying
the data between an SIU and memory.
CTL〈0—3〉:The user software must initialize the cor-
responding control register with the POSTMOD[1:0]
field programme d to 0x1 to enable two-dimensio nal
array accesses, the SIGCON[2:0] field programmed to
a value that defines when interrupts are generated, and
the AUTOLOAD field set to one so that no further core
interaction is needed.
DADD〈0—3〉 and SADD〈0—3〉:The user software
must initialize the corresponding destination and
source address registers to the top of th e input (desti-
nation) and output (source) arrays located in
memory. The DMAU automatically updates these reg-
isters in a row-major order as the transfer proceeds.
DBAS〈0—3〉 and SBAS〈0—3〉:The user software
must also initialize the corresponding destination and
source base regist ers to the top of the input (destina-
tion) and output (source) arrays located in
memory. These registers are used with the autoload
feature of the associated SW T channe l.
COL=0COL=1
RI
〈
0—3
〉
STR
〈
0—3
〉
SBAS〈0—3〉
SOURCE
SOURCE
AUTOLOAD
DESTINATION
DESTINATION
OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY
SINGLE
SOURCE DESTINATION
FRAME
COMPLETE
BUFFER
COMPLETE
ARRAY
COMPLETE
FRAME COMP LETE
(SIGCON=0x2)
BUFFER COMPLETE
(SIGCON=0x3)
ARRAY COMPLETE
(SIGCON=0x5)
BUFFER
DOUBLE
BUFFER
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
COL=
n
–1
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
COL=0COL=1
RI
〈
0—3
〉
STR
〈
0—3
〉
DBAS〈0—3〉
AUTOLOAD SINGLE
BUFFER
DOUBLE
BUFFER
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
COL=
n
–1
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
ROW=0
ROW=1
ROW=2
r
–1
ROW=
r
–1
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.3 Data Structures (continued)
4.13.3.2 Two-Dimensional Data Structure (SWT
Channels) (continued)
LIM〈0—3〉:The user so ft wa re must in it ialize the cor-
responding limit register with the dimens ions of the
array. The number of rows (or elements) is
r.
For a sin-
gle-buffered array, the LASTROW[ 12:0] field is pro-
grammed to
r
– 1. For a double-buff ered ar ray
(Figure 21 on page 84), the LASTRO W[ 12:0] field is
programmed to (2×
r
) – 1. The number of columns (
n
)
is the same as the number of buffers. Therefore, the
LASTCOL [6:0] field is programmed to
n
–1.
DCNT〈0—3〉 and SCNT〈0—3〉:The corresponding
destination and source count registers contain the row
and column counters for two-dimensional array access.
The user software must initially clear these registers.
The DMAU automatically clears these registers upon
the completion of an SWT transfer and increments the
row and column counter fields of these registers as the
transfer proceeds.
STR〈0—3〉:Th e user software must initialize the cor-
respon ding stride register with the number of memo ry
locations between common rows (elements) of dif ferent
columns (buf fers). T ypical data structures have buffers
that are contiguous in memory. In this case, the stride
is the same as the buffer length (number of rows per
column ). If the current column is not the last column,
the DMAU increm ents the contents of DADD〈0—3〉
and SADD〈0—3〉 by the stride value after each trans-
action, i.e., increments the address registers in row-
majo r order. This ca uses DADD〈0—3〉 and
SADD〈0—3〉 to address the common row in the next
column.
RI〈0—3〉:The user software must init ialize the corre-
sponding reindex register to the sign-magnitude pointer
postmodification value to be applied to SADD〈0—3〉
and DADD〈0—3〉 after the DMAU has accessed the
last column. For a single-buf f ered array of
r
rows and
n
columns (
n
> 1), the magnitude of the reindex value
is (
r
×(
n
– 1 )) – 1. Fo r a double-buffered array of
r
rows and
n
columns (
n
> 1), the magnitude is
(2
r
×(
n
– 1)) – 1. B ecaus e the reindex value is always
negative for a two-dimensional array , the user software
must set the sign bit of RI〈0—3〉.
DMCON0: The user software must set the corre-
sponding SRUN[3:0] and DRUN[3:0] fields in DMCON0
to enable source and destination tran sfers.
Advance Data Sheet
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.3 Data Structures (continued)
4.13.3.3 Me m ory-to-Memo ry Block Transfers (MMT
Channels)
Figure 22 illu s trate s a me mory - to-memory b lock tr an s -
fer using an MMT channel. See Sect ion 4.1 3.6, begin -
ning on page 90, for more information about MMT
channels. See S ect ion 4.13.9.3 on page 99 for an
example of a memory-to-memory block data transfer
using an MMT chann el.
Memory-to-memory block data structures for data
transfers use address, limit , counter, and control regis-
ters associated with the MMT channel transferring the
data between two memories.
DADD〈4—5〉 and SADD〈4—5〉:The user software
must initialize the corresponding destination and
source address registers to the top of th e input (desti-
nation) and output (source) blocks located in
memory. The DMAU automatically updates these reg-
isters as the transfer proceeds.
LIM〈4—5〉:The user softwar e must initialize the cor-
respon ding limit register with the dimensio ns of the
array. The number of rows (or elemen ts) is
r
. There-
fore, the user software writes
r
– 1 to
LASTROW[12:0]. The array is struc tured as one col-
umn (one buffer). Therefore, the user software writes
zero to LASTCOL[6:0].
DCNT〈4—5〉 and SCNT〈4—5〉:The corresponding
destinati on and source count registers contain the row
and column counters for memory-to-memory block
transfe rs. The user softw are must initially clear these
registers. The DMAU automati cally clear s these regis-
ters upon the complet ion of an MMT source trans fer,
and updates these registers as the source transfer pro-
ceeds.
CTL〈4—5〉:The user software must write the control
register with SIGCON[2:0] set to a value that defines
when interrupts are generated.
DMCON0: The user software must set the co rre-
spon ding TRIGG ER[5:4] field in DMCON0 to enable
MMT transfers.
Me m o ry - t o -M e m or y B lo c k Tr an s f er
Figure 22. Memory-to-Memory Block Transfer
4.13.4 The PIU Addressing Bypass Channel
If the PIUDIS field (DMCON1[6]—Table 32 on page 72) is cleared, a host microprocessor connect ed to the
DSP16411 PIU port can gain access to the entire memory space of the DSP16411. The access is arbitrated by
the DMAU. If PIUDIS is set to one, PI U requests are ignored by the DMAU.
All PIU transactions are handled through the addressing bypass channel. H os t requests are independent of both
cores and add no overhead to core processing. The host can issue commands, read status information, read and
write DSP16411 mem ory, and send messages via the host parallel port. Spec i fic transactions are acco mplished
by host commands issued to the PIU. See Section 4.15.5, beginning on page 147, for more det ails.
DESTINATION ARRAYSOURCE ARRAY TRANSFER INITIAL VALUEIN ITI AL VALUE
TRANSFER
OF SADD〈4—5〉OF DADD〈4—5〉
ROW=0
ROW=1
ROW=
r
–1
ROW=(
r
–1)>>1
COL=0
ROW=0
ROW=1
ROW=
r
–1
ROW=(
r
–1)>>1
COL=0
1/2 COMPLETE
Advance Data Sheet
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.5 Single-Word Transfer Channels (SWT)
The DMAU provides a total of four SWT channels.
SWT0 and SWT1 are dedicated to SIU0, and SWT2
and SWT3 are dedica ted to SIU1. Eac h SWT c hannel
is bidirectional and can transfer data to/from either
TPRAM 0, TPRAM1, or external memory a s defined by
the associated channel’s source and destination
address registers (SADD〈0—3〉 and DADD〈0—3〉).
Two SW T channel s are dedicated to each SIU so tha t
data fro m a single SIU ca n be routed to separat e mem-
ory spaces at any time. Eac h SIU’s ICIX〈0—1〉 and
OCIX〈0—1〉 control registe rs define the mapping of
serial port data to one of the two SWT channels dedi-
cated to that SIU. For example, this provides a method
for routing logical channel data on a TDM bit stream
to/from either TPRAM on a time-slot bas is.
If a specific SIU issues a request for service (input
buff er full or output buffer empty), an SWT channel per-
forms a transaction. SWT channels provide both
source and destinat ion transfers. A source transac-
tion is defined as a read from DSP16411 memory and
write to an SIU output register with the update of the
appropriate DMAU registers. A destination transac-
tion is defined as the read of an SIU input register and
write to DSP16411 memory with the update of the
appropriate DMAU registers. For a specific SWT chan-
nel, the size and structure of the data to be transf erred
to/from the SIU must be the same. A s an alternative,
the source or destination transfer for a specific channel
can be disabled, allowing separate DMAU channels to
be used for the source and destination transfers. F or
example, SWT0 can be used to service SIU0 input and
SWT1 for SIU0 output .
The DMAU supports address and counter hardware for
one- and two- dimensional memory accesses for each
SWT channel. The basic data structure is called an
array, which consists of columns (or buffers) and rows
(or elements). An array can be traversed in either row-
major (two-dimensio nal array) or column-ma jor (one-
dimensional array) order, as defined by the DMAU con-
trol registers for that channel (CTL〈0—3〉—Table 34 on
page 74). Each SWT channel has two dedicated inter-
rupt signals; one to represent the status of a source
transfer and another to represent the status of a d esti-
nation transfer. These signals c an be used to create
interrupt sources to either core. (S ee S ec tion 4.13. 7,
beginning on page 92, for details.)
The SIGCO N [2:0] field (CTL〈0—3〉[3 :1]) regis ters
defin e the exact meaning associated with both the
source and dest ination transfer interrupts. See
Table 50 on page 92 for a list of DMAU interrupts and
Table 34 on page 74 for the CTL〈0—3〉 bit field defini-
tions.
The following steps are taken during a source
transaction:
1. O ne of the cores sets the appropriate SRUN[3:0]
field (DMCON0[3:0]—Table 31 on page 71) to ini-
tiate transfers.
2. I f the SIU 16-bit output data register (SODR) is
empty, the SIU requests data from the D MAU. T he
DMAU reads one data word over the Z- bus from the
appropriate DSP16411 memory location using the
SWT channel’s source address register,
SADD〈0—3〉.
3. T he DMAU transfers the data word to the corre-
spon ding SODR register over the peripheral data
bus, DDO.
4. The DMAU updat es the SWT channel’s source
addres s register, SADD〈0—3〉, and the source
coun ter register, SCNT〈0—3〉.
5. T he DMAU can generat e a core interrupt, based on
the value of the SIGCON [2:0] field (CTL〈0—3〉[3:1]).
6. I f this is not the last locati on of the source array
(SCNT〈0—3〉≠LIM〈0—3〉), the DMAU returns to
step 2. If this is the l ast location of the source array:
If the AUTOLOAD field (CTL〈0—3〉[0]—Table 34
on page 74) is cleared, the DMAU clears
SCNT〈0—3〉, clears the co rresponding
SRUN[3:0] field (DMCON0[3:0]—Table 31 on
page 71), and terminates the source transfer.
If the AUTOLOAD field is set:
—The DMAU reloads SADD〈0—3〉 with the value
in the source base address register,
SBAS〈0—3〉.
—The DMAU clears the value in the source
counter register (SCNT〈0—3〉 is written with 0).
—The DMAU initiates a new source transfer with-
out core intervention.
The steps taken for a destination transaction are:
1. One of the cores sets the appropriate DRUN[3:0]
field (DMCON0[7:4]) to initiate transfers.
2. If the SIU 16-bit input data register ( SIDR) is full, the
SIU requests that the DMAU read the data. After the
DMAU acknowledges the request, the SIU places
the conte nts of SIDR onto the data bus (DSI).
Advance Data Sheet
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.5 Single-Word Transfer Channels
(SWT) (continued)
3. The DMAU transfers this data word over the Z-bus to
the appropriate DSP16411 memory location as
defined by the channe l’s destinat ion address regis-
ter, DADD〈0—3〉.
4. The DMAU updates the channel’s destination
address register, DADD〈0—3〉, a nd the destination
counter, DCNT〈0—3〉.
5. The DMAU can generate a core interrupt, based on
the value of the SIGCON[2:0] field
(CTL〈0—3〉[3:1]—Table 34 on page 74).
6. If this is not the las t location of the destination array
(DCNT〈0—3〉≠LIM〈0—3〉), the DMAU returns t o
step 2. I f this is th e l ast location of the destination
array:
If the AUTOLOAD field (CTL〈0—3〉[0]—Table 34
on page 74) is cleared, the DMAU clears
DCNT〈0—3〉, clears the corresponding
DRUN[3:0] field (DMCON0[7:4]—Table 31 on
page 71), and terminates the destination transfer.
If the AUTOLOAD field is set:
—The DMAU reloads DADD〈0—3〉 with the value
in the destinati on base address register,
DBAS〈0—3〉.
— The DMAU clears the value in the destination
counter register (DCNT〈0—3〉 is written with 0).
— The DMAU initiates a new destinat ion transfer
without core intervention.
The DMAU’s control and address registers determine
the data structure and access pattern supported by a
particular channel and reflect the status of the transfer.
These SWT channel registers are described in
Table 48, with additional detail provided in
Sect ion 4.1 3.2, beginning on page 67.
Table 48. SWT-Specific Memory -Map ped Registers
Register Type Size Description
SADD〈0—3〉Source
Address 32- bit The program must initialize the SADD〈0—3〉 register with the starting address of the
sou rce arr ay † for the correspondi ng channel (read data). The DMAU updates the reg is-
ter wi th the address of the next memory location to be read by the corresponding SWT
channel as the transfer proceeds. Table 37 on page 77 desc ribes the bit fields of the
SADD〈0—3〉 registers.
SBAS〈0—3〉Source
Base
Address
20-bit The program must initialize the SBAS〈0—3〉 register with the starting address of the
source array† for the cor respondi ng channel (read data). If the corresponding AUTO-
LOAD fiel d ( CTL〈0—3〉[0]) is set, the DMAU copies the contents of SBAS〈0—3〉 to the
corresponding SADD〈0—3〉 regist er aft er the transfer of an enti re arr ay is complete.
The DMAU does not modify SBAS〈0—3〉.
SCNT〈0—3〉Source
Counter 20- bit This regis ter contains the row and col um n counter of the source array† for the corre-
spondi ng chann el ( read d ata). The DMAU u pdat es th e r egist er as t he tr ansfer p roceeds
and automati cally clears the register upon the completion of the tr ansfer. The source
row (SROW) is encoded in SCNT〈0—3〉[19:7], and the sourc e column (SCOL) is
encoded in SCNT〈0—3〉[6:0].
Note: SCNT〈0—3〉 are not cleared by a reset of the DMAU channel via the DMCON1
register (Table 32 on page 72). Before an SWT ch annel can be used, the pro-
gram must clear t he corresponding SCNT〈0—3〉 register after a DSP16411
device res et. Otherwise, the value of this register i s undefin ed.
DADD〈0—3〉Destination
Address 32- bit The program must initialize the DADD〈0—3〉 register with the starting addr ess of the
destination array† for the correspondin g channel (write data). The DMAU updates t he
regi ster wi th the a ddress of th e next mem ory loc ation t o be wri tten by the corr espondi ng
SWT channe l as the transfer proceeds. Table 37 on page 77 describes the bit fields of
the DADD〈0—3〉 registers.
DBAS〈0—3〉Destination
Base
Address
20-bit The program must initialize the DBAS〈0—3〉 register with the starting address of the
destination array† for the correspondin g channel (write data). If the cor respondi ng
AUTO LO AD fi eld (CTL〈0—3〉[0]) is set, the DMAU copies the contents of DBAS〈0—3〉
to the corresponding DADD〈0—3〉 register after the transfer of an entire array is com-
plete. The DMAU does not modify DBAS〈0—3〉.
† The array can be either one-dimensional or two-dimensional.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
Table 48. SWT-Specific Mem ory -Mapped Registers (continued)
4.13.5 Single-Word Transfer Channels (SWT) (continued)
DCNT〈0—3〉Destination
Counter 20-bi t This regi ster co nta ins the r ow and colu mn count er of t he desti nation array† fo r the cor re-
sponding channel (wri te data). The DMAU upd ates the regis ter as the transfer pro-
ceeds and automati cally cl ears the register upon the completion of the transfer. The
destination row (DROW) is encoded in DCNT〈0—3〉[ 19:7], and the destination column
(DCOL) is encoded in DCNT〈0—3〉[6:0].
Note: DCNT〈0—3〉 are not cleared by a reset of the DMAU channel via the DMCON1
register (Table 32 on page 72). Before an SWT ch annel can be used, the pro-
gram must clear t he corresponding DCNT〈0—3〉 register after a DSP16411
device res et. Otherwise, the value of this r egister i s undefined.
LIM〈0—3〉L imit 20-bit The user pro grams LIM〈0—3〉 with t he las t row cou nt a nd the l ast col umn cou nt for both
the so urc e and dest inati on arrays† f or th e corr espond ing chan nel . For a si ngle- buff ere d
array, LIM〈0—3〉[19:7] is programm ed wit h the number of rows in each single buff er
minu s one (
r
– 1). For a doubl e-buf fered two-di mensional arr ay, LIM〈0—3〉[ 19:7] is pro-
gramme d with two times the number of rows i n each single buff er minus one
((2 ×
r
) – 1). The number of columns minus one (
n
– 1) is encoded in LIM〈0—3〉[6:0].
Refer to Section 4.13.9 on page 95 for examples.
STR〈0—3〉Stride
Register 16-bit For an SWT channel with one-dimensi onal array accesses, the program must cle ar t he
correspond ing STR〈0—3〉 register.
For an SWT channel with two-dimensional array accesses, the user software assigns
the n umber of m emory l ocati ons between c ommon r ows (element s) of di ff erent colum ns
(buffers). Typical ly, this value equals the number of rows per c olumn, which places the
buffer s back-to -back ( contiguous) in memory. Refer to Section 4.13.9.1 on page 95 for
details.
RI〈0—3〉Re index 20-bit For an SW T channel with one- dimensional array accesses, the program m ust clear the
correspond ing RI〈0—3〉 register.
For an SWT channel with two-dimensional array accesses, the DMAU adds the sign-
magnitude value in the corresponding RI〈0—3〉 registe r to the corresponding add ress
register (SADD〈0—3〉 for sour ce tran sacti ons and DADD〈0—3〉 for desti nation transac-
tions) after the last c olumn has been accessed. The magnitude of the r eindex value f or
an array of
r
rows and
n
columns (
n
>1) is (
r
×(
n
– 1)) – 1. The magnitude of the
rein dex va lue for a t wo-d imensio nal arr ay that empl oys do uble buf fer s lik e that s hown in
Figur e 21 on pag e 84 is (2
r
×(
n
– 1)) – 1. Because the rei ndex val ue is al way s nega-
tive, set the sign bit (bit 19) of RI〈0—3〉.
CTL〈0—3〉Control 16-bit CTL〈0—3〉 controls the following it em s for the correspondin g SWT channel:
E nabling or di sabling of AUTOLOAD for t he starting address.
Deter mining the point in the transa ction when a DMAU interr upt reques t is generat ed.
Determin ing whether the a ccess ta kes plac e in row-major (two-dimensional arra y) or
column-major (one-dimensional array) order.
CTL〈0—3〉 det ermines t hese attributes for both the source and desti nation arrays for
the corresponding SWT channel. See Table 34 on page 74 for the f ield descriptions of
CTL〈0—3〉.
Register Type Size Description
† The array can be either one-dimensional or two-dimensional.
Advance Data Sheet
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.5 Single-Word Transfer Channels
(SWT) (continued)
The two 16-bit DMAU master control registers,
DMCON0 and DMCON1, also influence the operation
of the SWT channels. The 32-bit DMAU status register ,
DSTAT, reflects the status of any SWT transfer . The bit
field definition of the DMAU control and status registers
is given in S ec tion 4.13.2, begi nning on page 67.
4.13.6 Mem ory-to-Memory Tran sfer Chan nels
(MMT)
The DSP16411 DMAU provides two MMT channels for
block transfers called MMT4 and M MT5. E ac h M MT
channel moves data between a sou rce bloc k and a
destination bloc k. Bo th the source and destination
blocks must be one-dimensional arrays with the same
size and structure, as defined by the MMT channel’s
control register, CTL〈4—5〉 (see Table 36 on
page 76). The user software initiates an MMT block
transfer request by writing a one to the corresponding
TRIGGER5 or TRIGGER4 field (DMCON0[1 1,10]—see
Table 31 on page 71). Each transfer can be 16 bits or
32 bits, as determined by the corresponding XSIZE5 or
XSIZE4 field (DMCON0[13,12]). If the tra nsfers are
32 bits, the source and destination addresses as speci-
fied by SADD〈4—5〉 and DADD〈4—5〉 must both be
even.
Once initiated, MMT channel block transfers proceed to
completion and then stop. The DMAU pauses an MMT
block transfer to allow an SWT or bypass chann el
transaction to complete, and then automatically
resumes the MMT block transf er. This prevents I/O
latencies and possible data ov erwrites due to long
MMT blocks. Ea ch MMT cha nnel has a dedicated
interrupt request that can be enabled in either core.
The SIGCON[2:0] field (CTL〈4—5〉[3:1]) determines
the exact meaning associated with the interrupt. See
Table 50 on page 92 and Table 34 on page 74 for more
information.
To optimize throughput, MMT ch annel read operation s
can be pipelined. This allows the DMAU to initiate mul-
tiple fetches from the source block before an associ-
ated write to the destination block is performed. The
DMAU stores the data f rom the multiple fetches into an
internal source look-ahead buffer. The user enables
multiple fetches into the source look-ahead buffer for
an MM T channel by setting the correspond ing SLKA5
or SLKA4 field (DMCON0[9,8]).
Assuming that source look-ahead is disabled, the
DMAU performs the follo wing steps during an MMT
block transfer:
1. The user software executing in one of the cores
writes a one to the corresponding TRIGGE R5 or
T R IGG ER 4 fie ld ( DMCON0[11,1 0 ]) to i n itiate th e
block transfer. T he DMAU aut om atically clears the
TRIGGER5 or TRIGGER4 field.
2. The DMAU initiates a read operation from the source
block using the address in the channel’ s source
addres s register, SADD〈4—5〉 (see Table 37 on
page 77). If the corresponding XSIZE5 or XSIZE4
field (DMCON0[13,12]) is cleared, the read opera-
tion is 16 bits. If the correspondin g XSIZE5 or
XSIZE 4 field is set, the read operation is 32 bits.
3. I f the read operation is 16 bits, the DMAU incre-
ment s SADD〈4—5〉 by one. If the read operation is
32 bits, the DMAU increments SADD〈4—5〉 by two.
The DMAU updat es the source counte r register
(SCNT〈4—5〉—Table 39 on page 78) by increment-
ing its SROW[ 12:0] field by one.
4. When the read data from step 2 becomes available,
the DMAU pla ces it into the source look-ahead
buffer.
5. The DMAU writes the data in the source look-ahead
buffer to the destination block using the address in
the channel ’s destination address register,
DADD〈4—5〉. If the correspondi ng XSIZE5 or
XSIZE4 field (DMCON0[13,12]) is cleared, the write
operati on is 16 bits. If the corresponding XSIZE5 or
XSIZE4 field is set, the write operation is 32 bits.
6. I f the write operation is 16 bits, the DMAU incre-
ment s DADD〈4—5〉 by one. If the write operation is
32 bi ts, the DMAU increment s DADD〈4—5〉 by
two. The DMAU upda tes the destination counter
register (DCNT〈4—5〉) by incrementing its
DROW[ 12:0] field by one.
7. Depending on the SIGCON[2:0] field
(CTL〈4—5〉[3: 1]), the DMAU can generate an inter-
rupt.
8. I f this is the last location of the block
(DCNT〈4—5〉=LIM〈4—5〉) , t he D M A U s t ops pro-
cessing for the channel. If this is not the l ast location
of the block, the DMAU returns to step 2.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.6 Memory-to-Memory Transfer Channels (MMT) (continued)
If sou rce look-ahe ad is enabled, the DMAU performs the same steps as above except that it initia lly repeats steps
2—4 multiple times in a pipelined manner. It then performs reads and writes to the source and destination blocks
as access cycles becom e available. It is strongly recommended that the user enable source look-ahead. See
Section 4.14.7.4 on page 133 for a performance comp arison.
The DMAU’s control and address registers determine the data size and location supported by a particular channel
and reflect the status of the request. These MMT channel registers are described in Table 49 on page 91 with
additional detail provided in Section 4.13.2, beginning on page 67.
Table 49. MMT-Specific Memory-Ma pped Registers
The two 16-bit DMAU master control registers, DMCON0 and DMCON1, influence the operation of the MMT chan-
nels. The 32-bit DMAU status register, DSTAT, reflects the status of any MMT transfer. The bit field definition of
the DMAU control and status registers is given in Section 4.13.2, beginning on page 67.
Register Type Size Descript ion
SADD〈4—5〉Source
Address 32-bit Prior to each MMT block move, the program must initialize the corresponding
SADD〈4—5〉 regi ster with t he starting address in mem ory for the sour ce block (read
data). The DMAU updates the register with the address of the next memory location to
be read by the specifi ed M MT channel as the block move proc eeds. Table 37 on
page 77 describes the bit fields of SADD〈4—5〉.
SCNT〈4—5〉Source
Counter 20-bit This register contains the sourc e row and col um n counter for the corresponding
channel . The DMAU updates the register as the block move proceeds and aut omatically
clears the register upon the completion of the block move. The source row (SROW) is
encoded in SCNT〈4—5〉[19: 7], and the source colum n (SCOL) is encoded in
SCNT〈4—5〉[6:0].
Note: SCNT〈4—5〉 ar e not cleared by a reset of the DMAU channel via the DMCON1
re g ister (Table 32 on page 72). Before an MMT channel can be used, the pro-
gram must clear the corresponding SCNT〈4—5〉 register after a DSP1641 1
device reset. Otherwise, the value of this reg ister is undefined.
DADD〈4—5〉Destination
Address 32-bit Prior to each MMT block move, the program must initialize the corresponding
DADD〈4—5〉 r egist er wit h the st arti ng addres s i n memory for the dest i nation b lock ( write
data). The DMAU updates the register with the address of the next memory location to
be writ ten by the specified MMT chan nel as the block move proceeds. Table 37 on
page 77 describes the bit fields of DADD〈4—5〉.
DCNT〈4—5〉Destination
Counter 20-bit This register contains the destination row and col um n counter for the corr espondin g
channel . The DMAU updates the register as the block move proceeds and aut omatically
clears the register up on the co mp letion of the block mo ve. The de stination row (DROW )
is encoded in DCNT〈4—5〉[19:7] and the destination column (DCOL) is encoded in
DCNT〈4—5〉[6:0].
Note: DCNT〈4—5〉 are not clear ed by a reset of the DMAU channel via the DMCON1
re g ister (Table 32 on page 72). Before an MMT channel can be used, the user
program must clear the corresponding DCNT〈4—5〉 register aft er a DSP16411
device reset. Otherwise, the value of this reg ister is und efined .
LIM〈4—5〉Limit 20-bit The user pr ograms LIM〈4—5〉 with the last r ow count and the last colum n count for both
the source and destination blocks for the correspon ding channe l. The last row count is
the number of rows minus one and i s encode d i n the LASTROW fiel d (LIM〈4—5〉[19:7]).
The last co lumn count is the number of columns minus o ne and is e ncoded in the LAST-
COL field (LIM〈4—5〉[6:0]). Typically , LASTCOL is zero for a block move.
CTL〈4—5〉Control 16-bit CTL〈4—5〉 controls interrupt generation for both the source and destinat ion block
moves.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.7 Interrupts and Priority Resolution
The DMAU provides information to both cores of the DSP16411 in the form of status and interrupts. A core can
determine status by reading the DMAU’s memory-mapped DSTAT register, which reflects the current state of any
DMAU channe l. T he field definitions for DSTAT are defined in Table 30 on page 69.
A core can con figure the DMAU interrupts by programming the correspondi ng SIGCO N[2:0] field
(CTL〈0—3〉[3:1]—Table 34 on page 74 and CTL〈4—5〉[3:1]—Table 36 on page 76). Several DMAU interrupt sig-
nals are multi plexed to each core, so not all DMAU interrupt requests can be monitored by a core simultaneously.
Refer to Section 4.4.2, beginning on page 28, regarding the interrupt multiplexer, IMUX. Table 50 provides a list of
the DMAU interrupt signals and their descriptions.
Table 50. D MAU Interru pts
DMAU Channel Description†
† The SI GCON[ 2:0] field of the channel’s CTL〈0—5〉 register dete rm i nes the cond i tion under w hi ch the DM AU a ss erts the int errupt . Se e Table 3 4 on
page 74 for a description of CTL〈0—3〉, or Table 36 on page 76 for a desc ri ption of CTL〈4—5〉).
DSP Core Int errupt Name
SWT0 SIU0 source ( output) transac ti on com plete DSINT0
SIU0 destination (input) tr ansaction complet e DDINT0
SWT1 SIU0 source ( output) transac ti on com plete DSINT1
SIU0 destination (input) tr ansaction complet e DDINT1
SWT2 SIU1 source ( output) transac ti on com plete DSINT2
SIU1 destination (input) tr ansaction complet e DDINT2
SWT3 SIU1 source ( output) transac ti on com plete DSINT3
SIU1 destination (input) tr ansaction complet e DDINT3
MMT4 Memory-to- memory transfer complete DMINT4
MMT5 Memory-to-memory transfer complete DMINT5
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.7 Interrupts and Priority Resolution (continued)
The DMAU provides arbitration for requests f rom many
sources. I f multiple requests are pending simul ta-
neously, the DMAU completes its current tran saction1
and then provides access to the source that has the
highest priority. The order of priority, from highest to
lowe st, is as follows:
1. S WT0 source transact ion (SIU0 output) (highest)
2. S WT0 dest ination tra nsactio n (SIU0 input)
3. S WT1 sourc e transact ion (SIU0 output)
4. S WT1 dest ination tra nsactio n (SIU0 input)
5. S WT2 sourc e transact ion (SIU1 output)
6. S WT2 dest ination tra nsactio n (SIU1 input)
7. S WT3 sourc e transact ion (SIU1 output)
8. S WT3 dest ination tra nsactio n (SIU1 input)
9. PIU
10. MMT4 destination write
11. MMT5 destination write
12. MMT4 source fetch
13. MMT5 source fetch (lowest)
MMT chann el block transfers that are in progress are
paused if any SWT or PIU bypass channel request
occurs. The single SWT or bypass channel transaction
completes , and then the paused MMT channel block
transfer resumes.
MMT channel priority can be changed by the user
softw are. T he default priority of the MMT channel s is
listed above. I f both MMT4 and M MT5 require service
at the same time, an MMT4 request has higher priority
than the correspon ding M MT5 request. The default
operation does not allow a new MMT req uest to inter-
rupt an MMT block transfer already in progress, i.e., the
DMAU ’s default con dition is to start and complete an
MM T block transfer before a new MMT block transfer
can begin. Any MM T block transfer can be interrupted
by any SW T or PIU bypass channel transacti on.
The def ault operation of the MMT channels can be
chan ged. T he HP RIM field (DMCON0[15]—Table 31
on page 71 ) is used to select the relative priority of
MM T4 and MMT 5. I f HPRIM is cleared (the default),
MMT4 has higher priority than MMT5. If HPRIM is set,
MMT5 has the higher priority.
A higher-priority MMT chann el can be made to in ter-
rupt a lower-priority MM T channel block transfer
already in progress. The MINT fi eld (DMCON0[14])
controls this feature. If MINT is cleared, M MT channels
do not interrupt each other, as stated above, and an
MMT block transfer already in pr ogress completes
before another MMT channel request is taken. If MINT
is set, the higher-priority MM T channel can interrupt
the lower-priority channel as det ermined by the HPRIM
field setting. In a typical application, the higher-priority
chan nel is assigned to moving small, time-critical data
block s, and the lower-priority channel is assigned to
large, less time-critical blocks. This feature alleviates
latenc y that can be incurred due to the t ransfer of large
data blocks.
1. A request to th e DMAU can resul t in mo re than one transact ion, a tr ansaction being the tr ansfer of one si ngle (16- bit) or double (32-bit) word.
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.8 Error Reporting and Recovery
Each of the ERR[5:0] fields of th e DSTAT re g i ster
(Table 30 on page 69) reflects a DMAU protocol failure
that indicates a loss of d ata for the co rrespo nding
channel. For the SWT〈0—3〉 channels, the DMAU s ets
the corresponding ERR[3:0] field if:
An SIU〈0—1〉 requests DMAU service for a cha nnel
before the DMAU has accepted the previous request
from that SIU〈0—1〉 for that chan nel.
An SIU〈0—1〉 requests DMAU service for a channel,
and that channel’s RESET[3:0] field
(DMCON1[3:0]—Table 32 on page 72) is set.
An SIU〈0—1〉 requests DMAU destination/s ource
service for a ch annel, and that channel ’s
DRUN[3:0]/SRUN[3:0] field
(DMCON0[7:0]—Table 31 on page 71) is cleared.
An SIU〈0—1〉 requests DMAU service for a channel,
and that channel’s source/destination transfer is
complete (SCNT〈0—3〉/DCNT〈0—3〉=LIM〈0—3〉),
and that channel’s AUTOLOAD field
(CTL〈0—3〉[0]—Table 34 on page 74) is cleared.
For the MMT〈4—5〉 channels, the DMAU sets the cor-
respon ding ERR[5:4] field if:
The user software attempts to set the TRIGGER[5:4]
field by writing 1 to DMCON0[11 :10] and the
TRIGGER[5:4] field is already set.
The user software attempts to set the TRIGGER[5:4]
field by writing 1 to DMCON0[11 :10] and the
RESET[5:4] field (DMCON1[5:4]) is set.
If servicing a DMAU channel interrupt, the user soft-
ware should poll DSTAT to determine whether an error
has occurred. If so, the user software must perform the
following steps:
1. Set the corresponding RESET[5:0] field
(DMCON1[5:0]) to terminate all channel activity.
2. Write a 1 to the co rresponding ERR[5 :0] field to
clear the field and the error condition.
3. Reinitialize the corresponding channel address and
coun t registers.
4. Clear the corresponding RESET[5:0] field to reallow
chan nel activity.
5. For an MMT channel, re-enable a channel transfer
by setting the appropriate TRIGG ER [5:4] field
(DMCON0[11:10]).
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.9 Programming Examples
Thi s se c ti on illus t r ates thr ee typ ic al D MAU ap plic a t ion s .
4.13.9.1 SWT Example 1: A Two-Dimensional Array
This example descr ibes the input and output of four channels of full-duplex TDM speech dat a from SIU0 with the
following assumptions:
The data is double-buffe red to avoid latencies and the potential of missing samples.
Input and outp ut data have the same array size and structure and are processed by the SWT0 channel .
There are four
logical channels (time slots) grouped in four conti guous double buffers, corresponding to the num-
ber of columns (
n
) in a two-dimensional array.
Each single buffer has 160 elements, or rows (
r
), and each double buffer has a length of 320 (0x140).
CORE 0 begins processing data after 160 samples have been input for all four logical channels.
SIU0 input (destination) data begins at address 0x01000 in TPRAM0.
SIU0 output (source) data begins at address 0x02000 in TPRAM0.
The auto load feature is used to minimize core intervention.
Figure 23 illust rates this data structure. T his exampl e does not discuss the setup and control of SIU0.
A Two-Dimensional Data Structure for Double-Buffering
n
Channels
Figure 23. Example of a T wo-Dimensional Double-Buffered Data Structure
STR0
(SBAS0)
SOURCE DESTINATION
OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY
SOURCE DESTINATION
BUFFER
COMPLETE
ARRAY
COMPLETE
BUFFER COMPLETE
(SIGCON=0x3)
ARRAY COMPLETE
(SIGCON=0x5)
0x02000
0x02140
0x02280
0x023C0
ROW=0
ROW=1
ROW=319
ROW=159
COL=0
SINGLE
BUFFER
DOUBLE
BUFFER
ROW=0
ROW=1
ROW=319
ROW=159
ROW=0
ROW=1
ROW=319
ROW=159
ROW=0
ROW=1
ROW=319
ROW=159
COL=1COL=2COL=3
(DBAS0)
0x01000
0x01140
0x01280
0x013C0
ROW=0
ROW=1
ROW=319
ROW=159
COL=0
SINGLE
BUFFER
DOUBLE
BUFFER
ROW=0
ROW=1
ROW=319
ROW=159
ROW=0
ROW=1
ROW=319
ROW=159
ROW=0
ROW=1
ROW=319
ROW=159
COL=1COL=2COL=3
RI0 = –959 (0x803BF)
AUTOLOAD
RI0 = –959 (0x803BF)
AUTOLOAD
(0x140)
STR0
(0x140)
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4 Hardware Architecture (continued)
4 .13 Direct Memory Access Unit
(DMAU) (continued)
4.13.9 Programming Examples (continued)
4.13.9.1 SWT Exam pl e 1: A Two- Dimensi onal
Array (continued)
The user software running in CORE0 must perform the
following steps to properly initialize SWT0:
1. The user software sets the source address
(SADD0—Table 37 on page 77) and the source
base address (SBAS0—Table 44 on page 81) to the
top of the output (source) array located in
TPRAM 0. T he user software writes 0x00002000 to
SADD0 and 0x02000 to SBAS0.
2. The user software sets the destination address
(DADD0—Table 37 on page 77) and the desti nation
base address (DBAS0—Table 45 on page 81) to the
top of the inp ut (destination) array located in
TPRAM 0. T he user software writes 0x00001000 to
DADD0 and 0x01000 to DBAS0.
3. The user software clears the source and destination
counter registers SCNT0 and DCNT0 (Table 38 on
page 78 and Table 40 on page 79).
4. The user software initializes the limit register
(LIM0—Table 42 on page 80) with the dimensions of
the array. The number of rows (or elements) is 2
r
(320), so the user software writes 319 (2
r
–1) into
the LASTROW[12:0] field (LIM0[19:7]). The number
of columns is 4, so t he user software writes 3 (
n
–1)
into the LAS TCO L[6:0] field (LIM0[6:0]). The user
software write s 0x09F83 into LIM0.
5. The user software initializes the stride register
(STR0—Table 46 on page 82) with the distance
between corresponding rows of consecutive col-
umns. B ecaus e the buffers are contiguous in this
example, the stride is the same as the buffer length
and the user software writes 0x014 0 into STR0.
6. The user software initializes the reindex regist er
(RI0—Table 47 on page 82) with the sign-magnitude
postmodific ation value to be applied to SADD0 and
DADD0 after each time th at the last column has
been accessed. The magnitude of the reindex value
is ((2r ×(n–1))–1) or (320×3) – 1 = 959 = 0x3BF.
The sign must be negative, so th e user software
writes 0x803BF into RI0.
7. The user software writes the con trol registers to
enable SWT0 and begin I/O processing. First, the
user software writes one into the POSTMOD[1:0]
field (CTL0[5:4]—Table 34 on page 74) to enable
two-dimens io nal array accesses, writes 0x3 to the
SIGCON[2:0] field (CTL0[3:1]), and writes 1 to the
AUTOLOAD fi e ld (CTL0[0]) so that no further core
interaction is needed . Th e user software writes
0x0017 to CTL0.
8. F inally, the user software sets both the SRUN0 a nd
DRUN0 fields (DMCON0[0] and DMCON0[4]—
Table 31 on page 71) to enable SWT0 source and
destina tion transfers. The user so ftware writes
0x0011 to DMCON0.
The DMAU begins processing the SWT0 input and out-
put channel s. For the outpu t channel, the DMAU per-
forms the following steps:
1. I t reads the single word at the TPRAM0 locat ion
point ed to by SADD0 (0x0000 2000) and transfers
the data to SIU0. This data is the first output sample
for the first logical channel (ROW = 0 and COL = 0).
2. I t increment s SADD0 by the contents of STR0, so
SADD0 contains 0x000021 40 and points to the first
output sa mple for the second logical channel
(ROW = 0 and COL = 1). It updates SCNT0 by
incre men ting the column counte r, so SCNT0 con-
tains 0x00001.
3. I t reads the da ta at 0x02140 and transfers it to SIU0.
4. I t increment s SADD0 by the content s of STR0, so
SADD0 contains 0x000022 80 and points to the first
output sample for t he third logical channel (ROW = 0
and COL = 2). It updates SCNT0 by incrementing
the colum n counte r, so SCNT0 contains 0x 00002.
5. As in steps 3 and 4, the DMAU continues to read
data, transfer the data to SIU0, and update SADD0
and SCNT0 until the column counter equals the last
column (SCNT0[6:0] = LIM0[6:0] = 3). SADD0 con-
tains 0x00002 3C0 and points to the first row of the
last column.
6. The DMAU subt racts the magnitude of the contents
of RI0 from SADD0 (0x000023C0 – 0x3B F) and
places the result into SADD0 (0x00002001).
SADD0 points to the second output s ample for the
first logical channel (ROW = 1 and COL = 0).
The DMAU co ntinues processing in this manner unt il it
processes row 159 of column 3. At this point,
ROW = LASTROW/2 and COL = LASTCOL. Because
this condition is met and SIGCO N[2 :0] = 0x3, the
DMAU asserts the DSINT0 interrupt to CORE0.
CORE0’s ISR changes SIGCON[2:0] to 0x5 so that the
DMAU asserts DSINT0 again after it has processed the
remaining samples in the buff ers. CORE0 can over-
write t he already-processed samples while the DMAU
con tin ues t o process the r emaining samp les.
The steps performed by the DMAU for the input chan-
nel are similar to those for the output channel.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.9 Programming Examples (continued)
4.13.9.2 SWT Examp le 2: A One-Dimensional Array
This example describes the input of four blocks of speech data from SIU1 with the following assumptions:
The data is single-buffered.
Data is processed by the SWT3 channel.
There are four
blocks of data gr ouped in four contiguous buffers, corresponding to the number of columns (
n
) in
a one-dime nsional array.
Each single buffer has 160 elements, or rows (
r
=0xA0).
The DMAU fills four buffers in sequenti al order, i.e., it receives all 160 samples of one buff er and th en all
160 sam ple s of the next buffer, etc.
The DMAU places the data in ascending linear order in mem ory, beginning at TPRAM1 addres s 0x01000.
CORE 1 begins processing data after 160 samples have been input.
The auto load feature is used to minimize core intervention.
Figure 24 illustrates the data structure for this example.
A One-D imensional Data St ructure for Buffer ing
n
Input Channels
Figure 24. Example of One-Dimensional Data Structure
DESTINATION
BUFFER COMPLETE
0x01000
0x010A0
0x01140
0x011E0
(DBAS3)
AUTOLOAD
ROW=0
ROW=1
ROW=159
COL=0COL=1COL=2COL=3
DESTINATION
BUFFER COMPLETE
DESTINATION
BUFFER COMPLETE
DESTINATION
BUFFER COMPLETE
ROW=0
ROW=1
ROW=159
ROW=0
ROW=1
ROW=159
ROW=0
ROW=1
ROW=159
INPUT DESTINATION ARRAY
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.9 Programming Examples (continued)
4.13.9.2 SWT Exam pl e 2: A One- Dim ensional
Array (continued)
The user software running in CORE1 must perform the
following steps to properly initialize SWT3:
1. The user software sets the destination address
(DADD3—Table 37 on page 77) and the desti nation
base address (DBAS3—Table 45 on page 81) to the
top of the inp ut (destination) array located in
TPRAM 1. T he user software writes 0x00101000 to
DADD3 and 0x01000 to DBAS3.
2. The user software clears the destination counter
(DCNT3—Table 40 on page 79 ).
3. The user software initializes the limit register
(LIM3—Table 42 on page 80) with the dimensions of
the array. The number of rows (or elements) is 160,
so the user software writes 159 (
r
– 1) into the LAS-
TROW[ 12:0 ] field (LIM3[19: 7]). The numbe r of col-
umns is 4, so the user software writes 3 (
n
–1) into
the LASTCOL[6:0] fi eld (LIM3[6: 0]). The user soft-
ware writes 0x04F83 to LIM3.
4. The user software writes the con trol registers to
enable SWT3 and begin I/O processing. First, the
user software writes two into the POSTMO D[1:0]
field (CTL3[5:4]—Table 34 on page 74) to enable
one-dimensi onal array accesses, writes 0x4 to the
S IGC O N [2:0] field ( CTL3[3:1]), and writes 1 to the
AUTOLOAD field (CTL3[0]) so that no further core
interaction is needed. The user software writes
0x0029 to CTL3.
5. Finally, the user software sets the DRUN3 fi eld
(DMCON0[7]—Table 31 on page 71 ) to enable
SWT3 destinat ion transfers. T he us er software
writes 0x0080 to DMCON0.
The DMAU begins processing the SWT3 input channel
and performs the following steps:
1. I t receives data from SIU1 and writes it to the single-
word TPRAM 1 location pointed to by DADD3
(0x00101000). This data i s the first input sample for
the first buffer (ROW = 0 and COL = 0).
2. I t increment s DADD3 by one, so DADD3 contains
0x00101001 and points to the second input sample
for the first buffer (ROW = 1 and COL = 0). It
update s SCNT3 by incrementing the row counter , so
SCNT3 contains 0x00080.
3. I t receives data from SIU1 and writes it to the single-
word TPRAM 1 location pointed to by DADD3
(0x00101001).
The DMAU co ntinues processing in this manner unt il it
fills row 159 of column 0. A t this point, ROW = L AS-
TROW and COL = 0. Because this condition is met
and SIGCON[2:0] = 0x4, the DMAU asserts the
DDINT3 interrupt to CORE1. CORE 1 can begin pro-
cessing the first buffer while the DMAU continues to fill
the second buffer.
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4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.9 Programming Examples (continued)
4.13.9.3 MMT Example
This example illustrates the use of MMT4 to move a source block of 100 rows or elements (
r
= 100) in TPRAM0 to
a desti nation block in TPRAM1, as Figure 25 illustrates. For this example, the source address in TPRAM0 is
0x01000 and the destination address in TPRAM1 is 0x02000.
Me m o ry - t o -M e m or y B lo c k Tr an s f er
Figure 25. Memory-to-Memory Block Transfer
The user software running in one of the cores must perform the following steps to properly initial ize MMT4:
1. The user software writes the sour ce address (SADD4—Table 37 on page 77) with the top of the output (source)
block located in TP RAM0. The user software writes 0x00001 000 to SADD4.
2. The user software writes the des tination address (DADD4—Table 37 on page 77 ) with the top of the in put (des-
tination) block located in TPRAM1. The user software writes 0x00102000 to DADD4.
3. The user softwar e clears the source and destination c ounter registers SCNT4 and DCNT4 (Table 39 on page 78
and Table 41 on page 79).
4. The user s oftware initializes the limit regi ster (LIM4—Table 43 on page 80) with the dimensions of the array. The
number of rows (or element s) is 100, so the use r software writes 99 (
r
– 1) into the LASTROW [1 2:0] field
(LIM4[19:7] = 0x63). The num ber of columns is one, so the user software writes zero into the LASTCOL[ 6:0]
field (LIM4[6:0]). The user so ftware writes 0x03180 to LIM4.
5. The user software writes the con trol registers to enable MMT 4 and begin block processing. First, the user soft-
ware writes two into the POSTM OD[1:0] field (CTL4[5:4]—Table 36 on page 76) to enable pointer and counter
update operations, and writes 0x1 to the SIGC ON[2: 0] field (CTL4[3:1]). The user software writes 0x0022 to
CTL4.
6. Fin ally, the user software sets the SLKA4 field (DMCON0[8]—Table 31 on page 71) to enable source look-
ahead, sets the XSIZE4 field (DMCON0[12] ) to transfer 32-bit words, and sets the TRIGGER4 field
(DMCON0[10]) to initiate MM T4 block transfers. Th e user software writes 0x1500 to DMCON0.
The DMAU begins proces sing the MMT4 channel. For each read operation from TPRAM0 starting at address
0x01000, the DMAU increments SADD4 by two and increments the SROW[12:0] field of SCNT4 by one. The
DMAU performs multiple fetches from TPRAM0 and places the data into th e source look-ahead buffer. F or each
write operation to TPRAM1 starting at address 0x02000, the DMAU increments DADD4 by two and increments t he
SROW[ 12:0] field of DCNT4 by one. B ecaus e SIG CON[ 2:0] = 0x1, the DMAU interrupts the cores when the trans-
fer is half complete (DROW [12:0] = LA STRO W/ 2 = LASTROW[ 12:0]>>1 = 0x31 or DCNT4 = 0 x1880). T he ISR
then changes SIGCON[2:0] to 0x4 to cause the DMAU to interrupt the cores again when the transfer is complete
(DROW[12:0] = LASTROW[12:0] or DCNT4 =LIM4 = 0x3180).
DESTINATION ARRAYSOURCE ARRAY TRANSFER 0x01020000x0001000(SADD4) (DADD4)
ROW=0
ROW=1
ROW=99
ROW=49
COL=0
TRANSFER
1/2 COMPLETE
ROW=0
ROW=1
ROW=99
ROW=49
0x0001002 0x0102002
COL=0
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI)
The system and external memory interface (SEMI) is
the DSP16411 interface to external memory and mem-
ory-mapped off-chip peripherals:
The SEM I supports a maximum tota l external mem-
ory size of 18 Mwords (16-bit words) through a com-
binat ion of an address bus, an address bus
extension, and decoded enables.
The SEM I can configure the external data bus as
eithe r 16 bits or 32 bits.
The SEM I can support a mix of asynchronous mem-
ory and synch ronous, pipelined
ZBT
(zero bus tu rn-
around) SRAMs .
The SEM I provides support for bus arbitration log ic
for shared-memory systems.
The SEMI provides programmable enable assertion,
setup, and hold times for external asynchronous
memory.
These features are controlled via a combination of
SEM I pins and control registers. Som e addit ion al fea-
tures of the SEMI are the following:
The SEMI arbitrates and prioritizes a ccesses from
both cores and from the DMAU.
The SEMI allows the cores to boot from internal or
external memory controlled by the state of an input
pin.
The SEMI controls the internal system bus, which
allows the cores, the DMAU, and the PIU to access
the shared internal I/O memory component. This
component includes the SLM and the internal mem-
ory-mapped registers within the DMAU, SIU0, SIU1,
PI U, and SEMI.
Figure 26 depicts the internal and external interfaces to
the SEMI . Th e SEM I interfaces directly to the X-mem-
ory space buses and Y-memory space buses for both
cores and to the DMAU’s external Z-memory space
buses. T h is a l lo w s:
Either core to perform external program or data
accesses.
Either core or the DMAU to access the SLM or inter-
nal memory-mapped registers.
SEMI Interface Block Diagram
Figure 26. SEMI Interface Block Diagram
YDB
YAB
XDB
XAB XAB0
XDB0
YAB0
32
20
32
CORE0
ZEAB
ZEDBZEDB
ZEAB
DMAU
SDB
SAB
ED[31:0]
EA[18:0]
ERAMN
EROMN
EION
ERWN[1:0]
ECKO
EREQN
EACKN
ERDY
EXM
ERTYPE
ESIZE
SEMI
CORE1
20
YDB0
ZSEG ZSEG
4
ESEG[3:0]
20
32
YDB
YAB
XDB
XAB XAB1
XDB1
YAB1
YDB1
32
20
32
20
SDB
SAB
ADDRESS
AND
DATA
CONFIGURATION
ENABLES
AND
STROBES
BUS
ARBITRATION
CLOCK
DSP16411 EXT ERNAL SIGNALS
SYSTEM BUS
(TO SL M, PI U,
SIU0, AND SIU1)
EYMODE
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.1 External Interface
Table 51 provides an ov erview of the SEMI pins. These pins are described in detail in the remainder of this section.
Table 51. Overv iew of SEMI Pins
Function Pin Type Description
Confi guration ESI ZE I Size of external SEMI data bus:
ESIZE = 0 selects 16-bit data bus.
ESIZE = 1 selects 32-bit data bus.
ERTYPE I EROM type:
ERTYPE = 0 selects asynchronous memory for the EROM component.
ERTYPE = 1 selects synchronous pipelined
ZBT
SRAM for the EROM component.
EXM I Boot source:
EXM = 0 selects IROM.
EXM = 1 selects EROM.
Bus Arbit ration
for Asynchronous
Memory
EREQN I Exter nal request for SEMI bus (negative assertion).
EACKN O SEMI acknowledge f or ext ernal request (negative assertion).
ERDY I External device ready for asynchronous access.
Enables
and Strobes ERAMN O/Z ERAM c om ponent enable (negative asserti on).
EROMN O/Z EROM com ponent enabl e (negative assertion).
EION O/Z EIO component enable (negative assertion).
ERWN[1:0] O/Z External read/write not:
If ESIZE = 0 (16-bit external bus):
ERWN1: Inactive (l ogic high).
ERWN0: Write enable (negative assertion).
If ESIZE = 1 (32-bit external bus):
ERWN1: Odd word (least significant 16 bits) write enable (negative assertion).
ERWN0: Even word (most significant 16 bits) write enable (nega ti ve assert ion).
External Cloc k ECKO O Exter nal clock. Can be program med as CKI, CLK, CLK/2, CLK/3, or CLK/4.
Address
and Data ED[31:0]†
† These address and data bus pins contain internal bus hold circuits. If BHEDIS (ECON1[12]—Table 61 on page 112) = 0, t hese b us hol d c i r c ui ts are acti -
vated. If BHEDIS = 0 and neither the SEMI nor an external device is driving these pins, the bus hold circuits hold them at their previous valid logic level.
Thi s el imina t es t h e need for extern al pul l - up or pul l - down re si stors on these pins. Se e S ecti on 10.1 on page 26 8 for details.
I/O/Z Bidirec ti onal 32- bit extern al dat a bus.
EA[18:1]†O/Z External address bus bits 18—1.
EA0†O/Z If ESIZE = 0:
External address bus bit 0.
If ESIZ E = 1 and the exte rnal compone nt is synchronous‡:
Write strobe (negative assertion ).
‡ The EROM component is synchronous if the ERTYPE pin is logic 1. The ERAM component is synchronous if the YTYPE field (ECON1[9]) is set and
the EIO compon ent i s syn ch r ono us if the ITYPE fi e ld (ECON1[10]) is set. ECON1 is descri bed in Table 61 on page 112.
ESEG[3:0]†O/Z External segment address.
EYMODE I This pin determines the mode of the external data bus. It must be static and t ied to
VSS (if the SEMI is used) or VDD2 (if t he SEMI is not used) . If EYMOD E = 0, the exter-
nal data bus ED[31:0] operates normally as described above. If EYMODE = 1,
ED[31:0] are statically configured as outputs (regardless of the state of RSTN) and
must not be connect ed externally. See Secti on 10.1 on page 268 for det ails.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.1 External Interface (continued)
4.14 .1.1 Conf igur a t ion
The SEMI config uration pins a re inputs that are individually tied high or low based on system requirements. The
ESIZE and ERTYPE pins reflect the configuration of the external memory system. The EXM pin sp ecifies the
memory boot area for the DSP16000 cores. Table 52 details the SEMI configuration pins.
Table 52. C onfigu ration Pin s for the SEMI Extern al Interface
FPin Value Description
ESIZE
(input) 0 Configures external data bus as 16 bits:
ED[31:16] is act ive and ED[15:0] is 3-st ate.
EA[18:0] provides the address.
For a single-word (16-bit) access, the SEMI pla ces the addr ess onto EA[18:0]:
— For a read, the SEMI transfer s the wor d from ED[31:16].
— For a write, the SEMI dri ves the word onto ED[31:16] and ass erts ER WN0.
For a double-word (32-bit) access, the SEMI performs two single-word (16-bit) accesses:
— First , t he SEM I accesses the most signif icant half of the dou ble word at the original address (see single-
word (16-b it) access described above).
— Second, the SEMI increments the address and accesses the l east significant half of the double word
(see single-word (16-bit) access described above).
1 Configures external data bus as 32 bits:
EA[18:1] provides the even addres s.
For a single-word (16-bit) access to an even location:
— For a read, the SEMI transfer s the wor d from ED[31:16] and ignores ED[15:0].
— For a write, the SEMI dri ves the word onto ED[31:16] and ass erts ER WN0†.
For a single-word (16-bit) access to an odd location:
— For a read, the SEMI transfer s the wor d from ED[15:0] and ignores ED[31:16].
— For a write, the SEMI dri ves the word onto ED[15:0] asserts ERWN1†.
For a double-word (32-bit) aligned access, i.e., an access to an even address:
— For a read, the SEMI transfer s the double word from ED[31:0].
— For a write, the SEMI dri ves the double word onto ED[31: 0] and asserts ERWN0 and ER WN1†.
For a double-word (32-bit ) m isaligned acces s, t he SEMI perform s two single-word (16-bit) acc esses:
— First , t he SEM I accesses the most signif icant half of the dou ble word at the original address (see single-
word (16-b it) access to an odd locati on descri bed above) .
— Second, the SEMI increments the address and accesses the l east significant half of the double word
(see single-word (16-bit) access to an even location described above).
† For a synchronous write, the SEMI also asserts EA0 as a write strobe. The EROM component is synchronous if the ERTYPE pin is logic high. The
ERAM comp onent is sy nchr onous if th e YTYPE field (ECON1[9]) is set. The EIO component i s synchr onous if the IT YPE fiel d ( ECON1[10]) i s
set. ECON1 is described in Tabl e 61 on pa ge 112 .
ERTYPE
(input) 0 The EROM component is popul ated with ROM or asynchronous SRAM, and the SEMI perform s asynchro-
nous accesses to th e EROM component.
1 The EROM component is populated wi th synchronous
ZBT
SRAM, and the SEMI performs synchronous
accesses to the EROM component.
EXM
(input) 0 If EXM is logi c low when the RSTN pin makes a low- to-high transition, bot h cores begi n program exe cution
from their internal ROM (IROM) memory at location 0x30000.
1 If EXM is logic high when the RSTN pin makes a low-to-high transition, both cores begin program execution
from exter nal ROM (EROM) memor y at l ocatio n 0x80000. The SEMI arb itrates the accesses fro m the two
cores.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.1 External Interface (continued)
4.14.1.2 Asynchronous Memory Bus Arbitration
The SEMI allows an external device to request direct access to an asynchronous external memory by asserting the
EREQN pin. T he SEM I acknowledges the external request by asserting its EACKN pin. The SEMI allows an
external device to extend the duration of an external asynchronous access by deas serting the ERD Y pin.
Table 53. Asynchro nou s Mem ory Bus Arbitration Pins
Pin Description
EREQN
(negative-
assertion input)
An external device ass ert s EREQ N (low) to reques t direct access to an asynchronous external memor y. If
the NOSHARE fi eld (ECON1[8]—see Table 61 on page 112) is set, the DSP16411 ignores the request. If
NOSHARE is clea red, a mi nimum of f our cycl es later the SEM I grants the r equest by perform ing the fol low-
ing:
First, the SEMI compl etes any ext ernal access that is already in progress.
The SEMI 3-st ates the address bus and segment address ( EA[18:0] and ESEG[3: 0]), the data bus
(ED[31: 0]), and all the external enables and strobes (ERAMN, EROMN, EI ON , and ERWN[1:0]) until the
external device deasserts EREQN. The SEMI continues to dri ve ECKO.
The SEMI acknowledges the re quest by asse rting EACKN.
The cores and the DMAU continue processing. If a core or the DMAU attempts to perf orm an external
memory acc ess, it stal ls unt il the external devi ce relinquish es the bus. If the external device deassert s
EREQN (c hanges EREQN from 0 to 1), four cycles later the SEMI deassert s EACKN (changes EACKN
from 0 to 1). To avoid external bus contention, the external device m ust wait for at least
ATIME
MAX
cycles†
after it deasserts EREQN (changes EREQN from 0 to 1 ) bef ore reasserting EREQN (changing EREQN
from 1 to 0). The soft ware can read the state of the EREQN pin in the EREQN field (ECON1[4]—see
Table 61 on page 112).
Note: If EREQN is not in use by the application, it must be tied high.
†
ATIME
MAX
is the greatest of IATI M E (ECON0[11:8]), YATIME (ECON0[7:4]), and XATIME (ECON0[3:0]).
EACKN
(negative-
assertion output)
T he SE MI acknowledges the request of an external device for di rect acc e ss to an asynchronous exter nal
memor y by assert ing EACKN. See the descript ion of the EREQN pin above for details. The software can
read the state of the EACKN pin in the EACKN field (ECON1[5]—see Table 61 on page 112).
ERDY
(positive-
assertion input)
An externa l device instructs the SEMI to extend th e duration of the current asynchronous external memory
acces s by driv ing ERDY l ow . See Secti on 4.14.5.2 on page 120 for detai ls. The software can read the state
of the ERDY pin in the EREADY field (ECON1[6] —see Table 61 on page 112).
Note: If thi s pin is not in use by the appl ication or if all externa l memory is synchronous, ERDY must be
tied hi gh.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.1 External Interface (continued)
4.14.1.3 Enables and Strobes
The SEMI provides a negative-assertion external memory enable output pin for each of the three external memory
components: ERAM, EIO, and EROM. These pins are the acti ve-low enables for the external memory components
ERAM (external RAM), EROM (external ROM), and EIO (external I/O). Refer to the memory maps described in
Section 4.5 on page 38 and shown in Figures 6, 7, 8, and 9 for details about the se mem ory components . T he
SEMI provides two negative-assertion write strobe output pins, ERWN[1:0]. Table 54 details the SEMI enables and
strobe pins. The SEMI 3-states the enables and strobes if it grants a request by an external device to access the
external memory (see description of the EREQN pin in Table 53 on page 103 ).
Table 54. En abl e and Stro be Pins for the SEMI Externa l Interface
Pin Value Description
ERAMN
(negative-
assertion output)
0 The SEMI is sel ecti ng the ERAM memory com ponent f or an access . The SEMI asserts thi s enable
for a duration based on whether the ERAM memory component is configured as asynchronous or
synchronous:
If th e ERAM memory component is configur ed as asynchr onous (the YTYPE fie ld
(ECON1[9]—see Table 61 on page 112) is cleared), the SEMI asserts ERAMN for the number of
instructi on cycl es specified by the YATIME[3:0] fiel d (ECON0[7:4]—see Table 60 on page 111).
If t he ERAM memory compon ent is con figur ed as syn chronous (the YTYPE fiel d is set) , the SEMI
asserts ERAMN for one ECKO cycle† for a read or write operation.
1 The SEMI is not sel ecting the ERAM me mo ry component for an access .
Z The SEMI 3-states ERAMN if it grants a request by an external device to access the external mem-
ory (see des cription of the EREQN pin in Tab le 53 on page 10 3).
EION
(negative-
assertion output)
0 The SEMI is select ing the EIO memory component for an access. The SEMI asserts this enabl e for
a duration based on whether the EIO memory component is configured as asynchronous or syn-
chronous:
If t he EIO memory component is configured as as ynchron ous (the ITYPE f ield (ECON1[ 10]—see
Table 61 on page 112) is cleared), the SEMI asserts EION for the number of instruction cycles
specified by the IATIME[3:0] field (ECON0[11:8]—see Table 60 on page 111).
If th e EIO memory compon ent is confi gured as sync hronous (the IT YPE fi eld is set), the SEMI
asserts EIO N for one ECKO cycle† for a read or write operati on.
1 The SEMI is not sel ecting the EIO memory component for an access.
Z The SEMI 3-st ates EION if it grants a request by an externa l device to access the external memory
(see description of the EREQN pin in Table 53 on page 103).
EROMN
(negative-
assertion output)
0 The SEMI is select in g the EROM memor y comp onent fo r an acces s †. The SEMI as serts this en able
for a duration based on whether the EROM memory component is configured as asynchronous or
synchronous:
If th e EROM memory component is configured as asyn chronous (the ERTYPE pi n is l ow), the
SEMI asserts EROMN for the number of instructi on cycles specified by the XATIME[3:0] field
(ECON0[3:0]—see Table 60 on page 111).
If th e EROM memory component is configured as sync hronous ( the ERTYPE pin is high), the
SEMI asser ts EROMN for one ECKO cycle† for a read or write operation‡.
1 The SEMI is not selecting the EROM memory component for a read access.
Z The SEMI 3-states EROMN if it grants a request by an external device to access the external mem-
ory (see des cription of the EREQN pin in Tab le 53 on page 10 3).
† If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, CLK/3, or CLK/4 (see the ECKOB[1:0] and
ECKO A[1 :0 ] fields of ECON1—Table 61 on pag e 112 ).
‡ The SEM I can writ e t he ERO M com pone nt only if the WEROM field (ECON1[11]—see Tabl e 61 on pag e 112) is set.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
Table 54. En able and Strobe Pin s for the SE M I External Interface (continued)
4.14.1 External Interface (continued)
4.14.1.3 Enables and Strobes (continued)
4.14 .1.4 Ex t e r nal Clock
The ECKO output pin provides an external clock for interfacing the SEM I to external synchronous memory. The
ECKOB[1:0] and ECKOA[1:0] fields (ECON1[3:0]—Table 61 on page 112) select one of several configurations for
ECKO, as specified in Table 55. See Section 4.19 on page 204 for additional detail.
Table 55. ECKO Output Clock Pin Configuration
ERWN1
(negative-
assertion output)
0 The external memor y is configur ed for 32-bit data (th e ESIZE pin is high) , and t he SEMI is perform-
ing an external write access over the least significant half of the external data bus (ED[15:0]).
1 The external memor y is configur ed for 16-bit data (th e ESIZE pin is low) or the external memory is
configured for 32-bit data (the ESIZE pin is high), and the SEMI is not performing an external write
access over the least signif icant half of the external dat a bus (ED[15: 0]).
Z The SEMI 3-states ERWN1 if it grants a request by an external device to access the external mem-
ory (see des cription of the EREQN pin in Tab le 53 on page 10 3).
ERWN0
(negative-
assertion output)
0 The SEMI is perf orming an external write access over the most sig nificant half of the ext ernal data
bus (ED[31: 16]).
1 The SEMI is not performing an ex ternal write access over the most significant half of the external
data bus (ED[31:16]).
Z The SEMI 3-states ERWN0 if it grants a request by an external device to access the external mem-
ory (see des cription of the EREQN pin in Tab le 53 on page 10 3).
ECKOB[1:0] ECKOA[1:0] ECKO Pin
ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description
0000CLK/2†
† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.
Frequency of CLK‡ divided by two.
‡ CLK is the internal (core) clock. See Secti on 4. 17 on page 200 fo r deta ils.
0001CLK Frequency of CLK‡.
0010CKI Input clock pin.
00110 Logic zero .
0 1 X X Reserved —
1 0 X X CLK/3 Frequency of CLK‡ divided by three .
1 1 X X CLK/4 Freque ncy of CLK‡ divided by four.
Pin Value Description
† If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, CLK/3, or CLK/4 (see the ECKOB[1:0] and
ECKO A[1 :0 ] fields of ECON1—Table 61 on pag e 112 ).
‡ The SEM I can writ e t he ERO M com pone nt only if the WEROM field (ECON1[11]—see Tabl e 61 on pag e 112) is set.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.1 External Interface (continued)
4.14.1.5 Address and Data
Table 56 details the address and data buses (ED[31:0]), EA[18:0], and ESEG[3:0]) and the EYMOD E signal.
Table 56. A ddress and Data Bus Pins for the SEMI External Interface
Pins Description
ED[31:16]†
(input/output)
If t he exter nal memory i s confi gured f or 16-bit data (t he ESIZE pin is low), t he SEMI uses ED[ 31:16] f or all
external accesses.
If th e exte rnal memory is configured for 32-bit data (the ESIZE pin is high), the SEMI uses ED[31:16] if:
— The SEMI is accessing a singl e word (16 bits) at an even address.
— The SEMI is accessing a double word at an even (al igned) address.
— The SEMI is accessing the l east signif icant half of a double wor d at an odd (misali gned) doubl e-word
address.
If the SEMI is not currently performing one of the above types of accesses, it 3-states ED[31:16]. The
SEMI 3-states ED[31:16] if it grants a request by an external device to access the external memory (see
description of the EREQN pin in Tab le 53 on page 103 ).
ED[15:0]†
(input/output)
If the external memory is configured for 32-bit dat a (the ESIZE pin is high), the SEMI uses ED[15:0] if:
— The SEMI is accessing a singl e word (16 bits) at an odd address.
— The SEMI is accessing a double word at an even (al igned) address.
— The SEMI is accessing the most signif icant half of a double word at an odd (mi saligned) doubl e-word
address.
If t he SEMI is not cur re ntly pe rformi ng one of th e above ty pes o f access es, it 3-st ate s ED[15:0 ]. The SEMI
3-states ED[15:0] if it grants a r equest by a n extern al device to acces s the ext ernal memor y (see des crip-
ti on o f t h e E RE Q N pin i n Tabl e 53 on page 103).
EA[18:1]†
(output)
If th e exte rnal memory is configured for 16-bit data (the ESIZE pin is low), t he SEMI places the 18 most
significant bits of the 19-bit external address onto EA[18:1].
If the external memory is configured for 32-bit data (the ESIZE pin is high), the SEMI places the 18-bit
external address onto EA[18:1].
After an access is comp let e and befor e the st art of a new access, the SEMI continues to dri ve EA[18:1]
with its current state.
The SEMI 3-states EA[18:1] if it grants a request by an external device to access the external memory
(see descript ion of the EREQN pin in Table 53 on page 103).
EA0†
(output)
If th e external mem ory is configured for 16-bit data (t he ESIZE pin is low), the SEMI places the least si g-
nificant bi t of the 19-bi t external address onto EA0.
If t he exter nal m emory is c onfigu red for 32-bit data (t he ESIZE pi n is hi gh), t he SEMI does not use EA0 as
an address bit:
— If the selected memory component is configured as asy nchronous‡, the SEMI driv es EA0 wit h it s pre-
vious value.
— If the selected memory component is configured as sy nchronous‡, t he SEMI drives a negative-asser -
tion write strobe ont o EA0 (the SEMI dri ves EA0 with the logical AND of ERWN1 and ER WN0) .
The SEMI 3-states EA0 if it grants a request by an external device to access the external memory (see
description of the EREQN pin in Tab le 53 on page 103 ).
† These addres s and da ta bus pi ns contain intern al bus hold ci rcuit s. If BHEDIS (ECON1[12]—Table 61 on pa ge 112 ) = 0, these bus hold circui ts are
act iv at ed. If BH ED IS = 0 and ne ither t he SEMI nor an ext ernal devic e i s driving these pins , the bus hol d circuits hold th em at their previous valid logic
level. This eliminates the need for external pull-up or pull-down resistors on these pins. See Section 10.1 on page 268 for d etails.
‡ The EROM compo nent is sync hronou s if the ER TYPE pin is logi c 1. The ERAM compon ent is s ynchr onous if YTYPE fie ld (ECON1[9]) i s se t. The E IO
com ponen t is synchro nous if the ITYPE fi el d (ECON1[10]) is set. ECON1 is de scribed in Ta bl e 61 on pa ge 112.
Advance Data Sheet
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
Table 56. Address and Data Bus Pins for the SEMI External Interface (continued)
4.14.1 External Interface (continued)
4.14.1.5 Address and Data (continued)
The SEMI provides a 32-bit external data bus, ED[31:0]. If the external memory is configured for 16-bit data (the
ESIZE input pin is low) , the SEMI uses only the upper half of the data bus (ED[31:16]). The SEMI provides a 19-bit
external address bus, EA[18:0], to select a location within the selected external memory component (ERAM, EIO,
or EROM). If the external memory is configured for 16-bit data, the SEMI uses EA[18:0] to address single (16-bit )
words within the selected mem ory compon ent . I f the external memory is con figured for 32-bit data (the ESIZE
input pin is high), the SEMI uses EA[18:1] to address double (32-bit) words within the selected memory component
and does not use EA0 as an address bit. For mo re detail, see Section 4.14.2 and Section 4.14.3 on page 109.
Note: The data and address bus pins (ED[31:0], EA[18:0], and ESEG[3:0]) contain internal bus hold circuits. If
BHEDIS (ECON1[12]—Ta ble 61 on page 112) = 0, these bus hold circuits are activated. If BHEDI S = 0 and
neither the SEMI nor an external device is dr iving these pins, the bus hold circuits hold them at their previous
valid logic level. This eliminates the need for external pull-up or pull-down re sistors on these pins. See
Section 10.1 on page 268 for details.
ESEG[3:0]†
(output)
If CORE0 acces ses EROM, the SEMI drives ESEG[3:0] with the contents of the XSEG0[3: 0] f iel d
(EXSEG0[3:0]—see Table 63 on page 114).
If CORE1 acces ses EROM, the SEMI drives ESEG[3:0] with the contents of the XSEG1[3: 0] f iel d
(EXSEG1[3:0]—see Table 64 on page 114).
If CORE0 accesses ERAM, the SEMI drives ESEG[3:0] with the contents of the YSEG0[3:0] field
(EYSEG0[3:0]—see Table 65 on page 115).
If CORE1 accesses ERAM, the SEMI drives ESEG[3:0] with the contents of the YSEG1[3:0] field
(EYSEG1[3:0]—see Table 66 on page 115).
If CORE0 acces ses EIO, the SEMI drives ESEG[3:0] with the contents of the I SEG0[3:0] fi eld
(EYSEG0[7:4]—see Table 65 on page 115).
If CORE1 acces ses EIO, the SEMI drives ESEG[3:0] with the contents of the I SEG1[3:0] fi eld
(EYSEG1[7:4]—see Table 66 on page 115).
If one of the DMAU SWT〈0—3〉 or M M T 〈4—5〉 channel s accesses EROM, ERAM, or EIO , th e SEMI
places the contents of the ESEG[3 :0] fiel d (SADD〈0—5〉[26:23] for read operations and
DADD〈0—5〉[26:23] for write operations—see Table 37 on page 77) onto its ESEG[3:0] pins .
If the PIU accesses EROM, ERAM, or EIO via the DMAU bypass channel, the SEMI places the contents
of the ESEG[3 :0] fi eld (PA[26:2 3]— see Tab le 80 on page 138) onto its ESEG[3:0] pin s.
After an access is complete and before the star t of a new access, the SEMI cont inues to dri ve ESEG[3:0]
with its current state.
The SEMI 3-st ates ESEG[3:0] if it grants a request by an external device to access the ext ernal memory
(see descript ion of the EREQN pin in Table 53 on page 103).
EYMODE
(input) This pi n det ermines the mode of the exter nal data bus. It m ust be stat ic an d tied to VSS (if the SEMI is us ed)
or VDD2 (i f the SEMI is not used) . If EYMODE = 0, the external data bus ED[31:0] operates normally as
described abov e. I f EYMODE = 1, ED[31: 0] are stati cally configured as outpu ts ( regardless of the state of
RSTN) and must not be connected extern all y. See Section 10.1 on page 268 for det ails.
Pins Description
† These addres s and da ta bus pi ns contain intern al bus hold ci rcuit s. If BHEDIS (ECON1[12]—Table 61 on pa ge 112 ) = 0, these bus hold circui ts are
act i vat ed. If BH ED IS = 0 and ne i ther the SEMI nor an ext ernal devic e i s driving these pins , the bus hol d circuits hold th em at their previous valid logic
level. This eliminates the need for external pull-up or pull-down resistors on these pins. See Section 10.1 on page 268 for d etails.
‡ The EROM compo nent is sync hronou s if the ER TYPE pin is logi c 1. The ERAM compon ent is s ynchr onous if YTYPE fie ld (ECON1[9 ]) is se t. The E IO
com ponen t is synchro nous if the ITYPE fi el d (ECON1[10]) is set. ECON1 is desc ribed in Table 61 on pa ge 112 .
Advance Data Sheet
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.1 External Interface (continued)
4.14.1.6 Address and Data
The SEMI 3-states ED[31:0], EA[18: 0], and ESEG[3:0]
if it grants a request by an external device to access
the external memory (see description of the EREQN
pin in Table 53 on page 103).
The SEMI provides the ESEG[3:0] pins to expand the
size of each of the external memory components, using
one of the following methods:
1. E SEG[3: 0] can be interpreted by the external mem-
ory system as four separate decoded addr ess
enable signals. Each ESEG[3:0] pin individually
selects one of four segme nts for each memory
component. This results in four glueless 512 Kword
(1 Mbyte) ERAM segments, four glueless 512 Kword
(1 Mbyte) EROM segments, and four glueless
128 Kword (256 Kbytes) EIO segments.
2. E SEG[3: 0] can be interpreted by the external mem-
ory system as an extension of the address bus, i.e.,
th e ESEG[3 :0] pin s c an be con ca tenated with the
EAB[18:0] pins to form a 23-bit address. This results
in one glueless 8 Mword (16 Mby tes) ERAM seg-
ment, one glueless 8 Mwo rd (16 Mbytes) EROM
segment, and one glueless 2 Mword (4 Mbytes) EIO
segment.
For external accesses by either core, the SEMI places
the conte nts of a field in one of four segment address
exten s i o n re g isters onto the ESEG [3 :0] pin s . The four
segment address extension registers are described in
Sect ion 4.1 4.4.3 on page 114. For external accesses
by the DMAU or PIU, the contents of address registers
within those units determine the state of the ESEG[3:0]
pins. See Table 56, beginning on page 106, for more
detail.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.2 16-Bit External Bus Accesses
Regardless of the configuration of the e xternal data bus via the ESIZE pin, e ach access by a core or the DMAU
can be a 16-bit (single-word) or 32-bit (double-word) access. Table 57 summarizes each type of access for a 16-bit
external bus configuration (ESIZE = 0).
Table 57. 16-Bit External Bus Configuration
4.14.3 32-Bit External Bus Accesses
Regardless of the configuration of the e xternal data bus via the ESIZE pin, e ach access by a core or the DMAU
can be a 16-bit (single-word) or 32-bit (double-word) access. Table 58 summarizes each type of access for a 32-bit
external bus configuration (ESIZE = 1).
Table 58. 32-Bit External Bus Configuration
Internal Address Type of Access External Address External Data ERWN1 ERW N0
Eve n or O d d S in gle-W o rd R ea d E ven or Od d E A[ 18: 0] E D[3 1: 16] 1 1
Single-Word Write EA[18:0] ED[31:16] 1 0
Even (aligned†)
† The SE M I performs t wo s eparate back-to-back 16-bi t acces ses, ev en address (most si gnif icant d ata) fi rst and odd add ress (l east signi fic ant data) sec-
ond.
Double-Word Read Even EA[18:0] ED[31:16] 1 1
Odd EA[18:0] ED[31:16] 1 1
Double-Word Write Even EA[18:0] ED[31:16] 1 0
Odd EA[18:0] ED[31:16] 1 0
Odd (misaligned‡)
‡ The SEMI pe rforms two s epara te 16-b it acc esses, odd address (m ost si gnifican t data) firs t and even address (least si gnifica nt data) second . The two
acces ses are not necessarily back-t o-back, i.e., they can be separa ted by other accesses.
Double-Word Read Odd EA[18:0] ED[31:16] 1 1
Even EA[18:0] ED[31:16] 1 1
Double-Word Write Odd EA[18:0] ED[31:16] 1 0
Even EA[18:0] ED[31:16] 1 0
Internal Address Type of Access External Address External Data ERWN1 ERWN0
Even Single-Word Read EA[18:1] ED[31:16] 1 1
Single-Word Write EA[18:1] ED[31:16] 1 0†
† For a wr i te oper at ion to a syn chro nous mem ory c om ponent, th e SEM I also drive s t he EA0 pi n lo w for use as a writ e enable. Th e EROM co m ponen t is
synchronous if the ERTYPE pin is logic 1. The ERAM component is synchronous if the YTYPE field (ECON1[9]) is set. The EIO component is syn-
chronous i f the ITYPE field (ECON1[10]) is set. ECON1 is descri bed in Table 61 on pag e 112.
Odd Single-Word Read EA[18:1] ED[15:0] 1 1
Single-Word Write EA[18:1] ED[15:0] 0†1
Even (ali gned) Double-Word Read EA[18:1] ED[31:0] 1 1
Double- Word Writ e EA[18:1] ED[31: 0] 0†0†
Odd (misaligned‡)
‡ The SE M I performs t wo s eparate 16-bit ac cesses. It acces ses the most si gnif ic ant data in th e odd addr ess first, and then t he l e ast significan t da ta in
the ev en address second. The t wo accesses are no t necessari l y back-t o-bac k, i.e. , t hey can be sepa rated by ot her ac cesses .
Double-Word Read EA[18:1] ED[15:0] 1 1
EA[18:1] ED[31:16] 1 1
Double- W ord W ri te EA[18:1] ED[15: 0] 0†1
EA[18:1] ED[31:16] 1 0†
Advance Data Sheet
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.4 Reg ist ers
There are six 16-bit mem ory-mappe d control registers that configure the operation of the SEMI, a s shown in
Table 59.
Table 59. SE M I Memory-Mapped Registers
Register Name Address Description Size
(Bits) R/W Type Reset Valu e
ECON0 0x40000 SEMI Contro l 16 R/W Contr ol 0x0FFF
ECON1 0x40002 SEMI Status and Control 16 R/W†Control 0‡
EXSEG0 0x40004 External X Segment Register for CORE0 16 R/ W Address 0
EYSEG0 0x40006 External Y Segment Register for CORE0
EXSEG1 0x40008 External X Segment Register for CORE1
EYSEG1 0x4000A External Y Segment Register for CORE1
† Some bi ts in thi s regis t er are read-onl y or w ri t e-only.
‡ With the fol l owing ex cepti ons: ECON1[6,4 ] are a reflecti on of the state of ex tern al pi ns and are unaffec ted by reset, and ECON1[5] i s se t.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.4 Reg ist ers (continued)
4.14.4.1 ECON0 Reg ister
ECON0 determines the setup, hold, and assertion times for the three external memory componen t enables . Th e
programmer needs to use the ECON0 register only if one or more of the external mem ory component s (ERAM ,
EROM , or EIO) is configu red as async hronous (se e S ect ion 4.1 4.4 .2 on page 112 and Section 4.14.1.1 on
page 102).
Table 60. ECON0 (Exter nal Control 0) Register
The memory address for this register is 0x40000.
15 14 13 12 11—8 7—4 3—0
WHOLD RHOLD WSETUP RSETUP IATIME[3:0] YATIME[3:0] XATIME[3:0]
Bit Field Value Description R/W Reset
Value
15 WHOLD 0 The SEMI does not extend the wri te cycle. R/W 0
1 The SEMI extends the write cycle for one CLK cycle, appl ies the target address,
deasserts all enables, deasserts all write strobes, and 3-states ED[31:0].
14 RHOLD 0 The SEMI does not ext end the read cycle. R/W 0
1 The SEMI extends the read cycle for one CLK cycl e, applies the target addr ess,
and deasserts all enables.
13 WSETUP 0 The SEMI does not delay the asser tion of the wr it e strobe , the memor y enable,
and the assertion of ED[31:0] for write oper ations. R/W 0
1 The SEMI delays the ass ert ion of the wri te strobe, the memory enab le, and
ED[31:0] during a write cycle for one CLK cycle. During the setup time, the SEMI
applies the target address to EA[18:0], deasserts all enables and ERWN signals,
and 3-states ED[31:0].
12 RSETUP 0 The SEMI does not delay the assertion of the memory enable for read operations. R/W 0
1 The SEMI delays the ass ert ion of the memor y enable during a read cycle for one
CLK cycle. During the setup time, the SEMI appli es the target address to
EA[18:0], deasserts all enables and ERWN signals, and 3-states ED[31:0].
11—8 IATIME[3:0] 0— 15 The duration in CLK cycles (1—15) that the SEMI asserts EION for an asynchro-
nous access to the EIO component. A value of 0 or 1 corresponds to a 1 CLK
cycle assertion time.
R/W 0xF
7—4 YATIME[3:0] 0—15 The duration in CLK cycles (1—15) that the SEMI asserts ERAMN for an asyn-
chronous access to the ERAM component. A value of 0 or 1 corresponds to a 1
CLK cycle assertion time.
R/W 0xF
3—0 XATIME[3:0] 0—15 The duration in CLK cycles (1—15) that the SEMI asserts EROMN for an asyn-
chronous access to the EROM component. A value of 0 or 1 corresponds to a 1
CLK cycle assertion time.
R/W 0xF
Advance Data Sheet
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.4 Reg ist ers (continued)
4.14.4.2 ECON1 Reg ister
The ECON1 register (Table 61) reports status information and controls additional features of the SEMI.
Table 61. ECO N 1 (Exter nal Control 1) Register
The memory address for this register is 0x40002.
15—14 13121110 9 8
Reserved BHPDIS BHEDIS WEROM ITYPE YTYPE NOSHARE
7654 3—2 1—0
Reserved EREADY EACKN EREQN ECKOB[1:0] ECKOA[1:0]‡
Bit Field Value Description R/W Reset
Value
15—13 Reser ved 0 Reserved —writ e with zero. R/W 0
13 BHPDIS 0 Enable the bus hold c ir cuits on t he PD[15:0] and PADD[3:0] pi ns (s ee Sect ion 10.1
on page 268 for detai ls). R/W 0
1 Disable the bus hold circuits on the PD[15:0] and PADD[3:0] pins.
12 BHEDIS 0 Enable the bus hold circui ts on the ED[31:0], EA[18:0] , and ESEG[3:0] pins (see
Section 10.1 on page 268 for details). R/W 0
1 Disable the bus hold cir cui ts on the ED[31:0], EA[18:0], and ESEG[3: 0] pins.
11 WEROM 0 The exter nal portio n of Y-memory and Z-mem ory space is ERAM (see
Section 4.5.3 on page 39). R/W 0
1 The exter nal portion of Y-memo ry and Z-memory space is EROM (see
Section 4.5.3 on page 39).
10 I TYPE 0 EION is asynchronous SRAM. R/W 0
1 EION is pipelined, sync hronous SRAM.
9 YTYPE 0 ERAMN is asynchronous SRAM. R/W 0
1 ERAMN is pipelined, synchronous SRAM.
8 NOSHARE 0 SEMI wo rks as a bus-shared interface and assert s EACKN in respons e to EREQN. R/W 0
1 SEMI ignores request s for the external bus and does not assert EACKN.
7 Reserved 0 Reserved—write with zero. R/W 0
6 EREADY 0 The ERDY pin i ndicates an exter nal device is r equesting the SEMI to extend the
current asy nchronous external memory access (see Table 53 on page 103). RP
†
1 The ERDY p in i ndicates an exter nal device is not requesting the SEMI to extend
the current asynchronous exte rnal memory acces s (see Table 53 on page 103).
5 EACKN 0 The EACKN pi n indicates the SEMI ackno wledges a request by an external device
for access to external memory (see Table 53 on page 103). R1
1 The EACKN p in i ndicates the SEMI does not acknowledge a request by an ext er-
nal device for access to external memory (see Table 53 on page 103).
4 EREQN 0 The EREQN pin indicates an ext ernal device is requesting access to ex ternal
memory (see Table 53 on page 103). RP
†
1 The EREQN pin indicates an ext ernal device is not requ esting access to external
memory (see Table 53 on page 103).
† The state (P) is a reflection of the state of the external pins and is unaffected by reset.
‡ The state of th is field i s ignore d unl ess EC K O B [1:0] = 00.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
Table 61. ECO N1 Register (continued)
4.14.4 Reg ist ers (continued)
4.14.4.2 ECON1 Reg ister (continued)
The ECKOB [1:0] and ECKO A[1: 0] fields (ECON1[3:0 ]) determine the state of the ECKO output clock pin as sum-
marized in Table 62. If any of the external memory components (ERAM, EROM, or EI O) are conf igured as synchro-
nous1, the ECKO pin must be configured as CLK/2, CLK/3, or CLK/4.
Table 62. ECKO Output Clock Pin Configuration
3—2 ECKOB[1:0] 00 The ECKOA[1:0] fiel d deter m ines the configuration of the ECKO pin. R/W 00
01 Reserved.
10 The ECKO pin i s CLK/3 f or synchronous operation of the SEMI.
11 The ECKO pin i s CLK/4 f or synchronous operation of the SEMI.
1—0 ECKOA[1:0]‡00 The ECKO pin is CLK/2 for syn chronous operat ion of the SEMI. R/W 00
01 The ECKO pin i s the internal cl ock CLK.
10 The ECKO pin i s the buffered input clock pin CKI.
11 The ECKO pin is held low.
1. The EROM c ompo nen t i s sy nc hron o us i f th e ER T YPE p in is logic 1. Th e ERAM co mpon ent is s yn chro nou s if the YT YPE fie ld (ECON1[9]) i s se t. The
EIO compo n ent is synch ron ou s if the ITYPE fi e ld (ECON1[10]) is set. ECON1 is described in Tabl e 61 on p age 11 2.
ECKOB[1:0] ECKOA[1:0] ECKO Pin
ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description
0000CLK/2†
† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.
Frequency of CLK‡ divided by two.
‡ CLK is the internal (core) clock. See Secti on 4. 17 on page 200 fo r deta ils.
0001CLK Frequency of CLK‡.
0010CKI Input clock pin.
00110 Logic zero .
0 1 X X Reserved —
1 0 X X CLK/3 Frequency of CLK‡ divided by three .
1 1 X X CLK/4 Freque ncy of CLK‡ divided by four.
Bit Field Value Description R/W Reset
Value
† The state (P) is a reflection of the state of the external pins and is unaffected by reset.
‡ The state of th is field i s ignore d unl ess EC K O B [1:0] = 00.
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4 4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.4 Reg ist ers (continued)
4.14.4.3 Segment Registers
The external program and data memory components
(EROM, ERAM, and EIO) can each be expanded for
each core through a combination of registers and pins.
The ESEG[3:0] pins (see S ecti on 4.14.1 on page 101)
reflect the value of the EXSEG0, EXSEG1, EYSEG0,
or EYSEG1 external segm ent re gisters for a given
external access. A user’s program executing in either
core can write to these registers to expand the external
ERAM and EROM data components. The value written
to any one of these re gisters is driven onto the
ESEG[3:0] pins for a corresponding memory compo-
nent as described below , and can be interpreted by the
system as an address extension (EA[22:19], for exam-
ple) or as decoded enables.
The SEMI dr ives bits 3:0 of the 16-bit EXSEG0 register
onto the ESEG[3:0] pins at the same time as it drives
the address onto EA[18:0] for an external ROM
(EROM) access from CORE0.
The SEM I drives bits 3:0 (for ERAM ) or bits 7:4 (for
EIO) of the 16-bit EYSEG0 reg ister onto the ESEG[3:0]
pins at the same time as it drives the address onto
EA[18:0] for an external RAM (ERAM or EIO) access
from CORE0.
The SEMI dr ives bits 3:0 of the 16-bit EXSEG1 register
onto the ESEG[3:0] pins at the same time as it drives
the address onto EA[18:0] for an external ROM
(EROM) access from CORE1.
The SEM I drives bits 3:0 (for ERAM ) or bits 7:4 (for
EIO) of the 16-bit EYSEG1 reg ister onto the ESEG[3:0]
pins at the same time as it drives the address onto
EA[18:0] for an external RAM (ERAM or EIO) access
from CORE1.
Table 63. EXSEG0 (CORE0 External X Segment Address Extension) Register
Table 64. EXSEG1 (CORE1 External X Segment Address Extension) Register
The memory address for this register is 0x40004.
15—4 3—0
Reserved XSEG0[3:0]
Bit Field Descr iption R/ W Reset Value
15—4 Reserved Reserved—write with zero. R/W 0
3—0 XSEG0[3:0] External segment address extens ion for X-memory acc esses to EROM by
CORE0. R/W 0
The memory address for this register is 0x40008.
15—4 3—0
Reserved XSEG1[3:0]
Bit Field Description R/W Reset Value
15—4 Reserved Reserved—write with zero. R/W 0
3—0 XSEG1[3 :0] Exter nal segment address extension for X-me mory accesse s to EROM by
CORE1. R/W 0
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.4 Reg ist ers (continued)
4.14.4.3 Se gm ent R egisters (continued)
Table 65. EYSEG0 (CORE0 External Y Segment Address Extension ) Register
Table 66. EYSEG1 (CORE1 External Y Segment Address Extension ) Register
The memory address for this register is 0x40006.
15—8 7—4 3—0
Reserved ISEG0[3:0] YSEG0[3:0]
Bit Field Description R/ W Reset Value
15—8 Reserved Reserved—write with zero. R/W 0
7—4 ISEG 0[3:0] External segment address ext ension for Y-memory accesses to EIO by
CORE0. R/W 0
3—0 YSEG0[3 :0] Exter nal segment address extension for Y-memory accesses to ERAM by
CORE0. R/W 0
The memory address for this register is 0x4000A .
15—8 7—4 3—0
Reserved ISEG1[3:0] YSEG1[3:0]
Bit Field Descript ion R/W Res et Val ue
15—8 Reserved Reserved—write with zero. R/W 0
7—4 ISEG 1[3:0] External segment address ext ension for Y-memory accesses to EIO by
CORE1. R/W 0
3—0 YSEG1[3 :0] Exter nal segment address extension for Y-memory accesses to ERAM by
CORE1. R/W 0
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.5 Asynchronous Memory
This section describes the functional timing and inter-
facing for external mem ory compone nts that are con-
figured as asynchronous. The EROM component is
asynchronous if the ERTYPE pi n i s logi c 0. The ERAM
component is asynchronous if the YTYPE field
(ECON1[9]) is cleared, and the EIO component is
asynchronous if the ITYPE fi eld (ECON1[10]) i s
cleared. ECON1 is described in Table 61 on page 112.
In this section:
The designat ion
ENABLE
refers to the EROMN,
ERAMN, or EION pin.
The designat ion
ERWN
refers to:
— The ERWN0 pin if the external data bus is config-
ured as 16 bits, i.e., if the ESIZE pin is logic low .
— The ERWN1 and ERWN0 pins if the external data
bus is configured as 32 bits, i.e ., if the ESIZE pin
is logic high.
The designat ion
EA
refers to:
— The external address pins EA[18:0] and the exter-
nal segment address pins ESEG [3:0] if the exter-
nal data bus is configured as 16 bits, i.e., if the
ESIZE pin is logic low.
— The external address pins EA[18:1] and the exter-
nal segment address pins ESEG [3:0] if the exter-
nal data bus is configured as 32 bits, i.e., if the
ESIZE pin is logic high.
The designat ion
ED
re fe r s to:
— The external data pins ED[31:16] if the external
data bus is configured as 16 bits, i.e., if t he ESIZE
pin is logic low.
— The external data pins ED[31:0] if the external
data bus is configured as 32 bits, i.e., if t he ESIZE
pin is logic high.
The designat ion
ATIME
refers to IATIME
(ECON0[11:8]) for accesses to the EIO space,
YATIME (ECON0[7:4]) for accesses to the ERAM
space, or XATI ME (ECON0[3:0]) for accesses to the
ERO M spac e.
RSETUP refers to the RSETUP field
(ECON0[12]—see Table 60 on page 111 ).
RHOLD refers to the RH OLD field (ECON0[14]).
WSETUP refers to the WSETUP field (ECON0[13]).
WHOLD refers to the WHOLD field (ECON0[15]).
4.14.5. 1 Functional Timing
The following describes the functional timing for an
asynchronous read operation:
1. On a ris ing e dge of t he inter nal clock (CLK ), t he
SEMI asserts
ENABLE
and drives the read address
onto
EA
. If RSETUP is set, the SEMI asse rts
ENABLE
one CLK cycle later.
2. T he SEM I asserts
ENABLE
for
ATIME
CLK cycles.
3. The SEMI dea sserts
ENABLE
on a rising edge of
CLK and latches the data from
ED
.
4. The SEMI continues to drive the read address onto
EA
for a minimum of one CLK cycle to guarantee an
address hold time of at l east one cycle. If RHOLD i s
set, the SEMI continues to drive the read address for
an additional CLK cycle.
The SEM I continues to drive the a ddress until another
external memory access is initi ated. Another read or a
write to the same memor y component can i mmediately
follow the read cycle described above.
The following describes the functional timing for an
asynchronous write operation:
1. On a ris ing e dge of t he inter nal clock (CLK ), t he
SEMI asserts
ERWN
and drives the write address
onto
EA
. If WSETUP is set, the SEMI asserts
ERWN
one C LK cycle later.
2. One CLK cycle after the SEMI asserts
ERWN
, th e
SEMI asserts
ENABLE
and drives valid data onto
ED
to
guarantee one CLK cycle of setup time.
3. T he SEM I asserts
ENABLE
for
ATIME
CLK cycles.
4. The SEMI dea sserts
ENABLE
on a rising edge of
CLK.
5. The SEMI continues to drive
ED
with the write data,
drive
EA
with the write address, and assert
ERWN
for one additional CLK cycle to guarantee one cycle
of hold time. I f WHOLD is set, the SEMI continues
to drive the write address for an additional CLK
cycle.
The SEM I continues to drive the a ddress until another
external mem ory access is initiated. An other write to
the same memory component can immediately follow
the write cycle described above. If a read to the same
mem ory compone nt follows the write cycle described
above, the SEMI inserts an idle bus cycle (one CLK
cycle).
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.1 4.5 .1 Fu nct i on a l Timing (continued)
Fig ur e s 27 through 30 provide examples of asynchronous me mory accesse s for various SEMI configurations.
These examples ass ume that the DMAU is performing the external memory accesses. The access rate shown is
not achievable if the accesses are performed by one or both cores. For details on SEMI performance for an asyn-
chronous interface, see Section 4.14.7.2 on page 129. For a summary of SEMI performance, see Section 4.14.7.4
on page 133 .
Asynchrono us Timi ng
Notes:
It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 112) is pr og ram med to 0x 0 a nd th e
ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.
It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111) i s programmed to 0x2 and th e IATIME [3:0 ] field (ECON0[11:8 ]) is
programmed to 0x3.
It is assumed that the DMAU is performing the external me mory accesses. The access rate show n is not achi evable if the accesses are per-
formed by one or both cores.
Figure 27. Asynchrono us Me m ory Cycles
EION
ERWN
ECKO
ERAMN
DON’T CARE
HIGH-IMPEDANCE OUTPUT
ERAM ERAM ERAMERAM ERAM EIO EIO
READ READ WRITEWRITE WRITE READ READ
IATIME
A5A4
A6
A3A2A1A0
IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ
EA
D1 D2 D6Q3 Q4 Q5
ED
Q0
YATIME YATIME YATIME YATIME YATIME
IATIME
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.1 4.5 .1 Fu nct i on a l Timing (continued)
Asynchronous Memory Cycles (RSETUP = 1, WSETUP = 1)
Notes:
It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 112) is pr og ram med to 0x 0 a nd th e
ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.
It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111) i s programmed to 0x2 and th e IATIME [3:0 ] field (ECON0[11:8 ]) is
programmed to 0x3.
It is assumed that the DMAU is performing the external memory access es. T he access rate shown is no t achievab le if the accesses are per-
formed by one or both cores.
Figure 28. Asynch ronou s Memo ry Cycl es (RSETUP = 1, WSE TUP = 1)
EIO
ERWN
ERAM
D1 D2
IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ
EIO
ECKO
EA
ED
Q0 D1 D2
HIGH-IMPEDANCE OUTPUT
ERAM ERAMERAM EIO
A0
ERAM
D5
A1 A2 A3 A4 A5
READ WRITE WRITE READ READ WRITE
RSETUP
YATIME
IATIME
WSETUP WSETUP WSETUP
RSETUP
RSETUP
Q3 Q4
YATIME YATIME YATIME
IATIME
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.1 4.5 .1 Fu nct i on a l Timing (continued)
Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1)
Notes:
It is ass ume d th at EC KO is p r ogra mme d as CL K, i .e. , t h e ECKO B[ 1:0 ] fi el d (ECON1[3:2]—Table 61 on page 112) is pr og ram m ed to 0x 0 a nd th e
ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.
It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111) i s programmed to 0x2 and th e IATIME [3:0 ] field (ECON0[11:8 ]) is
programmed to 0x3.
It is assumed that the DMAU is performing the external me mory accesses. The access rate show n is not achi evable if the accesses are per-
formed by one or both cores.
Figure 29. Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1)
ECKO
EIO
ERWN
EA
ERAM
ED
D1 D2 D5
A0 A1
A2
A3
A4
A5
RHOLD
YATIME
IATIME
WHOLD WHOLD WHOLDRHOLD RHOLD
IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ
HIGH-IMPEDANCE OUTPUT
EIOERAM ERAMERAM EIOERAM
READ WRITE WRITE READ READ WRITE
Q3 Q4Q0
IATIME
YATIME YATIME YATIME
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.14.5.2 Extending Access Time Via the ERDY Pin
An external device can delay the completion of an external memory access to an asynchronous memory compo-
nent by control of the ERDY pi n (see Figure 30). If driven low by the external device, the SE MI extends the curr ent
external memory ac cess that is already in pr ogress. To guarantee proper operation, ERDY must be driven low at
least 4 CLK cycles before the end of the acc ess and the enable mus t be programm ed for at least 5 CLK cycles of
assertion (via the YATIME, XATIME, or IATIME field of ECON0—see Table 60 on page 1 11). The SEMI ignores the
state of ERDY prior to 4 CLK cycles before the end of the access. The access is extended by 4 CLK cycles after
ERDY is driven high. The state of ERDY is readable in the EREADY field (ECON1[6]—see Table 61 on page 112).
This feature of the SEMI provides a convenient interface to peripherals that have a variable access time or require
an access time greater than 15 CLK cycle s in duration.
Use of ERDY Pin to Extend Asynchronous Accesses
Figure 30. Use of ERDY Pin to Extend Asynchronous Accesses
ENABLE
††
ERDY
4T‡
N
× T‡
SEMI
SAMPLES
ERDY PIN
ECKO§
ATIME
†
END OF
ACCESS
(UNSTALLED)
N
× T‡
4T‡
END OF
ACCESS
(STALLED)
†
ATIME
mus t be pr ogrammed as gr eater than or equal t o five CLK cycles. Otherwise, th e SEM I ignores the s tate of ERDY.
‡ T = internal clock period (CLK).
N
must be greater than or equal to one, i.e., ERDY must be hel d low for at least one CLK cycle af ter the
SEMI samples ERDY.
§ ECKO reflects CLK, i.e., ECON1[1:0] = 1.
†† The designation
ENABLE
refers to one of the following pins: EROMN, ERAMN, or EION.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.14.5.2 Extending Access Time Via the ERDY Pin (continued)
Figure 31 illust rates an examp le read and write operation using the ERDY pin to extend the accesses.
Use of ERDY Pin to Extend Asynchronous Accesses
Notes:
It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 112) is pr og ram med to 0x 0 a nd th e
ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.
It is assumed that the YATIME[3:0] field (ECON0[7:4]—Table 60 on page 111) is programmed to 0x7.
Figure 31. Example of Using the ERDY Pin
D1
HIGH-IMPEDANCE OUTPUT
ECKO
ERAMN
ED
ERDY
YATIME STALL YATIME STALL
ERWN
A0 A1
EA
DON’T CARE
Q1
ERAM ERAM
READ WRITE
4T 4T
SAMPLE
POINT SAMPLE
POINT
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.14.5.3 Interfacing Examples
Figures 32 and 33 illustrate two examples of interfacing 16-bit asynchron ous SRAM s to the SEMI. Th e use r can
individually configure the EROMN, ERAM N, and EION enables to suppo rt asynchronous dev ices. Th e ERTYPE
pin must be at logic low for the EROM component to be configured for asynchronous accesses. Clearing the
YTYPE field (ECON1[9]) and ITYPE field (ECON1[10]) configures the ERAM and EIO components for asynchro-
nous accesses.
The programmer can individually configure the access time (defined as the number of CLK cycles that the enable
is asserted) for each enable. The YATIME field (ECON0[7:4]) specifies t he number of CLK cycles that the ERAMN
enable is asserted. The XATIME field (ECON0[3:0]) specifies the number of CLK cycles that the EROMN enable is
asserted. The IATIME field (ECON0[11:8]) specifies the number of CLK cycles that the EION enable is asserted.
The range of values for these fields is from 0 to 15 (corresponding to a range of 1 to 15 CLK cycles). A value of 0
or 1 programs a 1 CLK assertion time for the corresponding enable.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.5 Asynchronous Memory (continued)
4.14.5.3 Interfacing Examples (continued)
32-Bit External Interface with 16-Bit Async hronous SRAMs
Figure 32. 32-Bit External Inte rface with 16-Bit Asynchro no us SRAMs
16-Bit External Interface with 16-Bit Async hronous SRAMs
Figure 33. 16-Bit External Inte rface with 16-Bit Asynchro no us SRAMs
SRAM
A[15:0]
WE
CE
DB[15:0]
SRAM
A[15:0]
WE
CE
DB[15:0]
DSP16411
SEMI
ESIZE VDD
EA[16:1]
ERWN0
ERAMN
ED[31:16]
ERWN1
ED[15:0]
EVEN ADDRESS
ODD ADDRESS
ERTYPE VSS
SRAM
A[16:0]
WE
CE
DB[15:0]
DSP16411 SEMI
ESIZE VSS
EA[16:0]
ERWN0
ERAMN
ED[31:16]
ERTYPE VSS
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.6 Synchronous Memory
This section describes the functional timing and inter-
facing for external mem ory compone nts that are con-
figured as synchronous. The EROM co mpo nent is
synchronous if the ERTY PE pin is logic 1. The ERAM
component is synchronous if the YTYPE field
(ECON1[9]) is set, and the EIO component is synchro-
nous if the ITYPE field (ECON1[10]) is set. ECON1 is
described in Table 61 on page 112 .
If any of the external memory components (EROM ,
ERAM, or EIO) are configured as synchronous, the
SEMI external output clock (ECKO) must be pro-
grammed as CLK/2, CLK/3, or CLK/4 (see the
ECKOB[1:0] and ECKOA[1:0] fields of ECON1[1:0]).
After reset, the default state of ECKO is CLK/2.
In this section:
The designat ion
ENABLE
refers to the EROMN,
ERAMN, or EION pin.
The designat ion
ERWN
refers to:
— The ERWN0 pin if the external data bus is config-
ured as 16 bits, i.e., if the ESIZE pin is logic low .
— The ERW N1, ERWN0, and EA01 pins if the exter-
nal data bus is configured as 32 bits, i.e., if the
ESIZE pin is logic high.
The designat ion
EA
refers to:
— The external address pins EA[18:0] and the exter-
nal segment address pins ESEG [3:0] if the exter-
nal data bus is configured as 16 bits, i.e., if the
ESIZE pin is logic low.
— The external address pins EA[18:1] and the exter-
nal segment address pins ESEG [3:0] if the exter-
nal data bus is configured as 32 bits, i.e., if the
ESIZE pin is logic high.
The designat ion
ED
re fe r s to:
— The external data pins ED[31:16] if the external
data bus is configured as 16 bits, i.e., if t he ESIZE
pin is logic low.
— The external data pins ED[31:0] if the external
data bus is configured as 32 bits, i.e., if t he ESIZE
pin is logic high.
4.14.6. 1 Functional Timing
The following describes the functional timing for a syn-
chronous read operation (see Figure 34 on page 125):
1. On a rising edge of the external output clock
(ECKO), the SEMI drives the read address onto
EA
and asserts
ENABLE
for one ECKO cycle.
2. On the rising edge of the second ECKO cycle, the
SEMI deasserts
ENABLE
.
3. On the rising edge of the third ECKO cycle, a new
access can begin because synchronous accesses
are pipelined.
4. On the rising edge of the fourth EC KO cycle, the
SEM I latches the data from
ED
.
The following describes the functional timing for a syn-
chrono us write operation (see Figure 34 on page 125):
1. On a rising edge of the external output clock
(ECKO), the SEMI drives the write address onto
EA
and asserts
ERWN
and
ENABLE
for one ECKO
cycle.
2. On the rising edge of the second ECKO cycle, the
SEMI deasserts
ENABLE
and
ERWN
.
3. On the rising edge of the third ECKO cycle, a new
access can begin because synchronous accesses
are pipeline d. O n this edge, the SEMI drives
ED
with the write data for one ECKO cycle.
4. On the rising edge of the fourth cycle, the external
memory latches the data from
ED
.
1. The EA0 pin is a strobe only if the bus is configured for 32 bits and the memory is conf igur ed as synchronous .
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.6 Synchronous Memory (continued)
4.1 4.6 .1 Fu nct i on a l Timing (continued)
Figure 34 illustrates an examp le of synchronous memory accesses. This example assumes that the DMAU is per-
forming the external memory access es. The access rate shown is not achievable if the accesses are perfor med by
one or both cores. For details on SEMI performanc e for a synchronous interface, see Section 4.14.7.3 on
page 131. For a summary of SEMI performance, see Section 4.14.7.4 on page 133.
Synchronous Timing
Figure 34. Synchronous Memory Cycles
CLK
EION
ERWN
EA
ERAMN
ED
HIGH-IMPEDANCE OUTPUT
D1
ECKO
ERAM READ
ERAM
WRITE
ERAM READ
ERAM READ
EIO READ
A0 A1 A2 A6A3 A4 A5
Q0 D2 Q3 Q4 Q5 D6
ERAM
WRITE
EIO
WRITE
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.6 Synchronous Memory (continued)
4.14.6.2 Interfacing Examples
If any of the external memory components (EROM ,
ERAM, or EIO) are configured as synchronous, the
SEMI external output clock (ECKO) must be pro-
grammed as CLK/2, CLK/3, or CLK/4 (see the
ECKOB[1:0] and ECKOA[1:0] fields of
ECON1—Table 61 on page 112 ). After reset, the
default state of ECKO is CLK/2.
Fig u r e s 35 and 36 illustrate examples of interfacing
16-bit and 32-bit pipelined synchronous
ZBT
SRAMs t o
the SEMI. The program m er can individually configure
EROMN, ERAMN, and EION enables to support this
type of synchronous device. The ERTYPE pin must be
at logic high for the EROM component to be configured
for synchronous accesses. Setting the YTYPE fi e ld
(ECON1[9]) and ITYPE field (ECON1[10]) configures
the ER AM and EIO com ponent s for synchron ous
accesses.
Figure 35 illustrates interfacing the SEMI to a 16-bit
synchronous, pipelined
ZBT
SRA M. In this example:
1. The SEMI add ress bus (EA[17:0]) is connected to
the SRAM’s address bus (A[17:0]). One of the SEMI
ESEG[3:0] pins can be optionally connected to the
SRAM ’s active-high chip selec t input (CE2).
2. The upper 16 bits of the SEMI data bus (ED[31:16])
are connected to the SRAM’s bidirectional data bus
(DQ[15:0]).
3. The SEMI external clock (ECKO) is programmed for
operation at CLK/2, CLK/3, or CLK/4, and is con-
nected to the SRAM’s CLK input.
4. The SEMI external dat a compone nt enable
(ERAMN ) and external read/write strobe (ERWN0)
are connected to the SRAM’s active-low chip enable
and write enable inputs, respectively.
5. The SRAM ’s active-low ADV/LD must be tied low.
6. The SEMI’s ESIZE pin is tied low to configure the
data bus for 16-bit accesses.
16-Bit E xt ernal Interf ace wi t h 16- Bit
ZBT
Pipelined Synchronous SRAMs
Figure 35. 16-Bit External Interface with 16-Bit Pipelined, Synchr onous
ZBT
SRAMs
A[17:0]
CLK
CE1
DQ[15:0]
VSS
EA[17:0]
ECKO
ERAMN
ED[31:16]
DSP16411 16-bit SYNCHRONOUS
ERWN0 WE
ADV/LD
ESIZE
VSS
SRAM
BWa
BWb
VSS OE
CE2
ESEG[3:0]
VDDERTYPE
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.6 Synchronous Memory (continued)
4.14.6.2 Interfacing Examples (continued)
32-Bit E xt ernal Interf ace wi t h 32- Bit
ZBT
Pipelined Synchronous SRAMs
† SEMI is c onfigu red for a 32-bit da ta bus. In this con figuration, EA0 is RWN for 3 2-bit accesses (logical AND of ERWN0 and ERWN 1).
Figure 36. 32-Bit External Interface with 32-Bit Pipelined, Synchr onous
ZBT
SRAMs
A[16:0]
CLK
CE
DQa[7:0]
VDD
EA[17:1]
ECKO
ERAMN
ED[31:24]
32-bit SYNCHRONOUS
ERWN1
ESIZE
SRAM
BWa
BWb
VSS OE
ERWN0 BWc
BWd
ED[23:16]
ED[15:8]
ED[7:0]
RW
EA0†
DQb[7:0]
DQc[7:0]
DQd[7:0]
DSP16411
VDDERTYPE
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.7 Performance
The following terms are used in this section:
A requester, a core or t he DMAU, requests the SEMI
to access external memory or the system bus.
Conten tion refers to multiple requests for the same
resource at the same time.
The designat ion
ATIME
refers to IATIME
(ECON0[11:8]—see Table 60 on page 111) for
accesses to the EIO space, YATIME (ECON0[7:4])
for accesses to the ERAM space, or XATIME
(ECON0[3:0]) for accesses to the EROM space.
RSETUP refers to the RSETUP field (ECON0[12]).
RHOLD refers to the RH OLD field (ECON0[14]).
WSETUP refers to the WSETUP field (ECON0[13]).
WHOLD refers to the WHOLD field (ECON0[15]).
Misali gned refers to 32-bit accesses to odd
addresses.
SLKA
refe rs to th e SLKA〈5—4〉 fields
(DMCON0[9:8]—see Table 31 on page 71 ).
TCLK refers to one period of the internal clock CLK.
The SEMI controls and arbitrates two types of memory
accesses. The first is to external memory. The second
is to th e int ern a l I/ O segme nt accessed via the system
bus. Section 4.14.7.1 describes the SEMI perfor-
mance fo r system bus accesse s. Section 4.14.7.2 on
page 129 des cribes th e SEMI performance for asyn-
chronous external memory accesses and
Section 4.14.7.3 on page 131 desc ribes the SEMI per-
formance for synchronous external memory accesses.
The performance for all of these types of accesses are
summarized in Section 4.14.7.4 on page 133.
For the remainder of this section, unless otherwise oth-
erwise stated, the followin g assumptions apply:
There is only a single requester, i.e., no contention.
SEM I requests by the DMAU are from a memory-to-
memory (MMT) channel and the user program has
enabled the source look-ahead feature by setting the
appropriate
SLKA
field (Section 4.13.6, beginning on
page 90).
The source of the request (core vs. DMAU), the config-
uration of the SE M I data bus size (16-bit vs. 32-bit),
and the type of access (read vs. write) determine the
throughput of any external memory access.
Section 4.14.7.2, beginning on page 129, and
Section 4.14.7.3, beginning on page 131, describe the
performanc e for all combinations.
The DMAU source look-ahead feature takes advantage
of the DMAU pipeline and allows the DMAU to read
source data before completing the previous write to the
destination. Secti on 4.14.7.4 on page 133 s hows per-
formanc e figures with this featur e both enabled and
disabled.
For an MMT channel, each DMAU access consists of a
read of the source location and write to the dest ination
location. Therefore, the DMAU performance values
state d in this se ction assume two operations per trans-
fer.
4.14.7.1 System Bus
The SEM I controls and arbitrates acce sses to internal
I/O segmen t a cce ssed via th e system bus . Only 16-b i t
and aligned 32-bit trans fers are permitted via the sys-
tem bus. The syst em bus is used to access a ll the
mem ory-mapped registers in the DMAU, SIU0, SIU1,
PIU, and SEMI. See Section 6.2.2 on page 231 for
details on the memory-mapped registers. Misaligned
32-bit accesses to internal I/O space cause undefined
results.
Table 67 specifie s the minimum syste m bus access
time for either a single-word (16-bit) or double-word
(32-bit) acces s by a single re queste r. The SEMI pro-
cesses system bus accesses by multiple requesters at
a maximum rate of one access per CLK cycle.
For example, if a program executing in CORE0 per-
forms a read of the 1 6-bit DMCON0 register, the read
requires a minimum of five CLK cycles. The access
could take longer if the SEMI is bus y processing a prior
reques t, i.e., if there is contention. A s a second exam-
ple of an S-bus transfer, assum e the DMAU is moving
data between TPRAM0 and the SLM. The SLM is a
memory block accessed via the S- bus. Assuming no
contention, the DMA U can read a word from TPRAM0
and write a word to the SLM at an effective rate of two
16-bit words per two CLK cycles.
Table 67. System Bus M inimu m Access Times
Access Minimum Acces s Time
Read 5×TCLK
Write 2×TCLK
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.2 External Memory, Asynchronous Interface
External Accesses by Either Core, 32-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by either core to asynchronous
memory with the external data bus configured as 32-bit
(the ESIZE pin is logic high):
READS—For the cores, 16-bit and 32-bit aligned
external as ynchronous memory reads occur with a
minimum period of the enable assertion time (as pro-
grammed in
ATIME
), plus a one CLK cycle enforced
hold time, plus th ree CLK cycles for the SEMI pipeline
to complete the core access. This assumes that
RSETUP and RHOLD are cleared. The core treats
misaligned 32-bit reads as two separate 16-bit reads
requiring two complete SEMI accesses.
The core read access time for a 32-bit data bus is the
following:
[
ATIME
+ 4 + RSETUP + RHOLD] ×
misaligned
× TCLK
where:
misaligned
= 1 for 16-bit and aligne d 32-bit
accesses.
misaligned
= 2 for misaligned 32-bit accesses.
WRITES—F or the cores, 16-bit and 32-bit aligned
asynchronous mem ory writes can occur with a mini -
mum period of the enable assertion time (as pro-
grammed in
ATIME
), plus a one CLK cycle enforced
setup time, plus a one CLK cycle enforced hold time.
This assumes that WSETUP and WHOLD are cleared.
Unlike read cycles, t he core does not wait for the SEMI
pipeline to complete the access, so the three CLK
cycle pipeline delay is not incurred on core writes. The
core treats misaligned 32-bit writes as two separate
16-bit wr ites requiring two complete SEMI accesses.
The core write access time for a 32-bit data bus is the
following:
[
ATIME
+ 2 + WSETUP + WHOLD] ×
misaligned
× TCLK
where
misaligned
has the same definition as for reads.
External Accesses by the DMAU, 32-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by a DMAU MMT channel to
asynchrono us memory with the external data bus con-
figured as 32-bit (the ESIZE pin is logic high):
READS—For the DMA U MMT channel s with
SLKA
= 1, 16-bit and 32-bit aligned external asynchro-
nous memory reads (with corresponding writes to inter-
nal TPRAM) occur with a minimum period of the enable
assertion time (as programmed in
ATIME
), plus a one
CLK cycle enforced hold time. This assumes that
RSETUP and RHOLD are cleared. Misaligned 32-bit
reads are not permitted.
The DMAU read ac cess time for a 32-bit data bus with
SLKA
= 1 is the following:
[
ATIME
+ 1 + RSETUP + RHOLD] × TCLK
WRITES—For the DMAU MMT channels with
SLKA
= 1, 16-bit and 32-bit aligned asynchronous
memory writes (with corresponding reads from internal
TPRAM) can occur with a minimum period of the
enable assertion time (as programmed in
ATIME
), plus
a one CLK cycle enforced setup time, plus a one CLK
cycle enf orce d hold time. This a ssumes that WSETUP
and WH OLD are cleared. Misal igned 32-bit writes are
not perm itted.
The DMAU write access time for a 32-bit data bus with
SLKA
= 1 is the following:
[
ATIME
+ 2 + WSETUP + WHOLD] × TCLK
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.2 External Memory, Asynchronous
Interface (continued)
External Accesses by Either Core, 16-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by either core to asynchronous
memory with the external data bus configured as 16-bit
(the ESIZE pin is logic low):
READS—For the cores, 16-bit external asynchronous
memory reads occur with a minimum period of the
enable assertion time (as programmed in
ATIME
), plus
a one CLK cycle enf or ce d hold ti me, p lus th re e CLK
cycles for the SEMI pipeline to complete the core
access. This assumes that RSETUP and RHOLD are
cleared. The SEMI coordinates two separate accesses
for aligned 32-bit reads, adding two CLK cycles to the
above descript ion. The core treats misaligned 32-bit
reads as two sep arate 16-bit reads requiring two com-
plete SEMI accesses.
The core read access time for a 16-bit data bus is the
following:
[
ATIME
+
aligned
+ RSETUP + RHOLD] ×
misaligned
× TCLK
where:
aligned
= 4 and
misaligned
= 1 for 16-bit accesses.
aligned
= 6 and
misaligned
= 1 for 32-bit aligned
accesses.
aligned
= 4 and
misaligned
= 2 for 32-bit misaligned
accesses.
WRITES—For the cores, 16-bit asynchronous memory
writes can occur with a minimum period of the enable
assertion time (as programmed in
ATIME
), plus a one
CLK cycle enforced setup time, plus a one CLK cycle
enforced hold time. This assumes that WSETUP and
WHOLD are cleared. Unlike rea d cycles, the cor e
does not wait for the SEMI pipeline to complete the
access, so the three CLK cycle pipeline delay is not
incurred on core writes. T he SEM I coordinates and
treats aligned 32-bit writes as two separ ate
accesses. The core treats misaligned 32-bit writes as
two separate 16-bit writes requiring two complete SEMI
accesses.
The core write access time for a 16-bit data bus is the
following:
[
ATIME
+ 2 + WSETUP + WHOLD] ×
longword
× TCLK
where:
longword
= 1 for 16-bit accesses.
longword
= 2 for 32-bit accesses.
External Accesses by the DMAU, 16-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by a DMAU MMT channel to
asynchronous memory with the external data bus con-
figured as 16-bit (the ESIZE pin is logic low):
READS— For the DMAU MMT channels with
SLKA
= 1, 16-bit external asynchronous memory reads
(with corresponding writes to internal TPRAM) occur
with a minimum period of the enable assertion time (as
programm ed into
ATIME
) plus a one CLK cycle
enforced hold time. This assumes that RSETUP and
RHOLD are cleared. The SEMI coordinates and treats
aligned 32-bit reads as two separate accesses. M is-
aligned 32-bit reads are not permitted.
The DMAU read ac cess time for a 16-bit data bus with
SLKA
= 1 is the following:
[
ATIME
+ 1 + RSETUP + RHOLD] ×
longword
× TCLK
where:
longword
= 1 for 16-bit accesses.
longword
= 2 for 32-bit aligned accesses.
WRITES—For the DMAU MMT channe ls with
SLKA
= 1, 16-bit asynchronous memory writes (with
corresponding reads from internal TPRAM) can occur
with a minimum period of the enable assertion time (as
programmed in
ATIME
), plus a one CLK cycle enforced
setup time, plus a one CLK cycle enforced hold
time. T his assu mes that WSETUP and WHOLD are
cleared. The SEM I coordin ates and treats aligned
32-bit writes as two separate accesses . Misali gned
32 -b it w rites are not permitted.
The DMAU write access time for a 16-bit data bus with
SLKA
= 1 is the following:
[
ATIME
+ 2 + WSETUP + WHOLD] ×
longword
× TCLK
where
longword
has the same meaning as for DMAU
reads.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.7 Performance (continued)
4.1 4.7 .3 E x te rnal Me m ory, Synchron ous Interfa ce
The primary advantage of synchronous memory is
bandwidth, not latency. The cores’ unpipelined inter-
face to the SEMI cannot take advantage of this band-
width. However, the DMAU has a pipelined interface to
the SEMI and takes advantage of the synchronous
bandwidth . The following sections specify the SEMI
performance f or accesses by a core or by the DMAU to
external synchronous memory.
For sy nchronous operation, the SEMI external output
clock (ECKO) must be programmed as CLK/2, CLK/3,
or CLK/4 (see the ECKOB[1:0] and ECKOA[1:0] fields
of ECON1—Table 61 on page 112).
External Accesses by Either Core, 32-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by either core to synchronous
memory with the external data bus configured as 32-bit
(the ESIZE pin is logic high):
READS—For the cores, 16-bit and 32-bit aligned
external synchronous memory reads occur with a mini-
mum period of eight CLK cycles (four ECKO cycles if
ECKO = CLK/2), plus three CLK cycles for SEMI to
arbitrate the core access, plus one CLK cycle to syn-
chronize ECKO with a rising edge of CLK. The core
treats misaligned 32-bit reads as two separate 16-bit
reads requiring two complete SEMI accesses.
The core read access time for a 32-bit data bus is the
following:
12 ×
misaligned
× TCLK if ECKO = CLK/2
16 ×
misaligned
× TCLK if ECKO = CLK/3
20 ×
misaligned
× TCLK if ECKO = CLK/4
where:
misaligned
= 1 for 16-bit and aligne d 32-bit
accesses.
misali gned = 2 for misaligned 32-bit access es.
WRITES—For the cores, 16-bit and 32-bit aligned syn-
chronous memory writes can occur with a minimum
period of four CLK cycles (two ECK O cycles if
ECKO = CLK /2 ) per transfer. Th e core treats mis-
aligned 32-bit writes as two separate 16-bit writes
requiring two complete SEMI accesses.
The core write access time for a 32-bit data bus is the
following:
4 ×
misaligned
× TCLK if ECKO = CLK/2
6 ×
misaligned
× TCLK if ECKO = CLK/3
8 ×
misaligned
× TCLK if ECKO = CLK/4
where
misaligned
has the same definition as for reads.
External Accesses by the DMAU, 32-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by a DMAU MMT channel to syn-
chrono us memory with the external data bus config-
ured as 32-bit (the ESIZE pin is logic high):
READS—For the DMA U MMT channel s with
SLKA
= 1, 16-bit and 32-bit aligned external synchro-
nous memory reads (with corresponding writes to inter-
nal TPRA M) occur with a minimu m period of four CLK
cycles (two ECKO cycles if ECKO = CLK/2). Mis-
aligned 32-bit reads are not permitted.
The DMAU read ac cess time for a 32-bit data bus with
SLKA
= 1 is four CLK cycles.
4 × TCLK if ECKO = CLK/2
6 × TCLK if ECKO = CLK/3
8 × TCLK if ECKO = CLK/4
WRITES—For the DMAU MMT channels with
SLKA
= 1, 16-bit and 32-b it aligned synchronous mem-
ory writes (with correspo nding reads from internal
TPRAM) can occur with a minimum period of four CLK
cycles (two ECKO cycles if ECKO = CLK/2). Mis-
aligned 32-bit writes are not permitted.
The DMAU write access time for a 32-bit data bus and
SLKA
= 1 is four CLK cycles.
4 × TCLK if ECKO = CLK/2
6 × TCLK if ECKO = CLK/3
8 × TCLK if ECKO = CLK/4
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface
(SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.3 External Memory, Synchronous
Interface (continued)
External Accesses by Either Core, 16-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by either core to synchronous
memory with the external data bus configured as 16-bit
(the ESIZE pin is logic low):
READS—For the cores, 16-bit external synchronous
memory reads occur with a minimum period of eight
CLK cycles (four ECKO cycles if ECKO = CLK/2), plus
th ree CLK cycles fo r SEMI to a rbitr ate the cor e access ,
plus one CLK cycle to synchronize ECKO with a rising
edge of CLK. The SEMI coordinates and treats aligned
32-bit reads as t wo separate accesses. The core
treats misaligned 32-bit reads as two separate 16-bit
reads requiring two complete SEMI accesses.
The core read access time for a 16-bit data bus is the
following:
(12 +
aligned
) ×
misaligned
× TCLK if ECKO = CLK/2
(16 +
aligned
) ×
misaligned
× TCLK if ECKO = CLK/3
(20 +
aligned
) ×
misaligned
× TCLK if ECKO = CLK/4
where:
aligned
= 0 and
misaligned
= 1 for 16-bit accesses.
aligned
= 4 and
misaligned
= 1 for 32-bit aligned
accesses.
aligned
= 0 and
misaligned
= 2 for 32-bit misaligned
accesses.
WRITES—F or the cores, 16-bit synchronous memory
writes can occur with a minimum period of four CLK
cycles (two ECKO cycles if ECKO = CLK/2) per trans-
fer. The SEM I coordinates and trea ts aligned 32-bit
writes as two separate ac cesses. The core treats mis-
aligned 32-bit writes as two separate 16-bit writes
requiring two complete SEMI accesses.
The core write access time for a 16-bit data bus is the
following:
4 ×
longword
× TCLK if ECKO = CLK/2
6 ×
longword
× TCLK if ECKO = CLK/3
8 ×
longword
× TCLK if ECKO = CLK/4
where:
longword
= 1 for 16-bit accesses.
longword
= 2 for any 32-bit accesses.
External Accesses by the DMAU, 16-Bit SEMI Data
Bus
The following describes the SEMI performance for read
and write operations by a DMAU MMT channel to syn-
chrono us memory with the external data bus config-
ured as 16-bit (the ESIZE pin is logic low):
READS— For the DMAU MMT channels with
SLKA
= 1, 16-bit external synchronous me mory reads
(with corresponding writes to internal TPRAM) occur
with a minimum period of four CLK cycles (two ECK O
cycles if ECKO = C LK/2). The SEMI coordinates and
treats aligned 32-bit reads as two separate accesse s.
Misali gned 32-bit reads are not permitted.
The DMAU read ac cess time for a 16-bit data bus with
SLKA
= 1 is the following:
4 ×
longword
× TCLK if ECKO = CLK/2
6 ×
longword
× TCLK if ECKO = CLK/3
8 ×
longword
× TCLK if ECKO = CLK/4
where:
longword
= 1 for 16-bit accesses.
longword
= 2 for any 32-bit aligned a ccesses.
WRITES—For the DMAU MMT channe ls with
SLKA
= 1, 16-bit sy nchronous memory writes (with cor-
responding reads from internal TPRAM) can occur with
a minimum period of four CLK cycles (two ECKO
cycles if ECKO = C LK/2). The SEMI coordinates and
treats aligned 32-bit writes as two separate
accesses . M isaligned 32-bit writes are not permitted .
The DMAU write access time for a 16-bit data bus with
SLKA
= 1 is the following:
4 ×
longword
× TCLK if ECKO = CLK/2
6 ×
longword
× TCLK if ECKO = CLK/3
8 ×
longword
× TCLK if ECKO = CLK/4
where
longword
has the same meaning as for DMAU
reads.
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.4 Summary of Access T imes
Tables 68 through 71 summarize the information in Section 4.14.7.2, beginning on page 129, and Section 4.14.7.3,
beginning on page 131.
Table 68. Access Time Per SEMI Tra nsaction, Asynchr onous Interface, 32-Bit Data Bus
F
Table 69. Access Time Per SEMI Tra nsaction, Asynchr onous Interface, 16-Bit Data Bus
F
Table 70. Access Time Per SEMI Tra nsaction, Sync hronous In terface, 32-Bit Data Bus
F
Table 71. Access Time Per SEMI Tra nsaction, Sync hronous In terface, 16-Bit Data Bus
F
Requester Access Type Reads Writes
Core 16-bit [
ATIME
+ 4 + RSETUP + RHOLD] × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × TCLK
32-bit ali gned
32-bit misaligned [
ATIME
+ 4 + RSETUP + RHOLD] × 2 × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × 2 × TCLK
DMAU,
SLKA
= 1 16-bit [
ATIME
+ 1 + RSETUP + RHOLD] × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × TCLK
32-bit ali gned
Requester Access Type Reads Writes
Core 16-bit [
ATIME
+ 4 + RSETUP + RHOLD] × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × TCLK
32-bit ali gned [
ATIME
+ 6 + RSETUP + RHOLD] × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × 2 × TCLK
32-bit misaligned [
ATIME
+ 4 + RSETUP + RHOLD] × 2 × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × 2 × TCLK
DMAU,
SLKA
= 1 16-bit [
ATIME
+ 1 + RSETUP + RHOLD] × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × TCLK
32-bit ali gned [
ATIME
+ 1 + RSETUP + RHOLD] × 2 × TCLK [
ATIME
+ 2 + WSETUP + WHOLD] × 2 × TCLK
Requester Access Type Reads Writes
CLK/2†
† Value of ECKO, depending on t he prog ram ming of th e EC KOB[ 1:0] and ECKOA[1:0] fie l ds of ECON1—Table 61 on page 112.
CLK/3†CLK/4†CLK/2†CLK/3†CLK/4†
Core 16-bit 12 × TCLK 16 × TCLK 20 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK
32-bit ali gned
32-bit misaligned 24 × TCLK 32 × TCLK 40 × TCLK 8 × TCLK 16 × TCLK 32 × TCLK
DMAU,
SLKA
= 1 16-bit 4 × TCLK 6 × TCLK 8 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK
32-bit ali gned
Requester Access Type Reads Writes
CLK/2†
† Value of ECKO, depending on t he prog ram ming of th e EC KOB[ 1:0] and ECKOA[1:0] fie l ds of ECON1—Table 61 on page 112.
CLK/3†CLK/4†CLK/2†CLK/3†CLK/4†
Core 16-bit 12 × TCLK 16 × TCLK 20 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK
32-bit ali gned 16 × TCLK 20 × TCLK 24 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK
32-bit misaligned 24 × TCLK 32 × TCLK 40 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK
DMAU,
SLKA
= 1 16-bit 4 × TCLK 6 × TCLK 8 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK
32-bit ali gned 8 × TCLK 12 × TCLK 16 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK
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4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.4 Summary of Access Times (continued)
Tables 72 and 73 show example access times under various conditions, including DMAU accesses with SLKA = 0.
These access times are derived from actual measureme nts. For the asynchronous ac ces s times, it is assumed
that the programmed enab le assertion time is one (
ATIME
= 1) and that RSETUP = RHOLD = WS E TUP =
WHOLD = 0. The actual value of these fields is application-dependent. For the synchronous access times, it is
assumed that ECKO is programmed as CLK/2.
Table 72. Example Average Access Time Per SEMI Transaction, 32-Bit Data Bus
F
Table 73. Example Average Access Time Per SEMI Transaction, 16-Bit Data Bus
4.14.8 Priority
SEMI prioritizes the req uests from both cores and the DMAU in the followin g order:
1. CORE0 program (X) and data (Y) requests have the highest priority. If CORE0 requires a simultaneous X and Y
access, X is performed first, then Y.
2. CORE1 program (X) and data (Y) requests have the second-highest priority. If CORE1 r equires a simultaneous
X and Y access, X is per formed fi rst, then Y.
3. DM AU data reques ts have the lowest priority.
Requester Access Type Asynchronous Synchronous (ECKO = CLK/2)
Reads Writes Reads Writes
Core 16-bit 5 × TCLK 3 × TCLK 12 × TCLK 4 × TCLK
32-bit ali g n ed
32-bit misaligned 10 × TCLK 6 × TCLK 24 × TCLK 8 × TCLK
DMAU,
SLKA
= 1 16-bit 2 × TCLK 3 × TCLK 4 × TCLK 4 × TCLK
32-bit ali g n ed
DMAU,
SLKA
= 0 16-bit 9 × TCLK 5 × TCLK 14 × TCLK 5 × TCLK
32-bit ali g n ed
Requester Access Type Asynchronous Synchronous (ECKO = CLK/2)
Reads Writes Reads Writes
Core 16-bit 5 × TCLK 3 × TCLK 12 × TCLK 4 × TCLK
32-bit ali g n ed 7 × TCLK 6 × TCLK 16 × TCLK 8 × TCLK
32-bit misaligned 10 × TCLK 6 × TCLK 24 × TCLK 8 × TCLK
DMAU,
SLKA
= 1 16-bit 2 × TCLK 3 × TCLK 4 × TCLK 4 × TCLK
32-bit ali g n ed 4 × TCLK 6 × TCLK 8 × TCLK 8 × TCLK
DMAU,
SLKA
= 0 16-bit 9 × TCLK 5 × TCLK 14 × TCLK 5 × TCLK
32-bit aligned 11 × TCLK 6 × TCLK 18 × TCLK 8 × TCLK
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU)
The parallel interfa ce unit (PIU) is the DSP16411 inter-
face to a host microprocessor or microcontroller. This
interface is a 16-bit parallel port that is passive only,
i.e., the DS P16411 is the slave to the host for all trans -
actions. The PIU is both
Intel
®
and
Motorola
® memo ry
bus compatible and pr ovides select logic for a shared-
bus interface. As an additional feature, the host can
access the entire DSP16411 mem ory (internal and
external) through the PIU.
The PIU control and data registers are memory-
mapped into the DSP16411 shared internal I/O m em -
ory component (Section 4.5.7 on page 43). The host
can access all of the PIU data and control registers via
external pins. Both cores and the DMAU can access
these registers directly via the system bus. The DMAU
can directly access the PIU data registers PDI and
PDO.
The DMAU supports the PIU via a dedicated bypass
channel. Unli ke the DMAU SWT and MMT channels,
the PIU bypass channel must be configured by the host
via commands over the PIU address pins, PADD[3:0].
The PIU provides three interru pt signals to the cores.
These interrupts indicate a host-generat ed request or
the completion of an input or output transaction.
The PIU provides the following features:
A high-speed, 16-bit parallel host interface
Compatibility with industry-standard microproce ssor
buses
Chip select logi c for sh ar ed bus system arch it e ctu res
Interrupt output pin for DSP16411-to-host interrupt
generation
Dedicated host and core scratch registers for conve-
nient messaging
Supported by DMAU to access all memory
4.15.1 Registers
As su mma r ize d in Table 74, the PIU contains seven
mem ory-map ped registers that are accessible by the
host and the cores. The host accesses these registers
by issuing commands through the PIU. Please refer to
Section 4.15.5 on page 147. All PIU registers are
accessed by the host as 16-bit quantities. The cores
access the PIU registers as 32-bit mem ory-ma pped
locations residing in the shared internal I/O memory
component (Secti on 4.5.7 on page 43). The PIU regis-
ters are aligned to even addresses and occ upy
addresses 0x41000 to 0x4100A, as noted in Table 74.
Sect ion 6. 2.2 on page 231 provides an overview of
mem ory-map ped registers.
Table 74. PIU Registers
Register
Name Address Size
(Host) Size
(Cores) R/W
(Host) R/W
(Cores) Type†Description
PCON 0x41000 16 32 R/W‡R/W‡c & s PIU cont rol and sta tus. The appl ication mu st choose
one of the cor es to write PCON.
PDI§0x41008 16 32 W R data PIU data in from host.
PDO 0x4100A 16 32 R R/W dat a PIU dat a out to host. For a typical appli cation, the
DMAU writes PDO, but either core can also write
PDO. The applic ation must choo se one of these enti-
ties to write PDO.
PAH 0x41004
(PA)16 32 R/W R/W data PIU address for host access to DSP16411 memory.
The appli cati on must choose ei ther t he h ost or on e of
th e c or e s to write this re g is te r.
PAL 16 R/W
DSCRATCH 0x41002 16 32 R R/W data DSP scratch. The application must choose one of
t h e cor es to wr i t e DSCRATCH.
HSCRATCH 0x41006 16 32 W R data Host scratch.
† c & s means control and status.
‡ All bits of PCON are readable by both the host and the cores. Not all bits are writable—see Tab le 7 5 on pa ge 1 36 for details.
§PDI is double-buffered (unlike the DSP16XX PHIF PDX re gister). Therefore, a ho st write to PDI can be issued (but not completed) befor e a
previous ho st writ e to PDI is c omplet ed.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.1 Reg ist ers (continued)
The PCON register is the PIU status and control register. This register reflects the state of the PIU flags (PIBF and
POBE) and provides a mechanism f or the host and a core to interrupt each other or reset the PIU. The bit fields of
PCON are detailed in Table 75. For eac h bit field, the table defines what ac tions can be per formed by the host or a
core: read, write, clear to zero, or set to one. All the bit fields of PCON can be read by the host and by the cores. If
the PCON register is read, only the lower 7 bits contain valid information. The upper bits are undefined. If the host
or a c or e wr ites PCON, it must write the upper 25 bits with zero.
Table 75. PCO N (PIU Control) Register
The memory address for this register is 0x41000. The application must ensure that both cores do not write PCON
at the same time.
31—7 6 5 4 3 2 1 0
Reserved DRESET HRESET HINT§PINT§PREADY PIBF POBE
Bit Field Name Value Description R/W
(Cores) R/W
(Host) Reset
Value†
† Dev ic e res et or PIU res et.
31—7 Reserved — — Reserv ed—write with zero; undef ined on read . — — —
6 DRESET DSP
Reset 0 Always read as zero. Wr ite with zer o—no effect. S et/
Read —0
1 The program r unning in a core rese ts‡ the PIU by writ ing a 1
to thi s field. The PIU r eset clears this fi eld autom ati cally.
‡ The purpose of the PIU reset is to reinitialize all PIU sequencers and flags to their reset state.
5 HRESET Host
Reset 0Always read as zero. Wr ite with zer o— no eff ect. — Set/
Read 0
1 The hos t re se t s ‡ the PIU by writ ing a one to this field. The
PIU reset clears this field autom ati cally.
4HINT
§
§ If the host and a cor e attempt to set/clea r this bit simu ltaneo usly, the PI U clears the bit.
Interrupt
from Host 0Read as zero—no outstanding interrupt from host.
Write with zero—no effect. Clear/
Read Set/
Read 0
1 If this field is initially cleared and the host sets it, the PIU
asserts the PHINT interrupt. The interrupted core’s service
rout ine m ust cl ear th is fi eld af ter s ervic ing the PHINT r equest
to allow the host to request a subsequent interrupt. The ser-
vice routine clears the field by writing one to it.
3PINT
§PIU
Interrupt
to Host
0Read as zero—no outstanding interrupt to host.
Write with zero—no effect. Set/
Read Clear/
Read 0
1 If this field is initially cleared and a program running in either
core sets it, the PIU asserts t he PINT pin to interrupt the
host. The host mus t cl ear this fi eld after servici ng the PINT
request to all ow a core to request a subseque nt interrupt. It
clears the fi eld by writi ng 1 to i t.
2PREADY PIU
Ready — This bit is th e logi cal OR of the PIBF and POBE flags. (It is
not the same as the PRDY pin.) If set, the PIU is not ready. Read Read 1
1 P IBF P IU In p ut
Buffer
Full
0PDI contains data that has al ready been re ad by one of the
cores. The host may write PDI with new data. Read Read 0
1PDI contains data from a prior host write re quest. To avoid
loss of data, t he host must not wri te PDI.
0 POBE PIU Output
Buffer
Empty
0PDO contains new data. To avoid loss of data, the cores
mus t not write PDO.Read Read 1
1PDO contains data that has already been r ead by the host.
The co res m a y write PDO with new data.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.1 Reg ist ers (continued)
The PDI and PDO registers (Table 76 and Table 77) are the 16-bit PIU input and output data registers. PDI con-
tains data written by the host at the conclusion of a valid host write cycle. PDO contains data written by a core or
the DMAU that is driven onto the PIU data bus during a valid host read cycle.
Table 76. PDI (PIU Data In) Register
Table 77. PDO (PIU Data Out) Register
The DSCRATCH and HSCRATCH registers (Table 79 and Table 78) are the DSP and host scratch registers that
can be used to pass messaging data between a core and the host. After a core writes 16-bit data to DSCRATCH,
the host can read this data by issuing a read_dscratch com man d. Conv ersel y, the host can write 16-bit data to
HSCRATCH by issuing a write_hscratch command. S ee S ection 4.15. 5 on page 147 for details on host com-
mands.
Table 78. HSCRATCH (Host Scratch) Register
Table 79. DSCRATCH (DSP Scratch) Register
The memory address for this register is 0x41008.
31—16 15—0
Reserved PIU Input Data
Bit Field Description R/W (Cores) R/W (Host) R eset Value
31—16 Reserved Reserved—read as zero. R W 0
15—0 PIU Input Data PIU data in from host. R W 0
The memory address for this register is 0x4100A . F or a typical application, th e DMAU writes PDO, but the cores
can also write PDO. The application must ensure that these entities do not write PDO at the same time.
31—16 15—0
Reserved PIU Output Data
Bit Field Description R/W (Cores) R/W (Host) R eset Value
31—16 Reserved Reserved—write with zero. R/W R 0
15—0 PI U Output Data PIU data out to host. R/W R 0
The memory address for this register is 0x41006.
31—16 15—0
Reserved Host Scr atch
Bit Field Description R/W (Cores) R/W (Host) R eset Value
31—16 Reserved Reserved—read as zero. R W 0
15—0 Ho st Scratch Host scrat ch data to DSP16411. R W 0
The memory address for this register is 0x41002. The appl ication must choose one of the cores to write
DSCRATCH.31—16 15—0
Reserved DSP Scrat ch
Bit Field Description R/W (Cores) R/W (Host) R eset Value
31—16 Reserved Reserved—write with zero. R/W R 0
15—0 DSP Scratch DSP scratch data to host. R/W R 0
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.1 Reg ist ers (continued)
The PA regist er (Table 80) provides the DSP16411 memory address for any host accesses to DSP16411 memory.
The host m ust access this register as two 16-bit quantities: the high h alf (PAH) and the low half (PAL). A core
accesses PA as a double-word (32-bit) location at address 0x41004. See Figure 37 for details. As shown in
Table 80, the ADD[19:0] field (PA[19:0]) contains the memory address to be accessed within the selected memory
component determined by the CMP[2:0] field (PA[22:2 0]) . The ESEG[ 3:0 ] fi eld ( PA[26:23]) determines the external
segment extension for external memory accesses through the SEMI. The SEMI drives the v alue in the ESEG[3:0]
field onto the ESEG[3:0] pins at the sam e time that it asserts the appropriate enable pin (ERAMN, EION, or
EROM N) and drives the e xternal mem ory address onto EA[18:0].
Table 80. PA (Parallel A ddr ess) Register
32-Bit PA Register Host and DSP Access
Figure 37. 32-Bit PA Register Host and Core Access
The memory address for this register is 0x41004. The application must choose either the host or one of the cores
to write this register.
31—27 26—23 22—20 19—0
Reserved ESEG[3:0] CMP[2:0] ADD[19:0]
Bit DSP
Access Host
Access Field Value Definition R/W Reset
Value
31—27 PA†PAH[15:0]‡Reserved 0 Reserved—write with zero. R/W 0
26—23 ESEG[3:0] 0x0
to
0xF
External memor y address extension . The value
of this field is placed directly on the ESEG[3:0]
pins for PIU accesses to external memor y§.
R/W 0x0
22—20 CMP[2:0] 000 The selected memory componen t is TPRAM0. R/W 000
001 The selected mem ory componen t is TPRAM1.
01X Reserved.
100 The selected memory componen t is ERAM††,
EIO, or inter nal I/O.
101 Reserved.
11X Reserved.
19—16 ADD[19:0] 0x00000
to
0xFFFFF
The address within the select ed m em ory space. R/W 0x00000
15—0 PAL[15:0]‡‡
† Mem ory-mapped to do ubl e wor d at add ress 0x4100 4.
‡ Write with write_pah command; read with read_pah command.
§ This field is valid only for external memory accesses (CMP[2:0] = 100) and is ignored for in ternal memory accesses.
†† If the WERO M field (ECON1[11]—Table 61 on page 112) is set, EROM is selected in place of ERAM.
‡‡ Writ e wi th write_pal command; read with read_pal comm and.
ADD[15:0]ADD[19:16]MEM[2:0]ESEG[3:0]Reserved 19—022—2026—2331—27
HOST ACCESS ES PA[15:0] AS PAL[15:0] VIAHOST ACCESSES PA[31:16] AS PAH[15: 0] VIA
CORES ACCESS PA[31:0] AS DOUBLE-WORD MEMORY-MAPPED REGISTER AT LOCATION 0x41004
15 015 0
THE read_pah AND write_pah COMMANDS THE read_pal AND write_pal COMMANDS
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.1 Reg ist ers (continued)
The host ac ce sse s PAH and PAL by executing the read_pah, read_pal, write_pah, and write_pal comma nds.
After certain host commands, the PIU autoincrements the value in PA. See Section 4.15.5 on page 147 for details
on host commands . Unli ke the DSP1620 and DSP16210 MIOU, the PIU increments the value in the PA register
linearly and does not wrap it.
4.15.2 Hardware Interface
The host interface to the PIU consists of 29 pins, as summarized in Table 81. The remainder of this section
describes these pin s in detail.
Table 81. PIU External Interface
.Function Pin Type Description
Address and
Data PD[ 15:0] I/ O/Z 16-bit bidirectional, parallel dat a bus. 3-stated if PCSN = 1.
Note: If BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits con-
nected to PD[15:0] are act ivated. I f BHPDIS = 0 and neithe r the PIU n or an
external device is dri ving PD[15:0], the bus hol d cir cuits hold PD[15:0] at their
previous valid logic level. This eliminates the need for external pull-up or pull-
down resistors on PD[15:0]. See Section 10.1 on page 268 for details.
PADD[3:0]†I PIU 4-bit address and co ntrol input.
Note: If BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits con-
nected to PADD[3:0] are activated. If BHPDIS = 0 and an external device is not
driving PADD[3:0] , the bus hold circuit s hold PADD[3:0] at their previ ous valid
logi c leve l. Th is elimi nates the nee d f or ext er nal pul l-u p or pu ll- down r esist ors o n
PADD[3:0] . See Section 10.1 on page 268 for details.
Enables and
Strobes PODS‡I PI U output data strobe.
Intel
host: Connect to the host activ e-l ow read data strobe.
Motorola
host: Connect to the host data strobe.
PIDS‡I PIU input data strobe.
Intel
host: Connect to the host activ e-l ow write data st robe.
Motorola
host: Connect to logic 0 to program an acti ve-hi gh data strobe. Connec t to
logic 1 to program an active-low data strobe.
PRWN‡I PIU read/wri te not .
Intel
host: Connect to the host activ e-l ow host write strobe.
Motorola
host: Connect to host RWN strobe.
PCSN‡IPIU chi p select —active-l ow.
Flags, Interrupt,
and Ready POBE O PIU output buf fer empty flag.
PIBF O PIU i nput buffer full fl ag.
PINT O PIU interrupt (inter rupt signal to host).
PRDY O PIU ready.
Indicates the status of the c urrent host read operation or prev ious host write oper ati on.
The PRDYMD pin determines the logic level of this pin.
PRDYMD†I PIU ready pin mode.
0: PRDY pin is activ e-l ow (PRDY = 0 indicates the PIU is ready).
1: PRDY pin is activ e-high (PRDY = 1 indicates the PIU is ready).
† If the system application does not use thes e pins, they must be tied low.
‡ If the system application does not use thes e pins, they must be tied high.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.2 Hardware Interface (continued)
4.15.2.1 Enables and Strobes
The PIU provides a chip select input pin (PCSN) that allows the host to connect t o multiple DSP16411 or ot her
devices. The function of the enable and strobe pins (PODS, PIDS, and PRWN) is based on whether the host type
is
Intel
or
Motorola
. In order to support both types of hosts, the PIU generates a negative-assertion internal strobe
PSTRN that is a logical combi nation of PCSN, PODS, and PIDS as follows:
PSTRN = PCSN |(PIDS ^ PODS)
The PIU initiates all transactions on the falling edge of PSTRN and completes all transactions on the rising edge of
PSTRN.
Table 82. Enable and Strobe Pin s
Pin Name Value Description
PCSN
(input) PIU Chip
Select 0 The host is selecting this devi ce for PIU trans fers.
1 The host is not sel ecting this device for PIU transfer s and the PIU 3- states PD[15:0] and
ignores any acti vity on PIDS, PODS, and PRWN.
PODS
(input) PIU Out put
Data Strobe —
For an
Intel
host, PO DS functions a s an output data s trobe and must be co nnected to the
host active-low read data strobe. The host initiates a read transaction by asserting (low)
both PCSN and PODS. The host conclud es a read t ransact ion by deass ert ing (high)
either PCSN or PODS.
For a
Motorola
host, PO DS functions as a data strobe and m ust be connected t o the ho st
data str obe. The state of t he PIDS pin determine s the active level of PODS. If PIDS = 0,
PODS is an act ive-high data strobe. If PIDS = 1, PO DS is an active-low data s trobe. The
host initi ates a r ead transaction by asser ti ng both PCSN and PODS. The host concludes
a read transaction by deasserting either PCSN or PODS.
PIDS
(input) PIU Input Data
Strobe —
For an
Intel
host, PIDS f unctions as an input data strobe and m ust be connected to the
host acti ve-low write data st robe. The host initiates a write trans actio n by asserting (low)
both PCSN and PIDS. The host concludes a writ e transaction by deasserting (high)
either PCSN or PIDS.
For a
Motorola
host, the state of PIDS det ermines the ac ti ve level of the hos t dat a strobe,
PODS.
PRWN
(input) PIU
Read/Write
Not Strobe
— The host drives PRWN high during host reads and lo w duri ng host writes. PR W N must be
stable for the entire access (while PCSN and the appropriate data strobes are asserted).
For an
Intel
host, PR W N and PIDS ar e connec ted to the host active-low write data s tr obe.
For a
Motorola
host, PRWN funct ions as an act ive read/write strobe and must be con-
nected to t he host RWN output.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.2 Hardware Interface (continued)
4.15.2.2 Address and Data Pins
The PIU provides a 16-bit external data bus (PD[15:0]). It provides a 4-bit input address bus (PADD[3:0]) that the
host uses to select be tween PIU registers and to issue PIU comm ands.
Table 83. Address and Data Pins
Pin Name Description
PD[15:0]
(input/
output)
Data Bus
If t he host issues a read command, the PIU drive s the dat a contai ned in PDO onto PD[15:0].
If t he h ost issu es a write command, it dri ves the data ont o PD[15:0] and the PI U latches th e data
into PDI.
If t he PIU is not sel ected by the host (PCSN is high), the PIU 3-states PD[15:0].
Note: I f BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits connected to
PD[15:0] are activated. If BHPDIS = 0 and neither the PIU nor an external device is driving
PD[15:0], the bus hold circ uits hold PD[1 5:0] at thei r previous valid logic level . This eli mi-
nates the need for external pul l-up or pull-down resistors on PD[15:0]. See Section 10.1 on
page 268 for details.
PADD[3:0]
(input) Addres s Bus A 4-bit address input dr iven by the host to select bet ween vari ous PIU registers and to issue PIU
commands. See Section 4.15.5 on page 147 for details.
Note: I f BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits connected to
PADD[3:0] are activa ted. I f BHPDIS = 0 and an externa l devic e is not d riving PADD[3:0], the
bus hold ci rcui ts hol d PADD[3:0] at the ir previous valid logi c level. This elimi nates the need
for ext ernal pull -up or pull- down resistors on PADD[3:0] . See Section 10.1 on page 268 fo r
details.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.2 Hardware Interface (continued)
4.15.2.3 Flags, Interrupt, and Ready Pins
The PIU provides buffer statu s flag pins, an interrupt to the host, and a host ready and mode pin pair.
Table 84. Fl ags, Interrupt, and Ready Pins
Pin Name Value Description
POBE†
(output) PIU Output
Buffer Empty 0PDO contains data read y for the host to read.
1PDO is empty, i.e., there is no data for the host to read.
PIBF‡
(output) PIU Input
Buffer Full 0PDI is empty, so the host can safely write anot her word into PDI.
1PDI is full wit h the previous word that was writ ten by the host. If the host
writes PDI, the previous data is overwritten.
PINT
(output) PIU Interr upt
Host 0 A core has not reque sted an int errupt to the host.
1 A core has requested an inter rupt to the host by setti ng the PINT fiel d
(PCON[3]—Table 75 on page 136). The host ackno w ledges the interrupt
by writing a 1 to the PINT field, clear ing it.
PRDYMD
(input) PIU Ready
Mode 0 PRDY is active-low.
1 PRDY is active-high.
PRDY§
(output) PIU Ready If
PRDYMD = 0 0
For a host data read operati on, t he rea d data in PDO and on PD[15:0] i s
vali d and the host can latch the data and conclude the read cyc le††.
For a host write operation, the previous write operation has been pro-
cessed by the DSP16411 (PDI is em pty) and the host can conclude the
current write cycle††, i .e. , can write PDI with new data.
1
For a host data read oper ation, the DSP16411 is processing the curr ent
read opera tion (PDO is stil l empty) and t he host must ext end the curr ent
access until the PIU drives PRDY low before concluding the read
cycle††.
For a host write operation, the DSP16411 is process ing the previous
write operation (PDI is sti ll full) and the host must extend the cu rrent
access until the PIU drives PRDY low bef ore concluding the wri te
cycle††.
If
PRDYMD = 1 0
For a host data read oper ation, the DSP16411 is processing the curr ent
read opera tion (PDO is stil l empty) and t he host must ext end the curr ent
access until the PIU drives PRDY hig h before concluding the read
cycle††.
For a host write operation, the DSP16411 is process ing the previous
write operation (PDI is sti ll full) and the host must extend the cu rrent
access until the PIU drives PRDY high before conc luding the write
cycle††.
1
For a host data read operati on, t he rea d data in PDO and on PD[15:0] i s
vali d and the host can latch the data and conclude the read cyc le††.
For a host write operation, the previous write operation has been pro-
cessed by the DSP16411 (PDI is em pty) and the host can conclude the
current write cycle††, i .e. , can write PDI with new data.
† The stat e of this pi n i s also re adable by the core s in the POB E field (PCON[0]—see Table 75 on page 13 6 ).
‡ The stat e of this pi n i s also re adable by the core s in the PIBF f i el d (PCON[1]—see Table 75 on pag e 136).
§ For the descriptions in this table to be valid, the PIU must be activated, i.e., PSTRN must be asserted. See Section 4.15.2.1 on page 140 for a defini-
tion of PSTRN.
†† See descri ption of PI DS and PO DS in Ta bl e 82 on pa ge 140.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.3 Host Data Read and Write Cycles
This section describes typical host read and write
cycles of data for both
Intel
and
Motorola
hosts.
Figure 38 on page 144 is a functional timing diagram of
a data read and a data writ e cycle for both an
Intel
and
a
Motorola
host. T he addres s that the host applies to
PADD[3:0] during the cycle determines the transaction
type, i.e., de termines the host comm and. S ee
Section 4.15. 5 on page 147 for details on host com-
mands.
The following sequence c orresponds to the
Intel
data
read cycle shown in Figure 38:
1. The host drives a valid address onto PADD[3:0].
The host must hold PIDS high for the entire duration
of the access.
2. The host ini ti a tes th e cycl e by assert i n g (low) PCSN
and PODS.
3. When data becomes available in PDO, the PIU
drives the data onto PD[15:0].
4. To notify the host that the data in PDO and on
PD[15:0] is valid, the PIU asserts PRDY and deas-
serts POBE. If the data in PDO is not yet valid, the
PIU continues deasserting PRDY and the host must
wait unt il th e PIU assert s PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
6. The PIU 3-states PD[15:0].
The following sequence c orresponds to the
Intel
data
write cycle shown in Figure 38:
1. The host drives a valid address onto PADD[3:0].
The host must hold PODS high for the entire dura-
tion of the access.
2. The host i nitiat es the cycl e by assert ing (low) PCSN,
PI DS, a n d PRWN.
3. The host d rives data onto PD[15: 0].
4. If PDI is empty, the PIU notifies the host by asserting
PRDY and deasserting PIBF. If PDI is still full from a
previous host write, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PIDS, causing the PIU to latch the data from
PD[15:0] into PDI.
6. The host 3-states PD[15:0].
The following sequence corresponds to the
Motorola
data read cycl e shown in Figure 38. In the figure and in
the timing sequences described below, it is assumed
that PIDS is tied high, selecting an active-low data
strobe (POD S).
1. T he hos t drives a valid address onto PADD[3:0].
The host m ust hold PRWN high for the duration of
the access.
2. T he host initiates the cycle by asserting PCSN and
POD S (low).
3. When dat a becomes availa ble in PDO, the PIU
drives the data onto PD [15:0].
4. To notify the host that th e data in PDO and on
PD[15: 0] is valid, the PIU asserts PRD Y and deas-
serts PO BE. If the data in PDO is not yet valid, the
PIU continues deass erting PRDY and the host must
wait until the PIU asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
6. T he PIU 3-states PD[15:0].
The following sequence corresponds to the
Motorola
data write cycle shown in Figure 38. In the figure and
in the timing sequences described below , it is assumed
that PIDS is tied high, selecting an active-low data
strobe (POD S).
1. The host drives a valid address onto PADD[3:0] and
drives PRWN low.
2. T he host initiates the cycle by asserting PCSN and
POD S (low).
3. The host drives data onto PD[15:0].
4. If PDI is empty , the PIU notifies the host by asserting
PRDY and deasserting PIBF. If PDI is still full from a
previous host wr ite, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS, causing the PIU to latch the data from
PD[ 15:0] into PDI.
6. The host 3-states PD[15:0] .
Note: Once the host initiates a data read or data write
transacti on, it must complete it properly as
described above. If the host concludes the
transaction before the PIU asserts PRDY, the
results are undefined and the PIU must be
reset. In this case, the h o st can r e se t the PIU by
setting the HRESET field (PCON[5]—Tab le 75
on page 136), or a c ore can re se t th e P IU by set -
ting the DRESET field (PCON[6]).
Advance Data Sheet
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.3 Host Data Read and Write Cycles (continued)
PIU Functional Timing for a Data Read and Write Op eration
Figure 38. PIU Functional Timing for a Data Read and Write Operation
PRDY§
12 3456 123
PIBF
456
DATA READ DATA WRITE
† For the
Motorola
inter face, it is assumed that PIDS is ti ed high, s electi ng an activ e-low data str obe (PODS).
‡ PSTRN is an inter nal signal that is a logi cal combination o f PCSN, PIDS, and PODS as follows: PSTRN = PCSN |(PIDS ^ PODS).
§ It is assumed that the PR DYMD input pin is logic lo w, ca using PRDY to be active -low.
POBE
PADD[3:0]
PD[15:0] DSP
DATA HOST
DATA
PSTRN‡
PODS
PIDS/
PCSN
ADDRESS ADDRESS
PRWN
PODS†
PRWN
INTEL
INTERFACE
MOTOROLA
INTERFACE
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.4 Host Register Read and Write Cycles
This section describes typical host read and write
cycles of PIU registers for both
Intel
and
Motorola
hosts. Figure 39 on page 146 is a f unctional timing dia-
gram of a register read and a register write cycle for
both an
Intel
and a
Motorola
host. Th e addres s that
the host applies to PADD[3:0] during the cycle deter-
mines how the host accesses the register, i.e., deter-
mines the host command. See Sec tion 4.15.5 on
page 147 for details on host commands.
The following sequence c orresponds to the
Intel
host
read of the PAH, PAL, PCON, o r DSCRATCH regist er
shown in Figure 39:
1. The host drives a valid address onto PADD[3:0].
The host must hold PIDS high for the entire duration
of the access.
2. The host ini ti a tes th e cycl e by assert i n g (low) PCSN
and PODS.
3. The PIU drives the contents of the register onto
PD[15:0].
4. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
5. The PIU 3-states PD[15:0].
The following sequence c orresponds to the
Intel
host
write of the PAH, PAL, PCON, or HSCRATCH register
shown in Figure 39. The PIU uses the PDI register to
temporarily hold the write data.
1. The host drives a valid address onto PADD[3:0].
The host must hold PODS high for the entire dura-
tion of the access.
2. The host i nitiat es the cycl e by assert ing (low) PCSN,
PI DS, a n d PRWN.
3. The host d rives data onto PD[15: 0].
4. If PDI is empty, the PIU notifies the host by asserting
PRDY and deasserting PIBF. If PDI is still full from a
previous host write, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PIDS, causing the PIU to latch the data from
PD[15:0] into PDI. The PIU transfers the data in PDI
into PAH, PAL, PCON, or HSCRATCH.
6. The host 3-states PD[15:0].
The following sequence corresponds to the
Motorola
read of the PAH, PAL, PCON, or DSCRATCH re g i ster
shown in Figure 39. In the figure and in the timing
sequences described below, it i s as sumed that PIDS is
tied high, selecting an active-low data strobe (PODS).
1. The host drives a val id address onto PADD[3:0].
The host m ust hold PRWN high for the duration of
the access.
2. The hos t initiates the cycle by asserting (low) PCSN
and PODS.
3. The PIU drives the data in the register onto
PD[15:0].
4. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
5. T he PIU 3-states PD[15:0].
The following sequence corresponds to the
Motorola
write of the PAH, PAL, PCON, or DSCRATCH register
shown in Figure 39. In the figure and in the timing
sequences described below, it i s as sumed that PIDS is
tied high, selecting an active-low data strobe (PODS).
1. The host drives a valid address onto PADD[3:0] and
drives PRWN low.
2. The hos t initiates the cycle by asserting (low) PCSN
and PODS.
3. The host drives data onto PD[15:0].
4. If PDI is empty , the PIU notifies the host by asserting
PRDY and deasserting PIBF. If PDI is still full from a
previous host wr ite, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS, causing the PIU to latch the data from
PD[15:0] into PDI. The PIU transfers the data in PDI
into PAH, PAL, PCON, or HSCRATCH.
6. The host 3-states PD[15:0] .
Note: Once the host initiates a register write transac-
tion, it must complete it properly as described
above . I f the host con cludes the transactio n
before the PIU asserts PRDY, the results are
undefi ned and the PIU must be reset. In this
case, the host can reset the PIU by setting the
HRESET field (PCON[5]—Table 75 on
page 136) or a core can reset the PIU by setting
the DRESET field (PCON[6]).
Advance Data Sheet
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.4 Host Register Read and Write Cycles (continued)
PIU Functional Timing for a Register Read and Write Operation
Figure 39. PIU Functional Timing for a Register Read and Write Operation
PRDY§
12 3 45 123
PIBF
456
REGISTER READ REGISTER WRITE
† For the
Motorola
inter face, it is assumed that PIDS is ti ed high, s electi ng an activ e-low data str obe (PODS).
‡ PSTRN is an inter nal signal that is a logi cal combination o f PCSN, PIDS, and PODS as follows: PSTRN = PCSN |(PIDS ^ PODS).
§ It is assumed that the PR DYMD input pin is logic lo w, ca using PRDY to be active -low.
PADD[3:0]
PD[15:0] DSP
DATA HOST
DATA
PSTRN‡
PODS
PIDS/
PCSN
ADDRESS ADDRESS
PRWN
PODS†
PRWN
INTEL
INTERFACE
MOTOROLA
INTERFACE
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.5 Host Commands
The ho st comm ands ar e su mmar ized in Table 85. A host command is a host read or wri te cycle with the PADD[3:0]
pins configured to select one of sever al commands. Each command has a corresponding mnemonic as defined in
the table. These mnemonics are defined to simplify the explanations that follow and are also used by the
DSP16411 mo del in the
LUxWORKS
™ debugger. These com ma nds are detailed in the remainder of this se ction.
Table 85. Summary of Host Comma nds
Command
Type Pins Command
Mnemonic Description
(PIU/DMAU Response) Flow
Control
PRWN PADD[3:0]
Memory Write 0 00 00 write_pdi Write DSP16411 memory location pointed t o by PA with
data on PD[15:0]. Yes
0 0001 write_pdi++ 1. Write DSP16411 memory location pointed to by PA
with data on PD[15:0].
2. Increment PA by one.
PIU Register Write 0 100X write_pah W rite high hal f of PA via PDI with data from PD[15:0]. Yes
0 101X write_pal Write low half of PA via PDI with data from PD[15:0].
0 110X write_pcon Write PCON via PDI with data from PD[15:0].
0 111X write_hscratch Write HSCRATCH vi a PDI with data from PD[15:0].
Memory Read 1 0000 read_pdo Read DSP164 11 memory locat ion poi nted t o by PA, and
place the contents onto PD[15:0]. Yes
1 0001 read_pdo++ 1. Read DSP16411 memory locat ion pointed to by PA,
and place the contents onto PD[15:0].
2. Increment PA by one.
1 0010 — Reserved. —
1 0011 rdpf_pdo++ Perf orm a memory re ad operat ion with prefetch . This is
the highest-performance command for host reads of
contigu ous blocks of me mo ry.
See Section 4.15.5.3 on page 149 for details.
Yes
1 0100 load_pdo 1. Read DSP16411 memory location pointed to by PA,
and plac e th e con ten ts i n PDO.
2. Follow with unld_pdo.
No
1 0101 load_pdo++ 1. Re ad DSP16411 memory locati on pointed to by PA,
and plac e th e con ten ts i n PDO.
2. Increment PA by one.
3. Follow with unld_pdo.
1 0110 unld_pdo Pl ace the contents of PDO onto PD[15: 0]. Yes
PIU Register Read 1 100X read_pah Place the contents of the hi gh half of PA onto PD[15:0]. No
1 101X read_pal Place the contents of the low half of PA onto PD[15:0].
1 110X read_pcon Place the content s of PCON onto PD[15: 0].
1 111X read_dscratch Plac e the cont ents of DSCRATCH onto PD[15:0] .
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.5 Host Commands (continued)
The host issues commands to the PIU through the PIU’s external interface. Ho st comm ands allow the host to
access all DSP16411 internal and external memory locations. Host comm ands can also read or write PIU scratch
and control/status registers. All commands are executed by a combination of actions performed by the PIU and by
the DMAU bypass channel.
A host command consist s of four parts:
1. Read v s. write operation is determ ined by the state of the PRWN pin.
2. The selection of a PIU internal register ( PDI, PDO, PA, PCON, HSCRATCH, or DSCRATCH) is made by
PADD[3:1].
3. The command can be qualified by the state of th e PADD[0] pin. This pin determines if a read or write command
requires a postincrement of the PA register.
4. Dat a is read or driv en onto PD[15:0 ] by the host.
4.15.5.1 Status/Control/Address Register Read Commands
The host can read the PA, PCON, and DSCRATCH registers by issuing the appropr iate command as par t of a host
read cycle. These commands do not affect the state of the PA, PCON, or PDO registers or the state of the PIBF,
POBE, or PRDY pins. No flow control is required for these commands.
Table 86. Statu s/Contro l/Address Register Read Commands
4.15.5.2 Status/C ontrol /Addre ss Regi ster Write Comman ds
The host can write the PA, PCON, and HSCRATCH registe rs by executing the appropria te comman d as part of a
host writ e cy cle. Flow control is required for these commands, i.e., the host must check the status of the PRDY pin
to ensure that any previous data write has completed before writing to PA, PCON, or HSCRATCH. For a descrip-
tion of flow control, see the flow control description in Section 4.15.5.5 on page 151.
Table 87. Statu s/Contro l/Address Register Write Comm ands
Command
Mnemonic Description
read_pah This command causes the PIU to plac e the upper 16-bit contents of the PA register (PAH) onto PD[15:0].
read_pal This command causes the PIU to place the lower 16-bit contents of the PA register (PAL) onto PD[15:0].
read_pcon This command causes the PIU to place the 16-bit contents of the PCON register onto PD[15:0].
read_dscratch This command causes the PIU to place the 16-bit contents of the DSCRATCH register onto PD[15:0].
Command
Mnemonic Description
write_pah This command causes the PIU to move the contents of the PDI regi ster into t he upper 16 bits of the PA reg -
iste r (PAH). The data move beg ins at the termi nation of a PIU host write cycle.
write_pal This command causes the PIU to move the contents of the PDI r egister i nto the lower 16 bits of the PA reg-
iste r (PAL). The data move begins at the termination of a PIU host write cycle.
write_pcon This command causes the PIU to move the contents of the PDI regist er i nto the PCON register. Th e data
mov e begins at the termination of a PIU host write cycl e.
write_hscratch This command causes the PIU to move the contents of the PDI r egister i nto the HSCRATCH re gister. The
data move begins at the termination of a PIU host write cycle.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.5 Host Commands (continued)
4.15.5.3 Memory Read Commands
The DMAU1 coord inates and executes host data read comm ands via its PIU bypass channel (Section 4.13.4 on
page 86). Prior to issuing a data read command, the host must initialize the PA register with the starting address in
memory by executing the write_pah and write_pal command s. Table 88 describes eac h host read command in
detail.
Table 88. Memory Read Command s
1. A core can coordinate host data read commands by progr am control, but th is is very inefficient compa red to using the DMAU for this pur-
pose.
Command
Mnemonic Description
load_pdo This command causes the PIU to:
Request the DMAU to fetch the single word (16 bits ) poi nted to by the contents of PA.
Place the word into PDO.
The host does not wait for the data af ter issuing this com m and (flow control can be ignored) , but mus t issue
a subsequent unld_pdo command.
load_pdo++ This command causes the PIU to:
Request the DMAU to fetch the single word (16 bits ) poi nted to by the contents of PA.
Place the word into PDO.
Postincrem ent the addr ess in PA by one to point to the next single-word location .
The host does not wait for the data af ter issuing this com m and (flow control can be ignored) , but mus t issue
a subsequent unld_pdo command.
unld_pdo This command causes the PIU to drive the current contents of PDO onto PD[15:0]. The host must use
proper flow cont rol with this command (see Section 4.15.5.4 on page 150).
read_pdo Thi s command causes the PIU to:
Request the DMAU to fetch the single word (16 bits ) poi nted to by the contents of PA.
Place the word into PDO.
Drive the content s of PDO onto PD[15:0].
The host must use proper flow control with this command (see Section 4.15.5.4 on page 150).
read_pdo++ Thi s command causes the PIU to:
Request the DMAU to fetch the single word (16 bits ) fr om the addr ess in PA.
Place the word into PDO.
Drive the content s of PDO onto PD[15:0].
Postincrem ent the addr ess in PA by one to point to the next single-word location .
The host must use proper flow control with this command (see Sect ion 4.15.5.4 on page 150).
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
Table 88. Memory Read Comm ands (continued)
4.15.5 Host Commands (continued)
4.15.5.3 Memory Read Commands (continued)
4.15.5.4 Flow Control for Memory Read Commands
The host performs flow contr ol for memory r ead commands by one of two methods:
1. The host can monitor the PRDY pin to extend an access that has been initiated and wait for PRDY to be
asserted. This method must be used for the read_pdo, read_pd o+ +, and rdpf_pdo++ commands and can be
used for th e unld_pdo command.
2. If the host is unable to use the PRDY pin for fl ow control, it cannot use the read_pdo, read_pdo++, o r
rdpf_pdo++ command to read memory and mus t instead use the combination of the load_pdo and unld_pdo
commands. The host monitors the POBE field (PCON[0]—see Table 75 on page 136) to determine if PDO is full
and can be read with the unld_pdo comm and, as shown in the following pseudocod e:
Issue the load_pdo command to the core // Fetch a word from DSP16411 memory
Do: // and place into PDO register.
Issue a read_pcon command to the core // Host read of PCON.
Repeat until POBE is 0 // Wait for POBE = 0.
Issue the unld_pdo command // Data in PDO now on PD[15:0].
rdpf_pdo++ T his command is a host read with prefetch. It is the highest-per formance command for host r eads of con tig-
uous blocks of memo ry because it causes the DMAU to fetch the block of data as doubl e words (32 bits).
Becaus e the host read s the data as singl e wor ds (16 bit s), t he PIU stor es the ot her hal f of th e double wor d in
a prefetch buffer. As a result, the host must adh ere t o the followi ng rules to use this comman d:
Before the host issues its first rdpf_pdo++ command with a new memory address, it must first issue a
read_pdo++ co mmand. This flushes the prefet ch buff er from any previously issue d rdpf_pdo++ com -
mand.
The host m ust not issue a comm and th at read s or wr it es PA, PCON, HSCRATCH, or DSCRATCH within
a s e ries of rdpf_pdo++ commands.
The host must use proper fl ow control wit h thi s com m and (see Section 4.15.5.4).
F or every two rdpf_pdo++ commands issued by the host, the DMAU and PIU perfor m the fo ll owing:
The PIU requests the DMAU to fetch the double word† pointed to by the contents of PA.
The PIU postincrements PA by two to point to the next double-word location.
The PIU places the first word (the si ngle word at the addr ess in PA) into PDO, places the second word
(the si ngle word at the address in PA + 1) into the prefetch buffer, and drives the word in PDO onto
PD[15:0].
In re spons e to th e second rdpf_pdo++ c ommand i ssued by the host, the PIU pla ces the secon d word (t he
contents of the prefetch buffer) into PDO and drives the word in PDO onto PD[15:0].
This command achieves an average throughput of one word per seven CLK cycles.
† If PA contains an odd address, the PIU requests a single-word access for the first rdpf_pdo++ command in the sequence because the DMAU
requires all double-word accesses to have even addresses. All subsequent rdpf_pdo++ commands in the sequence have even addresses
and the PIU requests double-word accesses.
Command
Mnemonic Description
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.5 Host Commands (continued)
4.15.5.5 Memory Write Commands
The DMAU1 coordinates and executes host data write commands via its PIU bypass channel (Section 4.13.4 on
page 86). Prior to issuing a data write command, the host must initialize th e PA register with the starting address in
memory by executing the write_pah and write_pal command s. Table 89 describes each hos t write command in
detail.
Table 89. Memory Write Commands
4.15.5.6 Flow Control for Control/Status/A ddress Register and Memo ry Write Comman ds
The host must use proper flow control for write commands (write_pdi, write_pdi++, write_pah, write_pal,
write_pcon, o r write_hscratch) using one of two methods:
1. After the host initiates a write cycle, it can monitor the PRDY pin to determine if PDI is alr eady full. If so, the host
can extend the access and wait for the PIU to assert PRDY.
2. If the host is unable to use the PRDY pin for fl ow control, it can monitor the PIBF field (PCON[1]—see Table 75
on page 136 ) before initiating the transaction. For example, the host can execute the following pseudocode:
Do:
Issue a read_pcon command to the core // Host read of PCON.
Repeat until PIBF = = 0 // Wait for PIBF = 0.
Issue the write_pdi command // Write word into PDI.
1. A core can coordinate host data read commands by progr am control, but th is is very inefficient compa red to using the DMAU for this pur-
pose.
Command
Mnemonic Description
write_pdi This command causes the PIU to:
Latch the data from PD[ 15:0] into PDI.
Request the DMAU to wr it e the contents of PDI to the single word pointed to by the cont ents of PA.
The host must use proper flow control with this command (see Section 4.15.5.6).
write_pdi++ This command causes the PIU to:
Latch the data from PD[ 15:0] into PDI.
Request the DMAU to wr it e the contents of PDI to the single word pointed to by the cont ents of PA.
Postincrem ent the addr ess in PA to point to the next single-word location.
The host must use proper flow control with this command (see Section 4.15.5.6).
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.6 Host Command Examples
4.15.6.1 Download of Program or Data
This example illustrates a host d ownloa d to DSP16411 TPRAM1 (CORE1) me mory. Download will begin at
address 0x0 in TPRAM1 and proceed for 1000 16-bit words. For all the following steps, the host must observe
proper flow control.
1. First , the host must write the starting address into the PA register. The sta rting address is location 0x0 in
TPRAM 1, so the host issues the following two host write commands :
write_pah 0x0010 // Host sets PADD[3:0] to 0x8 and writes 0x0010 to PD[15:0]
write_pal 0x0 // Host sets PADD[3:0] to 0xA and writes 0x0 to PD[15:0]
2. Nex t, the host begins to write the data to TPRAM1. This is done by repeatedly issuing the following comman d
999 times. Each iteration writes the appropriate data to be loaded to each sequential 16-bit location in TPRAM1.
write_pdi++ data // Host sets PADD[3:0] to 0x1 and writes data to PD[15:0]
3. For the write of the last data word (in this example, the 1000th word), the host issues the following command:
write_pdi data_ // Host sets PADD[3:0] to 0x0 and writes data_ to PD[15:0]
4.15 .6.2 Upload of Data
This example illustrates a host upload from DSP16411 TPRAM0 ( CORE0) memory. The upload begins at address
0x0200 in TPRAM0 and proceeds for 160 16-bit words. For all the following steps, the host must observe proper
flow control.
1. First , the host must write the starting address into the PA register. The starting address is location 0x0200 in
TPRAM 0, so the host issues the following two host write commands :
write_pah 0x0 // Host sets PADD[3:0] to 0x8 and writes 0x0 to PD[15:0].
write_pal 0x0200 // Host sets PADD[3:0] to 0xA and writes 0x0200 to PD[15:0].
2. Next, the host be gins to read the data from TPRA M0 , as transferred to the PIU’s PDO register via the DMAU.
This is done by first issuing the following command, which drives PD[15:0] with the data from TPRAM0 address
0x00200:
read_pdo++ // Host sets PADD[3:0]=0x1 and reads data (address 0x00200) on PD[15:0].
// (PIU requests DMAU to fetch single word from address 0x00200.)
3. The host then issues the following comm ands. Because the address is initially misaligne d, the first command
causes the PIU to request the DMAU to fetch a single word. For the remaining commands, the PIU requests the
DMAU to fetch a double word for every other command.
rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data (address 0x00201) on PD[15:0].
// (PIU requests DMAU to fetch single word from address 0x00201.)
rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data (address 0x00202) on PD[15:0].
// (PIU requests DMAU to fetch double word from address 0x00202.)
rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data(address 0x00203)on PD[15:0].
// Repeat rdpf_pdo++ command 156 more times for a total of 159 times.
Note: The host must not issu e a command that reads or writes PA, PCON, HSCRATCH, or DSCRATCH within a
series of rdpf_pdo++ commands.
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4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.7 PIU Interrupts
A core can request an interrupt to the host by setting
the PINT field (PCON[3]—see Table 75 on page 136).
If this field is initially cleared and the cor e sets it, the
PIU asserts (h igh) the PINT pin. The host must clear
this field after servicing the PINT request to allow a
core to request a subsequent interrupt. It clears the
field by writing 1 to it.
The host can request an interrupt to the cores by set-
ting the HINT field (PCON[4]—see Table 75 on
page 136). If this field is initially cleared and the host
sets it, the PIU asserts the PHINT interrupt to the
cores. The interrupted core’s service routine must
clear this field after servicing the PHINT request to
allow the host to request a subsequent interrupt. It
clears the field by writing 1 to it. See Section 4.4,
beginning on page 25, for more information on inter-
rupts.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU)
The DSP16411 provide s two identical serial interface
units (SIU) to interface to codecs and various time divi-
sion multiplex (TDM ) bit streams . Each SIU is a full-
duplex, double-buffered serial port with independent
input and output frame and bit cloc k control. The S IU
can generate clocks and frame syn cs internally
(active), or can use clocks and fram e syncs generated
externally (passive ). The programm able modes of the
SIU provide for T1/E1 and ST-bus compatibi lity.
The SIU control registers SCON〈0—12〉, the SIU sta-
tu s registers (STAT and FSTAT), and the SIU input and
output chann el index registers (ICIX〈0—1〉 and
OCIX〈0—1〉) are memory-mapped into the DSP16411
shared I/O memory comp onent (see Section 4.5.7 on
page 43). Section 4 .16.15 on page 184 provides a
detailed description of the encoding of these registers.
The DMAU supports each SIU with two bidirectional
SWT (single-word transfer) channels. SIU0 is directly
connected to DMAU channels SWT0 and SWT1. SIU1
is d irectly connected to DMAU channels SWT2 and
SWT3. The SWT channels provide transfers between
the SIU input and output data registers and any
DSP1641 1 memory space with minimal core overhead.
Each of the SWT channels can perform two-dime n-
sional memory accesses to support the bufferi ng of
TDM data to or from the SIU. Refer to Section 4.13 on
page 64 for more information on the DMAU.
Each SIU provides two interrupt signals directly to each
DSP core, indicating the completion of an input or out-
put transaction. Each core can individually enable or
mask t hese interrupts by programming the core’s inc0
register.
The DSP16 411 SIU provides the following features:
Two mo des of operation: channel m ode and frame
mode:
— Both modes support a maximum frame size of
128 logical channels.
— Frame mode selects all channels within a given
frame.
— Channel mode with a maximum of 32 channels in
two subframes allows minimum core intervention
(a core configures the input and output sections
independently only once or on frame bound-
aries).
— Channel mode with a maximum of 128 channels
in eight subframes is achievable if a core config-
ures the input and output sections independently
on subframe boundaries.
Independe nt input and output sections:
— Program mable data length (4 bits, 8 bits , 12 bits,
or 16 bits).
— LSB or MSB first.
— Program mable frame sync active level, fre-
quency, and position relative to the first data bit in
the frame.
— Program mable bit clock active level and fre-
quency.
— Programmable active or passive frame syncs and
bit clocks.
Compatible with T1/E1 and ST-bus framer dev ices.
Hardware for µ-law and A-law companding.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
Figure 40 is a block diagram of an SIU.
SIU Block Diagram
Figure 40. SIU Block Diagram
SICK
SIFS
SOCK
SOD
SOFS
SCK
PIN
CONDITIONING
CLOCK
AND
FRAME SYNC
SELECTION
ACTIVE CLOCK
AND FRAME SYNC
GENERATOR
AGFS AGCKI AGCKO
CLK
SIFSK
ICK
IFS
OCK
OFS
M
U
X
1
0
SIOLB
SID
INPUT SHIFT
REGISTER
SIB
REGISTER
OPTIONAL
(µ-LAW OR A-LAW)
SIDR
REGISTER
16
16
16
16
MUX
SODR
REGISTER
16 DSI
DDO
16
16
16 16
SDB
OUTPU T SHIFT
REGISTER
OPTIONAL
(µ-LAW OR A-LAW)
16
16
ICK
OCK
CONTROL AND
STATUS REGISTERS
SCON〈0—12〉
STAT
FSTAT
INPUT
CHANNEL
ICIX〈0—1〉
INDEX REGISTERS
OUTPUT
CHANNEL
OCIX〈0—1〉
INDEX REGISTERS
MUX MUX
SOCIX
SICIX
16 16 16
16 16
TO
DMAU
INTERNAL
BIT CLOCKS
AND
FRAME SYNCS
INPUT
SIGNALING OUTPUT
SIGNALING
SOINT
(TO
CORES)
SIINT
(TO
CORES)
IFIX[4] OFIX[4]
IFIX[3:0] OFIX[3:0]
Note: The signals within ovals are control/status register bits. SIOLB is SCON10[8] . IFIX [6:0] is FSTAT[6:0]. OFIX[6:0] is
FSTAT[14:8].
COMPRESSIONEXPANSION
OINTSEL[1:0]
OUTPUT
REQUEST
INPUT
REQUEST
(TO DMAU )
IINTSEL[1:0]
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.1 Hardware Interface
The system interface to the SIU consists of seven pins, described in Table 90.
Table 90. SIU Exter nal Interface
Pin†Type Name Description
SID I SIU Inp ut
Data The SIU latches data from SID into its input shift register. By default, the SIU latches data from
SID on each falling edge of the i nput bit clock.
SICK I/ O /Z SI U In put
Bit Clock By defa ult , SICK is configured as an input (passiv e) that provides the ser ial input bit clock. Alter-
nati vely, the SIU can gener ate the in put bit clock int ernally and can dr ive thi s clock ont o the SICK
output (acti ve).
SIFS I/O/Z SIU In put
Frame Sync SIFS specifies the beginning of a new input fram e. By default, SIFS is active-high and is config-
ured as an input (passive). Alternati vely, the SIU can generate the input fram e sync internally
and can dri ve thi s sync on to the SI FS ou tput ( activ e). To supp ort a 2x ST -b us i nterf ace, SI FS can
be configured as an input that synchronize s the i nternall y generat ed (active) input and output bi t
clocks.
SOD O/Z SIU Output
Data The SIU drives data ont o SOD from it s output shif t regist er. By defau lt , the SIU drives data ont o
SOD on each risi ng edge of th e output bit cl ock. The SIU 3-stat es SO D duri ng inact ive or
masked channel periods.
SOCK I/O/Z SIU Output
Bit Clock By default, SOCK is confi gured as an inp ut ( passive ) that provides the seri al output bit clock.
Alt ernati vely, t he SIU can gener ate the out put bit c lock i nternal ly and can dr ive this cl ock onto the
SOCK output (activ e).
SOFS I /O/Z SIU Output
Frame Sync SOFS speci fie s the b eginning of a new outpu t fram e. By defau lt , SOFS i s active-hi gh and i s con-
fig ured as an i nput ( passive ). Alternat ivel y, the SIU can ge nera te the output frame sy nc i nter nally
and can drive this sync onto the SOFS output (act ive) .
SCK I S IU Ext erna l
Clock Source SCK is an input that provi des an exter nal clock source for generating the active mode input and
output bit clocks and frame syncs.
† The name of the pins has a 0 suffix for SIU0 and a 1 suffix for SIU1.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic
Figure 41 on page 158 diagrams the pin conditioning logic, bit clock selection l ogic, and f rame sync selection logic.
This logic is controlled by fields in the SCON10, SCON3, SCON2, and SCON1 registers, as detailed in
Table 91. Inpu t functional timing is described in detail in Sec tion 4.16.3 on page 159. Output functional timing is
described in detail in Section 4.16.4 on page 160 . Active clock and frame sync generation is described in detail in
Section 4.16. 5 on page 161. SIU loopba ck is described in detail in Section 4.16.7 on page 168.
Table 91. Control Register Fields for Pin Conditioning, Bit Clock Selection, and Frame Sync Selection
Field Val ue Description
SIOLB SCON10[8] 0 Disable SIU loopback mode.
1 Enable SIU loopbac k mo de.
OCKK SCON10[7] 0 The SIU driv es output data onto SOD on the risi ng edge of the output bit cloc k.
1 The SIU drives out put data onto SOD on the fal ling edge of t he output bit cl ock.
OCKA SCON10[6] 0 The output bit clock is provided externally on the SOCK pin (passive).
1 The output bit clock is int ernally generated (active).
OFSK SCON10[5] 0 The output frame sync is active- high.
1 The output frame sync is active-low.
OFSA SCON10[4] 0 The output frame sync is provided externally on the SOFS pi n (passive).
1 The output fra me sync is internally gen erated (active).
ICKK SCON10[3] 0 The SIU latches input data from SID on th e falling edge of the outpu t bit clock.
1 The SIU latches input data from SID on the risi ng edge of the output bit cloc k.
ICKA SCON10[2] 0 The in put bit cloc k is pr ovided ext ernally on the SICK pin (pa ssive).
1 The input bit clock is int ernally generated (active) .
IFSK SCON10[1] 0 The input frame sy nc is active- high.
1 The input frame sync is acti ve-low.
IFSA SCON10[0] 0 The input frame sy nc is provided externally on the SI FS pin ( passive).
1 The input frame sync is int ernally generated (active).
OFSE†SCON3[15] 0 Do not drive internally generated output frame sync onto SOFS.
1 Drive inte rnal ly gener ated output frame sy nc onto SOFS.
OCKE†SCON3[14] 0 Do not drive inter nally generated output bit cl ock onto SOCK.
1 Drive internally generated output bit clock onto SOCK.
IFSE†SCON3[ 7] 0 Do not drive internally generated input frame sync onto SIFS.
1 Drive inte rnal ly gener ated input frame syn c onto SIFS.
ICKE†SCON3[6] 0 Do not drive inter nally generated input bit clock onto SICK.
1 Drive inte rnal ly gener ated input bi t clock onto SICK.
ORESET SCON2[10] 0 Activate output section and begin output processing aft er next output frame sync.
1 Deactivate output section and initi alize bit and frame count ers.
OFSDLY[1:0] SCON2[9: 8] 00 Do not delay output fram e sync.
01 Delay output f rame sync by one cycle of the out put bit clo ck.
10 Delay output frame sy nc by two cycle s of the outpu t bit clock.
IRESET SCON1[10] 0 Activate input section and begin input processing after next input frame sync.
1 Deactivate input section and initialize bit and frame counters.
IFSDLY[1:0] SCON1[9:8] 00 Do not delay input frame sync.
01 Delay input frame syn c by one cycle of the in put bit clock.
10 Delay input frame syn c by two cycle s o f the input bi t clock.
† Se t this field in active mode only, i.e., if the co rresponding OCKA/OFSA/ICK A/IFSA fi eld is set.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic (continued)
Fi gure 41. P i n Condition i ng Log ic, B i t Cloc k Se l ec t i on Lo gic, an d Fram e Syn c Sele ction Lo gic
SIFS
M
U
X
0
1
IFSK
IFSA
AGFS
(FRO M AC TIVE
M
U
X
0
1
IFS
IFSDLY[1:0]
IFSE IFSK
SOFS
OFSK
OFSE OFSK
M
U
X
0
1
OFSA
IRESET
DQ
CLOCK GENERATOR)
DQ
M
U
X
2
1
0
ICK ICK
SIFSK
(TO ACTIV E
CLOCK GENERATOR) SIOLB
OFS
OFSDLY[1:0]
ORESET
DQ DQ
M
U
X
2
1
0
OCK OCK
SICK
M
U
X
0
1
ICKK
ICKA
AGCKI
(FRO M AC TIVE
M
U
X
0
1
ICKE ICKK
SOCK
OCKK
OCKE OCKK
M
U
X
0
1
OCKA
CLOCK GENERATOR) SIOLB
AGCKO
(FRO M AC TIVE
CLOCK GENERATOR)
ACTIVE/PASSIVE
ACTIVE/PASSIVE
LOOPBACK
PIN CONDITIONING CLOCK AND FRAME S YNC SELECTION
DELAY
DELAY
ICK
OCK
ACTIVE/PASSIVE
ACTIVE/PASSIVE
LOOPBACK
Not e: The signals within ov als are cont ro l re gister fields. SIO LB i s SCON10[8], IFSE is SCON3[7], IFSK is SCON10[1], IFSA is SCON10[0],
IRESET is SCON1[10], IFSDLY[1:0] is SCON1[9:8], OFSE is SCON3[15], OFSK is SCON10[5 ], OFSA is SCON10[4], ORESET is
SCON2[10], OFSDL Y[1:0] is SCON2[9:8], ICKE is SCON3[6], I CK K is SCON10[3], ICKA is SCON10[2], OCKE is SCON3[14], OCKK is
SCON10[7], and OCKA is SCON10[6].
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.3 Basic Input Processing
The SIU begins input processing when the user soft-
ware clears the IRESET field (SCON1[10]). The sys-
tem application must ensure that the input bit clock is
applied before IRESET is cleared. If an input bit clock
is a ctive (internally generated), the user program must
wait at least two bit clock cycles between changing
AGRESET (SCON12[15]) and clearing IRE SET. I f the
DMAU is used to service the SIU, the user software
must activate the DMAU channel before clearing
IRESET.
Figure 42 illust rates the default functional input
timing. SI CK (SIU input bit clock) synchronizes all SIU
input transactions. The SIU samples SIFS (SIU input
frame sync) on the rising edge of SICK. If the SIU
detects a rising edge of SIFS, it initiates inpu t process-
ing for a new frame. The SIU latches data bits from
SID (SIU input data ) on the falling edge of SICK for
active channels (i.e., channels selected via software).
Serial Input Functional T iming
Figure 42 . Default Serial Input Function al Timing
To vary the functiona l input timing from the default
operati on described abov e, either core can program
control register fields as follows:
If either core sets the ICKK field (SCON10[3]—see
Table 113 on page 191 ), the SIU inverts SIC K and:
— D etects the as ser t ion of SI FS o n the falling ed ge
of SICK.
— Latches data from SID on each rising edge of
SICK.
If the software sets the IFSK field (SCON10[1]), SI FS
is active-low and the start of a new frame is specified
by a high-to-low transition (falling edge) on SIFS,
detected by an activating edge1 of the input bit clo ck.
By default, the SIU latch es the first data bit of an
input frame from SID one phase of SICK after the
detection of the input frame sync. E ither core can
increase this delay by one or two input bit clock
cycles by programmi ng the IFSDLY [1:0] field
(SCON1[9:8]—see Ta ble 104 on page 186).
An exte rnally generated input bit clock can drive SICK
(passive mode) or the SIU can generate an internal
input bit clock that can be appl ied to SICK (active
mode). A n externally generated input frame sync can
drive SIFS (passive mode) or the SIU can generate an
internal input frame sync that can be applied to SIFS
(active mode). See Section 4.16.5 on page 161 for
detai ls on clock and frame sync generation .
Note: T he combi nati on of passive input bit clock and
active input frame sync is not supported.
The SIU clocks the dat a for the selected ch a nnel i n to a
16-bit input shift register (see Figure 40 on
page 155). Aft e r the SIU clo cks in a complete 4 bits,
8 bits, 12 bits, or 16 bits according to the ISIZE[1:0]
field (SCON0[4:3]—see Table 103 on page 185), it
tran sfers the d a ta to SIB (serial input buffer register)
and sets the SIBV (serial in put buffer valid) flag
(STAT[1]—see Table 118 on page 197). SIB is not a
user-accessible register. Either core can program the
IMSB fi eld ( SCON0[2]) to select MSB- or LSB-first data
transfer from the input shift register to SIB. For data
lengths that are less than 16 bits, the SIU right justif ies
the data (places the data in the lower bit positions) in
SIB and fills the upper bits with ze ros.
SICK
SIFS
SID B0B1
DATA
LATCHED DATA
LATCHED
START OF
FRAME
1. The a c tivat ing edge of the inp ut bit cl ock is the rising e dge of the
clock if the ICKK field (SCON10[3]) is cleared and the falling edge
of the clock if the ICKK fi eld is set.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.3 Basic Input Processing (continued)
If SIDR (serial input data register) is empty (the SIDV
flag (STAT[ 0]) is cleared), the following actions occur:
1. The SIU formats the data (µ-law, A-law, or no modif i-
cation) in SIB according to the IFORMAT[ 1:0] field
(SCON0[1:0]—see Table 103 on page 185).
2. The SIU transfers the formatted data to SIDR.
3. The SIU clears the SIBV (serial input buffer vali d)
flag (STAT[1]).
4. The SIU sets the SIDV flag to indicate that SIDR is
full.
5. The SIU signals the DMAU that serial inp ut data is
ready for transfer to memory.
6. If the IINTSEL[1:0] field (SCON10[12:11] —see
Table 113 on page 191 ) equals two, the SIU asserts
the SIINT in terrupt to th e cores to request service.
Dat a rem ains in SIDR and SIDV remains set until the
data is read by the DMAU or by one of t he cores. After
SIDR has been read, the DSP16411 clears the SIDV
flag.
If new data is completely shifted in before the old data
in SIB is tr ansferred to SIDR (i.e. , whi l e SIBV and SIDV
are both set), an input buffer overflow occurs and the
new data overwrites the old data. The SIU sets the
IO F L OW fi eld (STAT[6]) to reflect this error condition.
If the IINTSEL[1:0] field (SCON10[12:1 1]) equals three,
the SIU asserts the SIINT interrupt to the cores to
reflect this condition.
4.16.4 Basic Output Processing
The SIU begins output processing when the user soft-
ware clears the ORESET field ( SCON2[10]). The sys-
tem application must ensure that the output bit cloc k is
applied before ORESE T is cleared. If an output bit
clock is active (internally generated), the use r program
must wait at least four bit clock cycles between chang-
in g AGR ESET (SCON12[15]) and clearing ORESET. If
the DMAU is used to service the SIU, the user sof tware
must activate the DMAU channel before clearing
ORESET.
Figure 43 illustrates the default serial functional output
timing. SOCK (SIU out put bit clock) synchronizes all
SIU output transacti ons. The SIU samples SOFS (SIU
output frame sync) on the rising edge of SOCK. If the
SIU detects a rising edge of SOFS, it initiates output
processin g for a new frame. Th e SIU drives data bits
onto SOD (SIU output data) on the rising edge of
SOCK for active channels (i.e., channels selected via
software). The SIU 3-states SOD for inactive channels
and during idle periods . (S ee Section 4.16.8 on
page 168 for details.)
Figure 4 3. Def ault Se rial Out p ut Fu nc ti onal Timi ng
To vary the serial function output timing from the default
operation des cribed above, either core can program
control register fields as follows:
If either core sets the OCKK field (SCON10[7]—see
Table 113 on page 191 ), the SIU inverts SOCK and:
— Detects the assertion of SOFS on the falling edge
of SOCK.
— Drives dat a onto SOD on each falling edge of
SOCK.
If either core sets the OFSK field (SCON10[5]),
SOFS is active-low and the start of a new frame is
specified by a high-to-low transition (falling edge) on
SOFS, detected by an activating edge 1 of the output
bit clock.
By default, the SIU drives output dat a onto SOD
immediately after the detection of the output frame
sync. Either core can program the OFSDL Y[1:0] field
(SCON2[9:8]—see Table 105 on page 187) to cause
the SIU to delay dr iving data onto SOD by one or two
output b it clock cycl e s.
SOC K can provide an externa lly generated outp ut bit
clock (passive mode ) or the SIU can generate an inter-
nal output bit clock (active mode) that can be applied to
SOC K. SOFS can provide an external ly generated
output frame sync (passive mod e) or the SIU can gen-
erate an internal output frame sync (active mode) that
can be applied to SOF S. See Section 4.16.5 on
page 161 for details on clock and frame sync genera-
tion.
Note: T he combi nation of passive outp ut bit clock and
active output frame syn c is not supported.
1. The a ctivating edge of the output bit clock is the ris ing edge if the
OCKK field (SCON10[7]) is cleared and the falling edge if the
OCKK field is set.
SOCK
SOFS
SOD B0B1
START OF
FRAME
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.4 Basic Output Processing (continued)
The DMAU or either of the cores writes output data into
SODR (serial output data re gister). Se e F igure 40 on
page 155.If SODR is empty, the SIU cl ears t he SODV
flag (serial output data valid, STAT[3]—Table 118 on
page 197). This indicates that a core or the DMAU can
write new data to SODR. The following describes the
sequence of even ts that follow this condition:
1. The SIU signals the DMAU that it is ready to accept
new data. If the OINTSEL [1:0] field
(SCON10[14:13]) equals two, the SIU generates the
SOINT interrupt signal to both cores.
2. The DMAU or one of the cores writes SODR with
new data.
3. The SIU sets SODV to indicate that SODR is full.
4. At the beginning of the time slot for the next active
channel (on an activating edge of the output bit
clock), the SIU transfers the contents of SODR to the
16-bit output shift register, clears SODV, and drives
the first data bit onto SOD. While transferring the
data from SODR to the output shift register, the SIU
formats the data (µ-la w, A-law, or no modification)
according to the value of the OFORM AT[1:0] field
(SCON0[9:8]—see Table 103 on page 185). Based
on the value of the OMSB field (SCON0[10]), the
SIU shifts the data out LSB-first or MSB -first. Based
on the value of the OSIZE[1:0] field ( SCON0[12:1 1]),
the SIU drives 4 bits, 8 bits, 12 bi ts, or 16 bit s of the
data in the output shift register onto SOD. If
OSIZE [1:0] is programmed to select a data size of
4 bits, 8 bits, or 12 bits, the data must be right-j usti-
fied in (placed in the least significant bits of) the
16-bit SODR register.
Output buffer underfl ow can occur if the DMAU or core
does not write new data into SODR before the contents
of SODR are to be transferred to the output shift regis-
ter. Specifically, an output buffer underflow occurs if all
three of the following conditions exist:
SODR is empty (SODV = 0).
The output shift register is empty.
The time slot for an active channel is pending.
If output buffer underflow occurs, the SIU sets the
OUF LOW field (STAT[7]) and continues to output the
old data in SODR (repe ats step 4) for any active chan-
nels until the DMAU or core w rites new data to
SODR. If the OINTSEL[1:0] field (SCON10[14:13])
equals three, the SIU asserts the SOINT interrupt to
notify the cores of the underflow condition.
4.16.5 Clock and Frame S ync Generati on
Generation of the SIU bit clocks (SICK and SOCK) and
frame syncs (SIFS and SOFS) can be active or pas-
sive. In active mode, these signals can be derived
from the DSP clock, CLK, or from an external clock
source appl ied to the SCK pin. In either ca se, the
active clock source is divided down by a programmable
clock divide r to generate the desired bit clock and
frame sync frequencies. In passive mode, the external
clock source applied to the SICK pin is used directly as
the input bit clock, the signal applied to SIFS is used
directly as the input frame sync, the clock source
applied to the SOCK pin is used directly as the output
bit cloc k, and the signal applied to SOFS is used as the
output frame sync. All of the bit fields that control bit
clock and frame syn c generatio n are summa rized in
Table 92 on page 164.
The input section and the outp ut section of each SIU
operate independently and require individual clock
sources to be specified.
Note: T he combi nati on of passive input bit clock and
active input frame sync is not supported, and the
combination of passive output bit clock and
active output frame syn c is not supported. If the
combinat ion of an a ctive bit clock and a passive
frame sync is selected, the frame sync must be
derived from the bit clock and must meet the tim-
ing requirem ents specified in Section 11.11,
beginning on page 294.
The def ault operation specifies that the SIU clocks
input data bits from SID on the falling edge of SICK and
drive output dat a bits onto SOD on the rising edge of
SOC K. The DSP16411 c an invert the polarity (active
level) of the SICK pin by setting the ICKK field
(SCON10[3]—see Tab le 113 on page 191) and the
polarity (active level) of the SOCK pin by setting the
OC KK field (SCON10[7]). The SIU can gener ate one
or both bit clocks internally (a ctive) or externally
(passive). Setting the ICKA field (SCON10[2]) puts
SICK into active mode, and setting the OCKA field
(SCON10[6]) puts SOCK into active mode.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.5 Clock and Frame Sync
Generation (continued)
Active bit clocks are generated by dividing down either
the internal clock (CLK) or a clock source applied to the
SCK pin, depend ing on the AGEXT field
(SCON12[12]—see Table 115 on page 195). The
active clock generator must also be enabled by clearing
the AGRESET field (SCON12[15]) and programming a
divide ratio into the AGCKLI M[7:0] field
(SCON11[7:0]—see Table 114 on page 194). If either
bit cloc k is internally generated, the corresponding
clock pin (SICK or SOCK ) is an output that can be
turned off by clearing the ICKE field (SCON3[ 6]—s ee
Table 106 on page 188 ) or the OCKE field
(SCON3[14]—see Table 106 on page 188), placing the
corresponding pin into 3-state.
Passive bit clocks are externally generated and applied
directly to the corresponding SICK or SOCK pins. In
this case, the ICKA or OCKA field (SCON10[2] or
SCON10[6] ) is cleared. The program should disabl e
the active clock generator by setting the AGRESET
field (SCON12[15]) only if both clocks and bot h fr ame
syncs are externally generated.
The default operation of the SIU specifies the active
level of the input and output frame sync pins to b e
active-high, so the rising edge of SIFS or SOFS indi-
cates the beginning of an input or output frame, respec-
tively. The program can invert the active level (active-
low) by setting the IFSK and OFSK fields ( SCON10[1]
and SCON10[5] ). Th e program can configure one or
both frame syncs as internally generated (active) or
externally generated (pas sive), based on the states of
the IFSA and OFSA fields (SCON10[0] and
SCON10[4]).
The active frame syncs are generated by dividing down
the internally generated active mode bit clock. The
active clock generator must also be enabled by clearing
the AGRESET field (SCON12[15]) and by program-
ming a divide ratio in to the AGFSLI M[10:0] field
(SCON12[10:0]). If either frame sync is internally gen-
erated, the corresponding frame sync pin (SIFS or
SOFS) is an output that can be turned off by clearing
th e IF SE fi e ld (SCON3[7]—see Table 106 on
page 188) or the OF SE field (SCON3[15]—see
Table 106 on page 188), placing the corresponding pin
into 3- state.
Passive frame syncs are ex ternally generated and
applied directly to the SIFS or SOFS pins. In this case,
the IFSA field (SCON10[0]—see Table 113 on
page 191) or the O FSA field (SCON10[4]) is cleared.
The program should disable the active clock generator
by setting the AGRESET field (SCON12[15]—see
Table 115 on page 195) only if both frame syncs and
both bit clocks are externally generated.
The active clock generator has the ability to synchro-
nize to an external source (SIFS). If the AGSYNC field
of (SCON12[14]) is set, the internal clock generat or is
synchroni zed by SIFS. This feature is used only if an
external clock sou rce is applied to the SCK pin and
drives the internal clock gene rator, i.e., if the program
set the AGEXT field (SCON12[12]). A typical applica-
tion for using external synchronization is an ST-bus
interface that employs a 2X external clock source. This
feature is dis cussed in more detail in Section 4.16.6,
beginning on page 166.
The active clock generator also has the ability to pro-
vide addit ional input data setup time if an external
source (the SCK pin, selected by AGEXT = 1) is
selec ted to generate the input and output bit clocks.
If the I2XDLY field (SCON1[11]—s ee Table 104 on
page 186) is set, the high phase of the internally gener-
ated inpu t bit clock, ICK , is stretched by one SCK
phas e, providing extra data capture time. This feature
is illustrated in Figure 53 on page 183.
The relative location of data bit 0 of a new frame can be
delayed by a maximum of two bit clo ck periods with
respect to the location of the frame sync. T his feature
is controlled by the IFSDLY [1:0] field (SCON1[9:8]—
see Table 104 on page 186) for input and the
OFSDLY[1:0] field (SCON2[9:8]—see Table 105 on
page 187) for output. The location of the leading edge
of frame sync is approxim ately coincident with bit 0 by
defaul t. Howev er, bit 0 can be delayed by one or two
bit clocks after frame sync as shown in Figure 44.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.5 Clock and Frame Sync Genera tion (continued)
Frame Sync to Data Delay Timing
Figure 44. Frame Sync to Data Delay Timing
5-7849 (F)
Bn – 2 Bn – 1 B0B1B2B3B4B5B6B7
Bn – 3 Bn – 2 Bn – 1 B0B1B2B3B4B5B6
Bn – 4 Bn – 3 Bn – 2 Bn – 1 B0B1B2B3B4B5
S〈I,O〉CK
S〈I,O〉FS
S〈I,O〉D
(〈I,O〉FSDLY = 0)
S〈I,O〉D
(〈I,O〉FSDLY = 1)
S〈I,O〉D
(〈I,O〉FSDLY = 2)
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.5 Clock and Frame Sync Generation (continued)
Table 92. A Summa ry of Bit C lock and Frame Sy nc Control Register Fields
Bit Field Register Description
AGRESET SCON12[15] Enables the internal acti ve clock divider /generator.
AGSYNC SCON12[14] Enables synchronization of the internal active clock generator to SI FS. If set,
AGEXT must also be set. This feature is enabled for 2x ST-bus operation.
SCKK SCON12[13] Defines the active level of the external clock source, SCK.
AGEXT SCON12[12] Defines the clock source to the internal clock divider /generator (either the DSP
CLK or external SCK pin).
AGFSLIM[10:0] SCON12[10:0] Defines the clock divider ratio for the internal generation of frame syncs (active
mode).
AGCKLIM[7:0] SCON11[7:0] Defines the clock divider ratio for the internal generation of bit clocks (active
mode).
SIOLB SCON10[8] En ables SIU loopback mode. See Section 4.16.7 on page 168.
OCKK SCON10[7] Defi nes the active level of the SOCK pin.
OCKA†SCON10[6] Defines SO CK as internally (acti ve mode, SOCK is an output) or externall y (pas-
sive mode, SOCK is an input) generated.
OFSK SCON10[5] Defi nes the active level of the SOFS pin.
OFSA†SCON10[4] Defi nes SO FS as internally (act ive mode, SOFS is an output) or ext ernally ( pas-
sive mode, SOFS is an input) generated.
ICKK SCON10[3] Defines t he activ e level of the SICK pin.
ICKA†SCON10[2] Defines SICK as internall y (SICK is an outpu t) or externa ll y (SI CK is an input)
generated.
IFSK SCON10[1] Defi nes the act ive level of the SIFS pin.
IFSA†SCON10[0] Defines SIFS as internally (acti ve m ode, SIFS is an out put) or externally (passive
mod e, SIFS is an input ) generated.
IFSE SCON3[7] For active mode SIFS, this bit det ermines if the SIFS pin is driv en as an output.
ICKE SCON3[6] For active mode S ICK, this bit det ermines if the SICK pin is driven as an output.
OFSE SCON3[15] For active mode SOFS, this bit determines if the SOFS pin is driven as an output.
OCKE SCON3[14] For acti ve m ode SOCK, t his bit de termines if the SOCK pin is driven as an output.
I2XDLY SCON1[11] If set, the SIU stretches the high phase of the int ernally gener ated input bi t clock,
ICK, by one SCK phase to provide additional serial input data setup (capture)
time. Thi s feature is valid only if AGEXT = 1 and ICKA = 1.
† Th e combina tion of passive output bit clo ck (OC KA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-
sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.5 Clock and Frame Sync
Generation (continued)
Table 93 offers three typical settings for the SIU contr ol
register fields that determine bit clock and frame sync
generation. The term as requi red used in this table
refers to the user’s system requirem ent s.
Example 1 shows the bit field values if both bit clocks
and frame syncs are supplied directly from an exter-
nal serial device (e.g., a codec).
Exam ple 2 show s the bit fi eld v alues i f bot h bit clocks
and frame syncs are active and generated directly
from the internal clock, CLK. This example assumes
that the SICK , SOCK, SIFS, and SOFS pins are out-
puts driven by the SIU.
Exam ple 3 show s the bit fi eld v alues i f bot h bit clocks
and the output frame sync are active and generated
directly from the external clock source applied to the
SCK pin. The SIFS pin is driven by an external
source and is used to synchronize the internal frame
bit counter. The SICK, SOCK, and SOFS pins are
not driven by the SIU, and the high phase of the
internal input bit clock is stretche d. T hes e settings
are valid for a double-rate clock ST-bus interfa ce.
The effect of these SIU control register settings is
illustrated by Figure 53 on page 183.
Table 93. Examples of Bit Clock and Frame Sync Control Register Fields
Bit Fie ld Regi ster Example 1
All Passi ve Example 2
All Active (CLK) Example 3
All Active (SCK)
Double-Rate ST-Bus
AGRESET SCON12[15] 1 0 0
AGSYNC SCON12[14] 0 0 1
SCKK SCON12[13] 0 0 1
AGEXT SCON12[12] 0 0 1
AGFSLIM[10:0] SCON12[ 10:0] 0 as required as required
AGCKLIM[7:0] SCON11[7:0] 0 as re quired 1
SIOLB SCON10[8]000
OCKK SCON10[7 ] as requ ired as required as required
OCKA†SCON10[6]011
OFSK SCON10[5 ] as requ ired as required as required
OFSA†SCON10[4]011
ICKK SCON10[ 3 ] as requ ired as required as required
ICKA†SCON10[2]011
IFSK SCON10[ 1 ] as requ ired as required 1
IFSA†SCON10[0]011
IFSE SCON3[7]010
ICKE SCON3[6]010
OFSE SCON3[15] 0 1 0
OCKE SCON3[14] 0 1 0
I2XDLY SCON1[11] 0 0 1
† Th e combina tion of passive output bit clo ck (OC KA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-
sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.6 ST-Bus Timing Examples
Figures 45 and 46 illustrate SIU timing examples for 2x ST -bus compatibility, which requires active clock generation
with SCK as the clock source and SIFS syn chronization enabl ed (AGEXT = 1, IFSA = 1, and AGS YNC = 1). The
input frame sync, SIFS, is externally generated.
Figure 45 illustrates the functional timing of the internally generated bit clocks, ICK and OCK, assuming the bit
clock divide ratio is two (AGCKLIM = 1). This results in bit cl ocks that have a period that is twice the period of SCK.
Since the div ide ratio is even, the duty cycle of the generated bit clock is 50%. Also shown are the internally gener-
ated frame syncs, IFS and OFS. Refer to Figure 40 on page 155 for a block diagram of the interna l clock genera-
tor.
Clock and Frame Sync Generation with External Clock and Synchronization
(AGCKLIM = 1, SCKK = 1, IFSK = 1, SIFS Has No Effec t)
Note: The timing reference TACKG is the active clock period de term ined by the AGCKLIM[7: 0] field (SCON11[7:0]).
Figure 45. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires No Resynchronization)
SCK
OCK
SIFS
ICK
OFS
IFS
TACKG
SOD B0B1BNBN – 1
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.6 ST-Bus Timing Examples (continued)
Figure 46 illustrates the functional timing of the internally generated bit clocks and frame syncs, ICK , OCK, IFS,
and OFS, assu ming the bit clock divide ratio is two (AGC K LIM = 1, same as Figure 45 on page 166) and SIFS is
asserted while the internally generated bit clocks are high. In this case, the internal bit clocks are forced to remain
high a t the falling edg e o f SIFS . Thi s effe ctiv e ly s tret c h es the int e rn al b it cl oc ks b y on e SC K cyc le, sync hr oniz ing
th e int ern al bit clocks to th e externa l frame sync, SIFS. As a result, th e first frame fo l lowing synchron i za tion is
lost. The SIU 3-states the SOD pin during the lost frame. Subs equent frames are synchronized and function cor-
rectly. The dotted lines in this figure show the location of SIFS and the active bit clocks and sy ncs if SIFS had
occurred one SCK cycle later (i.e., if the internal frame bit counter had expi red prior to the assertion of SIFS, the
same as Figure 45).
Clock and Frame Sync Generation with External Clock and Synchronization
(AGC KLIM= 1, SCKK=1, IFSK = 1, SIFS Cause s Re s y nchronization)
Figure 46. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = AGS Y NC = IFSA = IFSK = 1 and Timing Requires Resync hro nizatio n)
SCK
OCK
SIFS
ICK
OFS
IFS
SOD BNBN – 1BN – 2
THIS FRAME IS LOST
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.7 SIU Loopback
Each SIU of the DSP16411 includes an internal diag-
nostic mode to verify functionality of the SIU wit hout
requiring system intervention. If the SIOLB field
(SCON10[8]—see Table 113 on page 191) is set, th e
SIU output data pin (SOD) is internally looped back to
the SIU input data pin (SID), the output bit clock is
internally connected to the input bit clock, and the out-
put frame sync is internally connected to the input
frame sync. A ny input at the SID pin is ignored while
loopback is enabled.
There are two ways tha t SIU loopback can be used:
1. The user’ s code can define the output bit clock and
output frame sync to be active and the input bit clock
and input frame sync to be passive. See
Section 4.16.5, beginning on page 161, for informa-
tion on configuring the bit clocks and frame syncs as
active or passive. If SIU loopback is enabled, the
act iv e sig nals g enera te th e necessa ry clocks and
frame syncs for the SIU to send and receive data to
itself. Unless enabled by the user, the SICK, SOCK,
SIFS, and SOFS pins are 3-state. To enable these
outputs, set the ICKE, OCKE, IFSE, and OFSE
fields (see SCON3 in Table 106 on page 188).
2. The user’s code can define all th e SIU clocks and
syncs to be passive. S ee Secti on 4.16.5, beginning
on page 161, for information on configuring the bit
clocks and frame syncs as active or passive. The
system must supply a bit clock to the SOCK pin and
a frame sync to the SOFS pin.
4.16.8 Basi c Frame St ructure
The primary data structure processed by the SIU is a
fram e, a sequence of bits that is in itiated by a frame
sync. E ac h inpu t and output frame is compos ed of a
numbe r of channels, as determined by the IFLIM[6:0 ]
field (SCON1[6:0]—Table 104 on page 186) for input
and the OF LIM[6:0 ] field (SCON2[6:0]—Table 105 on
page 187) for output. Eac h channel consists of 4 bits,
8 bits , 12 bits, or 16 bi ts, as determined by the
ISIZE[1: 0] and OSIZE[ 1:0 ] fields (SCON0[4:3] and
SCON0[1 2:11]—see Table 103 on page 185), and has
a programmable data format (µ- law , A-law , or linear) as
determined by the IFORMAT[1:0] and OFORMAT[1:0]
fields (SCON0[1:0] and SCON0[9:8]). All channels in a
frame must have the same data length and data format.
Figure 47 illustrates the basic frame structure assum-
ing five channels per frame (〈I,O〉IFLIM[6:0] = 4) and a
chan nel size of 8 bits (〈I,O〉SIZE[1:0] = 0). Figure 48
on page 169 ill u strates the same frame structure wit h
idle time. The SIU 3-states the SOD pin during idle
time.
Note: If the output section is configured for a one-chan-
nel frame (OFLIM[6: 0] = 0x0) and a passive
frame sync (OFSA(SCON10[4]) = 0), the SOFS
frame sync interval must be constant and a mul-
tiple of the OCK output bit clock.
Basi c Frame Stru cture
Figure 47. Basic Frame Structure
CHANNEL
〈I,O〉CK
S〈I,O〉D
〈I,O〉SIZE
〈I,O〉FS
02176534 02176534 02176534 02176534 02176534 02176534
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 0
FRAME PERIOD
〈I,O〉FLIM + 1 CHANNELS
FRAME
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.8 Basic Frame Structure (continued)
Figure 48 . Basic Frame S tructu re with Idle Time
To assist channel selection within a frame, a frame is
partitioned into a maximum of eight subframes. Each
subframe has 16 logical chann els, for a to tal channel
capacity of 128 channels per frame.
4.16.9 Assign ing SIU Logical Channels to DMAU
Channels
Regardless of the operating mode, the channel index
registers for the SIU must be initialized via software if
the DMAU is used to transfer data to and from memory.
There are a total of four 16-bit chan nel index registers:
two for input (ICIX〈0—1〉) and two for output
(OCIX〈0—1〉). Each bit corresponds to one logical
channel within the currently selected even or odd sub-
frame. These bit fields determine the assignmen t of
logical channels within a subfram e to a specific DMAU
SWT channel dedicated to that SIU. Recall that two
bidirectional SWT channels of the DMAU support each
SIU so that logical channels can be routed to two sepa-
rate memory spaces.
In channel mode, ICIX0 correspo nds to the currently
selected even input subframe, as determined by the
ISFID_E[1:0] field (SCON3[1:0]—see Table 106 on
page 188). ICIX1 corresponds to the currently
selected odd input subfram e, as determined by the
ISFID_O[1:0] field (SCON3[4:3]). OCIX0 corresponds
to the currently selected even output subframe, as
determined by the OSFID_E[1:0] field
(SCON3[9:8]—see Table 106 on page 188). OCIX1
correspond s to the currently selected odd output sub-
frame, as determined by the OSFID_O[1:0] field
(SCON3[12:11]). In frame mode, ICIX〈0—1〉 and
OCIX〈0—1〉 are circularly mapped to multiple channels
in the frame as illustrated by Ta ble 122 on page 199
and Tabl e 1 21 on page 198.
If a bit field of SIU0’s ICIX〈0—1〉 or OCIX〈0—1〉 regis-
ter is cleared, the corresponding logical channel of
SIU0 is assigned to SWT0. If a bit field of these regis-
ters is set to one, the correspon ding logic al channel of
SIU0 is assigned to SWT1. If a bit field of SIU1’s
ICIX〈0—1〉 or OCIX〈0—1〉 register is cleared, the cor-
respon ding logical channel of SIU1 is assigned to
SWT2. If a bit field of these same registers is set to
one, the corresponding logical channel of SIU1 is
assig ned to SWT3 . Fo r exam ple, to assign SIU0 input
chan nels 0 to 7 to SW T0 and 8 to 15 to SWT1, the
value written to ICIX0 is 0xFF00.
CHANNEL
FRAME PERIOD
〈I,O〉FLIM + 1 CHANNELS
〈I,O〉CK
S〈I,O〉D
〈I,O〉SIZE
〈I,O〉FS
02176534 02176534 02176534 02176534 02176534 021534
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 0
FRAME
000000
IDLE†
† T he SI U 3-states SOD during idle ti me.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.10 Frame E rror Detectio n and Reporting
The SIU suppor ts back -to-back frame processing.
However, when a frame has completed , the SIU stops
processing until the beginning of another frame is
detected by sampling a new frame sync. If the new
frame sync is detected before a frame has complet ed,
the follo wing actions are taken by the SIU:
1. A n interrupt request is generated, if
enabled. S pecif ical ly, if the occurren ce of SIFS is
detected before the end of the input frame, an input
error has occurred. If enabled via the IINTSEL[1: 0]
field (SCON10[12:1 1] —see Table 1 13 on page 191),
the SIINT interrupt is asserted to the DSP cores. If
the occurrence of SOFS is detected before the end
of the output frame, an output error has occurred. If
enabled via the OINTSE L[1:0] field
(SCON10[14:13]), the SOINT interrupt is asserted to
th e cores.
2. The IFERR flag (input frame error) or OFE RR flag
(output frame error) is set in the STAT register
(Table 118 on page 197), as appropriate. A ll sub-
frame, channel, and bit c ounters are reinitialized and
a new input or output frame transaction is
initiated. The data from the incomplete frame can be
erroneous and the core software should perform
error recovery in response to the setting of IFERR or
OFERR.
3. If the SIU is in passi ve mode (clocks and frame syn c
are externally generated) or in active mode with the
AGSYNC field (SCON12[14]) cleared, the new
frame t ransaction begins immediately after the new
frame sync is detected. If the SIU is in active mode
with AGSYNC set and an externally generated clock
is applied to SCK, the new frame transaction begins
after the detection of the first frame sync that does
not cause resynchronization of the bit clocks. See
Section 4.16.6 on page 166 for details on resynchro-
nizing bit clocks in active mode.
4.16.11 Fr am e Mode
Frame mode allows for a high channel capacity, but
sacrifices channel s electivity. A program selects frame
mode by setting the IFRA ME field (SCON1[7]—
Table 104 on page 186 ) for input and the OFRAM E
field (SCON2[7]—see Table 105 on page 187 ) for
output. In this mode, the SIU processes all channels in
the frame. A maximum of 128 consecutive channels in
the frame can be accessed. The IFLIM[ 6:0] field
(SCON1[6:0]) and OFLIM[6:0] field (SCON2[6:0])
define the number of channels in each input and output
frame.
If using frame mode, the user performs the following
steps in software:
1. Configure the number of channe ls in the frame
structure (1 to 128) by programm ing the IFLIM[6:0]
field with the input frame size, and the OFLIM[6:0]
field with the output frame size. The input and out-
put frame size is the number of channels m inus
one. For simple serial communications (one chan-
nel per frame), these fields should be programmed
to zero.
2. Configure the channel size (4 bits, 8 bits, 12 bits, or
16 bits) by writing the ISIZE[1:0] and OSIZE[1:0]
fields (SCON0[4:3] and SCON0[12:11]—Table 103
on page 185). Select LSB-first or MSB-first by pro-
gramm ing the IMS B and OMS B fields (SCON0[2]
and SCON0[ 10]). Configure the data format by pro-
gramm ing the IFORM AT [1:0] and OFO RMAT [1:0]
fields (SCON0[1:0] and SCON0[9:8]).
3. P rogram the 16-bi t channel index registers,
ICIX〈0—1〉 and OCIX〈0—1〉 (Table 120 on
page 198), to assign specific SIU input and outp ut
chan nels to be routed to one of two DMAU SW T
channels (SWT0 or SWT1 for SIU0; SWT2 or SWT3
for SIU1). The ma ximum num ber of channel s that
ICIX〈0—1〉 or OCIX〈0—1〉 can specify is 32 (two
16-bit registers). If the number of channels is
greater than 32, the DMAU routing spec ified for
chan nels 0—3 1 is applied to channels 32—63,
chan nels 64— 95, etc., as shown in Table 122 on
page 199 and Table 121 on page 198. For the spe-
cial case of simpl e seria l communi cations (one
channel per f rame), program channels 0 and 1 to the
same value, i.e., program ICIX〈0—1〉[1:0] to th e
same v alue for input and OCIX〈0—1〉[1 :0 ] to th e
same v alue for output.
4. E nable frame mode by setting IFRAME ( SCON1[7])
and OFRAME (SCON2[7]).
5. Di sa ble channel mode by clearing the ISFIDV_E
field (SCON3[2]—see Table 106 on page 188),
ISFIDV _O field (SCON3[5]), OSFIDV_E field
(SCON3[10]), and OSFIDV_O field (SCON3[13]).
6. S ele ct pass ive vs. active bit clocks and frame sy ncs
(see Sec tion 4 .16.5 on page 161 for details).
7. P rogram the IINTSEL[1: 0] field (SCON10[12:11] )
and OINTSEL[1:0] field (SCON10[14:13]) as
required by the application.
8. Begin input and output processing by clearing the
IRESET fi e ld (SCON1[10]) and the ORESET field
(SCON2[10]).
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Chan nel Mode—32 Cha nne ls or Less in
Tw o Su bfram es or Le ss
Compared to frame mode, channel mo de provides for
channel selectivity with minimal core o verhead at the
expense of chann el density. For input, this mode is
selected if the following conditions are met:
The IFRAME field (SCON1[7]—see Table 104 on
page 186) is cleared.
The ISFIDV_E field (SCON3[2]—see Table 106 on
page 188), the ISFIDV_O field ( SCON3[5]), or both
are set.
For output, channel mode is selected if the follow ing
conditions are met:
The OFRAME field (SCON2[7]—see Table 104 on
page 186) is cleared.
The OSFIDV_E field (SCON3[10]), the OSF IDV_O
field (SCON3[13]), or both are set.
In this mode, the SIU processes a maximum of
32 channels within a given frame. The maximum frame
size is 128 channels. The IFLIM[6: 0] field
(SCON1[6:0]—Table 104 on page 186) for input and
the OF LIM[ 6:0] field (SCON2[6:0]—Ta ble 105 on
page 187) for output define the number of channels in
the frame structure.
To assist with channel selection, both input and output
frames are divided into eight subframes: four even (0,
2, 4, 6) and four odd (1, 3, 5, 7). The SIU can enable
only one even and one odd subframe at any one ti me.
Each subf rame cont ains 16 channels1 that can be indi-
vidually enabl ed. Figure 49 shows a 128- channel
frame and the relationship between frames, subframes,
and logical channels. Table 94 on page 172 specifies
the assoc iation of channe l numbers to even and odd
subframes.
Channel Mode on a 128-Channel Frame
Figure 49. Channel Mode on a 128-Channe l Frame
1. It is assumed that for channel mode , the numb er of chan nels per frame as determined by the IFLI M[6:0] and OFLIM[6: 0] fi elds is evenly divis-
ible by 16. This result s in exactly 16 channels per subframe . If the number of channels pe r frame is not evenly divisible by 16, the las t sub-
frame is a partial subframe of less than 16 cha nnels. If this is t he case and if int errupts are progr ammed to occur on subf rame boundaries
(see Figur e 51 on page 178), then an interrupt is not generated for the partial subframe.
1513
2
1
1413
SYNC
DATA
128-CHANNEL FRAME
〈I,O〉FLIM = 0x 7F
〈I,O〉FRAME = 0x0 ; DEFINE AS 128-CHANNEL FRAME
; TRANSFER ONLY SELECTED CHANNELS
8 SUBFRAMES PER TDM FRAME
16 CHANNELS PER SUBFRAME
[0:15] [16:31] [112:127][96:111][80:95][64:79][48:63][32:47]
SUBFRAME 2 SUBFRAME 5
0
01 2 1314
〈I,O〉SFID_E = 1
〈I,O〉SFIDV_E = 1
〈I,O〉SFVEC_E = 0xFFFF
OSF MS K_E = 0x7F F 9
CHANNEL DATA BITS
; SUBFRAME 2 SELECTED
; ALLOW INDIVIDUAL CHANNEL SELECTION
; ALL 16 CHANNELS ACCESSIBLE
; MASK ALL OUTPUT CHANNELS
; EXCEPT 15, 2, 1
〈I,O〉ISIZE = 1
〈I,O〉MSB = 1 ; 16-BIT CHANNELS
; MSB SHIFTED FIRST
ACTIVE CHANNELS
M ASKED C H AN N ELS
CHANNEL DATA BITS
15
1215
014
EVEN
SUBFRAME ODD
SUBFRAME ODD
SUBFRAME ODD
SUBFRAME
EVEN
SUBFRAME EVEN
SUBFRAME EVEN
SUBFRAME ODD
SUBFRAME
0
〈I,O〉SFID_O = 2
〈I,O〉SFIDV_O = 1
〈I,O〉SFVEC_O = 0xFFFF
OSF M SK_O = 0xBFF D
; SUBFRAME 5 SELECTED
; ALLOW INDIVIDUA L CHANNEL SELECTION
; ALL 16 CHAN N ELS ACC ESSIBLE
; MASK ALL OUTPUT CHANNELS
; EXC EPT 1 AN D 14
16 BITS PER CHANNEL
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Channel Mode— 32 Chan nels or Less in Two Subframe s or Less (continued)
Table 94. Su bframe Definition
For SIU processing of specific logical chann els, the
user enables at least one active even or odd subframe
within the input and output frames and defines the even
(0, 2, 4, or 6) or odd (1, 3, 5, or 7) input and output sub-
frame ID. Wit hin each active subframe, active input
channels and active outpu t channels are individuall y
selected via the channel activation vectors. These fea-
tures are controlled by the SIU control memory-
mapped registers, SCON〈3—9〉.
In channel mode, the SIU drives data onto the SOD pin
only during the time slots for active output
channels. Otherwise, the S IU 3-st ates SOD. Similarl y,
in channel mode, the SIU latches input data bits only
during the time slots for active input channels.
If the DMAU is used to transfer SIU input data to mem-
ory, each active input channel (time slot) can be individ-
ually routed to a specific SWT channel. See
Section 4.16.9 on page 169 for details.
Even Subframes Odd Subframes
Subframe Channels Subframe Channels
00—15 1 16—31
2 32—47 3 48—63
4 64—79 5 80—95
6 96—111 7 112—127
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Chan nel Mode—32 Cha nne ls or Less in
Tw o Su bfram es or Le ss (continued)
If using channel mode, the user performs the following
steps in software:
1. Configure the number of channels in the frame
structure (1 to 128) by programming the IFLIM[6:0]
field (SCON1[6:0 ]—see Table 104 on page 186) with
the frame size for input and the OFLI M [6:0] field
(SCON2[6:0]—see Tab le 105 on page 187) with the
frame size for output.
2. Conf igure the channel size (4 bits, 8 bits, 12 bits, or
16 bits) by writing the ISIZE[1:0] and OSIZ E[1:0]
fields (SCON0[4:3] and SCON0[12:11]—see
Table 103 on page 185 ). Select LSB-first or MSB-
first b y programm ing the IMSB and OM S B fields
(SCON0[2] and SCON0[10]). Con figure the data
format by programming the IFORMAT[1:0] and
OFORMAT[1:0] fields (SCON0[1 :0 ] a nd
SCON0[9:8]).
3. Disable frame mode by clearing the IFRAME field
(SCON1[7]— s ee Table 104 on page 186 ) and the
OFRAME field (SCON2[7]—see Tab le 105 on
page 187).
4. S elect the num ber of subframes (one or two) to be
enabled. If two subframes are enabled, one must be
even and one must be odd. S ee ste p 5.
5. S elect the active subframe(s) and channels within
each subframe. Tables 95 to 99 further detail the bit
fields described below:
— To activate an even input subframe, set the
ISFIDV_E field (SCON3[2]—see Table 106 on
page 188). Also program the ISFID_E[1:0] field
(SCON3[1:0]) with the address of the active even
subframe (active subframe numbe r is
2×ISFID_E). Within the active subframe, up to
16 logical channels can be individually enabled
via the ISFVEC_ E[15:0] field (SCON4—s ee
Table 107 on page 189). For each enabled chan-
nel, assign one of two DMAU SWT channels by
setting or clearing the corresponding bit in ICIX0
(Table 122 on page 199 ).
— To activate an odd input subframe, set the
ISFIDV_O fiel d (SCON3[5]—see Table 106 on
page 188). Also program the ISFID_O[1: 0] field
(SCON3[4:3 ]) with the address of the active odd
subframe (active subframe numbe r is
(2 ×ISFID_O) + 1). Within the active subframe,
up to 16 logical cha nnels can be individua lly
enabled via th e ISFVEC _O[15: 0] field
(SCON5—see Table 108 on page 189). For each
enabled channel, assign one of two DMAU SWT
channels by setting or clearing the corresponding
bit in ICIX1 (Table 122 on page 199).
— To ac tivate an even out put subframe , set the
OSFI DV_E field (SCON3[10]). Also program the
OSFID_E[1:0] field (SCON3[9:8]) with the
address of the active even subframe (active sub-
fram e numbe r is 2 ×OSFID_E). Within the
active subframe, up to 16 logical channels can be
individually enabled via the OSFVEC_E[15:0]
field (SCON6—see Table 109 on page 190). Any
enabled channel can be individually masked via
the OSFM S K_E [15:0] field (SCON8—s ee
Table 111 on page 190). Masking an output
channel retains the data structure (the DMAU
coun ters are updated) but does not drive data
onto SOD for that channel period. For each
enabled channel, assign one of two DMAU SWT
channels by setting or clearing the corresponding
bit in OCIX0 (Table 121 on page 198).
— To ac tivate an odd output subframe, set the
OSFIDV_O field (SCON3[13]). Also program the
OSF ID_O[ 1:0 ] field (SCON3[12: 11]) with the
address of the active odd subframe (active sub-
fram e number is (2 ×OSFID_O ) + 1). Wi th in the
active subframe, up to 16 logical channels can be
individually enabled via the OSFVEC_O[15:0]
field (SCON7—see Table 110 on page 190). Any
enabled channel can be individually masked via
the OSFM S K _O[ 15:0] field (SCON9—see
Table 112 on page 190). Mas king an output
channel retains the data structure (the DMAU
coun ters are updated) but does not drive data
onto SOD for that channel period. For each
enabled channel, assign one of two DMAU SWT
channels by setting or clearing the corresponding
bit in OCIX1 (Table 121 on page 198).
6. S ele ct pass ive vs. active bit clocks and frame sy ncs
(see Table 4.16.5 on page 161 for details).
7. P rogram the IINTSEL[1: 0] field (SCON10[12:11] )
OINTSEL[1:0] field (SCON10[14:13]) as required by
the applic ation.
8. Begin processing the active channels by clearing the
IRESET fi e ld (SCON1[10]—see Table 104 on
page 186) and the ORESET field (SCON2[10]—see
Table 105 on page 187). Further user software
intervention for SIU configuration is only required to
redefin e the subframe enab le, the subframe ID, or
the active channels within a subframe and their
associated channel index values.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Less (continued)
Table 95. Loc ation of Control Fields Used in Channel Mod e
Table 96. D escripti on of Control Fields Used in Channel Mode
Even Subframe Control Odd Subframe Control Description
Input/
Output Field Register Field Register
Input ISFIDV_E SCON3[2] ISFIDV_O SCON3[5] Subframe ID valid (enable).
ISFID_E[1:0] SCON3[1:0] ISFID_O[1:0] SCON3[4:3 ] S u b fra me ID .
ISFVEC_E[15:0] SCON4[15:0] ISFVEC_O[15:0] SCON5[15:0] Channel activation vector.
Output OSFIDV_E SCON3[10] OSFIDV_O SCON3[13] Subframe ID valid (enable).
OSFID_E[1:0] SCON3[9:8] OSFID_O[1:0] SCON3[12:11] Subframe ID.
OSFVEC_E[15:0] SCON6[15:0] OSFVEC_O[15:0] SCON7[15:0] Channel activation vector.
OSFMSK_E[15:0] SCON8[15:0] OSFMSK_O[15:0] SCON9[15:0] Channel masking vector.
Even Subframe Control Odd Subframe Control
Input/
Output Field Description Field Description
Input ISFIDV_E Enab le even input subfram es. ISFIDV_ O Enab le odd input subf rames.
ISFID_E[ 1:0] Select one of four even input
subframes 0, 2, 4, or 6
(active subframe = 2 ×ISFID_E).
ISFID_O[1:0] Select one of f our odd input sub-
frames 1, 3, 5, or 7
(active subframe =
(2 ×ISFID_O) + 1).
ISFVEC_E[15:0] Bit vector activates up to
16 logical channels indepen-
dently within selected even in put
subframe.
ISFVEC_O[15: 0] Bit vector activ ates up to 16 logical
channels independently within
selected odd input subframe.
Output OSFIDV_E Enable ev en output subframes. OSFIDV_O Enable odd output subfra me s.
OSFI D_E[1:0] Select one of four even output
subframes 0, 2, 4, or 6
(active subframe =
2×OSFID_E).
OSFI D_O[1:0 ] Select one of four odd output sub-
frames 1, 3, 5, or 7
(active subframe =
(2 ×OSFID_O) + 1).
OSFVEC_E[15:0] Bit vector activates up to
16 logical channels indepen-
dently withi n selected even out-
put subframe .
OSFVEC_O[15:0] Bit vector activates up to 16 l ogical
channels independently within
selected odd output subframe.
OSFMSK_E[ 15:0] Bit vect or s elects up to 16 logic al
channels independently within
selected even output subframe to
be mask ed †.
OSFMSK_O[15: 0] Bit vec tor select s up to 16 logi cal
channels independently within
selected odd output subframe to be
masked†.
† If an output channel is masked, then the SOD pin is forced to the high-impedance state during that channel’s time slot.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Less (continued)
Table 97. Subframe Selection
Table 98. Channel Activation Within a Selected Su bframe
Table 99. Channel Mask ing Within a Selected Subframe
Input/
Output Even/Odd
Subframes To Select
Subframe Set Control Bit Configure Control Field
Name Location Name Location Value
Input Even 0 ISFIDV_E SCON3[2] ISFID_E[1:0] SCON3[1:0] 0
2 1
4 2
6 3
Odd 1 ISFIDV_O SCON3[5] ISFID_O[1:0] SCON3[4:3] 0
3 1
5 2
7 3
Output Even 0 OSFIDV_E SCON3[10] OSFID_E[1:0] SCON3[9:8] 0
2 1
4 2
6 3
Odd 1 OSFIDV_O SCON3[13] OSFID_O[1:0] SCON3[12:11] 0
3 1
5 2
7 3
Input/
Output Selected
Even/Odd
Subframe
Control Field
Name Location Description
Input Even ISFVEC_E[15:0] SCON4[15:0] See Figure 50 on page 176.
Odd ISFVEC_O[15:0] SCON5[15:0] See Figure 50 on page 176.
Output Even OSFVEC_E[15:0] SCON6[15:0] See Figure 50 on page 176.
Odd OSFVEC_O[15:0] SCON7[15:0] See Figure 50 on page 176.
Input/
Output Selected
Even/Odd
Subframe
Control Field Description
Name Location
Output Even OSFMSK_E[15:0] SCON8[15:0] See Figure 50 on page 176.
Odd OSFMSK_O[15:0] SCON9[15:0] See Figure 50 on page 176.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Less (continued)
Subframe and Channel Selection in Channel Mode
Fig ure 5 0. Su bf ram e a n d C ha n ne l Sel ect i on in Cha nnel Mo de
0
SELECT SUBFRAME 6 (〈I,O〉SFID_E = 3)
ISFVEC_E[15:0] (if ISFIDV_E = 1)
OS FVEC_E[15:0] (if OS FIDV_E = 1)
OS FMSK_E[15:0] (if OSFIDV_E = 1)
ISFVEC_O[15:0] (if ISFIDV_O = 1)
OS FVEC_O[15:0] (if OSFIDV_O = 1)
OSFMSK_O[15:0] (if OSFIDV_O = 1)
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
10
BIT
11
BIT
12
BIT
13
BIT
14
BIT
15
BIT
96
CH
97
CH
98
CH
99
CH
100
CH
101
CH
102
CH
103
CH
104
CH
105
CH
106
CH
107
CH
108
CH
109
CH
110
CH
111
CH
64
CH
65
CH
66
CH
67
CH
68
CH
69
CH
70
CH
71
CH
72
CH
73
CH
74
CH
75
CH
76
CH
77
CH
78
CH
79
CH
32
CH
33
CH
34
CH
35
CH
36
CH
37
CH
38
CH
39
CH
40
CH
41
CH
42
CH
43
CH
44
CH
45
CH
46
CH
47
CH
0
CH
1
CH
2
CH
3
CH
4
CH
5
CH
6
CH
7
CH
8
CH
9
CH
10
CH
11
CH
12
CH
13
CH
14
CH
15
CH
SELECT SUBFRAME 0 (〈I,O〉SFID_E = 0)
SELECT SUBFRAME 4 (〈I,O〉SFID_E = 2)
SELECT SUBFRAME 2 (〈I,O〉SFID_E = 1)
0
SELECT SUBFRAME 7 (〈I,O〉SFID_O = 3)
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
10
BIT
11
BIT
12
BIT
13
BIT
14
BIT
15
BIT
112
CH
113
CH
114
CH
115
CH
116
CH
117
CH
118
CH
119
CH
120
CH
121
CH
122
CH
123
CH
124
CH
125
CH
126
CH
127
CH
80
CH
81
CH
82
CH
83
CH
84
CH
85
CH
86
CH
87
CH
88
CH
89
CH
90
CH
91
CH
92
CH
93
CH
94
CH
95
CH
48
CH
49
CH
50
CH
51
CH
52
CH
53
CH
54
CH
55
CH
56
CH
57
CH
58
CH
59
CH
60
CH
61
CH
62
CH
63
CH
16
CH
17
CH
18
CH
19
CH
20
CH
21
CH
22
CH
23
CH
24
CH
25
CH
26
CH
27
CH
28
CH
29
CH
30
CH
31
CH
SELECT SUBFRAME 1 (〈I,O〉SFID_O = 0)
SELECT SUBFRAME 5 (〈I,O〉SFID_O = 2)
SELECT SUBFRAME 3 (〈I,O〉SFID_O = 1)
EVEN SUBFRAMES
ODD SUBFRAMES
ACTIVATE/MASK CHANNEL CONTROL:
ACTIVATE/MASK CHANNEL CONTROL:
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.13 Chan nel Mode—Up to 128 Channels in a
Maximum of Eight Subfra me s
The SIU has the ab ilit y to p ro c e s s a maximu m o f
128 channel s in channe l mode if the SIU control is
properly synchronized with core intervention. The
steps required for the additional channel processing
are the same as for the channel m ode discus sed in
Section 4.16.12, beginning on page 171. However, the
SIU control registers must be reconfigured with greater
frequency, costing additional core overhead. In this
case, subframe activation and channel definition within
a subframe can occur as often as every subframe
boundary.
The SIU has the ability to interrupt either core at frame
boundaries, subframe boundaries, channel bound-
aries, or if an error is detected (overflow or underflow).
The interrupt signal trigger is determined by the
IINTSE L [1:0] fi e l d ( SCON10[12:11]—s ee Table 113 on
page 191) fo r input processing and by the
OINTSEL[1:0] field (SCON10[ 14:1 3]) for output
processing. When servicing subframe boun dary inter-
rupts generated by SIU0 or SIU1, either CORE0 or
CORE1 can modify the input and output subframe and
channel control fields without affecting the current sub-
frame being processed. S pecifically, the cores can
modify the OSFID_E [1:0] and OSFI D_O[ 1:0] fields
(SCON3—see Table 106 on page 188), the
ISFID_E[1:0] and ISFID_O[1 :0] fields (SCON3—see
Table 106 on page 188 ), the ISFVEC_ E[15: 0] field
(SCON4—see Table 107 on page 189), the
ISFVEC_O[15:0] field (SCON5—see Table 108 on
page 189), the OSF VEC_E [ 15:0] field (SCON6—see
Table 109 on page 190 ), the OSFVEC_O[15:0] field
(SCON7—see Table 110 on page 190), the
OSFMSK_E[15:0] field (SCON8—see Table 111 on
page 190), and the OSFMSK_O[15:0] field
(SCON9—see Table 112 on page 190). T his is al so
true for the ICIX0, ICIX1, OCIX0, and OCIX1 registers
(see Table 122 on page 199 and Ta ble 121 on
page 198). The SIU latches the values in these control
bit fields at the beginning of every subframe.
If one of the cores uses this feature in an SIINT or
SOINT interrupt service routine (ISR), the SIU can be
programmed to individually select channels for input or
outpu t anywhere within the frame. The use r can take
advantage of t his feature by updating the input and out-
put subframe and channel control fi elds after each sub-
frame is processed, allowing channels in more than two
subfram es to be processed during each frame. This
requires the ISR to count the subframe interrupts an d
program the neces sary SIU control registers with the
appropriat e values to process the next desired sub-
fram e. Th e user also has the option of programming
the input and output subframe and chan nel control
fields two subframes in advance, because these bit
fields are double-buff ered. For example, if the active
subframe is even, the user’s ISR can reprogram the
control bit fields with the appropriate values for t he nex t
even subframe without disturbing the processing of the
currently active subframe.
In channel mode, the SIU drives data onto the SOD pin
only during the time slots for active output channels.
Other wise, the SIU 3-states S OD. Similar ly, i n channel
mode, the SIU latches input data bits only during the
time slots for active input channels.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.13 Chan nel Mode— Up to 128 Channels in a Maximum of Eight Subfra mes (continued)
Figure 51 illustrates the conditions under which the SIINT or SOINT input or output interrupt is asserted if the
IINTSEL[1:0] or OINTSEL[1:0] field (SCON10[12:11] or SCON10[14:13]—see Table 113 on page 191) is pro-
grammed to cause the SIU to generate interrupts on subframe boundaries. The SIU computes the current channel
number mod ulo 16. It compares this value to 15 and generates SIINT or SOINT if th ere is a match. This not ifies
the cores of the completion of the subframe.
Generating Interrupts on Subframe Boundaries
Figure 51. Generating Interrupts on Subframe Boundaries
96
CH
97
CH
98
CH
99
CH
100
CH
106
CH
107
CH
108
CH
109
CH
110
CH
111
CH
64
CH
65
CH
66
CH
67
CH
68
CH
74
CH
75
CH
76
CH
77
CH
78
CH
79
CH
32
CH
33
CH
34
CH
35
CH
36
CH
42
CH
43
CH
44
CH
45
CH
46
CH
47
CH
0
CH
1
CH
2
CH
3
CH
4
CH
10
CH
11
CH
12
CH
13
CH
14
CH
15
CH
SELECT SUBFRAME 7 (〈I,O〉SFID_O = 3) 112
CH
113
CH
114
CH
115
CH
116
CH
122
CH
123
CH
124
CH
125
CH
126
CH
127
CH
80
CH
81
CH
82
CH
83
CH
84
CH
90
CH
91
CH
92
CH
93
CH
94
CH
95
CH
48
CH
49
CH
50
CH
51
CH
52
CH
58
CH
59
CH
60
CH
61
CH
62
CH
63
CH
16
CH
17
CH
18
CH
19
CH
20
CH
26
CH
27
CH
28
CH
29
CH
30
CH
31
CH
SELECT SUBFRAME 1 (〈I,O〉SFID_O = 0)
SELECT SUBFRAME 5 (〈I,O〉SFID_O = 2)
SELECT SUBFRAME 3 (〈I,O〉SFID_O = 1)
EVEN SUBFRAMES
ODD SUBFRAMES
SELECT SUBFRAME 6 (〈I,O〉SFID_E = 3)
SELECT SUBFRAME 0 (〈I,O〉SFID_E = 0)
SELECT SUBFRAME 4 (〈I,O〉SFID_E = 2)
SELECT SUBFRAME 2 (〈I,O〉SFID_E = 1)
(CURRENT CHANNEL NUMBER)MO DULO 16 = 15
(CURRENT CHANNEL NUMBER)MO DULO 16 = 15
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.13 Chan nel Mode—Up to 128 Channels in a
Maximum of Eight Subfra me s (continued)
For example, the following steps are performed by soft-
ware running in CORE0 to use SIU0 to process inpu t
channels 2, 3, 18, 20, 36, 55, 78, 100, and 111 as part
of a 128-channel input frame. I t is assumed that the
DMAU SWT0 and SWT1 channels are used to transfer
the input data to memory.
1. Ini tialize the SWT0 and SW T1 channel s (see
Section 4.13. 5 on page 87).
2. Conf igure the channel size (4 bits, 8 bits, 12 bits, or
16 bits) by writing the ISIZE[1:0] field
(SCON0[4:3]—Table 103 on page 185 ). Select
LSB-first or MSB-first by programming the IMSB field
(SCON0[2]). Configure the data for mat by program-
ming the IFOR MAT[1: 0] field (SCON0[1:0]).
3. Conf igure SIU0 for a 128-channel input frame struc-
ture by programming the IFLIM[6:0] field
(SCON1[6:0]—Table 104 on page 186 ) t o
127. Enable channel mode with two active sub-
frames by clearing the IFRAME field (SCON1[7])
and setting the ISFIDV_E and ISFIDV_O fields
(SCON3[2,5]—Table 106 on page 188 ). P rogram
input interrupts to occur at every subframe boundary
by programming the IINTSEL[1:0] field
(SCON10[12:11]—Table 113 on page 191) to 0x1.
4. P rogram SIU0 with th e active channels for the first
even (channels 2 and 3) and odd (18 and 20)
subframes. This is a ccompl ished by writing the first
subframe IDs (0 and 1) to the ISFID_E[1:0] and
ISFID_O[1:0] fields (SCON3—see Table 106 on
page 188) and enabling the channels within these
subframes via the ISFV EC_ E[15:0] field
(SCON4—see Table 107 on page 189) and
ISFVEC_O[15:0] field (SCON5—see Table 108 on
page 189). In summary, ISFID_E[1:0] = 0,
ISFID_O[1:0] = 0, ISVEC_E[15:0] = 0xC, and
ISVEC_O[15:0] = 0x14.
5. Program the input channel index registers to assign
each channel to either SWT0 or SWT1. The SWT
channel chosen determ ines the dest ination of the
data. In this example, channels 2 and 18 are
assigned to SWT0, and channels 3 and 20 are
assigned to SWT1. Theref ore, ICIX0 = 0x8 and
ICIX1 =0x10.
6. E nable the SIINT interrupt (see Section 4.4.6 on
page 31) and the SWT0 and SWT1 channels of the
DMAU by setting the DRUN[1:0] fields
(DMCON0[5:4]—Table 31 on page 71 ). Create a
softw are-managed s ubframe count er and initialize
the count er to zero. Clea r the IRESET field
(SCON1[10]—see Tab le 104 on page 186) to begin
input data processing by SIU0. CORE0 can con-
tinue to process the user’s application.
7. When the SIINT interrupt occurs, CORE0’ s ISR
immedia tely reads the software-mana ged subframe
counter to determine the current subframe in
progress and increm ent s the counter by one. The
ISR then reprograms the SIU to process the next
even subframe. In this example, the next even sub-
fram e is 2, so ISF ID_E[1: 0] is p rogram med to
0x1. The active channel for this subframe is 36, so
ISVEC_E[15:0] is written with 0x10. ICIX0 also must
be reprogrammed to assign channel 36 to either
SWT 0 or SWT1. If SWT1 is selected, then
ICIX0 = 0x10. This active channel setting takes
place at the next sub frame boundary. This ISR is
now complete and CORE 0 returns to the previous
activity.
8. When the next SIINT interrupt occurs, CORE0’s IS R
again reads the subf rame counter to determine the
current subframe in progress. If the counter value i s
7, it is re s et to zer o; oth er w i se, the value is incr e -
mented by one. The ISR then reprogr ams SIU0 to
process the next odd subframe. In this example, the
next odd subframe is 3, so ISFID_O[ 1:0] is pro-
grammed to 0x1. The desired active channel for this
subframe is 55, so ISVEC_O[15:0] is written with
0x80. ICIX1 must also be rep rogrammed t o assign
chan nel 55 to either SWT0 or SWT1. If SWT1 is
selec ted, then ICIX1 = 0x80. T his ac tive channel
setting takes place at the next subframe
boundary. This ISR is now complete, and CORE0
returns to the previous activity.
9. Steps 7 and 8 are repeated indefinitely, processing
all eight subframes and then beginning again with
subfram e 0 of the next frame.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.14 SIU Examples
The following section s illustrate examples of single-chan nel I/O and the ST-bus interface.
4.16.14.1 Single-Channe l I/O
If the SIU is interfaced directly to a single codec, the program typically configures the SIU as follows:
1. E nable frame m ode operat ion, one channel per frame.
2. Conf igure the data length as required by the external device (4 bi ts, 8 bits, 12 bits, or 16 bits).
3. E nable pass ive bit clocks and frame syncs, configured as required by the external device. See Table 93 on
page 165.
This configuration assum es that the codec device generates the bit clock and frame sync.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.14 SIU Examples (continued)
4.16.14.2 ST-Bus I nterface
The SIU is compatible with the
MITEL
® ST-bus. B oth single-rate and double-rate clock protocols are supported.
Table 100 desc ribes the SIU control field se ttings and resulting signals for both proto cols.
Tabl e 100. Co ntrol R eg i ster and Fie ld Co nf igur ation for ST-Bus I nterface
Control Field De scription Va lue
(Single-Rate
Clock)
Value
(Double-Rate
Clock)
OSIZE[1:0] SCON0[12:11] Clear for 8-bit output data. 00 00
ISIZE[1:0] SCON0[4:3] Clear for 8-b it input data. 00 00
I2XDLY SCON1[11] Set to extend high phase of ICK. 0 1
IFSDLY[1:0] SCON1[9:8] Clear for no IFS del ay. 00 00
OFSDLY[1:0] SCON2[9:8] Clea r fo r no OFS delay. 00 00
OFSE SCON3[15] For active OFS, selec ts whet her OFS is driven onto SOFS
pin. 00
OCKE SCON3[14] Clear to not drive active OCK onto SOCK pin. 0 0
IFSE SCON3[7] For active IFS, selects whether IFS is driv en onto SIFS pin. 0 0
ICKE SCON3[6] Clear to not drive active ICK ont o SICK pi n. 0 0
SIOLB SCON10[8] Clea r to disable loopba ck. 0 0
OCKK SCON10[7] Clear to driv e output data on ri sing edge of output bit clock. 0 X
OCKA SCON10[6] Clear to select passive OCK. Se t to select active OC K . 0 1
OFSK SCON10[5] Set to invert OFS (active-low frame sync). 1 X
OFSA SCON10[4] Clear to select passive OFS. Set to select active OFS. 0 1
ICKK SCON10[3] Clea r to capture input data on fall ing edge of input bit cl ock. 0 X
ICKA SCON10[2] Clear to sele ct pa ssive ICK . Set to se lect active ICK . 0 1
IFSK SCON10[1] Set to invert IFS. 1 1
IFSA SCON10[0] Clear to select passive IFS. Set to select active IFS. 0 1
AGCKLIM[7:0] SCON11[7:0] Active bit clock divide ratio. X 1
(ICK and OCK
are SCK/ 2)
AGRESET SCON12[15] Clear to activate act ive clock and fr am e sync generator. 0 0
AGSYNC SCON12[14] Set to synchronize acti ve generat ed bit clocks to SIFS pin. 0 1
SCKK SCON12[13] Set to invert SCK. Clear if AGEXT is cleared. 0 1
AGEXT SCON12[12] Clear to sel ect CLK as s our ce for ac tive c lock and fr ame sync
generator. Set to select SCK as source for active clock and
frame sync generator.
01
AGFSLIM[10:0] SCON12[10:0] Active frame sync di vide ratio. X 0x3FF
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.14 SIU Examples (continued)
4.16.14.2 ST-Bus I nterface (continued)
Table 101 describes the SIU control registers and control register fields that must be configured as required by the
particular system applicat ion using an ST-b us interface.
Table 101. Cont rol Register and Fields That Are Configured as Required for ST-Bus Interface
Contr ol Regist er or
Field Description
OMSB SCON0[10] Selects LSB- or MSB-f irst out put data.
OFORMAT[1:0] SCON0[9:8] Sele cts linear, µ-law, or A- law output for m at.
IMSB SCON0[2] Selects LSB- or MSB-first input data.
IFORMAT[1:0] SCON0[1: 0] Selects li near, µ- law, or A-law input format.
IFRAME SCON1[7] Clea r to sel ect input channel mo de. Set to select input fr ame mo de.
IFLIM[6:0] SCON1[6:0] Progr am to 127 for 128 channels per input frame.
OFRAME SCON2[7] Clear to sel ect output channel m ode. Set to select output frame mode.
OFLIM[6:0] SCON2[6:0] Progr am to 127 f or 128 channel s per output fr am e.
OSFIDV_O SCON3[13] Set to enabl e odd output subframes.
OSFID_O[1:0] SCON3[12:11] Selects odd output subframe 1, 3, 5, or 7.
OSFIDV_E SCON3[10] Set to enable even output subframes.
OSFID_E[1:0] SCON3[9:8] Selects even output subframe 0, 2, 4, or 6.
ISFIDV_O SCON3[5] Set to enable odd input subframes.
ISFID_O[1:0] SCON3[4 :3] Se lec ts odd inpu t su bfr a m e 1, 3, 5, or 7.
ISFIDV_E SCON3[2] Set to enable even input subframes.
ISFID_E[1:0] SCON3[1: 0] Selects even input subframe 0, 2, 4, or 6.
ISFVEC_E[15:0] SCON4[15:0] Set to enable corresponding channel of the selected even input subframe.
ISFVEC_O[15:0] SCON5[15:0] Set to enable corresponding channel of the selected odd input subframe.
OSFVEC_E[15:0] SCON6[15:0] Set to enable corresponding channel of the selected even output subf rame.
OSFVEC_O[15:0] SCON7[15:0] Set to enable corresponding channel of the selected odd output subframe.
OSFMSK_E[15:0] SCON8[15:0] Set to mask corresponding channel of the selected even output subframe.
OSFMSK_O[15:0] SCON9[15:0] Set to mask corresponding channel of the selected odd output subframe.
OINTSEL[1:0] SCON10[14:13] Selects one of four conditions for which the SIU output interrupt (SOINT) is asserted.
IINTSEL[1:0] SCON10[12:11] Selects one of four conditions for which the SIU input interrupt (SIINT) is asserted.
ICIX0[15:0] I nput c hannel index for the activ e even input subf rame—selects one of two DMAU SWT channel s (SWT0
or SWT1 for SIU0 ; SWT2 or SWT3 for SIU1) for each logi cal chann el i n the active even input subf rame.
ICIX1[15:0] I nput channel index for the acti ve odd input sub frame—s elect s one of two DMAU SWT channe ls (SWT0
or SWT1 for SIU0 ; SWT2 or SWT3 for SIU1) for each logi cal chann el i n the active odd i nput subframe.
OCIX0[15:0] Input channel index for the acti ve even outp ut subfram e—s elects one of two DMAU SWT cha nnels
(SWT0 or SWT1 for SIU0; SWT2 or SWT3 for SIU1) for each logical channel in the active even output
subframe.
OCIX1[15:0] Input channel index for the acti ve odd outpu t subframe —se lects one of two DMAU SWT chan nels
(SWT0 or SWT1 for SIU0; SWT2 or SWT3 for SIU1) for each logi cal chan nel in the active odd output
subframe.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.14 SIU Examples (continued)
4.16.14.2 ST-Bus I nterface (continued)
Figure 52 illustrates ST-bus operation with a single-rate clock.
ST-Bus Single Rate Clock
Fi gure 52. S T-Bus Si ngle -Rate Cl oc k
Figure 53 illustrates ST-bus operation with a double-rate clock applied to SCK, with an active mode bit cloc k and
output frame sync generat ion for internal use only. In addition , this figure assumes the use of SIFS for external
clock sy nchr onizati on (AGSYNC = 1) of both the in put and ou tput bi t clocks. ICK, OCK, IFS , and OFS are t he inte r-
nally generated bit clocks and frame sync s. Refer to Figure 40 on page 155 to review the block diagram of the
internal clock generator.
ST- Bus Double Rate Clock
Figure 53. ST-Bus Double-Rate Clock
S〈IO〉CK
S〈IO〉FS
SID B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2
SOD B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2
ICK
OCK
SID
IFS
B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2
SOD B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2
SCK
ICK
OCK
OFS
SIFS
CAPTURE
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers
Each SIU contains 21 contro l, status, and data regis-
ters as summarized in Table 102. These can be func-
tionally grouped as:
Thirteen control registers (SCON〈0—12〉)
Two status registers (STAT and FSTAT)
One read-only input data register (SIDR)
One write-only output register (SODR)
Two input channel ind ex registers (ICIX〈0—1〉)
Two out put channel index registers (OCIX〈0—1〉)
All of these 16-bit registers are aligned on even
addres ses in DSP16411 s hared I/O memo ry space.
The rema inder of this section provides detail on each
of these registers.
Table 102 summar izes all th e SIU memor y -mapped
registers. Tables 103 through 121 des cribe each regis-
ter individually.
Table 102. SIU Registers
Register
Name Address Description Size
(Bits)†R/W Type‡Reset
Value
SIU0 SIU1
SCON0 0x43000 0x44000 SIU Input/Output General Control 16 R/W control 0x000 0
SCON1 0x43002 0x44002 SIU Input Frame Control 0x0400
SCON2 0x43004 0x44004 SIU Outp ut Frame Control 0x0400
SCON3 0x43006 0x44006 SIU Input/Output Subframe Control 0x0000
SCON4 0x43008 0x44008 SIU Input Even Subfram e Vali d Vector Cont rol 0x0000
SCON5 0x4300A 0x4400A SIU In put Odd Subfra me Valid V ecto r Control 0x0000
SCON6 0x4300C 0x4400C SIU Output Even Subframe Valid Vector Contro l 0x0000
SCON7 0x4300E 0x4400E SIU Output Odd Subframe Valid Vec tor Control 0x0000
SCON8 0x43010 0x44010 SIU Outp ut Even Subframe Mas k Vector Cont rol 0x0000
SCON9 0x43012 0x44012 SIU Outp ut Odd Subframe Mask V ector Control 0x0000
SCON10 0x43014 0x44014 SIU Input/Output Gene ral Control 0x0000
SCON11 0x43016 0x44016 SIU Input/Output Acti ve Clock Cont rol 0x0000
SCON12 0x43018 0x44018 SIU Input/Output Active Frame Sync Control 0x8000
SIDR 0x4301A 0x4401A SIU Input Data 16 R data 0x0000
SODR 0x4301C 0x4401C SIU Output Data W
STAT 0x4301E 0x4401E SIU Input/Output General Stat us 16 R/W§c & s 0x0000
FSTAT 0x43020 0x44020 SIU Input/Output Frame Status 16 R status 0x0000
OCIX0 0x43030 0x44030 SIU Output Channel Index for Even Subfram es 16 R/W control 0x0000
OCIX1 0x43032 0x44032 SIU Output Channel Index for Odd Subframes
ICIX0 0x43040 0x44040 SIU In put Channel Index for Even Subframes 16 R/W contr ol 0x0000
ICIX1 0x43042 0x44042 SIU In put Channel Index for Odd Subframes
† The SI U memor y-mapped regi ster size s repre sent bi ts used. The regi sters are ri ght -j usti fied and padded to 32 bi ts (the unused upper bits are zero-
filled).
‡ c & s mean s control and s tatus.
§ All bits of STAT are readable, an d some ca n be writ ten wit h one to cl ear them .
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 103. SCON0 (SIU Input/Output General Control) Register
The memory address for this register is 0x43000 for SIU0 and 0x44000 for SIU1.
15—13 12—11 10 9—8 7—5 4—3 2 1—0
Reserved OSIZE[1:0] OMSB OFORMAT[1:0] Reserved ISIZE[1:0] IMSB IFORMAT[1:0]
Bit Field Value Description R/W Reset Value
15—13 Reserved 0 Reserved—write with zero. R/W 0
12—11 OSIZE[1:0]†0 The channel size for serial output data is 8 bits ‡.R/W0
1 The channel size for seri al output dat a is 16 bits.
2 The channel size for seri al output dat a is 4 bits‡.
3 The channel size for seri al output dat a is 12 bits‡.
10 OMSB†0 Shift data out onto SO D pin le ast significant bit (LSB) first. R/W 0
1 Shift data out onto SOD pin most significant bit (MSB) first.
9—8 OFORMAT[1:0]†00 When trans ferring dat a from the SODR register to the out put shift regis-
ter, do not format (modify) the data. R/W 00
01 Reserved.
10 When trans fer ring 16-bit data fr om the SODR r egister to the output shift
register, convert the most sig nificant 14 bits of SODR (SODR[ 15:2] ) from
lin ear PCM format to 8-bit µ-law PCM f ormat, place the result into the
lower half of the output shift register, and clear the upper half. Ignore the
least significant 2 bit s of SODR.
11 When trans fer ring 16-bit data fr om the SODR r egister to the output shift
register, convert the most sig nificant 13 bits of SODR (SODR[ 15:3] ) from
lin ear PCM format to 8-bit A-law PCM f ormat, place the result into the
lower half of the output shift register, and clear the upper half. Ignore the
least significant 3 bit s of SODR.
7—5 Reserved 0 Reserved—write with zero. R/W 0
4—3 ISIZE[1:0]§0 The channel size for seri al input data is 8 bits††.R/W0
1 The channel size for seri al input dat a is 16 bits.
2 The channel size for seri al input dat a is 4 bits††.
3 The channel size for seri al input dat a is 12 bits††.
2IMSB
§0 Capture input data fr om SID pin least signif icant bit (LSB) firs t. R/W 0
1 Capture input data fr om SID pin most significant bit (MSB) first.
1—0 IFORMAT[1:0]§00 When t ra nsferr ing 16- bit d ata fr om the SIB‡‡ regi ster t o the SIDR regis ter,
do not for m at (modify) the data. R/W 00
01 Reserved.
10 When trans fer ring data from the SIB‡‡ re gister to the SIDR register, con-
vert the lower 8 bits of SIB (SIB[7:0]) fro m µ-law PCM format to 14- bit li n-
ear PCM format, place the result into the 14 most significant bits of SIDR
(SIDR[15:2]), and clear the least signifi cant 2 bits of SIDR (SIDR[1:0]).
11 When trans fer ring data from the SIB‡‡ re gister to the SIDR register, con-
vert the lower 8 bits of SIB (SIB[ 7 :0]) fr o m A-law P C M format to 13-b it li n -
ear PCM format, place the result into the 13 most significant bits of SIDR
(SIDR[15:3]), and clear the least signifi cant 3 bits of SIDR (SIDR[2:0]).
† If the ORESET field (SCON2[10]) is cleared, do not change the value in this field.
‡ T he SIU shifts data from the low portion of the out put shift regis ter onto the S OD pin an d ignores the high portion of the register.
§ If the IRESET field (SCON1[10]) is cleared, do not change the value in this field.
†† The SIU right justifies the received serial input data, i.e., it places the data in the least significant bit positions of the 16-bit serial i nput bu ffer
register an d fill s the upper bits with ze ros.
‡‡ The SIB register is an intermediate register that holds the contents of the input shift register and is not user accessible.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
186 A gere System s— P rop rietary Agere Systems Inc.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 104. SCON1 (SIU Input Fram e Control) Register
The memory address for this register is 0x43002 for SIU0 and 0x44002 for SIU1.
15—12 11 10 9—8 7 6—0
Reserved I2XDLY IRESET IFSDLY[1:0] IFRAME IFLIM[6:0]
Bit Field Value Description R/W Reset
Value
15—12 Reserved 0 Reserved—write with zero. R/W 0
11 I2XDLY†0 Do not st ret ch the active genera ted input bit clock (ICK) r elative to the acti ve-
mod e generated output bit cl ock (OCK), i.e., ICK and OCK are identical and in-
phase.
R/W 0
1 Stretch the hi gh phase of the acti ve generat ed input clock (ICK) by one SCK
phase rela ti ve to the active generated outp ut bi t cl ock (OCK) to provi de addi-
tional input seri al data capture time.
10 IRESET 0 Activate input section and begin input processing at the start of the first active
input chan nel. R/W 1
1 Deactiv ate i nput section and initiali ze bit and frame counte rs.
9—8 IFSDLY[1:0]†00 No input frame sync del ay— capture input data from SID pin starting with the
sam e internal bit clock (ICK) that latches t he inp ut fram e sync (SIFS pi n for pas-
sive sync or IFS signal for active generated sync).
R/W 00
01 One -cycl e input frame syn c del ay—cap ture i nput dat a from SI D pin sta rtin g one
bit clock (I CK) after the bit cloc k that latches the input frame sync (SIFS pin for
passive sy nc or IFS signal f or active generat ed sync).
10 Two-cycle input frame sync delay—capture inpu t dat a fro m SID pi n starting two
bit clocks ( ICK) after t he bit cl ock that latches the in put frame sy nc (SIFS pin for
passive sy nc or IFS signal f or active generat ed sync).
11 Reserved.
7IFRAME
†0Channel mode—b ase the input tr ansfer decision on the ISFIDV_E fie ld
(SCON3[2]), the ISFVEC_E[15:0] field (SCON4[15:0]), the ISFIDV_O field
(SCON3[5]), and the ISFVEC_ O[15:0] fi eld (SCON5[15:0]).
R/W 0
1 Frame m ode—capture all IFLI M + 1 channel s in the frame.
6—0 IFLIM[6:0]†0—127 Input fram e channel cou nt l imit—t he num ber of chann els in the input frame is
IFLIM + 1. R/W 0
† If the IR ESET f i el d (SCON1[10] ) i s clea red, do not change th e value in t hi s field.
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. Agere Systems—Prop ri etary 187
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any instructions
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 105. SCON2 (SIU Output Frame Contro l) Register
The memory address for this register is 0x43004 for SIU0 and 0x44004 for SIU1.
15—11 10 9—8 7 6—0
Reserved ORESET OFSDLY[1:0] OFRAME OFLIM[6:0]
Bit Field Value Description R/W Reset
Value
15—11 Reserved 0 Reser ved— wri te with zero. R/W 0
10 ORESET 0 Activate outp ut sect ion, r eques t output ser vice f rom the DMAU, an d drive SOD
pin at the start of the first active output channel. R/W 1
1 Deactivate output section and i nitialize bit and frame counters.
9—8 OFSDLY[1:0]†00 No output fr am e sync dela y—d rive output data onto SOD pin st arting wit h the
same internal b it clo ck (OCK) that latches t he out put f rame sync (SOF S pi n for
passive sync or OFS signal for active generated sync).
R/W 00
01 One-cycle output frame sync delay—drive output data onto SOD pin starting
one bit clock (OCK) after the bit clock that latches the output frame sync
(SOFS pin for passive sync or OFS signal for active generat ed sync).
10 Two-cycle output frame sync delay—drive output data onto SOD pin starting
two bit clocks (OCK) after the bit clock that latches output frame sync (SOFS
pin for passive sync or OFS signal for active generated sync).
11 Reserved.
7OFRAME
†0Channel mode—base the out put transfer decisi on on the OSFIDV_E field
(SCON3[10]), the OSFVEC_E[ 15:0] fie ld (SCON6[15:0]), the OSFIDV_O field
(SCON3[13]), and the OSFVEC_O[15:0] fie ld (SCON7[15:0]).
R/W 0
1 Frame mode—transmit all OFLIM + 1 channels in the frame.
6—0 OFLIM[6:0]†0—12 7 Outp ut frame channel count limit—t he num ber of channels in t he output frame
is OFLIM + 1. R/W 0
† If the ORESET field (SCON2[10] ) i s c le ared, do not change the value in th i s field.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
188 A gere System s— P rop rietary Agere Systems Inc.
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ursuant to Com
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 106. SCON3 (SIU Input/Ou tput Subfram e Con trol) Register
The memory address for this register is 0x43006 for SIU0 and 0x44006 for SIU1.
15 14 13 12—11 10 9—8
OFSE OCKE OSFIDV_O OSFID_O[1:0] OSFIDV_E OSFID_E[1:0]
7 6 5 4—3 2 1—0
IFSE ICKE ISFIDV_O ISFID_O[1:0] ISFIDV_E ISFID_E[1:0]
Bit Field Value Description R/W Reset
Value
15 OFSE
(acti ve mode only) 0 Do not drive int ernally generated fr am e sync onto SOFS pin . R/W 0
1 Drive internally generated frame sync onto SOFS pin.
14 OCKE
(acti ve mode only) 0 Do not drive int ernally generated cl ock onto SOCK pin. R/W 0
1 Drive internally generated clock onto SOCK pin.
13 OSFIDV_O
(channel mode only) 0 Odd output subframe vector valid. Disable odd output subframes. In frame
mode (OFRAME(SCON2[7]) = 1), this fi eld must be cleared. R/W 0
1 Odd output subframe vect or val id. Enable odd output subframes.
12—11 OSFID_O[1:0]
(channel mode only) 00 F or odd subfram es, the output subframe ID of the subframe under
control of t he OSFVEC_O[15:0] field (SCON7[15:0]) and the
OSFMSK_O[15:0] field (SCON9[1 5:0]) i s:
2 × OSFID_O + 1
as shown at right.
1R/W00
01 3
10 5
11 7
10 OSFIDV_E
(channel mode only) 0 Even output subframe vector valid. Disable even output subframes. In
frame mode (OFRAME(SCON2[7]) = 1), thi s fi eld must be cleared. R/W 0
1 Even output subframe vector valid. Enable even output subframes.
9—8 OSFID_E[1:0]
(channel mode only) 00 For even subframes, the output subframe ID of the subframe under
control of t he OSFVEC_E[15 :0] field (SCON6[15:0]) and the
OSFMSK_E[15:0] field (SCON8[ 15:0]) is:
2 × OSFID_E
as shown at right.
0R/W00
01 2
10 4
11 6
7IFSE
(acti ve mode only) 0 Do not drive int ernally generated fr am e sync onto SIFS pin. R/W 0
1 Active m ode only. Drive internally generated fr am e sync onto SIFS pin.
6ICKE
(acti ve mode only) 0 Do not drive int ernally generated cl ock onto SICK pin. R/W 0
1 Active m ode only. Drive internally generated cl ock onto SICK pin.
5 ISFIDV_O
(channel mode only) 0 Odd input subframe vector valid. Disable odd input subframes. In frame
mode (OFRAME(SCON2[7]) = 1), this fi eld must be cleared. R/W 0
1 Odd input subframe vector valid. Enabl e odd input subframes.
4—3 ISFID_O[1:0]
(channel mode only) 00 F or odd subf rames, the input subframe I D of the subframe under c on-
trol of the ISFVEC_O[15:0] field (SCON5[15:0]) is:
2 × ISFID_O + 1
as shown at right.
1R/W00
01 3
10 5
11 7
2 ISFIDV_E
(channel mode only) 0 Even in put subframe vector vali d. Disable even input subframes. In frame
mode (OFRAME(SCON2[7]) = 1), this fi eld must be cleared. R/W 0
1 Even input subframe vector vali d. Enable even input subfr am es.
1—0 ISFID_E[1:0]
(channel mode only) 00 For even subframes, the input subframe ID of the subframe under
control of t he ISFVEC_E[ 15:0] field (SCON4[15:0]) is:
2 × ISFID_E
as shown at right.
0R/W00
01 2
10 4
11 6
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. Agere Systems—Prop ri etary 189
Use
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any instructions
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 107. SCON4 (SIU Input Even Sub frame Valid Vecto r Control) Register
Tab le 108. SC ON5 (SI U In put Od d S ubf rame Valid Vector Co nt ro l) R egi st er
The memory address for this register is 0x43008 for SIU0 and 0x44008 for SIU1.
15—0
ISFVEC_E[15:0]
Bit Field Value Description R/W Reset
Value
15—0 ISFVEC_E[15:0] 0 The corresponding channel of the selected even input subframe is disabled. R/W 0
1 The corresponding channel of the selected even input subframe is enabled.
The memory address for this register is 0x4300A for SIU0 and 0x4400A for SIU1.
15—0
ISFVEC_O[15:0]
Bit Field Value Description R/W Reset
Value
15—0 IS FVEC_O[15:0 ] 0 The corresponding channel of the sel ected odd i nput subframe is disabled. R/ W 0
1 The corre sponding channel of the sel ected odd input subfram e is enabled.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
190 A gere System s— P rop rietary Agere Systems Inc.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 109. SCON 6 (SIU Output Ev en Subfra m e Val id Vector Control) Register
Table 110. SCON7 (SIU Output Odd Subframe Valid Vector Control) Register
Table 1 11. SCON8 (SIU Output Even Subframe Mask Vector Control) Register
Table 1 12. SCON9 (SIU Output Odd Subframe Mask Vector Control) Register
The memory address for this register is 0x4300C for SIU0 and 0x4400C for SIU1.
15—0
OSFVEC_E[15:0]
Bit Field Value Description R/W Reset
Value
15—0 OSFVEC_E[15:0] 0 The correspo nding chann el of the sel ected ev en output sub fr am e is di sabled . R/W 0
1 The corr espondi ng channel of the sel ected ev en output sub fr am e is enabled.
The memory address for this register is 0x4300E for SIU0 and 0x4400E for SIU1.
15—0
OSFVEC_O[15:0]
Bit Field Value Description R/W Reset
Value
15—0 OSFVEC_O[15:0] 0 The corresponding channel of the selected odd output subframe is disabled. R/ W 0
1 The corresponding channel of the selected odd output subframe is enabled.
The memory address for this register is 0x43010 for SIU0 and 0x44010 for SIU1.
15—0
OSFMSK_E[15:0]
Bit Field Value Description R/W Reset
Value
15—0 OSFMSK_E[15:0] 0 Do not mask the correspondi ng output channel. R /W 0
1 For an acti ve even subfr ame, mask the cor responding output channel (do
not driv e SOD during the output time slot ).
The memory address for this register is 0x43012 for SIU0 and 0x44012 for SIU1.
15—0
OSFMSK_O[15:0]
Bit Field Value Description R/W Reset
Value
15—0 OSFMSK_O[15:0] 0 Do not mask the corresponding output channel. R/W 0
1 For an active odd subframe, mask the corresponding output channel (do
not dri ve SOD during the output time sl ot).
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. Agere Systems—Prop ri etary 191
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 113. SCO N10 (SIU Input/Output General Control ) Register
The memory address for this register is 0x43014 for SIU0 and 0x44014 for SIU1.
15 14—13 12—11 10—9 8 7 6 5 4 3 2 1 0
Reserved OINTSEL[1:0] IINTSEL[1:0] Reserved SIOLB OCKK OCKA OFSK OFSA ICKK ICKA IFSK IFSA
Bit Field Value Description R/W Reset
Value
15 Reserved 0 Reserved—write with zero. R/W 0
14—13 OIN TSEL[1:0] 00 Asse rt output inter rupt (S OINT) after out put fram e sync detected. R/W 00
01 Assert output interrupt (SOINT) after output subframe transfer complete.
10 Assert output interr upt (SOINT) aft er output channel transfer com plete.
11 Assert output interrupt (SOI NT) after out put frame erro r or ou tput un derf low er ror
occurs†.
12—11 IINTSEL[1:0] 00 Assert input interrupt (SIINT) after input frame sync detected. R/W 00
01 Assert input interrupt (SIINT) after input subframe transfer complete.
10 Assert input in terrupt (SIINT) af ter input channel transfer complete.
11 Assert input interrupt (SIINT) after input frame error or input overflow error
occurs†.
10—9 Reserved 0 Reserved—write with zero. R/W 0
8SIOLB
‡0 Normal operation. R/W 0
1 Place SIU in loop back mode (SOD int ernally conn ected to SID, OCK internally
connected to IC K, OFS int ernally connected to IFS).
7OCKK
§0 Drive output data onto the SOD pin on the rising edge of the output bit clock pin
(SOCK).
If OCKA is 0 (passive cloc k), do not invert SOCK to generate the internal out-
put bit clock (OCK).
If OCKA is 1 (active clock), do not invert the active generated output bit clock
(OCK) before applying to the SOCK pin.
R/W 0
1 Drive output data onto t he SOD pin on the falli ng edge of the output bit cl ock pin
(SOCK).
If OCKA is 0 (passive cloc k), invert SOCK to generate the internal output bit
c lock (OC K ).
If OCKA is 1 (active clock), invert the active generated output bit clock (OCK)
before applying to the SOCK pin.
6OCKA
§0 Passive mode output clock††—drive the i nternal output bit clock (OCK) from the
external output bit cl ock pin (SOCK pin mod ified according to OCKK). The SIU
configures SOCK as an input.
R/W 0
1 Activ e mo de output clock—dri ve the internal output bit clock (OCK) fro m the
active generated output bit clock derived from CLK or SCK. The SIU configures
SO CK as an ou tp ut.
† To determine the type of error, the program can read the contents of the STAT regis ter (see Table 118 on pag e 197).
‡If the IRESET field (SCON1[1 0 ]) or ORESET fie ld (SCON2[10]) is cleared, do not change the value in this field.
§If the ORESET field (SCON2[10]) i s cleared, do not change the value in this field.
†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-
sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.
§§ If the IRESET field (SCON1[10]) is clear ed, do not change the valu e i n this fi el d.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
192 A gere System s— P rop rietary Agere Systems Inc.
Use
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any instructions
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
Table 113. SCON10 (SIU Input/Output General Control) Register (continued)
4.16.15 Registers (continued)
5OFSK
§0 The external output frame sync pin (SOFS) is active-high.
If OFSA is 0 (p assive sy nc), do not i nvert SOFS to gener ate the i nternal out put
frame sync (OFS) .
If OFSA is 1 (act ive sy nc) , do not i nvert the act ive gene rat ed output frame sy nc
(OFS) before applying to the SOFS pin.
R/W 0
1 The external output frame sync pin (SOFS) is active-low.
If OFSA is 0 (passive sync) , i nvert SO FS to gener ate the internal output fram e
sync (OFS).
If OFSA is 1 (act ive syn c), inver t the act ive gen erated o utpu t frame s ync (OFS)
before applying to the SOFS pin.
4OFSA
§0Passive mode output frame sync—drive the internal output frame sync (OFS)
from the external output f rame sync pin (SO FS modified according to OFSK and
SCON2[OFSDLY]) . The SIU configur es SOFS as an input.
R/W 0
1 Activ e mo de o utput frame sync††—drive the internal out put fram e sync (OFS)
from the active generated fr am e sync (AGFS) modified according to
SCON2[OFSDLY]. The SIU configures SOFS as an output.
3ICKK
§§ 0 Capture input data from the SID pin on the falling edge of the input bit clock pin
(SICK).
If ICKA is 0 (pass ive clo ck), do not inver t the inp ut bit c lock pi n (SICK) to gener-
ate ICK.
If ICKA is 1 (active clock), do not invert the active generated input bit clock
(ICK) before applying to the SI CK pin.
R/W 0
1 Captur e input data from the SID pin on the risi ng edge of the input bit clock pin
(SICK).
If ICKA is 0 (passive clock), i nvert SICK to generate the internal input bit clock
(ICK).
If ICKA is 1 (active clock), invert the acti ve generat ed input bit clock (ICK)
before applying to the SICK pi n.
2ICKA
§§ 0 Passive mode input bit clock††—drive the internal input bit clock (ICK) from the
external input bit clock pin (SIC K pin modified according to ICKK). The SI U con-
figures SICK as an input.
R/W 0
1 Activ e mode inp ut b it clock —dri ve the i ntern al input b it clock (I CK) fr om the act ive
generated input bit clock derived fr om CLK or SCK. The SIU con fi gures SICK as
an output.
Bit Field Value Description R/W Reset
Value
† To determine the type of error, the program can read the contents of the STAT regis ter (see Table 118 on pag e 197).
‡If the IRESET field (SCON1[1 0 ]) or ORESET fie ld (SCON2[10]) is cleared, do not change the value in this field.
§If the ORESET field (SCON2[10]) i s cleared, do not change the value in this field.
†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-
sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.
§§ If the IRESET field (SCON1[10]) is clear ed, do n ot change the valu e i n this fi el d.
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. Agere Systems—Prop ri etary 193
Use
p
ursuant to Com
p
any instructions
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
Table 113. SCON10 (SIU Input/Output General Control) Register (continued)
4.16.15 Registers (continued)
1IFSK
§§ 0 The exter nal input fr am e sync pin (SIFS) is acti ve-hig h.
If IFSA is 0 (passive sync), do not inve rt SIFS to generat e the internal input
frame sync (IFS).
If IFSA is 1 (active sync) , do not invert the act ive gener ated input frame syn c
(IFS) before applying to the SIFS pin .
R/W 0
1 The exter nal input fr am e sync pin (SIFS) is acti ve-low.
If IFSA is 0 (passive sync), inver t the input fr ame sync pin (SIFS) to generate
the internal input frame sync (IFS).
If IFSA is 1 (active sync) , i nvert the acti ve genera ted input frame sync (IFS)
before applying to the SIFS pin.
0IFSA
§§ 0Passive mode input frame sync—drive the internal input frame sync (IFS) from
the external i nput frame sync pin (SIFS) modified according to IFSK and
SCON1[IFSDLY] . The SIU configur es SIFS as an input.
R/W 0
1 Active mode input frame sync††—drive the internal input frame sync (IFS) from
the active generated frame sync (AGFS) modified according to
SCON1[IFSDLY]. If SCON12[AGSYNC] is cleared, the SIU configures SIFS as
an output. If SCON12[AGSYNC] is set, the SIU configures SIFS as an input for
the purpose of synchronizing the active generated bit clocks.
Bit Field Value Description R/W Reset
Value
† To determine the type of error, the program can read the contents of the STAT regis ter (see Table 118 on pag e 197).
‡If the IRESET field (SCON1[1 0 ]) or ORESET fie ld (SCON2[10]) is cleared, do not change the value in this field.
§If the ORESET field (SCON2[10]) i s cleared, do not change the value in this field.
†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-
sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.
§§ If the IRESET field (SCON1[10]) is clear ed, do not change the valu e i n this fi el d.
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
194 A gere System s— P rop rietary Agere Systems Inc.
Use
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ursuant to Com
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any instructions
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 114. SCON11 (SIU Input/Output Active Clock Control) Register
The memory address for this register is 0x43016 for SIU0 and 0x44016 for SIU1.
15—8 7—0
Reserved AGCKLIM[7:0]
Bit Field Value Description R/W Reset
Value
15—8 Reserved 0 Reserved—write with zero. R/W 0
7—0 AGCKLIM[7:0]†0—25 5 Active clock divide rat io— controls the period and duty cycle of the active gener-
ated input and output bit clocks (ICK and O C K). R/W 0
The period of ICK and OCK (TAGCK) is the following:
TAGCK = TCKAG × (max (1, A GCKLIM[7:0]) + 1)
where TCKAG is the period of the clock source‡ for IC K an d O C K .
The high and lo w times of ICK and OCK (TAGCKH and TAGCKL) are as follows:
TAGCKH = T CKAG × int( (max(1, AGCKLIM [7:0]) + 2) ÷2)
TAGCKL = TCKAG × int( (max(1, AGCKL IM[7:0]) + 1) ÷2)
where T CKAG is the period of the clock source‡ for ICK and OCK and int( ) is the
integer function (truncation).
The following table illustrates examples:
† If the IR ESET f i el d (SCON1[10]) or ORESET field (SCON2[ 10]) i s cleared, do not change the value in this field.
‡ The clock source is selected by SCON12[AGEXT] as either the SCK pin (modified by SCON12[SCK K ]) or the proc essor cl ock, C L K .
Bit Clock
Period High Time Low Time
AGCKLIM[7:0] TAGCK TAGCKH TAGCKL
0 or 1 2 × TCKAG 1 × TCKAG 1 × TCKAG
23 × TCKAG 2 × TCKAG 1 × TCKAG
34 × TCKAG 2 × TCKAG 2 × TCKAG
45 × TCKAG 3 × TCKAG 2 × TCKAG
56 × TCKAG 3 × TCKAG 3 × TCKAG
67 × TCKAG 4 × TCKAG 3 × TCKAG
254 255 × TCKAG 128 × TCKAG 127 × TCKAG
255 256 × TCKAG 128 × TCKAG 128 × TCKAG
Advance Data Sheet
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 115. SCON 12 (SIU Input/Output Active Frame S ync Contro l) Register
The memory address for this register is 0x43018 for SIU0 and 0x44018 for SIU1.
15 14 13 12 11 10—0
AGRESET AGSYNC SCKK AGEXT Reserved AGFSLIM[10:0]
Bit Field Value Description R/W Reset
Value
15 AGRESET†0 Activate the active clock and fram e sync gener ator. R /W 1
1 Deactivate the active clock and frame sync generator.
14 AGSYNC†0 Do not synchroni ze the active generated inpu t and out put bit clocks to an
external source. R/W 0
1 Confi gure the external input frame sync (S IFS) pin as an input and synchro-
nize the active generated input and output bit clocks to SIFS.
13 SCKK†0 Do not inver t the SCK pin before appl ying it to the active cl ock generat or, i.e.,
if SCK is selected as the act ive clock source‡, t he rising edge of the active
generated i nput and output bit clocks is generated by the rising edge of SCK.
R/W 0
1 Inver t the SCK pin before applying it to the active clock gener ator, i.e ., if SCK
is s el ected a s t he act ive c loc k s ource‡, t he ri sing edge of t he activ e genera ted
input and output bi t clocks is generated by the fall ing edge of SCK.
Caution: Set this bit onl y if AGEXT is also set.
12 AGEXT†0 The processor clock (CLK) is the clock source for the active clock and frame
sync generat or. R/W 0
1 The SCK pin (modi fi ed accordi ng to SCKK) is the clock source for the act ive
clock and frame sync generator.
11 Reserved 0 Reserved—write with zero. R/W 0
10—0 AGFSLIM[10:0]†0—2047 Active fram e sync divide ratio— controls the period and duty cycle of the
active generated fram e syncs (IFS and OFS). R/W 0
The period of IFS and OFS (T AGFS) is the following:
TAGFS = T AGCK × (max(1, AGFSL IM[10:0]) + 1)
where TAGCK i s the period of the clock source§ for IFS and OFS.
The high and l ow ti me s of IF S and OFS (TAGFSH and TAGFSL) are as follows:
TAGFSH = TAGCK × int((max(1, AGFSLIM[10:0]) + 1) ÷2)
TAGFSL = T AGCK × int((max(1, AGFSLIM[10:0]) + 2) ÷2)
where TAGCK i s the period of the clock source§ for IFS and OFS and int( ) is
the int eger functi on (truncati on).
The foll owing table illu str ates exampl es:
† If the IR ESET f i el d (SCON1[10]) or ORESET field (SCON2[ 10]) i s clear ed, do no t c hange the value in this fiel d.
‡ SCK is selected as the cloc k s ource for the active clo ck generator i f AGE XT is 1.
§ The cl ock source is the act i ve gen erat ed bi t cl ock with per i od TAGCK.
Frame Sync
Period High Time Low Time
AGFSLIM[10:0] TAGFS TAGFSH TAGFSL
15 16 × T AGCK 8 × TAGCK 8 × T AGCK
16 17 × T AGCK 8 × TAGCK 9 × T AGCK
2047 2048 × TAGCK 1024 × TAGCK 1024 × TAGCK
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 116. SIDR (SIU Input Data) Register
Table 117. SODR (SIU Output Data) Register
The memory address for this register is 0x4301A for SIU0 and 0x4401A for SIU1.
15—0
Serial Input Data
Bit Field Description R/W Reset Value
15—0 Serial Input Data Read-only 16-bit serial input data. The SIU can optionally expand the
data in the input shift register before latching it into SIDR. The user
program controls this opti onal exp ansion by con fi gurin g the IF OR-
MAT[1:0] f iel d (SCON0[1:0]—Table 103 on page 185).
R0
The memory address for this register is 0x4301C for SIU0 and 0x4401C for SIU1.
15—0
Serial Output Data
Bit Field Description R/W Reset Value
15—0 Serial Output Data Write-on ly 16- bit seri al output data. The SIU opti onally compresses
the data in SODR before latching it into the output shift register. The
user program controls thi s optional compre ssion by configuring the
OFORMAT[1:0] field (SCON0[9:8]—Table 103 on page 185 ).
W0
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 118. STAT (SIU Input/Output General Status) Register
Table 1 19. FSTAT (SIU Input/Output Frame Status) Register
The memory address for this register is 0x4301E for SIU0 and 0x4401E for SIU1.
15—8 76543210
Reserved OUFLOW IOFLOW OFERR IFERR SODV Reserved SIBV SIDV
Bit Field Value Description R/W Reset
Value
15—8 Res erved 0 Reserv ed— write with zero. R/W 0
7OUFLOW
†0 Output underflow error has not occurred. R/ Clear 0
1 Output underflow error has occurred.
6IOFLOW
†0 Input overflow err or has not occ urred. R/Clear 0
1 Input overflow err or has occur red.
5OFERR
†0 Output frame error has not occurred. R/Clear 0
1 Output frame error has occurred.
4IFERR
†0 Input frame error has not occu rred. R/Clear 0
1 Input frame error has occur red.
3SODV0SODR does not contain valid data. R 0
1SODR contains valid data.
2 Reserved 0 Res erved—write with zero. R/W 0
1SIBV0SIB‡ does not contain valid data. R 0
1SIB‡ contains valid data.
0SIDV0SIDR does not contain valid data. R 0
1SIDR contains valid data.
† The pr ogramm er cle ars thi s bi t by writ i ng i t wi th 1. Writ i ng 0 to thi s bit leaves it unchanged.
‡ The SIB regist er is an int ermediate reg i st er that holds the conte nts of t he i nput shi f t regis ter an d i s not user accessible.
The memory address for this register is 0x43020 for SIU0 and 0x44020 for SIU1.
15 14—8 7 6—0
OACTIVE OFIX[6:0] IACTIVE IFIX[6:0]
Bit Field Value Description R/W Reset
Value
15 OACTIVE 0 No output channel s have been processed. R 0
1 At least one output channel has bee n processed following out put sect ion reset
(ORESET(SCON2[10]) = 0). (Distinguishes the first (index 0) and last (index
n
×8) output subframes.)
14—8 OFIX[6:0] 0—127 Channel index of the next enabled output channel. R 0
7 IACTIVE 0 No input channels have been proc essed. R 0
1 At least one input channel has been processed foll owing i nput section reset
(IRESET(SCON1[10]) = 0). (Distin guishes the first (index 0) and last (index
n
×8) input subframes.)
6—0 IFIX[ 6:0] 0—127 Current in put channel index. R 0
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 120. OCIX〈0—1〉 and ICIX〈0—1〉 (SIU Output and Input Channel Index) Registers
Table 121. OCIX〈0—1〉 (S IU Output Channe l Index) Registers
Register Address Description See
SIU0 SIU1
OCIX0 0x43030 0x44030 Output channel index for the active even subframe . Table 121
OCIX1 0x43032 0x44032 Output channel index for the active odd subframe. Table 121
ICIX0 0x43040 0x44040 Input channel index for the active even subframe. Table 122 on page 199
ICIX1 0x43042 0x44042 Input channel index for the active odd subframe. Table 122 on page 199
See Table 120 for the memory addresses of these registers.
1514131211109876543210
Channel Mode
(Each bit is mapped
to a logical channel
in the active sub-
frame.)
OCIX0 Subframe 01514131211109876543210
Subframe 247464544434241403938373635343332
Subframe 479787776757473727170696867666564
Subframe 6 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
OCIX1 Subframe 131302928272625242322212019181716
Subframe 363626160595857565554535251504948
Subframe 595949392919089888786858483828180
Subframe 7 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
1514131211109876543210
Frame Mo de †
(Each bi t i s circ ularl y
map ped to four logi -
cal channel s.)
OCIX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
OCIX1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
Bit Value Description
(SIU0) Description
(SIU1) R/W Reset
Value
15—0 0 Use DMAU channel SWT0 for output to the
logi cal cha nnel shown abov e. Use DMAU channel SWT2 for output to the
logi cal chann el shown above. R/W 0
1 Use DMAU channel SWT1 for output to the
logi cal cha nnel shown abov e. Use DMAU channel SWT3 for output to the
logi cal chann el shown above.
† I f t he number of lo gi cal cha nnels per fram e is one (OFLI M [6:0] (SCON2[ 6: 0]) = 0) i n frame mode, bi ts 1 and 0 of OCIX0 (OCIX0[1:0]) must be pro-
gram med wi th the same va l ue.
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4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 122. ICIX〈0—1〉 (SIU Input Channel Index) Registers
See Table 120 on page 198 for the memory addresses of these registers.
1514131211109876543210
Channel Mode
(Each bit is mapped
to a logical channel
in the active sub-
frame.)
ICIX0 Subframe 01514131211109876543210
Subframe 247464544434241403938373635343332
Subframe 479787776757473727170696867666564
Subframe 6 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
ICIX1 Subframe 131302928272625242322212019181716
Subframe 363626160595857565554535251504948
Subframe 595949392919089888786858483828180
Subframe 7 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
1514131211109876543210
Frame Mo de †
(Each bi t i s circ ularl y
mapp ed to four logi -
cal channel s.)
ICIX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
ICIX1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
Bit Value Description
(SIU0) Description
(SIU1) R/W Reset
Value
15—0 0 Use DMAU channe l SWT0 for i nput fr om the
logi cal cha nnel shown above . Use DMAU channel SWT2 for in put fr om the
logi cal chann el shown above. R/W 0
1 Us e DMAU channe l SWT1 for input from th e
logi cal cha nnel shown above . Use DMAU channel SWT3 for in put fr om the
logi cal chann el shown above.
† If the number of logical channels per frame is one (IFLIM[6:0](SCON1[6:0]) = 0) in frame mode, bit s 1 an d 0 of ICIX0 (ICIX0[1:0 ]) mus t be p rog ra mme d
with the same value.
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4 Hardware Architecture (continued)
4.17 Internal Clock Selection
The DSP1641 1 i nternal clock can be driven from one of
two sources. The prim ary source clock is an on-chip
programmable clock synthesizer that can be driven by
an external clock input pin (CKI) at a fraction of the
required instruction rate. The clock synthesizer is
based on a phase-lock loop (PLL ). The terms clock
synthesizer and PLL are used interchan geably.
Section 4.18, beginning on page 201, describes the
PLL and its associated pllcon, pll f rq, pllf rq1 , and
plldly registers in detail.
Note: Internal clock functions for the DSP16411 are
controlled by CORE0 because the registers
pllcon, pl l f rq, pllfrq1, and plldly are only avail-
able to programs executing in CORE0.
Figure 54 illu strates th e inte rna l cloc k selection logic
that selects the internal clock (CLK) from one of the fol-
lowi ng two source clocks:
CKI: This pin is dri ven by an ext ernal oscillator or the
pin’s associated boundary-s can logic under JTA G
control. If CKI is selected as the source clock, CLK
has the frequency and duty cycle of CKI. The
DSP16411 consumes less power if clocked with CKI.
PLL: The PLL generates a source clock with a pro-
grammable frequency. If the PLL is selected as the
source clock, fCLK has the frequency and duty cycle
of the PLL output fSYN.
After device reset, the default source clock signal is
CKI.
The program me r can select the PLL as the source
clock by setting the PLLSE L field (pllcon[0]—see
Table 124 on page 202). Before selecting the PLL as
the clock source, the user program must first enable
(power up) the PLL by setting the PLLEN field
(pllcon[1]), and then wait for the PLL to lock. See
Sect ion 4.1 8, beginning on page 20 1, for details.
Table 123 summarizes the selection of the two source
clocks as a function of the PLLSEL field.
Table 123. Source Clock Selection
Internal Clock Selection Logic
† The multiplexer is designed so that no partial clocks or glitching occurs.
Figure 54. Internal Clock Selection Log ic
PLLSEL
(pllcon[0]) fCLK Description
0f
CKI CKI pin
1f
SYN PLL
fCKI
CKI fCKI
fCLK
fSYN
PLLSEL
PLLEN
PLL
0
1
SYNC
MUX†
CLOCK SELECTION LOGIC
CLK
(pllcon[0])
(pllcon[1])
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4 Hardware Architecture (continued)
4.18 Clock Synthesis
Figure 55 is a block diagram of the clock synthesizer , or
phase-lock loop (PLL). The PLL is powered by two sup-
plie s: V DD1A and VDD2A. CORE0 enab les, selects,
and configures the PLL by writing to four registers:
pllcon, pllfrq, pllfrq1, and plldly (see Section 4.18.3
on page 202 ). pllcon is used to enable and select the
PLL clock synthesizer (see Section 4.17 on page 200).
pllfrq and pll f r q1 determine the frequency multipli er of
the PLL (see Section 4.18.1 on page 201 ). Before
selecting the PLL as the clock source, the user pro-
gram must first enable (power up) the PLL by setting
the PLLEN field (pllcon[1]) and then wait for the PLL to
lock. plldly is used for PLL LOCK fla g generation (see
Section 4.18. 2 on page 201).
4.18.1 PLL Operating Frequency
The PLL-synthesized clock frequency is determined by
the fields of the pllfrq and pllfrq1 registers. The syn-
thesized clock frequency is calculated as:
where:
M is a value in the range 4—48 and is determined by
the program ming of the M[5:0] field (pllfrq[5:0]).
N is a value in the range 0—4 and is determined by
the programmi ng of the N[3:0] field (pllfrq1[3:0]).
P is the value 0 or 1 and is determined by the pro-
gramm ing of the P field (pllfrq1[8]).
Table 188 on page 275 spec ifies the timing require-
me n ts for fSYN, for the phase detector input frequency
(fPD), and for the output frequency of the voltage-c on-
trolled oscillator (fVCO). The M[5:0], N[3:0], and P fields
must be programmed to values suc h that the fSYN, fPD,
and fVCO frequencies ar e within the required ranges
specified in Table 188. The following equations specify
fPD and fVCO:
4.18.2 PLL LO CK Flag Generati on
The DSP16 411 does not provide a PLL-generated s ta-
tus flag that indicates when the PLL has locked.
Instead, a user-program mable register, plldly
(Table 127 on page 202), and an associated delay
counter is used for this purpose. If the pllcon register is
written to enable the PLL, the DSP16411 loads the
delay counter with the value in plldly. The DSP16411
decrements this counter for each subsequent cycle of
the DSP input clock (CKI). When the counter reaches
zero, the LOCK status flag is assert ed. The st ate of t he
LOCK flag can be tested by conditional instruction s
(Section 6.1 .1 on page 226 ) and is also visible in the
alf register (Table 144 on page 235 ). The LOCK flag is
cleared on reset or by a write to the pllcon regist er.
The PLL requires 0.5 ms to achieve lock. The applica-
tion software should set the plldly register to a value
that produces a minimum delay of 0.5 ms. The register
setting needed to ach ieve this delay is dependent on
the frequenc y of the input clock (CKI). The pro-
gramm ed value for plldly that results in a countdown
delay of 0.5 ms is the following:
plldly = 500 x fCKI
where fCKI is the input clock frequency in MHz.
See Section 4.18.4 on page 203 for a PLL program-
ming example that includes the use of plldly.
Figure 55. Clock Synthesizer (PLL) Block Diagram
fSYN fCKI M2+
N1+()P1+()
--------------------------------------
×=
fVCO fCKI 2M 2+()
N1+
-----------------------
×=
fPD fCKI
N1+
--------------
=
PLL
fCKI
N[3:0]
M[5:0]
÷2(M + 2)
÷(N + 1) PHASE
DETECTOR CHARGE
PUMP VCO
CKI
fSYN
(pllfrq1[14:11])
(pllfrq[5:0])
÷(P + 1 )
P
(pllfrq1[8])
fPD ÷2
fVCO
(pllcon[1])
PLLEN
VDD2A
VSS2A
VDD1A
VSS1A
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4 Hardware Architecture (continued)
4.18 Clock Synthesis (continued)
4.18.3 PLL Registers
Table 124. pllcon (Phase-L ock L oop Contro l) Register
Table 125. pllfrq (Phase-Lo ck Loop Fr equ ency Control) Register
Table 126. pllfrq1 (Phase-Lo ck Lo op Frequ enc y Control 1) Register
Table 127. plldly (Phase -Lock Loop Delay Control) Register
Note: pllcon is acc es si ble in C OR E 0 on ly.
15—2 1 0
Reserved PLLEN PLLSEL
Bit Field Value Description R/W Reset Value
15—2 Reserved — Reserved—writ e wit h zero. R/W 0
1 PLLEN 0 Disable (power down) the PLL. R/W 0
1 Enable (power up) the PLL.
0 PLLSEL 0 Select the CKI i nput as the inte rnal clock (CLK) source. R/W 0
1 Select the PLL as th e int ernal clock (CLK) source.
Note: pllfrq is accessible in CORE0 only.
15—6 5—0
Reserved M[5:0]
Bit Field Value Description R/W Reset Value
15—6 Reserved — Res erved—write with ze ro. R/W 0
5—0 M[5:0] 4—48 Defines M , which d etermi nes the fe edback cl ock divider cont rol se tting
(2(M + 2)). The value of M must be in the range 4 ≤M≤48. R/W 0
Note: pllfrq1 is accessible in CORE0 only.
15—9 87—4 3—0
Reserved PReserved N[3:0]
Bit Field Value Descrip tion R/W Reset Value
15—9 Reserved — Reserved—write with zero. R/W 0
8 P 0—1 De fines P, which de ter mines t he VCO output di vider c ontrol set t ing (P + 1). (For a
value of fPCK of 240 MH z or less, P must be set to 1.) R/W 0
7—4 Reserved — Reserved—write with zero. R/W 0
3—0 N[3:0] 0—4 Defines N, which determines the reference clock divider control setting (N + 1).
The value of N must be in the ra nge 0 ≤N≤4. R/W 0
Note: plldly is ac c e s si ble in C OR E 0 o nly. 15—0
DLY[15:0]
Bit 15—0 Value Description R/W Reset Value
15—0 DLY[15:0] — The contents of DLY[15:0] are loaded i nto t he PLL delay
counter after a pllcon reg ister wri te. If PLLEN
(pllcon[ 1]) i s 1 , the count er decrement s each CKI cycl e.
When the counter re aches zero, t he LOCK flag† for bot h
CORE0 and CORE1 is assert ed.
R/W 0x1388
† The state of the LOCK flag can be tested by conditional instructions (Section 6 .1.1 on page 226) and is also visible in the alf register
(Table 144 on page 235). The LOCK flag is cleared by a device reset or a write to the pllcon register.
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4 Hardware Architecture (continued)
4.18 Clock Synthesis (continued)
4.18.4 PLL Prog ramming Exam ple
The following c ode example illustrates the recommended PLL programming sequence. It assumes the following
parameters:
CKI = 30 MHz.
The required PLL outp ut frequency (fSYN) is 240 MHz.
fVCO = 9 60 MHz.
The PL L multiplier is 8 (M = 30, N = 1, and P = 1).
As specified in Table 188 on page 275 , the maximu m PL L lock t ime (tL) is 0.5 ms, or 15,000 CKI cycle s.
pllcon=0x0000 // Turn off the PLL
plldly=15000 // Set countdown delay = 0.5 ms (500 x 30 = 15,000)
pllfrq=0x001E // M=30
pllfrq1=0x0101 // P=1, N=1
pllcon=0x0002 // Turn on PLL
// (DSP16411 automatically loads delay counter from plldly)
4*nop // Wait for pllcon write to complete
pllwait:
if lock goto pllon // Wait for delay countdown to complete
goto pllwait
pllon:
pllcon=0x0003 // Select PLL as CLK source
4.18.5 Powering Down the PLL
Clearing the PLLEN field (pllcon[1]) powers down the PLL. Do not power down the PLL (do not clear PLLEN) if
the PLL is selected as the clock source (PLLSEL (pllcon[ 0]) = 1). T he PLL must be deselected as the clock
source prior to or concurrent with powering down the PLL. See Section 4.20, beginning on page 205, for general
information on power management.
Caution: Do not power down the PLL (PLL EN = 0) while it is selected as the clock source (PLLSEL = 1). If
this occurs, the device freezes because it has no clock source and cannot operate. To recover
from this condit ion, the RSTN, TRST0N, and TRST1N pins must be asserted to reset the device.
4.18.6 Phase-Lock Loo p (PLL) Frequency Accu racy an d Jitter
Although the average frequency of the PLL output has almost the same relati ve accur acy as the input clock, noise
sources within the DSP16411 produce jitt er on the PLL clock. The PLL is guaranteed to have sufficiently low jitter
to operate the DSP1641 1. However , if the PLL clock is used as the clock source for external devices via the ECKO
pin, do n ot apply this clo ck to jitter-sens itive devices. S ee Table 188 on page 275 for the input jitter requirements
for the PLL.
Note: J itter on the ECKO output clock pin does not need to be taken into account with respect to the t iming require-
ments and characteristics specified in Sec tion 11, beginning on page 274.
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4 Hardware Architecture (continued)
4.19 External Clock Selection
The ECKO pin can be programm ed using the
ECKOB[1:0] and ECKOA[1:0] fields
(ECON1[3:0]—Table 61 on page 112) to select one of
the following outputs:
1. CLK /2: The internal clock CLK divided by 2.
2. CLK /3: The internal clock CLK divided by 3.
3. CLK /4: The internal clock CLK divided by 4.
4. CLK: The internal clock CLK.
5. CKI: The buff ered CKI pin.
6. ZE RO: Logic low.
Table 128 specifies the selection of the ECKO pin as a
funct ion of the ECK O B[1: 0] and ECK OA[1:0] fields
(ECON1[3:0]).
After reset, the ECKO out put pin is configured as
CLK/2 and CLK is configured as CKI. Therefore, after
reset, ECKO is configured as CKI/2.
The logic that contr ols the ECKO pin is illustrated in
Figure 56 on page 206. If the application does not
require a clock on t he ECKO pin, the user can program
ECKO as logi c low during initialization to reduce power
consumption.
Note: Although ECON1 can be accessed by either
core, the programme r should selec t only one
core (such as CORE0) to control the EC KO
pin. The pr ogrammer is responsible for develop-
ing a protocol between CORE0 and CORE 1.
Intercore coordination is not part of the
DSP16411 hardware.
Table 128. ECKO Outp ut Clock Pin Configuration
ECKOB[1:0] ECKOA[1:0] ECKO Pin
ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description
0000CLK/2†Freque ncy of CLK‡ divided by two.
0001CLK Frequency of CLK‡.
0010CKI Input clock pin.
00110 Logic zero .
0 1 X X Reserved —
1 0 X X CLK/3 Frequency of CLK‡ divided by three .
1 1 X X CLK/4 Freque ncy of CLK‡ divided by four.
† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.
‡ CLK is the internal (core) clock. See Section 4.17 on page 200 for details.
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4 Hardware Architecture (continued)
4.20 Power Management
A program running in a core can place that core into
low-power standby mode by setting the AWAIT field
(alf[15]—see Table 144 on page 235). In this mode,
the clock to that core and its associated TPRAM are
disabled except for the minimum core circuitry required
to process an inc oming interrupt or trap. The clock to
the peripherals is unaffected.
F igure 56 on p age 206 illustrates the following:
Distribution of CLK to the cores and peripherals.
Function of the AWAIT field.
Interrupts to the core used to exit low-power standby
mode.
ECK O pin selection logic (see Section 4.19 on
page 204 for details).
If a core is in low-power standby mode, program exe-
cution in that core is suspended without loss of state. If
an interrupt that was enabled by that core occurs or if a
trap occurs, the core clears its AWAIT field, exits low-
power standby mode, resumes program execution, and
services the inte rrupt or trap. Se e Se c tio n 4 .4.5 o n
page 30 and Section 4 .4.6 on page 31 for information
on enabling interrupts.
If the DMAU accesses the TPRAM while the associ-
ated core is in standby mode, the clock to the TPRAM
is re-en abled for that access. How ev er, if the core
goes into standby mode w hile an access to a memory
component is in progress, it locks out the DMAU from
accessing that compo nent . To prevent locking out the
DMAU, the user program must use the macro
SLEEP_ALF () in the 16411.h file. T he 16411.h file is
included with the Agere software generation system
(SGS) t ools. Using SLEEP_AL F () guarantees that the
core completes all pending memory accesses before
entering standby mode.
SLEEP_ALF () expands to the following:
.align
goto .+1
alf=0x8000
3*nop
The DSP16 411 includes addi tional mechanism s for
saving power that are independent of standby mode:
1. CORE0 can temporarily select the CKI p in as the
source clock to the cores and peripherals by c learing
the PLLS EL field (pllcon[0]—see Table 124 on
page 202). To sa ve additional power, CO RE0 can
temporarily disabl e (power down) the PLL by clear-
ing the PLLEN field (pllcon[1]).
2. CORE0 can drive the ECKO1 pin low by program-
ming the ECKO A[1:0] field (ECON1[1:0]—see
Table 61 on page 112) to 0x3 an d the ECKOB [1:0]
field (ECON1[3:2 ]) to 0x0.
3. E ach c ore can power down one or both o f its timers
(set timer〈0,1〉c[6]) . See Sect ion 4. 10 on page 53
for details.
Prior to entering standby mode, CORE0 can perform
any of the above steps to save addition al power. Prior
to entering standby mode, CORE1 can direct CORE0
to perform steps 1 and 2, and CORE1 can perfo rm
step 3 direct ly. (See Sectio n 4.8 on page 46 for infor-
mation on core-to-core communi c ation.)
An interrupt causes the associated core to exit standby
mode and immediat ely service the interrupt. If the pro-
gram running in CORE0 selects the CKI pin as the
source clock before entering standby mode , that clock
is selected as the source clock immed iately after the
core exits standby mode. Likewise, if the program run-
ning in CORE0 disable s the PLL before entering
standby mo de, the PLL is disabled immediate ly after
the core exits standby mode. Assuming the PLL is the
source clock for normal operation, the CORE0 program
must re-enable and then reselect the PLL after exiting
standby mo de in order to resume full-speed process -
ing. Only CORE 0 can control the PLL and clock selec-
tion. Therefore, if CORE1 exits standby mode and
needs to resume full-speed execution, it must direct
CORE0 to enable and reselect the PLL.
Note: If CORE0 selects the CKI pin as the source clock
before entering stan dby mode, the peripherals
also operate at the slower rate. This can result in
an increased delay for a peripheral to interrupt
the core to exit standby mode.
1. Although ECON1 can be accessed by eithe r core, t he pr ogr am-
mer should select only one core (such as CORE0) to control the
ECKO pin . The pr ogr amm er is r es po ns ib le fo r de ve lopi ng a p rot o-
col between CO RE0 and CORE 1. Intercore c oordination is not
part of the DSP16411 hardware.
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4 Hardware Architecture (continued)
4.20 Power Management (continued)
Power Management and Clock Distribution
† CLK is des cri be d in Section 4.17 on pag e 200.
‡ The IMUX is described in Section 4.4.2, beginning on page 28.
Figure 56. Power Management and Clock Dis tribution
CORE0
INTERRUPT
LOGIC
CLK
CLK†
AWAIT
(alf[15])
SYNC
GATE
TPRAM0
CLOCK
0
ECK
O
ECKOB[1:0],
CLK/2
CKI
÷2
IMUX0‡
MXI[9:0]
IMUX1‡
XIO
XIO
MGIBF
SIGIN T, PTRAP
MGIBF
SIGIN T, PTRAP
2
10
SEMI
TIMER1_0
SIU0MGU0 DMAU PIU MGU1 SIU1
TIMER0_0
TIMER1_1
TIMER0_1
AWAIT
(alf[15])
SYNC
GATE
CORE1
INTERRUPT
LOGIC
CLK
TPRAM1
CLOCK
MXI[9:0]
10
INT[1:0]
TIME0
TIME1
TIME0
TIME1
INT[1:0]
PHINT
PHINT
22
22
INT[1:0]
DMINT[5:4]
DMINT[5:4]
2 2
CLK/3
CLK/4
÷3
÷4
ECKOA[1:0]
(ECON1[3:0])
MUX
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4 Hardware Architecture (continued)
4.20 Power Management (continued)
Wake-up latency is the delay from the time that the core exits standby mode (due to an interrupt) to the time that
the core resumes full-speed execution. The wake-up latency is dependent on the configuration of clocks prior to
entering standby mode, as summarized in Table 129. The program mer must ensure that the wake-up latency is
acceptable in the application. Table 129 also illustrate s the trade-off of wak e-up lat enc y vs. power consum pti on.
Disabling the PLL during low-power standby mode results in the minimum power cons umption and highest wake-
up latency. S ee Section 10.3 on page 271 and Section 11.2 on page 276 for details on power dissipation and
wake-up latency for vario us operating mode s.
Table 129. Wake-Up Latency and Power Con su m ption for Low-Pow er S tandb y Mode
Source Clock
Selected In Standby
Mode
S tat us of PLL In
Standby Mode Wake- Up Latency Latency vs. Power Consumption Trade-Of f
PLL Enabled 3 PLL cycles Minimum wake-up latency (highest power)
CKI Pin Enabled 3 CKI cyc les —
Disabl ed 3 CKI cycles +
PLL lock-in time Minimum power (highest wake-up latency)
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5 Processor Boot-Up and Memory Download
The state of the EXM pin at the time of reset determines whether CORE0 and CORE1 boot from their internal boot
ROMs or from external memory, as specified in Table 130.
Table 131 summarize s the contents of the internal boot ROMs, IROM0 and IRO M1. The contents of IROM0 and
IROM1 are ident ical.
If the cores boot from their internal boot ROMs, then they execute a boot routine that is described in Section 5.1.
This routine simply waits for an external host to download code and data into the TPRAMs via the PIU. Wh en the
download is complete, the boot routine causes each core to branch to the first location in its TPRAM.
If the cores boot from EROM , then the user must place a boot routine for both cores into EROM prior to reset.
Section 5.2 on page 209 outlines a boot routine that downloads code and data into the TPRAMs via the DMAU and
then causes each core to branch to the first location in its own TPRAM.
Note: After the deassertion of RSTN and during the execution of the boot routine, the clock synthes izer (PLL) is
disabled and the frequency of the internal clock ( CLK) is the same as the input clock pin (CKI).
5.1 IROM Boot Routine and Host Download Via PIU
CORE0 and CORE1 boot from IROM0 and IR OM 1 if the EXM pin is low when RSTN is deasserted. The boot rou-
tine in IROM0 is identical to that in IROM1. The routine polls for the PHINT interrupt condition1 in th e ins register
(Table 154 on page 242 ) to determine when the external host has completed downloading to TPRAM via the PIU.
While the cores wait for PHINT to be set, the host can download code and data to any of the memory spaces in the
Z-memory space, summarized below:
Internal me mory and I/O:
— TPRAM0
— TPRAM1
— Internal I/O (includes SLM and memory-mapped peripheral registers)
Exte rnal memory and I/O:
— EIO space
— ERAM space
— EROM space
Table 130. Core Boot-Up After Reset
State of EXM Pin
on Rising Edge of RSTN CORE0 Begins
Executing Code From CORE1 Begi ns
Executing Code From
EXM = 0 IROM0 (address 0x30000) IROM1 (address 0x30000)
EXM = 1 EROM (address 0x80000) EROM (address 0x80000)
Table 131. Contents of IROM0 and IROM1 Boot ROMs
Address or Address Range Code
0x30000 Instruction: goto 0x30800 (boot routin e).
0x30004—0x303FF Res erved for HDS cod e.
0x30800—0x308FF Boo t routine.
0x30FFE—0x30FFF Processor type: 0x00000005.
1. Inter rupt s re main globally disabl ed during execution of the boot routine, and the PHINT interrupt cond ition i s detected by polling.
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5 Processor Boot-Up and Memory Download (continued)
5.1 IROM Boot Routine and Host Download Via PIU (continued)
The host accesses DSP164 11 memory by executing commands that cause the PIU to use the DMAU bypass
channel for downloading. See S ect ion 4.15.5 on page 147 for de tails. Wh en the host has completed the down -
load, it asserts the PHINT interrupt and sets the PHINT interrupt pending status field (ins[13]—see Table 154 on
page 242) by writi ng the HINT f i eld (PCON[4]—see Table 75 on page 136 ). After each boot routine detects the
assertion of PHINT, it bra nches to the first location of TPRAM (TPRAM0 for CORE0 and TPRAM1 for CORE1).
The boot routine is shown below:
.rsect “.rom” // Address 0x30000
goto PUPBOOT // Branch to boot routine.
// Other Vectors, HDS code, and Production test code go here.
.rsect “.PowerUpBoot” // Address 30800
PUPBOOT: pt0=0
pollboot: a0=ins
a0 & 0x0000002000 // Check ins[PHINT].
if eq goto pollboot // Wait for ins[PHINT] to be set.
r0=0x41000 // Point to the PCON register.
a0=0x0010
ins=0xffff // Clear pending interrupts in ins.
*r0=a0 // Write PCON to clear HINT bit.
a0=0; r0=0 // Cleanup.
goto pt0 // Jump to user code.
5.2 EROM Boot Routine and DMAU Download
CORE0 and CORE1 bot h boot from EROM at address 0x80000 if the EXM pin is high when RSTN is de asserted.
The cores access EROM via the SEMI, and the SEMI interleaves the accesses so that CORE0 executes the
instruction at address 0x80000 first, then CORE1 executes the instruction at address 0x80000 next, etc. The user
must place a boot routine for both cores in to EROM prior to re set. This boot routine can contain instruction s to
download code and data from ERAM to internal memory (TPRAM0 and TP RAM1 ) via the DMAU. T he downlo ad
can be performed either by both cores or by one core while the other core waits. In either case, the boot routine
must distinguish whether CORE0 or CORE1 is e xecuting it. It does this by reading the processor ID (pid) register
(Table 157 on page 242). CO RE0’s pid register contains 0x0 and CORE1’s pid register contains 0x1. Aft er deter-
mining the processor ID, the boot routine can branch to the correct boot proce dure for that core. Once the down-
load is complete, both cores can terminate the ir boot procedures by executing the following in structions:
pt0=0x0
nop
goto pt0
This causes CORE0 to begin executing instructions at address 0x0 of TPRAM 0 and CORE1 t o begin executing
instructions at address 0x0 of TPRAM 1.
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6 Software Architecture
6.1 Instruction Set Quick Reference
The DSP16411 instruction set consists of both 16-bit and 32-bit wide instructions and resembles C-code.
Table 132 defines the seven types of instructions. The assembler translates a line of assembly code into the most
eff icient DSP16411 instruction(s). See Tab le 1 34 on page 218 for instruction set notation conventions.
Table 132. DSP16411 Instruction Groups
Instruction
Group F Title
(If Applicable) Description
MAC F1 TRANSFER
F1E TRANSFER
if CON F1E
The powerful M AC instruction group is the pr imary g roup of instructions used fo r si g-
nal processing. Up to two dat a tra nsfers can be com bined with up to four parallel
DAU operations in a single MAC instruction to execute simultaneously†. The DAU
operat ion com binat ions inc lude (bu t are not limited to ) eith er a dual- MAC‡ oper ation ,
an ALU operati on and a BMU op eration, or an ALU/ACS oper ation and an
ADDER/ACS operat ion. The F1E instructions that do not include a transfer state -
ment can execute conditionally based on the state of flags§.
† Execut es in one instruct ion cycl e in most cases.
‡ A d ual-MAC operation consi s ts of two multipli es and an add or subtract ope rat ion by the ALU, an add or subtr act ope rat ion by the ADDER, or
both.
§See Section6.1.1 on page 226 for a descr ipti on of processor fla gs.
Special
Function if CON F2
ifc CON F2
if CON F2E
if c CON F2E
Special func tions i nclude roundi ng, negati on, absol ute v alue, and fixe d ari thmeti c lef t
and right shift operations. The operands are an accumulat or, another DAU register,
or an accumulato r and anot her DAU register. Some specia l fu nction instructions
increment counters. Speci al functions exec ute condi tiona ll y based on the st ate of
flags§.
ALU F3
if CON F3E ALU instr uctions operat e on two accumulat ors or on an accumu lator and another
DAU regist er. Man y instructions can also operate on an accumul ator and an im me-
diate data word. The ALU operations are add, subtract, logical AND, logical OR,
exclusive O R, maxi mu m, m inimum, and di vide- step. Some F3E i nstr uctions include
a parall el ADDER operation. The F3E instructions can execute conditionally based
on the stat e of flags§.
BMU F4
if CON F4E Full barrel shifting, exponent computation, normalization computation, bit-field
extraction or insert ion, and data shuf fl ing between two accumulators are BMU oper-
ation s that act on the accum ulat ors. BMU operati on s are cont ro lled by an accumul a-
tor, an auxiliary register, or a 16-bit immediate value. The F4E instructions can
execute conditionally based on the state of flags§.
Data Move
and
Pointer
Arithmetic
— Data move instructions transfer dat a between two registers or between a register
and me mory. This ins truction gr oup al so suppor ts i mmediate loa ds of r egist ers, con-
ditional register-to-register moves, pipeline block moves, and specialized stack
operations. Pointer arithmetic instructions perform arithmetic on data pointers and
do not perform a memory access.
Control — The con trol inst ruction group con tains branch and call subroutine instructions with
eithe r a 20-bi t absol ute addre ss or a 12-bit or 16 -bit PC-relat ive add res s. This gro up
also inc ludes instruct ions to enable and disable inter rupts. Some contr ol instructions
can execute condi tionall y based on the state of processor flags§.
Cache — Cache instructions implement low-overhead loops by loading a set of up to
31 instructions into cache m em ory and repet itivel y executing them as many as
216 – 1 times.
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
See the
DSP16000 Digital Signal Processor Core
Information Manual
for a detailed description of:
The instruction set
Pipe line hazards1
Instruction encodi ng format s and field descriptions
Instruction set reference
Table 133 on page 212 lists the entire instruction set with its cycle performance and the number of memory loca-
tions required for each. Figure 57 is an illustration of a single row of the table and a description of how to interpret
its contents.
Figure 57. Inter pretation of the Instr uction Set Summary Table
Table 134 on page 218 sum ma rize s the instruction set notation convent ions for interpreting the instruction syntax
descriptions. Table 135 on page 219 is an overall rep lacem ent table that summa rizes the replacem ent for e very
upper-case character string in the instruction set summary table (Table 133 on page 212) except for F1 and F1E in
the MAC instruction group. Table 136 on page 222 describes the replacement for the F1 field, and Table 137 on
page 224 desc ribes th e replacement for the F1E field.
1. A pipeline hazard occurs when a write to a register precedes an access that uses the same register and that register is not updat ed bec au se
of pipeline timing. The DSP16000 assembler automatically inserts a nop in this case to avoid the hazard.
Instruction Flags Cycles Words
szlme Out In
ALU Group
aD = aS OP 〈aT E , pE〉(F3) szlm– 1 1 1
INSTRUCTIO N SYNTAX.
INSTRUCTIONS ARE GROUPED INTO
CATEGORIES (ONE OF SEVEN).
QUANTITY OF PROGRAM MEMORY
USED BY THE INSTRUCTIO N.
(EITHER 1 OR 2 16-bit WORDS).
F TITLE
(IF APPLICAB LE).
THE NUMBER OF INSTRUCTION CYCLES
USED WHEN THE INSTRUCTION IS EXE-
CUTED OUTSIDE OF THE CACHE.
THE NUMBER OF INSTRUCTION CYCLES
USED WHEN THE INSTRUCTION IS EXE-
CUTED INSIDE OF THE CACHE.A DASH
(—) INDICA TE S THE INSTRUCTION IS NOT
CACHABLE.
FLAGS AFFECTED BY
THIS INST RU CTIO N†.
† szlme corresponds to the LMI (s), LEQ (z), LLV (l), LMV (m), and EPAR (e) flags.If a letter appears in this column, the corresponding flag is
af fe ct ed by t hi s i nstr uct io n.If a dash appears in this column, the corresponding flag is unaffected by this instruction.In the e xam pl e sh ow n,
the instruction affects all flags except for EPA R.For MAC group instructions with both an ALU/ACS operation and an ADDER or BMU oper-
ation, the ALU/ACS result affects the LMI, LEQ, LLV, and LMV flags, and the EPAR flag is unaffected.
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 133. Instruction Set Summary
Instruction Flags Cycles Words
szlme Out In
Multiply/Accumulate (MAC) Group
F1Yszlm– 1 1 1
F1x〈h,l〉 = Y szlm–
F1y〈h,l〉 = Y szlm–
F1a〈h,l〉 = Y s zlm–
F1Y = y〈h,l〉szlm–
F1Y = aT〈h,l〉szlm–
F1yh = aT h xh = X s zlm – 1+X C†
F1yh = Y xh = X szlm–
if CON F1E szlme 1 1 2
F1Eyh,l = aTEh,lszlme
F1EaTEh,l = yh,lszlme
F1Ey = aE _Ph szlm e
F1EaE_Ph = y szlme
F1Exh,l = YE szlm e
F1Eyh,l = YE szlm e
F1EaTEh,l = Y E szlm e
F1EaE_Ph = YE szlme
F1EYE = xh,lszlme
F1EYE = yh,lszlme
F1EYE = aTEh,lszlme
F1EYE = aE_Ph szlme
F1Eyh = *r0 r0 = rN E + jhb s zlme
F1EYE szlme
F1Exh,l = XE szlme 1+XC†
F1E aTEh,l = X E s zlm e
F1EaE_Ph = XE szlme
F1Ey = aE_P h xh = XE szlme
F1Eyh = aTEh xh = XE szlme
F1EaTEh = yhxh = XE szlme
F1Eyh,l = YE‡a4h = XE szlme
F1Eyh,l = YE xh = XE szlme
F1EYE = yh,lxh = XE szlme
F1Eyh = YE‡a4_5h = XE szlme
F1EYE = a6_7h xh = XE szlme
F1EYE = a6h‡xh = XE szlme
F1EYE = a6h‡a4h = XE szlme
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For thi s tr ansfer, the postincre m ent opt ions *rME an d *rME–– are not available for double-wor d loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.
‡‡ The instr uction perf orms t he same function whether or not near (opt io na l) is inc lude d.
§§ Not including the N instructions.
D
Table 133. Instruction Set Summary (continued)
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Multiply/Accumul ate (MAC) Group (continued)
F1Eyh = *r0 r0 = rNE+jlbj = kk
= XE szlme 1+XC†12
F1EXE szlme
Special Function Group
if CON aD = aS>>〈1,4,8,16〉(F2) szlme 1 1 1
ifc CON aD = aS>>〈1,4,8,16〉(F2) szlme
if CON aD = aS (F2) szlm–
ifc CON aD = aS (F2) szlm–
if CON aD = –aS (F2) szlm–
ifc CON aD = –aS (F2) szlm–
if CON aD = ~aS (F2) sz lm–
ifc CON aD = ~aS (F2) szlm–
if CON aD = rnd(aS) (F2) szlm–
ifc CON aD = rnd(aS) (F2) sz lm–
if CON aDh=aSh+1 (F2) szlm–
ifc CON aDh = aSh+1 (F2) sz lm–
if CON aD = aS+1 (F2) szlm–
ifc CON aD = aS+1 (F2) szlm–
if CON aD = 〈y,p0〉(F2) szlm–
ifc CON aD = 〈y,p0〉(F2) szlm–
if CON aD = aS<<〈1,4,8,16〉(F2) szlme
ifc CON aD = aS<<〈1,4,8,16〉(F2) szlme
if CON aDE = aSE>>〈1,2,4,8,16〉(F2E) szlme 1 1 2
ifc CON aDE = aSE> >〈1,2,4,8,16〉(F2E) szlme
if CON aDE = aSE (F2E) sz lm–
ifc CON aDE = aSE (F2E) szlm–
if CON aDE = –aSE (F2E) sz lm–
ifc CON aDE = –aSE (F2E) szlm–
if CON aDE = ~aSE (F2E) szlm–
ifc CON aDE = ~aSE (F2E) szlm–
if CON aDE = rnd(〈aSE,pE〉)(F2E)szlm–
ifc CON aDE = rnd(〈aSE,pE〉)(F2E)szlm–
if CON aDE = rnd(–pE) (F2E) szlm–
ifc CON aDE = rnd(–pE) (F2E) szlm–
if CON aDE = rnd(aSE+pE) ( F2E) szlm–
ifc CON aDE = rnd(aSE+pE) ( F2E) szlm–
if CON aDE = rnd(aSE–pE) (F2E) szlm–
ifc CON aDE = rnd(aSE–pE) (F2E) szlm–
Instruction Flags Cycles Words
szlme Out In
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For this transfer, the postincrement options *rME an d *rME–– are not available for do uble-word loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For condit ional branch instructions, the execution tim e is two cycles if the branch is no t taken.
‡‡ The instructi on per forms the same functi on whether or not near (optio na l) is inc lud e d.
§§ Not including the N instructions.
Table 133. Instruction Set Summary (continued)
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Advance Data Sheet
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Special Function Group (continued)
if CON aDE = abs(aSE) (F2E) szlm– 1 1 2
ifc CON aDE = abs(aSE) (F2E) szlm–
if CON aDE = aSEh+1 (F2E) sz lm–
ifc CON aDEh = aSEh+1 (F2E) szlm–
if CON aDE = aSE+1 (F2E) szlm–
ifc CON aDE = aSE+1 (F2E) szlm–
if CON aDE = 〈y,pE〉(F2E) szlm–
ifc CON aDE = 〈y,pE〉(F2E) szlm–
if CON aDE = 〈–y,–pE〉(F2E) szlm–
ifc CON aDE = 〈–y,–pE〉(F2E) szlm–
if CON aDE = aSE<<〈1,2,4,8,16〉(F2E) szlme
ifc CON aDE = aSE< <〈1,2,4,8,16〉(F2E) szlme
ALU Group
aD = aS OP 〈aTE,pE〉(F3) szlm– 1 1 1
aD = 〈aTE,pE〉 – aS (F3) szlm–
aD = FUNC(aS,〈aTE,pE〉)(F3)szlm–
aS – 〈aTE,pE〉(F3) szlm–
aS&〈aTE,pE〉(F3) szlm–
if CON aDE = aSE OP 〈pE,y〉(F3E) szlm– 1 1 2
if CON aDE = aSE OP aTE (F3E) szlm–
if CON aDE = 〈pE,y〉–aSE (F3E) szlm–
if CON aDE = FUNC(aSE,〈pE,y〉) (F3E) szlm–
if CON aDE = FUNC(aSE,aTE) (F3E) szlm–
if CON aSE – 〈pE,y〉(F3E) szlm–
if CON aSE&〈pE,y〉(F3E) szlm–
if CON aSE – aTE (F3E) szlm–
if CON aSE&aTE (F3E) szlm–
if CON aDEE = aSEE±aTEE aDPE = aSPE±aTPE (F3E) szlm–
if CON aDE = aSE+aTE else aDE = aSE–aTE (F3E) szlm–
aDE = aSE〈h,l〉 OP IM16§(F3 wit h immediate) szlm– 1 1 2
aDE = IM16–aSE〈h,l〉(F3 with immediate) szlm–
aSE〈h,l〉 – IM16 (F3 with immediate) sz lm–
aSE〈h,l〉 & IM16 (F3 with immediate) szlm–
Instruction Flags Cycles Words
szlme Out In
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For thi s tr ansfer, the postincre m ent opt ions *rME an d *rME–– are not available for double-wor d loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.
‡‡ The instr uction perf orms t he same function whether or not near (opt io na l) is inc lude d.
§§ Not including the N instructions.
Table 133. Instruction Set Summary (continued)
Advance Data Sheet
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any instructions
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
BMU Group
aD = aS SHIFT 〈aTEh,arM〉(F4) szlme 1 1 1
aDh = exp(aTE) (F4) szlme
aD = norm(aS, 〈aTEh,arM〉)(F4)szlme
aD = extr acts(aS,aTEh) (F4)
aD = extr actz(aS,aTEh) szlme
aD = inserts(aS,aTEh) (F4)
aD = insertz(aS,aTEh) szlme
aD = extract(aS,arM) (F4)
aD = extracts(aS,arM)
aD = extractz(aS,arM)
szlme
aD = ins e rt(a S ,a r M ) (F4 )
aD = inserts(aS,arM)
aD = insertz(aS,arM)
szlme
aD = aS:aTE (F4) szlm–
aDE = extr act(aSE,IM8W,IM8O) (F4 with immedi ate)
aDE = extr acts(aSE,IM8W ,IM8O)
aDE = extr actz(aSE,IM8W ,IM8O)
szlme 1 1 2
aDE = inser t( aSE,IM8W,IM8O) (F4 wit h immediate)
aDE = inser ts(aSE,IM8W ,IM8O)
aDE = inser tz(aSE,IM8W ,IM8O)
szlme
aDE=aSE SHIFT IM16 (F4 wit h immediate) szlme
if CON aDE = aSE SHIFT〈aTEh,arM〉 (F4E) szlme 1 1 2
if CON aDEh = exp(aTE) (F4E) szlme
if CON aDE = norm(aSE,〈aTEh,arM〉)(F4E)szlme
if CON aDE = extracts(aSE,aTEh) (F4E)
if CON aDE = extractz(aSE,aTEh) szlme
if CON aDE = inserts(aSE,aTEh) (F4E)
if CON aDE = insertz(aSE,aTEh) szlme
if CON aDE = extract(aSE,arM) (F4E)
if CON aDE = extracts(aSE,arM)
if CON aDE = extractz(aSE,arM)
szlme
if CON aDE = insert(aSE,arM) (F4E)
if CON aDE = inserts(aSE,arM)
if CON aDE = insertz(aSE,arM)
szlme
if CON aDE = aSE:aTE (F4E) szlm–
Instruction Flags Cycles Words
szlme Out In
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For this transfer, the postincrement options *rME an d *rME–– are not available for do uble-word loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For condit ional branch instructions, the execution tim e is two cycles if the branch is no t taken.
‡‡ The instructi on per forms the same functi on whether or not near (optio na l) is inc lud e d.
§§ Not including the N instructions.
Table 133. Instruction Set Summary (continued)
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Advance Data Sheet
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Data Move and Pointer Arit hm etic Group
RAB = IM20 —112
RA = IM4 — 1 1 1
RAD = RAS—111
if CONRABD = RABS—2
RB = aTE〈h,l〉—111
aTE〈h,l〉 = RB —
RA = Y — 1 1 1
Y = RA —
RAB = YE — 1 1 2
YE = RC —
RAB = *sp++2 — 1 1 1
*sp––2 = RC —
sp––2 —
*sp = R C —
push RC
pop RAB —
r3––sizeof(RAB) —
RA = *(sp+IM5) — 2 2 1
*(sp+IM5) = RA —
RAB = *(RP+IM12) — 2 2 2
*(RP+IM12) = RC —
RAB = *(RP+〈j,k〉)—
*(RP+〈j,k〉) = RC —
RY = RP+IM12 — 1 1 2
RY = RP+〈j,k〉—
RAB = *r7 r7 = sp+IM11 — 1 1 2
*r7 = RC r7 = sp+IM11 —
YE‡ = xhxh = XE —1+XC†12
Instruction Flags Cycles Words
szlme Out In
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For thi s tr ansfer, the postincre m ent opt ions *rME an d *rME–– are not available for double-wor d loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.
‡‡ The instr uction perf orms t he same function whether or not near (opt io na l) is inc lude d.
§§ Not including the N instructions.
Table 133. Instruction Set Summary (continued)
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Control Grou p
near goto IM12‡‡ —3—1
near call IM 12‡‡ —
if CON goto IM16 —3
†† —2
if CON c a ll IM1 6 —
far go to IM20 —3—
far call IM20 —
if CON goto ptE — 3†† —1
if CON call ptE —
if CON call pr —
tcall —3—
ic a ll IM 6 —
if CON return — 3†† —
ireturn — 3 —
treturn —
ei
di —11
Cache Group
do K {N_INSTR} — 1§§ —1
§§
redo K —2—1
do cloop {N_IN STR} — 1§§ —1
§§
redo cloop —2—1
Instruction Flags Cycles Words
szlme Out In
†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cach e.
‡ For this transfer, the postincrement options *rME an d *rME–– are not available for do uble-word loads.
§ The – (40-bit subtra ction) oper ation is encoded as aDE=aSE+IM16 with the IM16 value negated.
†† For condit ional branch instructions, the execution tim e is two cycles if the branch is no t taken.
‡‡ The instructi on per forms the same functi on whether or not near (optio na l) is inc lud e d.
§§ Not including the N instructions.
Advance Data Sheet
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any instructions
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 134 defines the symbols used in instruction descr iptions. S om e symbol s and charact ers are part of the
instruction syntax, and must appear as shown within the instruction. Other sym bols are representational and are
replaced by other characters. The table groups these two types of symbols sep arately.
Table 134. Notation Conventions for Instruction S et Descriptions
Symbol Meaning
Part of
Syntax * 16-bit x 16-bi t multiplication resul ting in a 32-bit prod uct.
Exception: if used as a prefix to an address register, denotes register-indirect addressing, e.g.,
*r3.
**2 Squaring is a 16-bit x 16-bit multiplication of the operand with itself, r esulting in a 32-bit product.
+ 40-bit addition†.
† The ALU/ACS and ADDER perform 40-bit operations, but the operands can be 16 bits, 32 bits, or 40 bits. In the special case of the split-mode
F1E instruction (xh=aSPEh±yh, xl=aSPEl±yl, aDE=aSEE+p0+p1, p0=xh**2, p1=xl**2), the ALU performs two 16-bit addition/subtraction
operations in parallel.
– 40-bit subtraction†.
++ Register postincrement.
–– Re gister postdecrem ent.
>> Arithmetic ri ght shift (with si gn-ext ension from bit 39).
<< Arithmetic left shift (padded with zeros).
>>> Logical right shift (zero guard bits before shift).
<<< Logical left shi ft (padded with zeros; sign-extended from bit 31).
& 4 0-bi t bitwise logical AND†.
| 40-bi t bitw ise logical OR†.
^ 40-bit bitwise logical exc lusive-OR †.
: Register shuffle‡.
‡ Note that this symbol does not denote compound addressing as it does for the DSP16XX family.
~ Ones complement (bitwise inverse).
( ) Parentheses encl ose mult ipl e operands deli m ited by commas that are al so part of the synt ax.
{ } Brace s enclose multiple instruct ions within a cache loop.
_
(underscore) T he un der score c har acter in dicate s a n accum ulato r vect or (conca ten ation of t he h igh hal ve s of a
pair of sequential accumula tors, e.g. , a0_1h).
lower-case Lower-case characters appear as shown in the instruction.
Not Part
of Syntax
(Replaced)
〈 〉Angle brackets enclose items delimited by commas, one of which must be chosen.
Mid bra ces enclos e one or more optional items delimited by commas.
±Replaced by either + o r –.
UPPER-
CASE Upper-cas e characters, character str ings, and characters plus numerals (e.g., M, CON, and
IM16) are replaced. Replacement tables accompany each instruction group description.
F Titl es Represents a stat em ent of a DAU function:
F1 MAC.
F1E Extended MAC.
F2 Special funct ion.
F2E Extended special function.
F3 ALU.
F3E Extended ALU.
F4 BMU.
F4E Extended BMU.
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 135. Over all Replacement Table
Symbol Used in
Instruction
Type(s)
Replaced By Description
aD F1, F2, F3,
F4 a0 or a1
(DSP16XX-compatible) D indicates destination of an operation.
aS S indicates source of an operation.
aT F1 T indi cates an a ccumul ator that is the so urce of a data
transf er.
a indi cates an accumulator other than the destination
accumulator.
aDE F1E, F2E,
F3/E, F4 /E a0, a1, a2, a3, a4, a5, a6, o r a7 D indicates destination of an operation. Sindicates
source of an operation. T i ndica tes an ac cu m u l a t o r
that i s eit her an additional source for an operation or
the source or desti nation of a data transfe r. E indi-
cates the extended set of accumulators.
aSE
aTE F1E, F3/ E,
F4/E,
data move
aDEE F1E, F3E a〈DPE – 1〉 → a0, a2, a4, or a6 D indicates destination of an operation. Sindicates
source of an operation. T i ndica tes an ac cu m u l a t o r
that i s eit her an additional source for an operation or
the sour ce or destination of a data tra nsfer. The f irst E
indicates an even accumu lat or that is pai red with it s
corresponding paired extended ( odd) accumul ator,
i.e., the matc hing aDPE, aSPE, or aTPE accumul ator.
The second E indicat es the extended set of accumu-
lators.
aSEE a〈SPE – 1〉 → a0, a2, a4, or a6
aTEE F3E a〈TPE – 1〉 → a0, a2, a4, or a6
aDPE F1E, F3E a〈DEE + 1〉 → a1, a3, a5, or a7 P indicates an o dd accumulator that is paired with an
even extended accumulator, i.e., the mat ching aDEE,
aSEE, or aTEE accumulator. E indicates t he
extended set of accumulators.
aSPE a〈SEE + 1〉 → a1, a3, a5, or a7
aTPE F3E a〈TEE + 1〉 → a1, a3, a5, or a7
aE_Ph F1E a0_1h, a2_3h, a4_5h, or a6_7h An accumulator vector, i.e., the concatenated 16-bit
high hal ves of two adjacent accumulators to form a
32-bit vector.
arM F4, F4E ar0, ar1, ar2, or ar3 One of the four auxiliary accumulators.
CON F1E, F2,
F2E , F3E,
F4E,
control,
data move
mi, pl, eq, ne, lvs, lvc, mvs, mvc, heads,
tails, c0ge, c0lt, c1ge, c1lt, true, false, gt,
le, oddp, evenp, smvs, smvc, jobf, jibe,
jcont, lock, mgibe, mgobf, somef, somet,
allf, or allt
Conditi onal mnemoni cs. Certain instructions are con-
diti onally executed, e.g., if CON F2E. Se e Table 138
on page 226.
FUNC F3, F3E max, min, or divs One of three ALU functions: maximum, minimum, or
divide-step.
IM4 d ata move 4-bi t unsign ed immediat e value (0 to 15) Signed/unsi gne d statu s of the I M4 value mat ches that
of the dest ination register of the dat a mov e assign-
ment instru cti on.
4-bit signed immediate value (–8 to +7)
IM5 d ata move 5-bi t unsign ed immediat e value (0 to 31) Added to stack pointer sp to form stack address.
IM6 control 6-bit unsigned immediate value (0 to 63) Vect or f or icall in struction.
IM8O
IM8W F4 8-bit unsigned i mme diate value (0 to 255) Offset and width for bit-field insert and extract instruc-
tions. The BMU truncat es these val ues to 6 bits.
IM11 d ata move 11-bit unsigne d imm ediate value
(0 to 2047) Added to stack pointer sp to form stack address.
† The s ize of the transfer (single- or double-word) depend s on the size of the regist er on the other side of the equa l sign.
‡ These postmodi ficat ion opt ions ar e not ava ilable for a do uble-word load e xcept fo r a load of an accu mulator vector.
DD
Table 135. Over all Replacement Table (continued)
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Advance Data Sheet
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IM12 co ntrol 12-bi t signed immediate value
(–2048 to +2047) PC- relative near address for goto and call instruc-
tions.
data move
and
pointer
arithmetic
Postmodi ficat ion t o a general YAAU pointe r regi ster to
form address for data move.
Added to t he val ue o f a ge nera l YAAU poi nter regi ste r ,
and the result is stored into any YAAU regi ster.
IM16 co ntrol 16-bi t signed immediate value
(–32,768 to +32,767) Offs et for conditional PC-rela tive goto/call ins t ruc -
tions.
F3, F4 Operand for ALU or BMU operation.
IM20 control,
data move 20-bit unsi gned immediate value
(0 to 1, 048,576) Absolute (unsigned) far addr ess for goto and call
instr u ctions. For dat a move instructions, the
signed/uns igned status of the IM20 value matches
that of the destination regi ster of the assignme nt
instruction.
20-bit signed immedia te val ue
(–524,288 to 524,287)
K cache 1 to 127 or the value i n cloop For the do K {N_INSTR} and redo K cache instruc-
tions.
N 1 to 31
OP F1, F1E, F 3,
F3E +, –, &, |, or ^40-bit ALU operati on.
pE F2E, F3,
F3E p0 or p1 One of the product registers as source for a special
function or ALU operation.
ptE F1E, control,
data move pt0 or pt1 One of the two XAAU pointer registers as addre ss for
an XE memory access (see XE entry in this table).
RA data move a0, a1, a2, a3, a4, a5, a6, a7, a0 h, a1h,
a2h, a3h, a4h, a5h, a6h, a7h, a0l, a1 l , a2l,
a3l, a4 l, a5 l , a6l, a7l, alf, auc0, c0, c1, c2,
h, i, j, k, p0, p0h, p0l, p1, p1h, p1l, pr,
psw0, pt0, pt1, r0, r1, r2, r3, r4, r5, r6 , r7,
rb0, rb1, re0, re1, sp, x, xh, xl, y, yh, or yl
One of the main core registers t hat is specified as t he
source or destination of a dat a mo ve operation. The
subscripts are used to indi cate that t wo differ ent reg is-
ters can be speci fi ed, e.g., RAD = RAS descr ibes a
register-to-register move instruction where RAD and
RAS are, i n general, two di ff erent registers.
RAD
RAS
RB core a0g, a1g, a2g , a3g, a4g, a5 g ,
a6g, a7g, a0_1h, a2_3h, a4_5h,
a6_7h, ar0, ar1, ar2, ar3, auc1,
cloop, cstate, csave, inc0, inc1, ins ,
pi, psw1, ptrap, vbase, or vsw
One of the s econd ary regi ster s that i s speci fied as t he
source or destination of a dat a mo ve operation. This
set includes core and off-core registers.
off-core cbit, imux, jiob, mgi, mgo, pid,
pllcon, pllfrq, pllfrq1, plldly, sbit,
signal, timer0, timer1, timer0c,
timer1c
RAB Any of the RA or RB registers
(see rows above) Any one of the registers i n the main (RA) or second-
ary (RB) set s of registers that is specifi ed as the
source or destination of a dat a mo ve operation. The
subscripts are used to indi cate that t wo differ ent reg is-
ters can be specified.
RABD
RABS
RC Any of the RA register s or any of the core RB
registers (see rows above) Any core register that is specified as the sour ce of a
data move operation.
rM F1,
data move r0, r1, r2, or r3 O ne of f our g eneral YAAU pointer registers used for a
Y-memory access (see Y entry in this table).
Symbol Used in
Instruction
Type(s)
Replaced By Description
† The s ize of the transfer (single- or double-word) depend s on the size of the regist er on the other side of the equa l sign.
‡ These postmodification options are not availa ble for a double-word load exce pt for a load of an accumulator vector.
Table 135. Over all Replacement Table (continued)
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
rME F1E,
data move r0, r1, r2, r3, r4, r5 , r6, or r7 One of eight general YAAU pointer registers used for
a YE memory access (see YE entry in this table). E
indicates the extended set of pointer registers.
rNE F1E r1, r2, r3, r4, r5, r6, or r7 One of seven general YAAU poin ter re gisters us ed f or
a table l ook-up pointer upda te.
RP data move
and
pointer
arithmetic
r0, r1, r2, r3, r4, r5, r6, or sp One of seven general YAAU pointer register s or the
YAAU stack pointer.
RY r0, r1, r2, r3, r4, r5, r6, r7, sp,
rb0, rb1, re0, re1, j, or kAny one of the YAAU registers , in cluding the stack
pointer, circular buffer pointers, and i ncrement regis-
ters.
XF1 *pt0++ or *pt0++iA single-word location pointed to by pt0.
YF1 *rM, *r M++, *rM––, or *rM++j A single-word location pointed to by rM.
F1YrM++, rM––, or rM++j Modi fi cation of rM point er register (no mem ory
access).
data move *rM, *rM++, *rM––, or *rM++j A sing le- or double-word † location pointed to by rM.
XE F1E,
data move *ptE‡, *ptE++, *ptE––‡, *ptE++h,
or *ptE++i A single-word or double-word† memory locati on
pointed to by ptE.
F1EXE ptE++, ptE––, ptE++h, ptE++i,
or ptE++2 Modification of ptE pointer register (no memory
access).
YE F1E,
data move *rME, *rME++, *rME––, *rME++j,
or *rME++k A single-word or double-word† memory location
pointed to by rME.
F1EYE rME++, rME––, rME++j, rME++k, rME++2,
or rME––2 Modifi cation of rME pointer regis ter (no memor y
access).
Symbol Used in
Instruction
Type(s)
Replaced By Description
† The s ize of the transfer (single- or double-word) depend s on the size of the regist er on the other side of the equa l sign.
‡ These postmodi ficat ion opt ions ar e not ava ilable for a do uble-word load e xcept fo r a load of an accu mulator vector.
Advance Data Sheet
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Use
p
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p
any instructions
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 136 defines the F1 instruction syn tax as any function statement combined with any transfer statement. Two
types of F1 func tion statements are shown: the MAC (multiply/accumulate) type and the arithmetic/logic type. The
MAC type is formed by co mbining any two items from the designated ALU and Multiplier columns. The arith-
metic/logic type is chosen from the items in the designated F1 Arithmetic/Logi c Function Statement co lumn.
Table 136. F1 Instructio n Syntax
Combine Any F1 Function Statement wi th Any Transfer Statement
F1 MAC Function Statement—
Combine Any Items in Following Two Columns: Transfer Statement Cycles
(Out/In
Cache)†
† Not including conflict, misalignment, or external wait-states (see the
DSP16000 Digi tal Signal Proce ssor Core
Informatio n Manual ).
16-Bi t
Words
ALU Multiplier
aD = aS ± p0 p0 = xh * yh Y‡
‡ This Y transfer statement must increment or decrement the contents of an rM register. It is not necessary to include the * before the rM reg-
is ter because no access is made to a memory location.
1/1 1
(no ALU operation)§
§ Leave the ALU column blank to specify no ALU operation, the multiplier column blank to specify no multiply operation, or both columns
blank to specify no F1 function statement. If both columns are left blank and a transfer statement is used (a transfer-only F1 instruction,
i.e., yh = *r2 xh = *pt0++), the assembler interprets the F1 function statem ent as a nop.
(no multiply operation)§〈x, y, a ††〉〈h, l〉 = Y
†† For this instruction, a must be the opposite of aD, e.g., if aD is a0, a mus t be a1 and vi ce vers a.
1/1
F1 Arithmetic/Logic Functi on Statement (ALU) Y = 〈y, aT〉〈h, l〉1/1
aD = aS OP yyh = 〈Y, aTh〉xh = X 1 + XC‡‡/1
‡‡ XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruction types an d
can only be avoided by use of the cache. See the
DSP16000 Digi tal Signal Proce ssor Core
Informatio n Manual .
aS – y (no tran sfer) §§
§§ The assembler encodes an instruction that consists of a function statement F1 with no transfer statement as F1 *r0.
1/1
aS & y
nop†††
†††nop is no-operati on. A program m er can write nop with or wi thout an accompanying tra nsfer statement. The assemble r encodes nop with-
out a transfer statement a s nop *r0.
(no F1 function statement)§
D
D
D
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 137 on page 224 summarizes the syntax for F1E function statements and the fo llowing paragraphs describe
each class of instruction.
Note: Each function stat ement can be combined wit h a parallel transfer statem ent to form a single DSP16411
instruction.
General -Pu rp ose MAC Com bine any ALU, ADDER, or ALU and ADDER operation from the left column
with any single- or dual-multiply operation from the right column. Either column
can be left blank.1
Additional General-Purpose MAC
These statements are general-purpose. The combinations of operations must be
as shown. The first statement clears two accumulators and both product
registers. The second sta tement is the equivalent of the F1 statement
aD = p0 p0 = xh * yh ex cept that any accum ulator aDE can be specified. The
third statement is the equivalent of the F1 statement aD = p0 except that any
accumulator aDE can be specified. The fourth statement is a no- operation and,
as with all F1E function statements, can be combined with a transfer statement.
Special-Purpose MAC for Mixed Precision
Combine any AD DER operation or any ALU and ADDER operation from the left
column with any dual-multiply operation from the right column. Either column can
be left blank.1These statemen ts are intended for, but are not limited to, mixed-
precision MAC applications. Mixed-precision multiplication is 16 bits x 31 bits.
Special-Purpose MAC for Double Precision
These statements are intended for , but are not limited to, double-precision MAC
applications. The combinations of operations must be as shown. Double-preci-
sion multiplication is 31 bits x 31 bits.
Special-Purpose MAC for Viterbi
These statements are intended for, but are not limited to, Viterbi decoding applica-
tions. The combinations of operations must be as shown. This group includes
ALU split -mode operations.
Special-Purpose MAC for FFT This statement is intended for, but is not limited to, FFT applications.
ALU These statements are ALU operations. The first three statements in this group
are the equivalent of the F1 a rithmetic/logic fun ction statement s.
Special-Purpose ALU/ACS, ADDER/ACS for Viterbi
These statements are intended for, but are not limited to, Viterbi decoding applica-
tions. They provide either an ALU/ACS operation with or without a pa rallel
ADDER/ACS operation or split-mode ALU and ADDER operations. The combina-
tions of operations must be as shown. This group includes the Viterbi co mpa re
functions.
Special-Purpose ALU, BMU These statements are intend ed for, but are not limited to, special-purpose
applications. They provide a BMU operation with or without a parallel ALU opera-
tion. The combinations of operations must be as shown.
1. If both columns are left blan k and a transfer stat ement is used, the DSP1600 0 assemb ler interprets the F1E function st atemen t as a no-oper-
at io n (nop).
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 137. F1E Function Statement Syntax
General-Purpose MAC Function Statements—Combine Any Items in Two Columns
ALU†ADDER†Multipliers
aDE=aSE±p0 p0=xh*yh
aDE=aSE±p0±p1‡p0=xh*yh p1=xl*yl
aDEE=aSEE±p0 aDPE=aSPE±p1 p0=xh*yl p1=xl*yh
(no ALU/ACS or ADDER operation) p0=xh*yh p1=xh*yl
p0=xl*yh p1=xl*yl
(no multiply operation)
Additional Gener al-Purp ose MAC Function Statements
ALU†ADDER†Multipliers
aDE=0 aSE=0 p0=0 p1=0
aDE=p0 p0=xh*yh
aDE=p0
nop
Special- Purpose MAC Functi on Statement s for Mixed Precisi on—Combine Any Items in Two Columns
ALU†ADDER†Multipliers
aDE=p0+(p1>>15)§p0=xh*yh p1=xh*(yl>>>1)
aDEE=aSE+aDPE aDPE=p0+(p1>>15)§p0=xl*yh p1=xl*(yl>>>1)
(no ALU/ACS or ADDER operation) (no multiply operation)
Special-Purpose MAC Function Statements for Double Precision
ALU†ADDER†Multipliers
aDE=aSE+p0+(p1>>15)‡ § p0=xh*yh p1=xh*(yl>>>1)
aDE=aSE+p0+(p1>>15)‡ §
aDE=p0+(p1>>15)§p0=0 p1=(xl>>>1)*yh
aDEE=aSE+aDPE aDPE=p0+(p1>>15)§p0=0 p1=(xl>>>1)*yh
aDE=(p0>>1)+(p1>>16) p0=(xl>>>1)*yh p1=xh*yh
aDEE=aSE+aDPE aDPE=(p0>>1)+(p1>>16) p0=(xl>>>1)*yh p1=xh*yh
aDE=aSE+(p0>>1) p0=xh*(yl>>>1) p1=(xl>>>1)*(yl>>>1)
aDE=(aSE>>14)+p1 p0=xh*(yl>>>1) p1=(xl>>>1)*(yl>>>1)
aDE=(aSE>>14)+p1
† DA U f l ags ar e aff ected by the ALU or ALU/ACS operat i on (ex cept for the spl it-mode funct i on which doe s not affect the fla gs). If there i s no ALU or
ALU/ ACS operatio n, the DAU fl ags are aff e cted by the AD DER or BMU opera tion.
‡If auc0[10] (FSAT field) is set, the result of the add/subtract of the first two operands is saturated to 32 bits prior to adding/subtracting the third operand
and the final result is saturated to 32 bits.
§If auc0[9] = 1, th e l east significan t bit of p1>>15 is cleared.
†† T hi s is a 16- bi t operation. The DA U st ores the resul t in th e hi gh half of t he desti natio n accumulator and c l ears the low half.
‡‡ T hi s split-mode ins truction does not affect the DAU flag s. Do n ot set FSAT for this instructi on beca use if FS AT is set , the entire 32 bits are saturated.
Table 137. F1E Function Statement Syntax (continued)
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Special-Purpose MAC Function Statements for Vite rbi
ALU†ADDER†Multipliers
xh=aSPEh+yh xl=aSPEl+yl†† aDE=aSEE+p0+p1 p0=xh**2 p1=xl**2
xh=aSPEh–yh xl=aSPEl–yl†† aDE=aSEE+p0+p1 p0=xh**2 p1=xl**2
aDE=aSE+p0+p1‡p0=xh**2 p1=xl**2
Special- Purpose MAC Functi on Stat em ent for FFT
ALU†ADDER†Multipliers
aDEE=–aSEE+p0 aDPE=–aSPE+p1 p0=xh*yh p1=xl*yl
ALU Function Statements
aDE=aSE OPy
aSE–y
aSE&y
aDE=aDE±aSE
Special -Purpose ALU/ACS, ADDER/ACS Funct ion Statements for Vit erbi
ALU/ACS†ADDER†
aDEE=cmp0(aSEE,aDEE) aDPE=aDPE+aSPE
aDEE=cmp0(aSEE,aDEE) aDPE=cmp0(aSPE,aDPE)
aDE=cmp0(aSE,aDE)
aDEE=cmp1(aSE,aDEE) aDPE=aDEE–aSE
aDEEh=cmp1(aSEEh,aSEEl)†† aDPEh=cmp1(aSPEh,aSPEl)††
aDE=cmp1(aSE,aDE)
aDEE=cmp2(aSE,aDEE) aDPE=aDEE–aSE
aDE=cmp2(aSE,aDE)
aDEE=aSEE+y aDPE=aSPE–y
aDEE=aSEE−y aDPE=aSPE+y
aDEEh=aSEh+yh aDEEl=aSEl+yl‡‡ aDPEh=aSEh−yh aDPEl=aSEl−yl‡‡
aDEEh=aSEh−yh aDEEl=aSEl−yl‡‡ aDPEh=aSEh+yh aDPEl=aSEl+yl‡‡
Special-Purpose ALU, BMU Function Stat em ents
ALU†BMU†
aDEE=rnd(aDPE) aDPE=aSEE>>aSPEh
aDE=aSEE>>aSPEh
aDE=abs(aDE) aSE=aSE<<ar3
aDE=aSE<<ar3
aDE=aSE<<<ar3
aDEE=min(aDPE,aDEE) aDPEh=exp(aSE)
† DA U f l ags ar e aff ected by the AL U or ALU/ACS operati on (ex cept for the spl it-mode funct i on which doe s not affect the fla gs). I f th ere is no AL U or
ALU/ ACS operatio n, the DAU fl ags are aff e cted by the AD DER or BMU opera tion.
‡If auc0[10] (FSAT field) is set, the result of the add/subtract of the first two operands is saturated to 32 bits prior to adding/subtracting the third operand
and the final result is saturated to 32 bits.
§If auc0[9] = 1, th e l east significan t bit of p1>>15 is cleared.
†† T hi s is a 16- bi t o perati on. T he DAU st ores the resul t i n the high half of t he desti natio n accum ul ator and clear s t he low hal f.
‡‡ T hi s split-mode ins truction does not affect the DAU flag s. Do n ot set FSAT for this instructi on beca use if FS AT is set , the entire 32 bits are saturated.
Advance Data Sheet
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6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
6.1.1 Conditions Based on the State of Fla gs
A conditi onal instr uction begins with either if C ON or ifc CON, where CON is replaced with a condition that is
tested. Table 138 describes the complete set of condition codes available for use in conditional instructions. It also
includes the state of the internal flag or flags that cause the condition to be true.
Table 138. DSP16411 Conditional Mnemo nics
CON
Encoding CON
Mnemonic Flag(s )
If CON Is True Type†
† All peripheral (off -co re) fla gs ar e accessible in the alf register.
Description
00000 mi LMI = 1 Core Most recent DAU res ult is negat ive.
00001 pl LMI ≠ 1 Core Most recent DAU result is positive or zero.
00010 eq LEQ = 1 Core Most recent DAU resul t is equal to zero.
00011 ne LEQ ≠ 1 Core Most rec ent DAU result is not equal to zero.
00100 lvs LLV = 1 Core Most rec ent DAU result has overflo w ed 40 bit s.
00101 lvc LLV ≠ 1 Core Most rec ent DAU result has not overflowed 40 bi ts.
00110 mvs LMV = 1 Core Most recent DAU result has overflowed 32 bits.
00111 mvc LMV ≠ 1 Core Most recent DAU resul t has not overflowed 32 bi ts.
01000 heads — Core Pseudorandom sequ ence generator outpu t i s set.
01001 tails — Core Pseudorandom bi t i s cleared.
01010 c0ge‡
‡ Eac h te st of c0ge or c0lt causes counter c0 to posti ncrem ent . Each test of c1ge or c1lt caus es counter c1 to postin crem en t.
— Core Current value in counter c0 is greate r than or equal to zero.
01011 c0lt‡— Core Current value in counter c0 is less than zero.
01100 c1ge‡— Core Current value i n counter c1 is greate r than or equal to zero.
01101 c1lt‡— Core Current value in counter c1 is less than zero.
01110 true 1 Core Always.
01111 false 0 Core Never.
10000 gt (LMI ≠ 1)
and (LEQ ≠ 1) Core Most recent DAU res ult is greater than zero.
10001 le (LM I = 1)
or (LEQ = 1) Core Most recent DAU result is less than or equal to zero.
10010 smvs SLMV = 1 Core A previous result has overflowed 32 bit s (sticky flag).
10011 smvc SLMV ≠ 1 Core A previous result has not overf lowed 32 b its since SLMV l ast cl eared.
10100 oddp EPAR ≠ 1 Core Most recent 40-bit BMU result has odd parity.
10101 evenp EPAR = 1 Core Most recent 40-bit BMU resu lt has even pari ty.
10110 j obf JOBF = 1 JTAG jiob output buffer full.
10111 jibe JIBE = 1 JTAG jiob input buffer empty.
11000 jcont JCONT = 1 JTAG JT AG co nti nue.
11001 lock LOCK = 1 CLOCK PLL delay counter has reached zero.
11010 mgibe MGIBE = 1 MGU Input mes sage buffer register mgi is empty.
11011 m gobf MGOBF = 1 MGU Input mes sage buffer register mgo is full.
11100 som ef SOMEF = 1 BIO Some false, some input bits tested did not com pare succe ssful ly.
11101 som et SOMET = 1 BIO Some true, some input bits test ed com pared suc cessfully.
11110 allf ALLF = 1 BIO All false, no BIO input bits tested compared successfully.
11111 allt ALLT = 1 BIO All true, all BIO input bits tested compared successfully.
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6 Software Architecture (continued)
6.2 Regis t e rs
DSP16411 registers fall into one of the following thr ee
categories:
■Directly program-ac cessible (or register-mapped)
registers are directly accessible in instructions and
are designate d with lower-case bold, e.g ., timer0.
These re gisters are described in Section 6.2.1.
■Mem ory-map ped registers are accessible at a mem-
ory address and are designated with upper-case
bold, e.g., DSTAT. These registers are described in
Sect ion 6.2 .2 on page 231.
■Pin-accessible registers are accessible only through
the external device pins and are designated with
upper-cas e bold, i.e., ID. Each JTAG port contain s
the pin-accessible identification register, ID,
described in Table 1 52 on page 241. This register is
accessible via its associated JTAG port.
Note: The program counter (PC) is an addressing reg-
ister not accessible to the programmer or
through external pins. The core automa tically
controls this register to properly sequence the
instructions.
6.2.1 Directly Progra m-Ac cessibl e (Register-
Mapped) Registers
F igure 58 on p age 228 depicts the directly program-
accessible (register-mappe d) registers. The figure dif-
ferentiates core and off-core registers. As th e figure
indicates, the pllcon, pllfrq, pllfrq1, and pl ld ly regis-
ters are available in CORE0 only.
Note: There is write-to-read latency associated with
the pipelined IDB. The assembler compensates
for this. S ee the
DSP16000 Dig ital Signal Pro-
cess o r Co r e
Information Manual for further
details.
As shown in Figure 58 on page 228, the register-
mappe d registers cons ist of three types:
Data registers store data either from the result of
instruction execution or from memo ry. D ata registers
become source operands for instructions. This class of
registers also includes postincreme nt registers whose
contents are added to address registers to form new
addresses.
Co nt ro l an d Sta tus r egis ter s ar e used to determine
the state of the machine or to set different configura-
tions to control the machine.
Address registers are used to hold memory location
point ers. In some case s, the user can treat address
registers as general-purpose dat a registe rs accessible
by data move instruc tions.
Table 139 on page 229 summarizes the register-
mapped regist ers. It lists all valid register designators
as they appear in an instruction syntax. For each reg-
ister, the table specifies its size, whether it is readable
or writable, its type, whether it is signed or unsigned,
and the hardware function block in which it is located. It
also indicates whether the register is in the core or is
off-core. Off-co re register-mapped registers cannot be
stored to memo ry in a single instruction. For example,
the fo llowing instruc tion is not allo w ed and w ill gene r-
ate an error by the assembler:
*r0 = mgi // NOT ALLOWED
To store the contents of an off-core register t o memory,
first stor e the register to an intermediate register and
then stor e the intermediate register to memory. See the
example below:
a0h = mgi // a0h is intermediate reg.
*r0 = a0h // store mgi to memory
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (continued)
DS P16410B Pr ogr am-Accessibl e R egist er s f or Each C ore
Figure 58. DSP 16411 Program- Acce ssible Registers for Ea ch Core
XAAU DAUSYS
YAAU
JTAG
y
p0
a0
auc0
psw0
c0
c1
c2
CONTROL &
STATUS ADDRESS DATA
jiob
inc0
ins
cloop
alf
pt0 x
p1
a1
a2
a3
a4
a5
a6
a7
auc1
ar0
pt1
pi
pr
h
i
vbase
r0
r1
r2
r3
r4
r5
r6
r7
j
k
rb0
rb1
re0
re1
inc1
cstate
csave
ar1
ar2
ar3
sp
ptrap
16 16
20
20
20
20
32
40
16
20
32
16
TIMER0
16
timer0c
timer0
BIO
16
TIMER1
16
DSP16000 CORE
CLOCKS
32
psw1
vsw
IMUX
imux
16
MGU
signal
pid
mgi
mgo
16
COR E 0 ON LY
CORE0
sbit
cbit
timer1c
timer1
pllfrq
plldly
pllcon
pllfrq1pllfrq1
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (continued)
Table 139. Program- Access ible (Register-Map ped ) Registers by Type, Listed Alphabetically
Register Name Descr iption Size
(Bits) R/W†Type‡Signed§/
Unsigned Core/
Off-Core Function
Block
a0, a1, a2, a3, a4, a5, a6, a7 Accumulators 0—7 40 R/W data signed core DAU
a0h, a1h, a2h, a3h,
a4h, a5h, a6h, a7h Accumulators 0—7 ,
high hal ves (bi ts 31—16) 16 R/W data signed core DAU
a0l, a1l, a2l, a3l,
a4l, a5l, a6l, a7l Accumulators 0—7 ,
low halv es (bi ts 15—0) 16 R/W data signed core DAU
a0g, a1g, a2g, a3g,
a4g, a5g, a6g, a7g Accumula tor s 0—7 ,
guard bits (bits 39—32) 8 R/W data signed core DAU
a0_1h, a2_3h,
a4_5h, a6_7h Accu m u lat o r vec to rs
(concatenated high halves
of two adjacen t accumulat ors)
32 R/W data signed core DAU
alf AWAIT and flag s 16 R/W c & s unsigned c ore SYS
ar 0 , ar1 , ar 2, ar3 Aux ilia r y re g is te rs 0 —3 1 6 R/W da ta signed core DAU
auc0, auc1 Arithmetic unit control 16 R/W c & s unsigned core DAU
c0, c1 Counters 0 and 1 16 R/W data signed core DAU
c2 Counter holding register 16 R/W data signed core DAU
cbit BIO control 16 R/W c ontrol unsigned o ff-core BIO
cloop Cache loop count 16 R/W data unsigned core SYS
csave Cache save 32 R/W control unsigned core SYS
cstate Cache state 16 R/W control unsigned core SYS
hPoint er postincrement 20 R/ W data signed core XAAU
iPoint er postincrement 20 R/ W data signed core XAAU
imux Interrupt multiplex control 16 R/W control unsigned off-core IMUX
inc0, inc1 Interrupt control 0 and 1 20 R/W control unsigned core SYS
ins Interrupt status 20 R/C†† status unsigned core SYS
jPointer posti ncrement/off set 20 R/W data signed core YAAU
jhb High byt e of j (b it s 15—8) 8 R data unsigned core YAAU
jlb Low byte of j (bits 7—0) 8 R data unsigned core YAAU
jiob JTAG test 32 R/W data unsigned off-core JTAG
kPointer posti ncrement/off set 20 R/W data signed core YAAU
mgi Core-to-core message input 16 R data unsigned off-core MGU
mgo Core-to-core message output 16 W data unsigned off-core MGU
p0 Product 0 32 R/W data signed core DAU
p0h High half of p0 (bit s 31—16) 16 R/W data signed core DAU
p0l Low half of p0 (bits 15—0) 16 R/W data signed core DAU
p1 Product 1 32 R/W data signed core DAU
p1h High half of p1 (bits 31—16) 16 R/W data signed c ore DAU
p1l Low half of p1 (bits 15—0) 16 R/W data signed core DAU
pi Program interr upt return 20 R/W address unsigned core XAAU
pid Process or i dentification 16 R c & s unsigned o ff-core MGU
† R indicates that the register i s read abl e by ins truct i ons; W in di cates the regist er is writ able by instructi ons.
‡ c & s means contro l and status.
§ Signed registers are in two’s complement format.
†† C i ndi cates that the regis t er i s clea red and not set .
‡‡ T he I EN fiel d (bi t 14) of the psw1 regis ter is re ad only (writ es to this bit are i g nore d).
§§ T he VAL UE [6:0] fiel d (bits 6— 0) are re ad only (w ri tes to t hese b its are ig nored) .
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Registers (continued)
Table 139. Program -Access ible (Register-Map ped ) Registers by Type, Listed Alphabetically (continued)
6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (cont inued )
pllcon Phase-lock loop control
(CORE0 only) 16 R/W control unsigned off-core Clocks
plldly Phase-lock loop delay control
(CORE0 only) 16 R/W control unsigned off-core Clocks
pllfrq, pllfrq1 Phase-lock loop frequency control
(CORE0 only) 16 R/W control unsigned off-core Clocks
pr Subroutine return 20 R/W address unsigned core XAAU
psw0, psw1 Program status words 0 and 1 16 R/W‡‡ c & s unsigned core DAU
pt0, pt1 Pointers 0 and 1 to X-memory space 20 R/W address unsigned core XAAU
ptrap Pr ogram trap return 20 R/W address unsigned core XAAU
r0 , r1, r2, r3 ,
r4, r5, r6, r7 Pointers 0—7 to Y-memory space 20 R/W address unsigned core YAAU
rb0 , rb 1 Circu lar buff er pointers 0 and 1
(begin address) 20 R/W address unsigned core YAAU
re0, re1 Circular buf fer point ers 0 and 1
(end address) 20 R/W address unsigned core YAAU
sbit BIO status/control 16 R/W§§ c & s unsigned off-core BIO
signal Core-to-core signal 16 W control unsigned off-core MGU
sp Stack pointer 20 R/W address unsigned core YAAU
timer0, timer1 Ti m er running count 0 and 1
fo r Timer0 an d Timer1 16 R/W data unsigned off-core Timer
tim e r0 c, ti m e r1 c Timer control 0 and 1
fo r Timer0 an d Timer1 16 R/W control unsigned off-core Timer
vbase Vector base offset 20 R/W address unsigned core XAAU
vsw Vi terbi support word 16 R/W control unsigned core DAU
xMulti plier in put 32 R/ W data signed core DAU
xh High hal f of x (b it s 31—16) 16 R/ W data signed core DAU
xl Low half of x (bits 15—0) 16 R/W data signed core DAU
yMulti plier in put 32 R/W data signed core DAU
yh High hal f of y (b it s 31—16) 16 R/ W data signed core DAU
yl Low half of y (bits 15—0) 16 R/W data signed core DAU
Register Name Descr iption Size
(Bits) R/W†Type‡Signed§/
Unsigned Core/
Off-Core Function
Block
† R indicates that the register i s read abl e by ins truct i ons; W in di cates the regist er i s writable by instructi ons.
‡ c & s means contro l and status.
§ Signed registers are in two’s complement format.
†† C i ndi cates that the regis t er i s clea red and not set .
‡‡ Th e IEN field (bit 14) of the psw1 re gi ster i s read on l y (writ es to this bit a re i g nore d).
§§ Th e VAL UE [6:0] field (bi ts 6— 0) are re ad only (writes to these bits are ig nored) .
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.2 Memory -Map ped Registers
The memory-mapped registers located in their associated peripherals are each mapped to an even address. The
sizes of these registers are 16 bits, 20 bits, or 32 bits. A register that is 20 bits or 32 bits must be accessed as an
aligned double word. A register that is 16 bits can be accessed as a single word with an even address or as an
aligned double word with the same even address. If a register th at is 16 bits or 20 bits is accessed as a double
word, the contents of the register are right-justified. Mem ory-mapped registers have the same internal format as
other registers and are different from memory. Figure 59 illustrat es three memor y- m apped regis t ers .
Figure 59. Example Memory-Mapped Registers
Note: Accessing memory-mapped registers w ith an odd address yields undefined results. The mem ory-m apped
registers are defined by name and equated to thei r even memo ry addresses in the include file that is pro-
vided with the
LUxWORKS
tools, 16411_mmregs.h. To differentiate the memory-mapped registers for SIU0
and SIU1, 16411_mmregs.h appends the suffix _U0 or _U1 to the register name. For example,
16411_mmregs.h defines SCON0_U0 as the address for the SIU0 SCON0 register and FSTAT_U1 as the
address for the SIU1 FSTAT register.
Memory-mapped regist ers are designated with upper-case bold. For example, the 32-bit DMAU status register
DSTAT is mapped to address 0x 4206C. The code segment example below acce sses DSTAT:
r0 = 0x4206C // Address of DSTAT.
nop
a0 = *r0 // Copy the contents of DSTAT to a0.
Alternatively:
#include "16411_mmregs.h"
r0 = DSTAT // Address of DSTAT (DSTAT defined as 0x4206C in 16411_mmregs.h).
nop
a0 = *r0 // Copy the contents of DSTAT to a0.
After the above code segme nt executes , the register a0 contains the value stored in DSTAT. The peripherals that
contain memory-m apped registers are listed below:
■DMAU (See Table 140 on page 232).
■SEMI (See Table 141 on page 233).
■PIU (See Table 142 on page 234 ).
■SIU0 and SIU1 (See Table 143 on page 234.)
CTL00x42060
0x4206C
ADDRESS
16 bits
32 bits
20 bits
SBAS0
DSTAT
REGISTER
0x42040
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.2 Memory -Map ped Registers (continued)
Table 140 summarizes the DMAU memory-mapped registers. These registers are described in detail in
Section 4.13. 2 on page 67.
Table 140. DMAU Memory-Ma pped Registers
Type Register
Name Channel Address Size
(Bits) R/W Type Signed/
Unsigned Reset
Value†
DMAU Status DSTAT All 0x4206C 32 R status unsigned X
DMAU Master Control 0 DMCON0 All 0x4205C 16 R/W control unsigned 0
DMAU Master Control 1 DMCON1 All 0x4205E
Channel Cont rol CTL0 SWT0 0x42060 16 R/W control unsigned X
CTL1 SWT1 0x42062
CTL2 SWT2 0x42064
CTL3 SWT3 0x42066
CTL4 MMT4 0x42068
CTL5 MMT5 0x4206A
Source Address SADD0 SWT0 0x42000 32 R/W address unsigned X
Destination Addr ess DADD0 0x42002
Source Address SADD1 SWT1 0x42004
Destination Addr ess DADD1 0x42006
Source Address SADD2 SWT2 0x42008
Destination Addr ess DADD2 0x4200A
Source Address SADD3 SWT3 0x4200C
Destination Addr ess DADD3 0x4200E
Source Address SADD4 MMT4 0x42010
Destination Addr ess DADD4 0x42012
Source Address SADD5 MMT5 0x42014
Destination Addr ess DADD5 0x42016
Source Count SCNT0 SWT0 0x42020 20 R/W data unsigned X
Destination Count DCNT0 0x42022
Source Count SCNT1 SWT1 0x42024
Destination Count DCNT1 0x42026
Source Count SCNT2 SWT2 0x42028
Destination Count DCNT2 0x4202A
Source Count SCNT3 SWT3 0x4202C
Destination Count DCNT3 0x4202E
Source Count SCNT4 MMT4 0x42030
Destination Count DCNT4 0x42032
Source Count SCNT5 MMT5 0x42034
Destination Count DCNT5 0x42036
† For this colum n, X ind i cates unkn own on po werup reset and unaff ected on su bsequent reset. Any reserv ed fields wit hi n the re gi ster are reset to zero.
‡ The reindex regist ers are i n sign-magnitud e fo rmat.
6 Software Architecture (continued)
6.2 Registers (continued)
Table 140. DMAU Memory-Ma pped Registers (continued)
6.2.2 Memory -Map ped Registers (continued)
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Table 141 summarizes the SEMI memory-m apped registers . T hese registers are described in detail in
Section 4.14. 4 on page 110.
Table 141. SEMI Memor y-Mapped Registers
Limit LIM0 SWT0 0x42050 20 R/W data unsigned X
LIM1 SWT1 0x42052
LIM2 SWT2 0x42054
LIM3 SWT3 0x42056
LIM4 MMT4 0x42058
LIM5 MMT5 0x4205A
Source Base SBAS0 SWT0 0x42040 20 R/W address unsigned X
Destination Base DBAS0 0x42042
Source Base SBAS1 SWT1 0x42044
Destination Base DBAS1 0x42046
Source Base SBAS2 SWT2 0x42048
Destination Base DBAS2 0x4204A
Source Base SBAS3 SWT3 0x4204C
Destination Base DBAS3 0x4204E
Stride STR0 SWT0 0x42018 16 R/W data unsigned X
STR1 SWT1 0x4201A
STR2 SWT2 0x4201C
STR3 SWT3 0x4201E
Reindex RI0 SWT0 0x42038 20 R/W data signed‡X
RI1 SWT1 0x4203A
RI2 SWT2 0x4203C
RI3 SWT3 0x4203E
Register Name Address Description Si ze
(Bits) R/W Type Reset Valu e
ECON0 0x40000 SEMI Contro l 16 R/W Contr ol 0x0FFF
ECON1 0x40002 SEMI Status and Control 16 R/W†
† Some bi ts in thi s regis t er are read-onl y or w ri t e-only.
Control 0‡
‡ With the fol l owing ex cepti ons: ECON1[6,4 ] are a reflecti on of the state of ex tern al pi ns and are unaffec ted by reset, and ECON1[5] i s se t.
EXSEG0 0x40004 External X Segment Register for CORE0 16 R/ W Address 0
EYSEG0 0x40006 External Y Segment Register for CORE0
EXSEG1 0x40008 External X Segment Register for CORE1
EYSEG1 0x4000A External Y Segment Register for CORE1
Type Register
Name Channel Address Size
(Bits) R/W Type Signed/
Unsigned Reset
Value†
† For this colum n, X ind i cates unkn own on po werup reset and unaff ected on su bsequent reset. Any reserv ed fields wit hi n the re gi ster are reset to zero.
‡ The reindex regist ers are i n sign-magnitud e fo rmat.
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.2 Memory -Map ped Registers (continued)
Table 142 summarizes the PIU memory-mapped registers. These registers are described in detail in
Section 4.15. 1 on page 135.
Table 142. PIU Registers
Table 143 summarizes the SIU memory-mapped registers. These registers are described in detail in
Section 4.16. 15 on page 184.
Table 143. SIU Memory-M apped Registers
Register Name Address Description Si ze
(Bits) R/W Type†Reset Value‡
PCON 0x41000 PIU Control and St atus 32 R/W§c & s 0x5
PDI 0x41008 PIU Data In from Host 32 R data X
PDO 0x4100A PIU Data Out to Host R/W
PA 0x41004 PIU Address for Host Access to DSP Memory 32 R/W address 0x0
DSCRATCH 0x41002 DSP Scratch 32 R/W data 0x0
HSCRATCH 0x41006 Host Scratch R
† c & s mean s control and s tatus.
‡ For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
§ Some bi ts of PCON are read-o nl y and som e bi ts are writ abl e by eit her the host or th e DSP, but n ot both.
Register
Name Address Description Size
(Bits)†R/W Type‡Reset
Value
SIU0 SIU1
SCON0 0x43000 0x44000 SIU Input/Output General Control 16 R/W control 0x000 0
SCON1 0x43002 0x44002 SIU Input Frame Control 0x0400
SCON2 0x43004 0x44004 SIU Outp ut Frame Control 0x0400
SCON3 0x43006 0x44006 SIU Input/Output Subframe Control 0x0000
SCON4 0x43008 0x44008 SIU Input Even Subfram e Vali d Vector Cont rol 0x0000
SCON5 0x4300A 0x4400A SIU In put Odd Subfra me Valid V ecto r Control 0x0000
SCON6 0x4300C 0x4400C SIU Output Even Subframe Valid Vector Contro l 0x0000
SCON7 0x4300E 0x4400E SIU Output Odd Subframe Valid Vec tor Control 0x0000
SCON8 0x43010 0x44010 SIU Outp ut Even Subframe Mas k Vector Cont rol 0x0000
SCON9 0x43012 0x44012 SIU Outp ut Odd Subframe Mask V ector Control 0x0000
SCON10 0x43014 0x44014 SIU Input/Output Gene ral Control 0x0000
SCON11 0x43016 0x44016 SIU Input/Output Acti ve Clock Cont rol 0x0000
SCON12 0x43018 0x44018 SIU Input/Output Active Frame Sync Control 0x8000
SIDR 0x4301A 0x4401A SIU Input Data 16 R data 0x0000
SODR 0x4301C 0x4401C SIU Output Data W
STAT 0x4301E 0x4401E SIU Input/Output General Stat us 16 R/W§c & s 0x0000
FSTAT 0x43020 0x44020 SIU Input/Output Frame Status 16 R status 0x0000
OCIX0 0x43030 0x44030 SIU Output Channel Index for Even Subfram es 16 R/W control 0x0000
OCIX1 0x43032 0x44032 SIU Output Channel Index for Odd Subframes
ICIX0 0x43040 0x44040 SIU In put Channel Index for Even Subframes 16 R/W contr ol 0x0000
ICIX1 0x43042 0x44042 SIU In put Channel Index for Odd Subframes
† The SI U memor y-mapped regi ster size s repre sent bi ts used. The regi sters are ri ght -j usti fied and padded to 32 bi ts (the unused upper bits are zero-
filled).
‡ c & s mean s control and s tatus.
§ All bits of STAT are readable, an d some ca n be writ ten wit h one to cl ear them .
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings
Tables 144—168 describe the encodings of the d irectly program-acces sible registers.
Table 144. alf (AW AI T Low-Power and Flag) Register
15 14—109876 5 4 3 210
AWAIT Reserved JOBF JIBE JCONT LOCK†MGIBE MGOBF SOMEF SOMET ALLF ALLT
Bit Field Value Description R/W Reset
Value‡
15 AWAIT 0 Core operates nor m ally. R/W 0
1 Core enters power-saving standby m ode.
14—10 Reserved 0 Reserved—write with zero. R/W 0
9JOBF0JTAG jiob output buf fer is empty. R/W X
1JTAG jiob out p ut bu ffe r is ful l.
8JIBE0JTAG jiob input buffer is full. R/W X
1JTAG jiob input buffer is empty.
7 JCONT — JTAG continue flag. R/W X
6LOCK
†0 The PLL delay counter has not reached zero . R/W 0
1 The PLL delay counter has reached zero.
5MGIBE0Core’s input message buf fer register mgi is full. R/W X
1 Core’ s input message buff er regi st er mgi is empty ( wai ting to be wri tten by other
core).
4 MGOBF 0 Core’s output mess age buffer register mgo is empty. R/W X
1 Core’s output message buff er register mgo is full (waiting to be read by other
core).
3 SOMEF 0 Either all th e tested BIO input pins match th e test pattern, none of the BIO inp ut
pins are tested, or all the BIO pins are configured as outputs. R/W X
1 SO ME false—some or all tested BIO inputs pins do not match the test pattern.
2 SOMET 0 Either none of the tes ted BIO input pins match the test patte rn, none of the BIO
input pi ns were tested, or all the BIO pins are configured as outputs. R/W X
1 SOME true— som e or all test ed BIO input pins match the test pattern.
1 ALLF 0 Some or all of the tested BIO input pins match the test pat tern. R/W X
1 ALL false—either no tested BIO input bits match the test pattern, none of the
BIO input pins are tested, or all t he BIO pins are configured as output s.
0 ALLT 0 Not all (som e or none) of the tes ted BIO input bits match the test patt ern. R/W X
1 ALL tr ue—either all test ed BIO input bits match the test pattern, n one of the BIO
input pi ns inputs are tested, or all the BIO pins are confi gured as outp uts.
†LO CK is cle a red on de vice r eset or i f t he pllcon register is written.
‡ For this col um n, X indi cates unknown on powerup res et and unaff ected on subsequ ent reset.
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 145. auc0 (Arithmetic Unit Control 0) Register
15—14 13—11 10 9 8 7 6 5—4 3—2 1—0
P1SHFT[1:0] Reserved FSAT SHFT15 RAND X=Y= YCLR ACLR[1:0] ASAT[1:0] P0SHFT[1:0]
Bit Fi eld Value Description R/W Reset
Value
15—14 P1SHFT[1:0] 00 p1 not shifted. R/W 00
01 p1>>2.
10 p1<<2.
11 p1<<1.
13—11 Reserved 0 Reserved—write with zero. R/W 0
10 FSAT 0 Disa bled when zero. R/ W 0
1 Enable 32-bit saturation for the f ollowing r esults: the scaled out-
puts of t h e p0 and p1 regi sters, the intermediate result of the
3-input ADDER†, a nd the results of the ALU/ACS, ADDER/ACS,
and BMU.
R/W 0
9 SHFT15 0 p1>>15 in F1E operations performs normally. R/W 0
1 To support GSM- EFR, p1>>15 in F1E operations actually per-
for m s (p1>>1 6)<<1 clearing the least si gnificant bit.
8 RAND 0 Enable pseud orandom sequence generator (PSG).‡R/W 0
1 Reset and disable pseudorandom sequence generator (PSG).
7 X=Y= 0 Normal operation. R/W 0
1 Data transfe r st atements that load the y regist er also load the x
regist er with the same value.§
6 YCLR 0 The DAU clear s yl if it loads yh.R/W0
1 The DAU leaves yl unch anged if it loads yh.
5 ACLR[1] 0 The DAU clear s a1l if it loads a1h.R/W0
1 The DAU leaves a1l unchanged if it loads a1h.
4 ACLR[0] 0 The DAU clear s a0l if it loads a0h.R/W0
1 The DAU leaves a0l unchanged if it loads a0h.
3 ASAT[1] 0 Enable a1 saturation†† on 32-bit overflow. R/W 0
1Disable a1 satura t i on on 32- bit o ve rfl o w.
2 ASAT[0] 0 Enable a0 saturation†† on 32-bit overflow. R/W 0
1Disable a0 satura t i on on 32- bit o ve rfl o w.
1—0 P0SHFT[1:0] 00 p0 not shifted. R/W 00
01 p0>>2.
10 p0<<2.
11 p0<<1.
† Satura tion takes effe ct onl y if the ADDER has th ree input op erands and there is no A LU/AC S oper at i on i n the sam e i nstructi on.
‡ Aft er re-enabling the PSG by clea ri ng RA ND, the prog ram must wait on e in struct ion cy cl e befo re test ing the head s or tails cond ition.
§ The following apply:
Instructi ons that expl i citly lo ad any pa rt of the x register (i. e., x, xh, or xl) take precedence over the X=Y= mode.
Inst ructi ons that load yh (but not x or xh) loa d xh with the same data. If YCLR is zero, the DAU clears yl and xl.
Inst ructi ons that load yl load xl wit h th e same data and l eave yh and xh unchanged.
†† If enabled, 32-bit saturation of the accumulator value occurs if the DAU stores the value to memory or to a register. Saturation also applies if the DAU
stor es the lo w half, hi gh half , or guard bi ts of th e accum ul ator. T her e is no chan ge to the contents stored in t he acc um ul ator; onl y the value stored to
memory or a register is saturated.
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 146. auc1 (Arithmetic Unit Control 1) Register
15 14—12 11—6 5—0
Reserved XYFBK[2:0] ACLR[7:2] ASAT[7:2]
Bit Field Value Descri pti on R/W Reset Value
15 Reserved 0 Reserved—write with zero. R/W 0
14—12 XYFBK[2:0]†000 Normal operation. R/W 000
001 Any DAU function result stored into a6[3 1:0] is also stored into x.‡
010 Any DAU function result stored into a6[3 1:16] is also stored into xh.‡
011 Any DAU function result stored into a6[3 1:16] is also stored into xh, and any
DAU function result stored into a7[31:16] is also stored into xl.‡
100 Reserved.
101 Any DAU function result stored into a6[3 1:0] is also stored into y.§
110 Any DAU function result stored into a6[3 1:16] is also stored into yh.§††
111 Any DAU function result stored into a6[3 1:16] is also stored into yh, and any
DAU function result stored into a7[31:16] is also stored into yl.§‡‡
11 ACLR[ 7] 0 The DAU clears a7l if it loads a7h.R/W0
1 The DAU leaves a7l unchang ed i f it load s a7h.
10 ACLR[ 6] 0 The DAU clears a6l if it loads a6h.R/W0
1 The DAU leaves a6l unchang ed i f it load s a6h.
9 ACLR[ 5] 0 T he DAU cle ars a5l if it loads a5h.R/W0
1 The DAU leaves a5l unchang ed i f it load s a5h.
8 ACLR[ 4] 0 T he DAU cle ars a4l if it loads a4h.R/W0
1 The DAU leaves a4l unchang ed i f it load s a4h.
7 ACLR[ 3] 0 T he DAU cle ars a3l if it loads a3h.R/W0
1 The DAU leaves a3l unchang ed i f it load s a3h.
6 ACLR[ 2] 0 T he DAU cle ars a2l if it loads a2h.R/W0
1 The DAU leaves a2l unchang ed i f it load s a2h.
5 ASAT[7] 0 Enable a7 saturation§§ on 32-bit overflow. R/W 0
1 Disable a7 saturation on 32-bit overflow.
4 ASAT[6] 0 Enable a6 saturation§§ on 32-bit overflow. R/W 0
1 Disable a6 saturation on 32-bit overflow.
3 ASAT[5] 0 Enable a5 saturation§§ on 32-bit overflow. R/W 0
1 Disable a5 saturation on 32-bit overflow.
2 ASAT[4] 0 Enable a4 saturation§§ on 32-bit overflow. R/W 0
1 Disable a4 saturation on 32-bit overflow.
1 ASAT[3] 0 Enable a3 saturation§§ on 32-bit overflow. R/W 0
1 Disable a3 saturation on 32-bit overflow.
0 ASAT[2] 0 Enable a2 saturation§§ on 32-bit overflow. R/W 0
1 Disable a2 saturation on 32-bit overflow.
† If th e appli catio n enables any of the XYF B K modes, i.e., XYFB K[2: 0] ≠000, th e following apply:
Only if the DAU writes its result to a6 or a7 (e.g., a6 = a 3+p0 ) will the result be written to x or y. Data transfers or da t a m ove ope rations (e.g.,
a6 = *r2) l eave the x or y register unchanged reg ardless of the st ate of the XY F BK[2:0] field setting.
If the i nstructio n i ts el f l oads the same porti on of the x or y r egist er that t he X YFBK[ 2:0] f ie l d speci fies, the ins truction load takes prece dence .
‡ If th e appli catio n enables the X = Y = m ode (auc0[7] = 1), the XYFBK mode takes precedence.
§ If th e appli catio n enables the X = Y = m ode (auc0[7] = 1), the DAU also write s the y register value into the x, xh, or xl regis ter, as appropriate.
†† If the appli catio n enables the Y CLR mode (auc0[6] = 0), the DAU clears yl.
‡‡ If the application enables the YCLR mode (auc0[ 6] = 0 ) and the ins truction contai ns a result writt en to a6 and the operation writes no result to a7, th e
DAU clears yl. If the applicatio n enables the Y CLR mode and the inst ructi on writ es a resul t to a7, t he XYFBK mo de t akes preced ence an d the DAU
does not cl ear yl.
§§ If sa tura tion is enabled and a ny porti on of an accumulat or is stored t o m emory or a reg is ter, the DAU saturate s t he entire accum ul ator val ue and
stor es the appropriate port i on. The DAU does not change the content s of the accumul ator.
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 147. cbit (BIO Control) Register
15 14—8 76—0
Reserved MODE[6:0]/MASK[6:0] Reserved DATA[6:0]/PAT[6:0]
Bit Field Value Description R/W Reset
Value
15 Reserved 0 Reserved—write with zero. R/W 0
14—8 MODE[6:0]
(outputs†)
†An IO〈0,1〉BI T [ 6:0] pi n i s confi gured a s an output if the cor respo ndi ng DI RE C[ 6: 0] field (sbit[14 : 8]) has be en se t by t he us er softwar e. An
IO〈0,1〉BIT[6:0] pin i s confi gured as an input if the corres ponding DI REC[ 6:0] field has been cleared by t he user sof t ware or by device reset.
0 The BIO drives the corresponding IO〈0,1〉BIT[6:0] output pin to the corre-
sponding value in DATA[6:0]. R/W 0
1■If the corr espo nding DATA[6: 0] fiel d is 0, the BIO does not change the st ate
of the corresponding IO〈0,1〉BIT[6:0] output pin.
■If the corres ponding DATA[6:0] field is 1, t he BIO tog gles (inverts) the stat e
of the corresponding IO〈0,1〉BIT[6:0] output pin.
MASK[6:0]
(inputs†)0 The BIO does not test t he stat e of t he co rrespon ding IO〈0,1〉BIT[6 :0] i nput pi n
to determine the state of the BIO flags‡.
‡ The BIO flags are ALLT, ALLF, SOMET, and SOMEF. See Table 19 on page 52 for d etai ls on BIO fla g s.
1 The BIO compares th e state of the corr espon ding IO〈0,1〉BIT[6:0] i nput pin to
the corr espondi ng value in the P AT[6:0] f ield to deter mine the state of the BIO
flags‡; t rue if pin mat ches or false if pin doesn’ t match.
7 Reserved 0 Reserved—write with zero. R/W 0
6—0 DATA[6:0]
(outputs†)0■If the corr espondi ng MODE[6:0] field i s 0, the BIO drives the correspondi ng
IO〈0,1〉BIT[6:0] output pin to logic 0.
■If the corresponding MO DE[6:0] fi eld is 1, the BIO does not change the
state of the corresponding IO〈0,1〉BIT[6:0] output pin.
R/W 0
1■If the correspondi ng MODE[6:0] field is 0, the BIO drives the correspondi ng
IO〈0,1〉BIT[6:0] output pin to logic 1.
■If the corresponding MO DE[6:0] fi eld is 1, the BIO toggl es (i nvert s) t he
state of the corresponding IO〈0,1〉BIT[6:0] output pin.
PAT[6:0]
(inputs†)0 If the correspo nding MASK[6:0] field i s 1, the BIO tests the state of the corre-
sponding IO〈0,1〉BIT[6:0] input pin to determine the state of t he BIO fl ags ‡;
true i f pi n is l ogic 0 or fal se if pin is logi c 1.
1 If the corr espondi ng MASK[6:0] fie ld i s 1, the BIO tests the state of the corre-
sponding IO〈0,1〉BIT[6:0] input pin to determine the state of t he BIO fl ags ‡;
true i f pi n is l ogic 1 or fal se if pin is logi c 0.
Advance Data Sheet
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 148. cloop (Cache Loop) Register
Table 149. csave (Cache Save) Register
Table 150. cstate (Cache State) Register
15—0
Cache Loop Count
Bit Field Description R/W Reset Value
15—0 Cach e Loop Count Contains t he count for the number of loop iterat ions for a do K, redo K, do
cloop, or redo cloop instruction. The core dec rements cloop after every
loop i teration and cloop contains zero after the loop has completed.
R/W 0
31—0
Cache Save
Bit Field Descr ipt ion R/W Reset Value†
31—0 Cache Save Contain s the opcode of the inst ructi on fol lowing a do K, redo K, do cloop, or
redo cloop in struction. R/W X
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
15 14 13 12—10 9—5 4—0
SU EX LD Reserved PTR[4:0] N[4:0]
Bit Field Value Description R/W Reset
Value
15 SU 0 T he cache is not sus pended—the core is not executing an interrup t or trap
service routine that has inte rr upted or trapped a cache lo op. R/W 0
1 The cache is suspend ed—the cor e is executi ng an inter rupt or trap ser vice
routine that has interrupted or trapped a cache loop.
14 EX 0 The core is not executing from cache—it is either loading the cache (exe-
cuting ite ration 1 of a cache l oop) or it is not executing a cache loop. R/W 0
1 The core is exec uting from cache—it is executing iterat ion 2 or higher of a
cache loop.
13 LD 0 T he co re is not l oading t he c ache—it is ei the r not e xecuti ng a cache l oop or
it is executing iteration 2 or higher of a cache loop. R/W 0
1 The core is loading the cache— it is executing it eration 1 of a cache loop.
12—10 Reserved 0 Reserved—write with zero. R/W 0
9—5 PTR[4:0] 0—30 Po inter to current in struc ti on in cache to load or execute. R/W 0
4—0 N[4:0]†0—31 Number of instructions in the cache loop to load/save/restore. R/W 0
† After execution of the first do K or do cloop inst ructi on, N[4:0] c ont ai ns a no nzero val ue.
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 151. imux (Interrup t Multiplex Control) Register
15—14 13—12 11—10 9—8 76543210
XIOC[1:0]†Reserved IMUX9[1:0] IMUX8[1:0] IMUX7 IMUX6 IMUX5 IMUX4 IMUX3 IMUX2 IMUX1 IMUX0
Bit Field Controls
Multiplexed
Interrupt
Value Interrupt
Selected Description R/W Reset
Value
15—14 XIOC[1:0]†XIO 00 0 (logic low) —R/W00
01 DMINT4 DMAU interrupt for MMT4.
10 DMINT5 DMAU interrupt for MMT5.
11 Reserved Reserved.
13—12 Reserved — 0 — Reserved—write with zero. R/W 0
11—10 IMUX9[1:0] MXI9 00 INT3 Pin. R/W 00
01 POBE PIU output buffer empty.
10 PIBF PIU input buffer full.
11 Reserved Reserved.
9—8 IMUX8[1:0] MXI8 00 INT2 Pin. R/W 00
01 POBE PIU output buffer empty.
10 PIBF PIU input buffer full.
11 Reserved Reserved.
7 IMUX7 MXI 7 0 SIINT1 SIU1 in put interr upt. R/W 0
1 DDINT2 DMAU destination int err upt for SWT2 (SIU1).
6 IMUX6 MXI 6 0 SOINT1 SIU 1 output int errupt. R/ W 0
1 DSINT2 DMAU sour ce interrupt for SWT2 (SIU 1).
5 IMUX5 MXI 5 0 SIINT0 SIU0 in put interr upt. R/W 0
1 DDINT0 DMAU destination int err upt for SWT0 (SIU0).
4 IMUX4 MXI 4 0 SOINT0 SIU 0 output int errupt. R/ W 0
1 DSINT0 DMAU sour ce interrupt for SWT0 (SIU 0).
3 IMUX3 MXI3 0 DDINT2 DMAU destination interrupt for SWT2 (SIU1). R/W 0
1 DDINT3 DMAU destination int err upt for SWT3 (SIU1).
2 IMUX2 MXI2 0 DSINT2 DMAU source interrupt for SWT2 (SIU1). R/W 0
1 DSINT3 DMAU sour ce interrupt for SWT3 (SIU 1).
1 IMUX1 MXI1 0 DDINT0 DMAU destination interrupt for SWT0 (SIU0). R/W 0
1 DDINT1 DMAU destination int err upt for SWT1 (SIU0).
0 IMUX0 MXI0 0 DSINT0 DMAU source interrupt for SWT0 (SIU0). R/W 0
1 DSINT1 DMAU sour ce interrupt for SWT1 (SIU 0).
† The XI OC[1:0] field control s the XIO in terrupt for th e other core .
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Each JTAG port has a read-only identification register , ID, as defi ned in Table 152. As specified in the table, the
contents of the ID register for JTAG0 are 0x1C815321 and the contents of the ID register for JTAG1 are
0x0C815321.
Table 152. ID (JTAG〈0—1〉 Identificati on) Registers
Table 153. inc0 and inc1 (Interrupt Con trol) Registers 0 and 1
31—28 27—19 18—12 11—1 0
DEVICE OPTIONS ROMCODE PART ID AGERE ID One
Bit Field Value Description R/W Reset Value
31—28 DEVICE OPTIONS 0x1 JTAG0—device options. R 0x1
0x0 JTAG1—d evice options. 0x0
27—19 ROMCODE 0x190 ROMCODE of device. 0x190
18—12 PART ID 0x15 Part ID—DSP16411. 0x15
11—1 AGERE ID 0x190 Agere identif ication . 0x190
0 On e 1 Logic one. 1
19—18 17—16 15—14 13—12 11—10 9—8 7—6 5—4 3—2 1—0
inc0 INT1[1:0] INT0[1:0] DMINT5[1:0] DMINT4[1:0] MXI3[1:0] MXI2[1:0] MXI1[1:0] MXI0[1:0] TIME1[1:0] TIME0[1:0]
inc1 MXI9[1:0] MXI8[1:0] MXI7[1:0] MXI6[1:0] MXI5[1:0] MXI4[1:0] PHINT[1:0] XIO[1:0] SIGINT[1:0] MGIBF[1:0]
Field Value Description R/W Reset
Value
INT〈0—1〉[1:0]
DMINT〈4—5〉[1:0]
MXI〈0—9〉[1:0]†
TIME〈0—1〉[1:0]
PHINT[1:0]
XIO[1:0]
SIGINT[1:0]
MGIBF[1:0]
00 Di sable the selected interrupt (no priority). R/W 00
01 Enable the sele cted interrup t at priority 1 (lowest) .
10 Enable the sele cted interrup t at priority 2.
11 Enable the sele cted interrup t at priority 3 (highest).
†See Table 5 on pag e 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 154. ins (Interrupt Status) Register
Table 155. mgi (Core-to-Core Message Input) Regis ter
Table 156. mgo (Core-to-Core Mess age Output) Register
Table 157. pid (Processor Identification) Register
19 18 17 16 15 14 13 12 11 10
MXI9 MXI8 MXI7 MXI6 MXI5 MXI4 PHINT XIO SIGINT MGIBF
9 8765432 1 0
INT1 INT0 DMINT5 DMINT4 MXI3 MXI2 MXI1 MXI0 TIME1 TIME0
Field Value Description R/W Reset Value
MXI〈0—9〉†
PHINT
XIO
SIGINT
MGIBF
INT〈0—1〉
DMINT〈4—5〉
TIME〈0—1〉
0 Read—corresponding interrupt not pending.
Wr ite—no effect. R/Clear 0
1 Read—corresponding interrupt is pending.
Wr it e—clears bit and changes correspondi ng interrupt status to not
pending.
†See Table 5 on pag e 28 for definition of MX I〈0—9〉 (IMUX〈0—9〉).
15—0
Mess age Input
Bit Field Descr ipt ion R/W Reset Value
15—0 Message Input Full-duplex message buffer that holds the input data word. R 0
15—0
Message Output
Bit Field Descr ipt ion R/W Reset Value
15—0 Message Output Full-duplex message buffer that holds the output data word. W 0
15—0
PID
Bit Field Value Description R/W Reset Value
15—0 PID 0x0000 CORE0 Processor identification t o all ow the software to dis ti n-
guish whet her it is running on CORE0 or CORE1. R 0x0000 CORE0
0x0001 CORE1 0x0001 CORE1
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6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 158. pllcon (Phase-L ock Loop Contro l) Register
Table 159. pllfrq (Phase-Lock Loop Frequency Control) Register
Table 160. pllfrq1 (Phase-Lo ck Lo op Frequ enc y Contro l 1) R egister
Table 161. plldly (Phase-Lock Loop Del ay Control) Register
Note: pllcon is acc es si ble in C OR E 0 on ly.
15—2 1 0
Reserved PLLEN PLLSEL
Bit Field Value Description R/W Reset Value
15—2 Reserved — Reserved—wri te with zero. R/W 0
1 PLLEN 0 Dis able (power down) the PLL. R/W 0
1 Enable (pow er up) the PLL.
0 PLLSEL 0 Sel ect the CKI input as the i nternal cl ock (CLK) sour ce. R/W 0
1 Select the PLL as the intern al cl ock (CLK) source.
Note: pllfrq is accessible in CORE0 only.
15—6 5—0
Reserved M[5:0]
Bit Field Value Description R/W Reset Value
15—6 Reserved — Res erved—write with zer o. R/W 0
5—0 M[5:0] 4—48 Defines M , which d etermi nes the fe edback cl ock divider cont rol se tting
(2(M + 2)). The value of M must be in the range 4 ≤M≤48. R/W 0
Note: pllfrq1 is accessible in CORE0 only.
15—9 87—4 3—0
Reserved PReserved N[3:0]
Bit Field Value Descrip tion R/W Reset Value
15—9 Reserved — Reserved—write with zero. R/W 0
8 P 0—1 Defines P, whi ch de termin es the VCO out put div ider c ont rol sett ing (P + 1). (Fo r a
value of fPCK of 240 M Hz or less, P must be set to 1.) R/W 0
7—4 Reserved — Reserved—write with zero. R/W 0
3—0 N[3:0] 0—4 Defines N, which determines the reference clock divider control setting (N + 1).
The value of N must be in the ra nge 0 ≤N≤4. R/W 0
Note: plldly is accessible in CORE0 only. 15—0
DLY[15:0]
Bit 15—0 Value Description R/W Reset Value
15—0 DLY[15:0] — The contents of DLY[15:0] are loaded i nto t he PLL delay
counter after a pllcon register wri te. If PLLEN
(pllcon[ 1]) i s 1 , the count er decrement s each CKI cycl e.
When the counter re aches zero, t he LOCK flag† for bot h
CORE0 and CORE1 is assert ed.
R/W 0x1388
† The state of the LOCK flag ca n be tested by condit i onal in st ructions ( Section 6.1.1 on page 226) and i s also v isi bl e in the alf regi ster (Table 14 4 on
page 235). T he LOCK flag is cleared by a device reset or a write to the pllcon regis ter.
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6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 162. psw0 (P ro cesso r Statu s Word 0) Regis ter
15 14 13 12 11 10 98—5 43—0
LMI LEQ LLV LMV SLLV SLMV a1V a1[35:32] a0V a0[35:32]
Bit Field Value Description R/W Reset
Value†
15 LMI 0 Mos t re cent DAU result‡ is not negative. R/W X
1 Most recent DAU result§ is negative (mi nus).
14 LEQ 0 Most recent DAU resul t§ is not zero. R/W X
1 Most recent DAU result§ is zero (equal).
13 LLV 0 Most re cent DAU operatio n§ did not result in logi cal overflow. R/W X
1 Most recent DAU operation§ resulted in logic al overflow.††
12 LMV 0 Mos t recent DAU operation did not result in mathematical ove rf low. R/W X
1 Most recent DAU operation§ resulted in mathematical overflow.‡‡
11 SLLV 0 Previous DAU operation did not result in logical overflow. R/W 0
1 Sticky version of LLV that remains active once set by a DAU operation until
explicitly cleared by a write to psw0.
10 SLMV 0 Previous DAU operation did not result in mathematical overflow. R/W 0
1 Sticky version of LMV that remains active once set by a DAU operation until
explicitly cleared by a write to psw0.
9 a1V 0 The current contents of a1 are not mathematically overflowed. R/W X
1 The current contents of a1 are mathematically overflowed.§§
8—5 a1[35:32] — Reflects the four lower guard bits of a1.††† R/W XXXX
4 a0V 0 The current contents of a0 are not mathematically overflowed. R/W X
1 The current contents of a0 are mathematically overflowed.§§
3—0 a0[35:32] — Reflects the four lower guard bits of a0.††† R/W XXXX
† In this co l um n, X indi cates unknown on powe rup reset and unaffected on su bsequ ent reset.
‡ ALU/ACS result or op erati on if th e i n structio n uses the ALU/ ACS; otherw i se, AD DER or BMU resu l t , whic hever applie s.
§ A LU/ AC S resul t i f the DA U operation uses the ALU/A CS; other wi se, ADDER or BM U result, whi che ver applies.
†† T he ALU or ADDER cannot repres ent the resu l t in 40 bits or the BM U con trol operan d i s out of range .
‡‡ T he ALU/ACS , A DDER, or BMU can not represen t the resu l t in 32 bit s. For t he BMU, othe r condit i ons can also cause mathemat ic al overflow.
§§ T he most recen t D AU result that was wri tten t o that accum ul ator result ed i n m athe m at i cal overflow (LMV ) wi th FS AT = 0.
††† Required for compatibility with DSP16XX family.
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6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 163. psw1 (Pro cesso r Status Word 1) Register
15 14 13—12 11—10 9—7 6 5—0
Reserved IEN IPLC[1:0] IPLP[1:0] Reserved EPAR a[7:2]V
Bit Field Value Description R/W Reset
Value†
15 Reserved 0 Reserved—write with zero. R/W 0
14 IEN‡0 Ha rdware inter rupts are gl obally disabled. R 0
1 Ha rdware inter rupts are gl obally enabled.
13—12 IPLC[1:0] 0 0 Current hardware int errup t priori ty l evel is 0; core handles pending int errupts of
priorit y 1, 2, or 3. R/W 00
01 Current hardware int errup t priori ty l evel is 1; core handles pending int errupts of
priority 2 or 3.
10 Current hardware int errup t priori ty l evel is 2; core handles pending int errupts of
priority 3 only.
11 Current hardware int errup t priori ty l evel is 3; core does not handle any pending
interrupts.
11—10 IPLP[1:0] 00 Previous hardware interrupt priority level§ was 0. R/W XX
01 Previous hardware interrupt priority level§ was 1.
10 Previous hardware interrupt priority level§ was 2.
11 Previous hardware interrupt priority level§ was 3.
9—7 Reserved 0 Reserved—write with zero. R/W X
6 EPAR 0 Mos t re cent BMU or special function shift resu lt has odd parity. R/W X
1 Mos t re cent BMU or speci al f unction shift result has even parity.
5 a7V 0 The current contents of a7 are not mathematically overflowed. R/W X
1 The current contents of a7 are mathematically overflowed.††
4 a6V 0 The current contents of a6 are not mathematically overflowed. R/W X
1 The current contents of a6 are mathemat ically overflowed.††
3 a5V 0 The current contents of a5 are not mathematically overflowed. R/W X
1 The current contents of a5 are mathemat ically overflowed.††
2 a4V 0 The current contents of a4 are not mathematically overflowed. R/W X
1 The current contents of a4 are mathemat ically overflowed.††
1 a3V 0 The current contents of a3 are not mathematically overflowed. R/W X
1 The current contents of a3 are mathemat ically overflowed.††
0 a2V 0 The current contents of a2 are not mathematically overflowed. R/W X
1 The current contents of a2 are mathemat ically overflowed.††
† In this co l um n, X indi cates unkn own on po werup reset and unaffected on subsequ ent reset.
‡ The user clears this bit by executing a di instructio n and sets it by ex ecuting an ei or ireturn instruction. The core clears this bit whenever it begins to
service an interrupt.
§ Previous int errup t priority level is th e priority level of the int errupt m ost recentl y servi ced pr i or to the curr ent interrupt. This f i el d i s use d for int errupt
nesting.
†† The most recen t D AU result that was wri tten t o that accum ul ator result ed i n m athe m at i cal overflow (LMV ) wi th FS AT = 0.
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 164. sbit (BIO Status/Control) Register
\
Table 165. signal (Core-to-Core Signal) Register
15 14—8 7 6—0
Reserved DIREC[6:0] Reserved VALUE[6:0]
Bit Field Value Description R/W Reset
Value†
15 Reserved X Reserved—writing to this field has no functional effect. R/W 0
14—8 DIREC[6:0]
(Con trols dir ec-
tion of pins)
0Configure the corresponding IO〈0,1〉BIT[6:0] pin as an input. R/W 0
1Configure the corresponding IO〈0,1〉BIT[6:0] pin as an output.
7 Reserved X Reserved—value is read-only and is undefined. R 0
6—0 VALUE[6:0]‡
(Current value of
pins)
0The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 0. RP
§
1The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 1.
† For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
‡ This fiel d i s read -only; writing the VALU E [6:0] fiel d of sbit has no eff ect. If the us er softw are toggl es a bit i n the DIREC[ 6:0] field, there is a lat ency of
one cycle until the V ALUE[6:0] field reflects the current state of the corresponding IO〈0,1〉BIT[ 6: 0] pin. If an IO〈0,1〉BIT[6:0] pi n is con f i gur ed as an out-
put (DIRE C[6:0] = 1) an d the user softw are write s cbit to ch ange the state of the pin, there is a la tency of two cyc l es unti l the VALUE[ 6:0] field ref l ects
the curre nt stat e of the co rresp onding IO〈0,1〉B IT[6:0] out put pin.
§ The IO〈0,1〉BIT [6:0] pi ns are configured as input s after reset . If ext ernal circu i tr y does n ot dri ve an IO〈0,1〉BIT[
n
] pin, t he VALUE[
n
] field is undefined
afte r reset.
15—11 1 0
Reserved SIGTRAP SIGINT
Bit Field Value Description R/W Reset
Value
1 5—11 Reser ved 0 Reserved—wr ite wi th zero. W 0
1 SIGTRAP 0 No effect . W 0
1 T rap the other core by asse rt ing its PTRAP signal.
0 SIGINT 0 No effect. W 0
1 Interr upt the other core by asse rt ing its SIGINT interr upt.
Note: If the program sets the SIGTRAP or SIGINT field, the MGU automatically clears the field after asserting the trap or interrupt. Th erefore, the pro-
gram must not explicitly clear the field.
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6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 166. timer0c and time r1c (TIMER〈0,1〉 Contr ol) Registers
15—7 6 5 4 3—0
Reserved PWR_DWN RELOAD COUNT PRESCALE[3:0]
Bit Fi eld Value Description R/W Reset
Value
15—7 Reserved 0 Reserved—write wit h zero. R/W 0
6 PWR_DWN 0 Power up the t imer. R/W 0
1 Power down the timer†.
5 RELOAD 0 Stop decrementi ng the down counter after it reaches zero. R/W 0
1 Automatically rel oad the down coun ter from the period regi ster after
the counter reaches zero and continue decrementing the counter
indefinitely.
4 COUNT 0 Hold the down counter at its current value, i.e. , st op the time r. R/W 0
1 Decrement the down counter, i.e., run the timer.
3—0 PRESCALE[3:0] 0000 Control s the counter prescaler to determ ine the fre-
quency of the timer, i.e., the frequency of the clock
appli ed to the timer down counter. This frequency is a
ratio of the internal clock frequency fCLK.
fCLK/2 R/W 0000
0001 fCLK/4
0010 fCLK/8
0011 fCLK/16
0100 fCLK/32
0101 fCLK/64
0110 fCLK/128
0111 fCLK/256
1000 fCLK/512
1001 fCLK/1024
1010 fCLK/2048
1011 fCLK/4096
1100 fCLK/8192
1101 fCLK/16384
1110 fCLK/32768
1111 fCLK/65536
†If TIMER〈0,1〉 i s powe red down , timer〈0,1〉 cannot be read or written. While the timer is powered down, the state of the down counter and period regis-
ter rem ain unc hanged.
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6.2 Regis t e rs (continued)
6.2.3 Register Encodings (continued)
Table 167. timer0 and timer1 (TIME R〈0,1〉 Running Count) Registers
Table 168. vsw (Viterbi Support Word) Register
15—0
TIMER〈0,1〉 Down Count er
TIMER〈0,1〉 Period Register
Bit Field†Description R/W‡Reset
Value§
15—0 Down Counter If the COUNT field (timer〈0,1〉c[4]) is set, TIMER〈0,1〉 decrements this portion
of the timer〈0,1〉 register every prescale period. When the down counter
reaches zero, TIMER〈0,1〉 generates an interrupt.
R/W 0
15—0 Peri od Register If the COUNT field (timer〈0,1〉c[4]) and the RELOAD field (timer〈0,1〉c[5]) are
both set and the down counter contains zero, TIMER〈0,1〉 reloads the down
counter with the contents of this portion of the timer〈0,1〉 register.
WX
† If the user program writ es t o the timer〈0,1〉 register, TIMER〈0,1〉 loads the 16-bit write val ue i nto the down counter and int o the pe ri od reg i st er
simultan eously. If the us er pro gram reads the timer〈0,1〉 register, TIMER〈0,1〉 r et urns the cur rent 16-bit va l ue from the dow n counter.
‡ To read or write the timer〈0,1〉 register , TIMER〈0,1〉 mus t be powered up, i .e., the PWR_DWN fiel d (timer〈0,1〉c[6]) must be cleared.
§ For thi s colu m n, X indic at es unk nown on power up rese t and un affected on sub seque nt reset .
15—6 543210
Reserved VEN MAX TB2 Reserved CFLAG1 CFLAG0
Bit Field V alue Descr ipt ion R/W Reset
Value
15—6 Reserved 0 Reserved—write with zero. R/W 0
5 VEN 0 Disables Viterbi side effects. R/W 0
1 E na ble s Vi t erb i side ef fec ts.
4MAX 0The cmp0( ) , cmp1( ), and cmp2( ) f uncti ons sel ect the min imum value
from the input operands. R/W 0
1The cmp0( ), cmp1( ), and cmp2( ) functions select the maximum
value from the input operands.
3TB2 0
(GSM/IS95-
compatible
mode)
For the single-ACS (40-bit) cmp1( ) function, the tracebac k encoder
stuffs one trace back bit into ar0. For the single-ACS (40-bit) cmp0( )
function, the traceback encoder stuffs one old traceback bit from ar0
into ar1. For the dual-ACS (16-bit) cmp1( ) fun ction, the traceback
encoder stuffs CFLAG into ar0 and ar2.
R/W 0
1
(IS54/IS136-
compatible
mode)
For the single-ACS (40-bit) cmp1( ) function, the tracebac k encoder
stuffs two traceback bits into ar0. For the single-ACS (4 0-bi t) cmp0( )
function, the traceback encoder stuffs two old traceback bits from ar0
into ar1.
2Reserved 0 Rese rved—wri te with zero. R/W 0
1CFLAG 1 — Previ ous val ue of CFLAG 0. The tr aceb ack encode r co pies t he va lue of
CFLAG0 to CFLAG1 if the DAU executes a cmp2( ) function and
VEN=1.
R/W 0
0CFLAG 0 — Previous val ue of CFLAG†. The traceba ck encoder copies the v alue of
CFLAG to CFLAG0 if the DAU executes a cmp2( ) function and
VEN=1.
† For the cmp2(aSE,a DE) function, CFLAG=0 if MAX=0 an d aS E≥aDE or if MA X=1 and aSE<aD E, and CFLA G=1 i f MAX=0 and aSE<aDE or if
MAX=1 and aSE≥aDE.
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6.2 Regis t e rs (continued)
6.2.4 Reset States
Pin reset occurs if a high-to-low transition is applie d to the RSTN pin. Tables 169 through 173 show how reset
affects the core and off-core registers. The following bit codes apply:
■Bit code • indicates that this bit is unknown on powerup res et and unaffected on a subsequent pin reset.
■Bit code P indic ates the value on the corresponding input pin.
Table 169. Core Register States After Reset—40-Bit Register s
Table 170. Core Register States After Reset—32-Bit Registers
Register Bits 39— 0
a0 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a1 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a2 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a3 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a4 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a5 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a6 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
a7 •••• •••• •••• •••• •••• •••• •••• •••• •••• ••••
Register Bits 31—0
csave •••• •••• •••• •••• •••• •••• •••• ••••
p0 •••• •••• •••• •••• •••• •••• •••• ••••
p1 •••• •••• •••• •••• •••• •••• •••• ••••
x•••• •••• •••• •••• •••• •••• •••• ••••
y•••• •••• •••• •••• •••• •••• •••• ••••
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.4 Reset States (continued)
Table 171. Core Register States After Reset—20-Bit Registers
Table 172. Core Register States After Reset—16-Bit Registers
Table 173. Off-Core (Peripheral) Register Reset Val ues
Register Bits 19—0 Register Bi ts 19—0
h•••• •••• •••• •••• •••• r1 •••• •••• •••• •••• ••••
i•••• •••• •••• •••• •••• r2 •••• •••• •••• •••• ••••
inc0 0000 0000 0000 0000 0000 r3 •••• •••• •••• •••• ••••
inc1 0000 0000 0000 0000 0000 r4 •••• •••• •••• •••• ••••
ins 0000 0000 0000 0000 0000 r5 •••• •••• •••• •••• ••••
j•••• •••• •••• •••• •••• r6 •••• •••• •••• •••• ••••
k•••• •••• •••• •••• •••• r7 •••• •••• •••• •••• ••••
PC†
†PC reset s to 0x30 000 (fir st addre ss of IRO M ) i f t he EXM pi n i s 0 at th e time of reset. It resets to 0x8000 0 (firs t addres s of
EROM) if the EX M pi n is 1 at the time of reset.
XXXX 0000 0000 0000 0000 rb0 0000 0000 0000 0000 0000
pi •••• •••• •••• •••• •••• rb1 0000 0000 0000 0000 0000
pr •••• •••• •••• •••• •••• re0 0000 0000 0000 0000 0000
pt0 •••• •••• •••• •••• •••• re1 0000 0000 0000 0000 0000
pt1 •••• •••• •••• •••• •••• sp •••• •••• •••• •••• ••••
ptrap •••• •••• •••• •••• •••• vbase 0010 0000 0000 0001 0100
r0 •••• •••• •••• •••• ••••
Register Bits 15—0 Register Bits 15—0
alf 0000 00•• •••• •••• c1 •••• •••• •••• ••••
ar0 •••• •••• •••• •••• c2 •••• •••• •••• ••••
ar1 •••• •••• •••• •••• cloop 0000 0000 0000 0000
ar2 •••• •••• •••• •••• cstate 0000 0000 0000 0000
ar3 •••• •••• •••• •••• psw0 •••• 00•• •••• ••••
auc0 0000 0000 0000 0000 psw1 0000 •••• •••• ••••
auc1 0000 0000 0000 0000 vsw 0000 0000 0000 0000
c0 •••• •••• •••• ••••
Register Bits 15—0 Register Bits 15—0
cbit •••• •••• •••• •••• pllfrq 0000 0000 0000 0000
imux 0000 0000 0000 0000 pllfrq1 0000 0000 0000 0000
mgi 0000 0000 0000 0000 plldly 0001 0011 1000 1000
mgo 0000 0000 0000 0000 sbit 0000 0000 0PPP PPPP
pid (C O R E0) 0000 0000 0000 0000 signal 0000 0000 0000 0000
pid (C O R E1) 0000 0000 0000 0001 timer〈0—1〉0000 0000 0000 0000
pllcon 0000 0000 0000 0000 timer〈0—1〉c0000 0000 0000 0000
jiob†•••• •••• •••• •••• •••• •••• •••• ••••
† The jiob regis ter is the only peri pher al regist er that is 32 bit s; ther ef ore, the bi t pattern sh own is for bi ts 31— 0.
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.4 Reset States (continued)
Table 174. Memory-Mapped Regist er Reset Va lues—32-Bit Regist ers
Table 175. Memory-Mapped Register Reset V alues—20-Bit Regist ers
Table 176. Memory-Mapped Register Reset V alues—16-Bit Regist ers
Register Bits 31—0
DADD〈0—5〉0000 0••• •••• •••• •••• •••• •••• ••••
DSCRATCH 0000 0000 0000 0000 0000 0000 0000 0000
DSTAT •••• •••• •••• •••• •••• •••• •••• ••••
HSCRATCH 0000 0000 0000 0000 0000 0000 0000 0000
PA 0000 0000 0000 0000 0000 0000 0000 0000
PCON 0000 0000 0000 0000 0000 0000 0000 0101
PDI 0000 0000 0000 0000 0000 0000 0000 0000
PDO 0000 0000 0000 0000 0000 0000 0000 0000
SADD〈0—5〉0000 0••• •••• •••• •••• •••• •••• ••••
Register Bits 19—0 Register Bits 19—0
DBAS〈0—3〉•••• •••• •••• •••• •••• RI〈0—3〉•••• •••• •••• •••• ••••
DCNT〈0—5〉•••• •••• •••• •••• •••• SBAS〈0—3〉•••• •••• •••• •••• ••••
LIM〈0—5〉•••• •••• •••• •••• •••• SCNT〈0—5〉•••• •••• •••• •••• ••••
Register Bits 15 —0 R eg ist er Bits 15—0
CTL〈0—3〉0000 0000 00•• •••• OCIX〈0—1〉0000 0000 0000 0000
CTL〈4—5〉0000 0000 00•• •••0 SCON0 0000 0000 0000 0000
DMCON〈0—1〉0000 0000 0000 0000 SCON〈1—2〉0000 0100 0000 0000
ECON0 0000 1111 1111 1111 SCON〈3—11〉0000 0000 0000 0000
ECON1 0000 0000 0P1P 0000 SCON12 1000 0000 0000 0000
EXSEG〈0—1〉0000 0000 0000 0000 SIDR 0000 0000 0000 0000
EYSEG〈0—1〉0000 0000 0000 0000 SODR 0000 0000 0000 0000
FSTAT 0000 0000 0000 0000 STAT 0000 0000 0000 0000
ICIX〈0—1〉0000 0000 0000 0000 STR〈0—3〉00•• •••• •••• ••••
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6 Software Architecture (continued)
6.2 Regis t e rs (continued)
6.2.5 RB Field En coding
Table 177 describes the encoding of the RB fie ld. This information supplem ents the instruction set encoding infor-
mation in the
DSP16000 Digital Signal Processor Core Instruction Set
Reference Man ual.
Table 177. RB Fie ld
RB†Register RB†Register RB†Register RB†Register
000000 a0g 010000 Reserved 100000 Reserved 110000 plldly
000001 a1g 010001 cloop 100001 Reserved 110001 Reserved
000010 a2g 010010 cstate 100010 pllfrq1 110010 Reserved
000011 a3g 010011 csave 100011 pllfrq 110011 Reserved
000100 a4g 010100 auc1 100100 signal 110100 Reserved
000101 a5g 010101 ptrap 100101 cbit 110101 Reserved
000110 a6g 010110 vsw 100110 sbit 110110 Reserved
000111 a7g 010111 Reserved 100111 timer0c 110111 Reserved
001000 a0_1h 011000 ar0 101000 timer0 111000 Reserved
001001 inc1 011001 ar1 101001 timer1c 111001 Reserved
001010 a2_3h 011010 ar2 101010 timer1 111010 Reserved
001011 inc0 011011 ar3 101011 mgo 111011 Reserved
001100 a4_5h 011100 vbase 101100 mgi 111100 Reserved
001101 pi 011101 ins 101101 imux 111101 Reserved
001110 a6_7h 011110 Reserved 101110 pid 111110 Reserved
001111 psw1 011111 Reserved 101111 pllcon 111111 jiob
† RB field s pecifies one of a secondary set of registers as the destination of a data move. Codes 000000 through 011111 correspond t o core regis t ers
and codes 100000 through 111111 correspond to off-core (peripheral) registers.
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7 Ball Grid Array Information
7.1 208-Ball PBGA Package
Figure 60 illust rates the ball assignment for the 208-ball PBGA pac kage. This view is fro m the top of the package.
Figure 60. 20 8-Ball PBGA Package Bal l Grid Array Assig nme nts (See -Throug h To p View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AVDD2 ED5 ED7 ED9 ED11 ED15 ED17 VSS VDD1 ED26 ED30 ERWN1 VSS EION EA1 VDD2 A
BED3 VDD1 ED6 ED8 VSS ED14 ED16 ED20 ED25 ED27 ED31 EROMN ERAMN EA0 VDD1 EA3 B
CED2 ED1 ED4 ED10 ED12 VDD1 ED18 ED21 ED24 VDD2 ED29 ERWN0 VDD2 EA2 EA4 EA5 C
DVSS ED0 VDD2 VDD1 ED13 VDD2 ED19 ED22 ED23 VSS ED28 EACKN VDD1 EA8 EA7 EA6 D
EEREQN ERDY ESIZE EXM EA11 EA10 VSS EA9 E
FTDO0 ERTYPE TRST0N TCK0 VDD2 VDD1 EA12 EA13 F
GTDI0 TMS0 VDD2A VSS2A VSS VSS VSS VSS EA17 EA16 EA14 EA15 G
HVDD1A CKI VSS1A RSTN VSS VSS VSS VSS ESEG1 ESEG0 EA18 VSS H
JVSS INT2 INT3 TRAP VSS VSS VSS VSS ESEG2 ESEG3 VDD1 ECKO J
KSICK0 SIFS0 INT0 INT1 VSS VSS VSS VSS VSS VDD2 TMS1 TDI1 K
LSOCK0 SOFS0 VDD1 VDD2 TCK1 TRST1N SOD1 TDO1 L
MSOD0 VSS SID0 SCK0 SID1 SCK1 SOCK1 SOFS1 M
NIO0BIT5 IO0BIT4 IO0BIT6 VDD1 PD10 PD6 VSS PD1 PD0 PRDY VDD2 PCSN VDD1 VDD2 SIFS1 VSS N
PIO0BIT3 IO0BIT2 IO0BIT0 VDD2 PD11 PD7 VDD2 PD2 POBE PINT VDD1 PADD3 PADD1 IO1BIT2 IO1BIT0 SICK1 P
RIO0BIT1 VDD1 EYMODE PD14 PD13 PD9 PD5 VDD1 PIBF PODS PRWN VSS PADD0 IO1BIT4 VDD1 IO1BIT1 R
TVDD2 VSS PD15 VSS PD12 PD8 PD4 PD3 VSS PRDYMD PIDS PADD2 IO1BIT6 IO1BIT5 IO1BIT3 VDD2 T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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7 Ball Grid Array Information (continued)
7.1 208-Ball PBGA Package (continued)
Table 178 describes the PBGA ball as signments sorted by symbol for the 208-ball package. For each signal or
power/ground connect ion, this table lists the PBGA coordina te, the symbo l name, the type (I = i nput , O = out put,
I/O = input/output, O/Z = 3-state output, P = power, G = ground), and descript ion.
Table 178. 208-Ball PBGA Ball Assignm ents Sorted Alphabeticall y by Symbol
Symbol 208-Ball PBGA Coordinate Type Description
CKI H2 I External Clock Input.
EA[18:0] H15, G13, G14, G16, G15, F16, F15, E13, E14, E16,
D14, D15, D16, C16, C15, B16, C14, A15, B14 O†SEMI Exter nal Address Bus, Bits 18—0.
EACKN D12 O‡SEMI External D evice Ackno wledge.
ECKO J16 O Programmable Clock Output.
ED[31:0] B11, A11, C11, D11 , B10, A10, B9, C9, D9, D8, C8,
B8, D7, C7, A7, B7, A6, B6, D5, C5, A5, C4, A4, B4,
A3, B3, A2, C3, B1, C1, C2, D2
I/O†SEMI External Memory Data Bus, Bits 31— 0. (If the
SEMI interface is not used, ED[31:0] can be statically
configu red as out puts by ass erting the EYMOD E pin. )
EION A14 O‡SEMI Enable for External I/O.
ERAMN B13 O‡SEMI External RAM Enable.
ERDY E2 I SEMI Exter nal Memory Device Ready.
EREQN E1 I‡SEMI External Device Request for EMI Interface.
EROMN B12 O‡SEMI Enable for External ROM.
ERTYPE F2 I SEMI EROM Type Control:
If 0, asynchronous SRAM mode.
If 1, synchronous SRAM mode.
ERWN0 C12 O‡SEMI Read/Write, Bit 0.
ERWN1 A12 O‡SEMI Read/Write, Bit 1.
ESEG[3:0 ] J14, J13, H13, H14 O†SEMI External Segment Address, Bits 3—0.
ESIZE E3 I SEMI External Memory Bus Size Cont rol:
If 0, 16-bit external interface.
If 1, 32-bit external interface.
EXM E4 I Ex ternal Boot- up Control fo r CORE0.
EYMODE R3 I SEMI External Data Bus Mode Configuration Pin.
INT[3:0] J3, J2, K4, K3 I External Interrupt Requests 3—0.
IO0BIT[6:0] N3, N1, N2, P1, P2, R1, P3 I/O BIO0 Status/Control, Bits 6—0.
IO1BIT[6:0] T13, T14, R14, T15, P14, R16, P15 I/O BIO1 Stat us/Cont rol, Bits 6—0 .
PADD[3:0] P12, T12, P13, R13 I†PIU Address, Bits 3—0.
PCSN N12 I‡PIU Chip Select.
PD[15:0] T3, R4, R5, T5, P5, N5, R6, T6, P6, N6, R7, T7, T8,
P8, N8, N9 I/O†PIU Data Bus, Bit s 15— 0.
PIBF R9 O PIU Input Buffer Full Flag.
PIDS T11 I PIU Input Data Strobe.
PINT P10 O PIU Inter rupt Request to Host.
POBE P9 OPIU Output Buffer Empty Flag.
PODS R10 IPIU Output Data Strobe.
PRDY N10 OPIU Host Ready.
PRDYMD T10 IPRDY Mode.
† These pins include bus hold circuits. If BHEDIS (ECON1[12]—Table 6 1 on pa ge 112) = 0, the bus hold circuits on EA[18:0], ESEG[3:0], and
ED[31:0] are acti vated. If BHPDIS (ECON1[13]) = 0, the bus hold circuits on PD[15:0] are activated. The bus hold circuits are enabled and
activated (BHEDIS = BHPDIS = 0) during and after reset. Activated bus hold circuits affect the electrical characteristics of the associated
pins . S ee Section 10.1, beginning on page 268, and Table 18 3 on page 267 for details.
‡ Negative-assertion.
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7 Ball Grid Array Information (continued)
7.1 208-Ball PBGA Package (continued)
PRWN R11 I‡PIU Read/Write.
RSTN H4 I‡De vice R es et.
SCK0 M4 IExternal Clock for SIU0 Active Generator.
SCK1 M14 IExternal Clock for SIU1 Active Generator.
SICK0 K1 I/O SIU0 In put Clock.
SICK1 P16 I/O SIU1 Input Clock.
SID0 M3 ISIU0 Input D a ta.
SID1 M13 IS IU1 In put Data .
SIFS0 K2 I/O SIU0 Input Frame Sync.
SIFS1 N15 I/O SIU1 Input Frame Sync.
SOCK0 L1 I/O SIU0 Output Clock.
SOCK1 M15 I/O SIU1 Output Clock.
SOD0 M1 O/Z SIU0 Output Data.
SOD1 L15 O/Z SIU1 Output Data.
SOFS0 L2 I/O SIU0 Output Frame Sync.
SOFS1 M16 I/O SIU1 Output Frame Sync.
TCK0 F4 IJTAG Test Clock for CORE0.
TCK1 L13 IJT AG Test Clock for CORE1.
TDI0 G1 IJTAG Test Dat a Input for CORE0 .
TDI1 K16 IJ TAG Test Data Input for CORE1.
TDO0 F1 OJTAG Test Data Output for CORE0.
TDO1 L16 OJTAG Test Data Output for CORE1.
TMS0 G2 IJTAG Test Mode Select for CORE0.
TMS1 K15 IJTAG Test Mode Select for CORE1.
TRAP J4 I/O TRAP/Breakpoint Indication.
TRST0N F3 I‡JTAG TAP Contr oller Reset for CORE0.
TRST1N L14 I‡JTAG TAP Contr ol ler Reset for CORE1.
VDD1 A9, B2, B15, C6, D4, D13, F14, J15, L3, N4, N13,
P11, R2, R8, R15 PPower Supply for Inter nal Circui tr y (1. 0 V nom inal).
VDD2 A1, A16, C13, D3, D6, F13, K14, L4 , N11, N14, P4,
P7, T1, T16, C10 PPower Supply for External (I/O) Cir cui try (3.3 V nomi-
nal).
VSS A13, A8, B5, D1, D10, E15, G7, G8, G9, G10, H7,
H8, H9, H10, H16, J1, J7, J8, J9, J10, K7, K8, K9,
K10, K13, M2, N7, N16, R12, T2, T4, T9
GGround.
VDD1A H1 PPower Supply 1 for PLL Circuitry (1.0 V nominal) .
VSS1A H3 GGround 1 fo r PLL Cir cui try.
VDD2A G3 PPower Supply 2 for PLL Cir cuitry (3.3 V nominal).
VSS2A G4 GGround 2 for PLL Circuitry.
Table 178. 208-Ball PBGA Ball Assignm ents Sorted Alphabeticall y by Symbol (continued)
Symbol 208-Ball PBGA Coordinate Type Description
† These pins include bus hold circuits. If BHEDIS (ECON1[12]—Table 6 1 on pa ge 112) = 0, the bus hold circuits on EA[18:0], ESEG[3:0], and
ED[31:0] are acti vated. If BHPDIS (ECON1[13]) = 0, the bus hold circuits on PD[15:0] are activated. The bus hold circuits are enabled and
activated (BHEDIS = BHPDIS = 0) during and after reset. Activated bus hold circuits affect the electrical characteristics of the associated
pins . S ee Section 10.1, beginning on page 268, and Table 18 3 on page 267 for details.
‡ Negative-assertion.
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8 Signal Descriptions
Figure 61 shows th e interface pinout for the DSP16411 . The signals can be separated into nine interfaces as
shown. Following is a de scription of these interfaces and the signals that com prise them.
DSP16411 Pinout by Interface
† These signals contain bus hold circuits. See Sect ion 1 0. 1 on page 268 for details.
Figure 61. DSP 16411 Pinout by Interface
SIU0
INTERFACE
ERWN1
ED[31:0]†
ERWN0
EA[18:0]†
TRST0N
SICK1
SCK1
SID1
SIFS1
SOFS1
TDI0
TCK0
SOCK1
SOD1
TDO0
TMS0
DSP16411
ESEG[3:0]†
ERTYPE
EION
ERAMN
EROMN
ERDY
SIU1
INTERFACE
TCK1
TDI1
TDO1
TMS1
TRST1N
INT[3:0]
CKI
ECKO
RSTN
IO0BIT[6:0]
TRAP
IO1BIT[6:0] BIO
INTERFACE
JTAG0
INTERFACE
SYSTEM AND
EREQN
EACKN
ESIZE
EXM
INTERFACE
MEMORY
EXTERNAL
SYSTEM
INTERFACE
PIDS
PD[15:0]†
PCSN
PADD[3:0]†
PRDY
PODS
PRDYMD
PRWN
PINT
PIBF
POBE
PIU
INTERFACE
SICK0
SCK0
SID0
SIFS0
SOFS0
SOCK0
SOD0
EYMODE
POWER
SUPPLY
VDD2
VDD1
VSS
VDD1A
VSS1A
JTAG1
INTERFACE
VDD2A
VSS2A
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8 Signal Descriptions (continued)
8. 1 Sys t em I nter f a ce
The system interface consists of the clock, interrupt,
and reset signals for the process or.
RSTN—D evice Reset: Negative assertion input. A
high-to-low transition causes the processor to enter the
reset state. Se e Section 4.3 on page 23 for details.
CKI—Input Clock: The CKI input buffer drives the
internal clock (CLK) directly or drives the on-chip PLL
(see Section 4.17 on page 200). The PLL allows the
CKI input clock to be at a lower frequen cy than the
internal clock.
ECKO— Prog rammab le Clock Ou tput: Buffered out-
put clock with opti ons programmable via the ECON1
register (see T able 61 on p age 112). The selectable
ECKO options are as fol lows:
CLK/2: A free-running output clock at half the fre-
quenc y of the internal clock. (This is the default
selection after reset.)
CLK/3.
CLK/4.
CLK: A free-running out put clock at the frequency of
the internal clock.
CKI: Clock input pin.
ZERO: A constant logic 0 output.
INT[3:0]—External Interrupt Request s: Positive
assertion inputs. Hardware interrupts to the DSP1641 1
are edge-sensitive, enabled via the inc0 register (see
Table 153 on page 241). If enabled and asserted prop-
erly with no equa l- or high er-priority interrupts being
serviced, each hardware interrupt causes the core to
vector to the memory location des cribed in Table 9 on
page 33. If an INT[3:0] pin is asserted for at least the
minimum required assertion time (see S ection 11 .7 on
page 281), the corresponding external interrupt request
is recorded in the ins register (see Table 154 on
page 242). If both INT0 and RSTN are asserted, all
output and bidirectional pins are put in a 3-state condi-
tion except TDO, which 3-states by JTA G control.
TRAP—TRAP/ Breakp oint Indication: Positive pulse
assertion input/output. If asserted, the processor is put
into the trap condition, which normally causes a branch
to the location vbase + 4. Although normally an input,
this pin can be configured as an output by the HDS
block. As an output, the pin can be used to signal an
HDS breakpoint in a multiple processor environment.
8.2 BIO Interface
I O 0 BIT[6:0]—BIO Sign a ls: Input/output. Each of
these pins can be independently configured via soft-
ware as either an input or an output by CORE0. A s
outpu ts, they can be independen tly set, toggled, or
cleared. As inputs, they can be tested independently
or in combinations for various data patterns.
I O 1 BIT[6:0]—BIO Sign a ls: Input/output. Each of
these pins can be independently configured via soft-
ware as either an input or an output by CORE1. A s
outpu ts, they can be independen tly set, toggled, or
cleared. As inputs , they can be tested independent ly
or in combinations for various data patterns.
8.3 Syst em and External Memory Interface
Note: The SEMI data and address buses (ED[31: 0],
EA[18:0], and ESEG[3:0]) contain internal bus
hold circuits. If BHEDIS (ECON1[12]—Table 61
on page 112 ) = 0, these bus hold c ircuits are
activate d. If BHEDIS = 0 and nei ther the SEM I
nor an external device is driving these buses, the
bus hold circuits hold them at their previous valid
logic level. This eliminates the need for external
pull-up or pull-down resistors on these pins. See
Section 10.1 on page 268 for details.
ED[31:0]—Bidirectiona l 32-Bit External Data Bus:
Input/ output. The external data bus ope rates as a
16-b it or 32-bit data bus, as determined by the state of
the ESIZE pin:
If defined as a 32-bit bus ( ESIZE = 1), the SEMI uses
ED[31:0]. If the cores or the DMAU attempt to initiate
a 16-bit transfer, the SEMI drives ED[31:16] for
accesses to an even address or ED[15:0] for
accesses to an odd address.
If defined as a 16-bit bus ( ESIZE = 0), the SEMI uses
ED[31:16] and 3-states ED[15: 0]. If the cores or the
DMAU attempt to initiate a 32-bit transfer to or from
external memory, the SEMI performs t wo 16-bit
transfers.
If the SEMI is not performing an external access , it
3-state s ED[31:0]. If the EYMODE pin is tied hig h,
ED[ 31:0] are statically configured as outp uts (see
description of EYMODE below).
ED[ 31:0] contain internal bus hold circuits. Se e
Section 10.1 on page 268 for details.
Advance Data Sheet
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8 Signal Descriptions (continued)
8.3 System and External Memory
Interface (continued)
EYMODE—E xternal Data Bus Mode: Input. This pin
determines the mode of the external data bus. It must
be static and tied to VSS (if the SEMI is used) or VDD2
(if the SEM I is not used). If EY MOD E = 1, the external
data bus pins ED[31:0] are statically configured as out-
puts (regardless of the state of RSTN) and must not be
connected external ly. If EY M ODE = 0, either external
pull-up resistors are needed on ED[31:0], or the bus
hold circuits must be enabled (BHEDIS (ECON1[12])
must be cleared). See Se ction 10. 1 on page 268 for
details.
EA[18:1]— E xtern al Address Bus Bits 18—1:
Output. The function of this bus depends on the state
of the ESIZE pin:
If the external data bus is configured as a 32-bit bus
(ESIZE = 1), the SEMI places the 18-bit external
addres s onto EA[18: 1].
If the external data bus is configured as a 16-bit bus
(ESIZE = 0), t he SEMI pl aces the 18 most significant
bits of the 19-bit external address onto EA[18:1].
After an access is complete and befor e the start of a
new access, the SEMI continues to drive EA[18:1] with
its current state. The SEMI 3-states EA[18:1] if it
grants a request by an external device to access the
external memory (see description of the EREQN pin).
EA[18:1] contain internal bus hold circuits. See
Section 10 .1 on page 268 for details.
EA0—External Address Bus Bit 0: Output. The func-
tion of th is bit depends on the state of the ESIZE pin:
If the external data bus is configured as a 32-bit bus
(ESIZE = 1), the SEMI does not use EA 0 as an
addres s bit:
— If the selected mem ory co mpo nent is configured
as asynchronous1, the SEMI drives EA0 with its
previous value.
— If the selected mem ory co mpo nent is configured
as synchronous1, the SEMI drives a negative-
assertion write strobe onto EA0 (the SEMI drives
EA0 with the logical AND of ERWN1 and
ERWN0).
If the external data bus is configured as a 16-bit bus
(ESIZE = 0), the SEMI places the least signifi cant bit
of the 19-bit external addre ss onto EA0.
After an acces s is complete and before the start of a
new access, the SEMI continues to drive EA0 with its
current state. The SEMI 3-states EA0 if it grants a
request by an external device to access the external
mem ory (see description of the EREQN pin).
EA0 contains an internal bus hold circuit. See
Section 10.1 on page 268 for details.
ESEG[3:0]—External Segment Address:
Output. The external segment address outputs provide
an additional 4 bits of address or decoded enables for
extending the external address range of the
DSP16411. The state of ESEG[3:0] is d et e r mi n ed by
the EXSEG0, EYSEG0, EXSEG1, and EYSEG1 re gis-
ters for a CORE0 or CORE1 external memory access.
Refer to Section 4.14.1.5 on page 106 for more details.
If the DMAU acce sses exte rnal memory, the SEM I
places the contents of the ESEG[3:0] field of the
SADD〈0—5〉 or DADD〈0—5〉 register onto the
ESEG[3:0] pin s ( se e Table 37 on page 77 for details).
If the PIU accesses external memory, the SEMI places
the conte nts of the ESEG[3:0] field of the PA register
onto the ESEG[3:0] pins (see Table 80 on page 138 for
details). ESEG[3:0] retain their previous state while
the SEMI is not performing external acce sses. The
SEMI 3-states ESEG[3:0] if it grants a request by an
external device t o access the external memory (see
descrip tion of the EREQN pin).
ERWN[1:0]—External Read/Write Not: Output. The
external read/write strobes are two separate write
strobes. In general, if driven high by the SEMI, these
signals indicat e an external re ad access. I f driven low,
these signal s indicate an external write access. How-
ever, the exact function of these pins is qualified by the
value of the ESIZE pin:
If ESIZE = 0 (16-bit data bus), ERWN1 is always
inactive (high) and ERWN0 is an active write strobe.
If ESIZE = 1 (32-bit data bus), ERWN0 is the write
enable for the upper (most significant) 16 bits of the
data (ED[31:16]) and ERWN1 is the write enable for
the lower (least significant) 16 bits of the data
(ED[15:0]).
The SEM I 3-states ERWN[1:0] if it grants a request by
an external device to access the external memory (see
descrip tion of the EREQN pin).
1. The EROM component is synchronous if the ERTYPE pin is
logic 1. The ERAM component is synchronous if YTYPE field
(ECON1[9]) is set. The EIO component is synchronous if the
ITYPE field (ECON1[10]) is set. ECON1 is described in Table 61
on page 112.
Advance Data Sheet
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8 Signal Descriptions (continued)
8.3 System and External Memory
Interface (continued)
ERAMN—ERAM Space Enable: Negative-assertion
output. Th e external RAM enable selects the ERAM
memory c omponent (external data memory). For asyn-
chronous accesses, the SEMI asserts ERAMN for the
number of cycles specified by the YATIME [3:0] field
(ECON0[7:4]—see Table 60 on page 111). For syn-
chronous accesses, the SEMI asserts ERAMN for one
ECKO cycle1. ERAM is configured as synchronous if
t h e YTYPE field ( ECON1[9]—see Table 61 on
page 112) is set. T he SEM I 3-states ERAMN if it
grants a request by an external device to access the
external memory (see description of the EREQN pin).
EROMN—EROM Space Enable: Negative -assertion
output. The external ROM enable selects the EROM
memory comp onent (external program memory ). F or
asynchronous accesses, the SEMI asserts EROMN for
the number of cycles specified by the XA TIME[3:0] field
(ECON0[3:0]—see Table 60 on page 111). For syn-
chronous accesses, the SEMI asserts EROMN for one
ECKO cycle1. EROM is configured as synchron ous if
the ER TYPE pin is high. The SEMI 3-st ates EROMN if
it grants a request by an external device to access the
external memory (see description of the EREQN pin).
EION—EIO Space Enable: Negative-assertion output.
The external I/O enable selects the EIO mem ory com-
ponent (external memory-map ped peripheral s or data
memory). For asynch ro nous acce sses, the SEMI
asserts EION for the number of cycles specifi ed by the
IATIME[3 :0 ] fi e ld (ECON0[11:8]—see Table 60 on
page 111). For synchronous accesses, the SEMI
asserts EION for one ECKO cycle2. EION is config-
ured as synchronous if the ITYPE field is set
(ECON1[10]—see Table 61 on page 112 ) is set. The
SEMI 3-states EION if it grants a request by an external
device to access the external memory (see description
of the EREQN pin).
ERDY—External Device Ready for SEMI Data: Posi-
tive-assertion input. The ext ernal READY input is a
control pin that allows an external device to extend an
external as ynchronous memory access. If driven low
by the external device, the SEMI extends the current
external memory access that is already in progress. To
guarantee proper operation, ERDY must be driven low
at leas t 4 CLK cycles befo re the e nd of t h e acc es s a nd
the enable must be programmed for at least 5 CLK
cycles of assertion (via the YATIME, XATIME, or
IATI ME field of ECON0— s ee Table 60 on page 111).
The SEM I ignores the state of ERDY prio r to 4 CLK
cycles before the end of the access. The access is
extended by 4 CLK cycles after ERDY is driven high.
The state of ERDY is readable in the EREADY field
(ECON1[6]—see Table 61 on page 112 .
Note: I f ERDY is not in use by the application or if all
external memory i s synchronous, ERDY must be
tied high.
EREQN—E xtern al Device Requests Access to
SEMI Bus: Negative-assertion input. An ex ternal
devic e asserts EREQN low to request the external
memory bus for access to extern al asyn ch ro nous
memory. If the NOSHARE field (ECON1[8]—see
Table 61 on page 112) is set, the DSP16411 igno res
the request . I f NOSHAR E is cleared, a minimum of
four cycles later the SE MI grants the request by per-
forming the following:
First, t he SEMI c ompletes any external access that is
already in progress.
The SEMI 3-states the address bus and segment
address (EA[18:0 ] and ESEG[3: 0]), the data bus
(ED[31:0]), and all the external enables and strobes
(ERAMN, EROMN, EION, and ERWN[1:0]) until the
external device deasserts EREQN. The SEMI con-
tinues to drive ECKO.
The SEMI ackno wledge s the request by asserting
EACKN.
The core s and the DMAU continue proc ess ing. If a
core or the DMAU attempts to perform an external
mem ory access, it stalls until the external device relin-
quishes the bus. If the external device deasserts
EREQN (changes EREQ N from 0 to 1), four cycles
later the SEM I deasserts EACKN (changes EACKN
from 0 to 1). To avoid external bus contention, the
external dev ice must wait for at least
ATIME
MAX
cycles3
after it deasserts EREQN (changes EREQN from 0 to
1) before reasserting EREQN (changing EREQN from
1 to 0). The softwar e can read the state of the EREQN
pin in the EREQN field (ECON1[4]—see Tab le 61 on
page 112).
1. If any memory compone nt is con figured as synchronous, ECKO
must be programmed as CLK/2, CLK/3, or CLK/4 (see t he
ECKOB[1:0] and ECKOA[1:0] fields (ECON1[3:0]—Tabl e 61 on
page 112).
2. If any memory compone nt is con figured as synchronous, ECKO
must be programmed as CLK/2, CLK/3, or CLK/4 (see t he
ECKOB[1:0] and ECKOA[1:0] fields (ECON1[3:0]—Tabl e 61 on
page 112). 3.
ATIME
MAX
is the greatest of IATIME(ECON0[11:8]), YATIME
(ECON0[7:4]), and XATIME (ECON0[3:0]).
Advance Data Sheet
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8 Signal Descriptions (continued)
8.3 System and External Memory
Interface (continued)
Note: If EREQN is not in use by the application, it must
be tied high.
EACKN—DSP16411 Acknowledges External Bus
Request: Negative-assertion output. The SEMI
acknowledges the request of an external device for
direct access to an asynchronous external memory by
asserting EACKN. See the description of the EREQN
pin on page 259 for details. The software can read the
state of the EA CK N pin in the EACKN field
(ECON1[5]— s ee Table 61 on page 112).
ESIZE—Si ze of Ext e rn a l SEMI Bu s: Input. The exter-
nal data bus size input determines the size of the active
data bus. If ESIZE = 0 , the external data bus is config-
ured as 16 bits and the SE MI uses ED[3 1:16] and
3-states ED[15:0]. If ESIZE = 1, the external data bus
is confi gured as 32 bits and the SEMI uses ED[31:0].
ERTYPE— EROM Type: Input. The external ROM
type input determines the type of memory device in the
EROM component (selected by the EROMN
enable). If ERTYPE = 0, the EROM component is pop-
ulated with ROM or asynchronous SRAM, and the
SEMI performs async hronous ac cesse s to the EROM
component . I f ERTYPE = 1, the EROM compo nent is
populated with synchronous
ZBT
SRAM and the SEMI
performs synchron ous accesses to the EROM comp o-
nent.
EXM—Boot Source: Input. The ext ernal executi on
memory input determines the active memory for pro-
gram execution after DSP16411 reset. If EXM = 0
when the RSTN pin makes a low-to-high transition,
both cores begin execution from their internal ROM
(IROM) memory at location 0x30000. If EXM = 1 when
the RSTN pin makes a low-to-high transition, both
cores begin execution from external ROM (EROM )
memory at location 0x800 00. I f the cores begin execu-
tion from external ROM, the SEMI arbitrates the
accesses from the two cores.
8.4 S IU0 In ter f a ce
SID0—External Serial Input Data: Input . By default,
data is latched on the SID0 pin on a falling edge of the
input bit clock (SI CK 0) during a selected channe l.
SOD0—External Serial Output Data: Output. B y
default, data is driven onto the SOD0 pin on a rising
edge of the output bit clock (SOCK0) during a selected
and unmasked channel. During inactive or masked
chan nel periods, SOD0 is 3-state.
SICK0—Input Bit Clock: Input/output. SICK0 can be
an input (passive input clock) or an output (active input
clock). The SICK0 pin is the input data bit clock. By
default, data on SID0 is latched on a falling edge of this
clock, but the active level of this cl ock can be changed
by the ICKK field (SCON10[3]—Table 113 on
page 191). SICK0 can be configured via software as
an input (passive, externall y generated ) or an outp ut
(active, internally generated) via the ICKA field
(SCON10[2]) and the ICKE field
(SCON3[6]—Ta ble 106 on page 188).
SOCK0—Output Bit Clock: Input/output. SOCK0 can
be an input (passive output clock) or an output (activ e
output clock). The SOCK0 pin is the output data bit
clock. By default, data on SO D0 is driven on a rising
edge of SOCK0 during active channel periods, but the
active level of this clock can be changed by the OCKK
field (SCON10[7]). SO CK0 can be configured via soft-
ware as an input (passive, externally generated) or an
output (active, intern ally generated) via the OCKA of
SCON10[6]) and the OCKE field (SCON3[14]).
SI FS 0 — In put Fra m e Synch ronizat i on : In put/ou tp u t .
The SIFS0 s ignal indicates the beginning of a new
input frame. By default, SIFS0 is active-high, and a
low-to-high transition (rising edge) indicates the start of
a new frame. The active level and position of the input
fram e sync relative to the first input data bit can be
chan ged via the IFSK field (SCON10[1] ) and the IFS-
DLY[1: 0] field (SCON1[9:8]—Table 104 on page 186 ),
respectively. S IFS 0 can be configured via software as
an input (passive, externall y generated ) or an outp ut
(active, internally generated) via the IFSA field
(SCON10[0]) and the IFSE field (SCON3[7]).
SOFS0 — Out p ut Fram e Sync hroniz at io n: Inpu t/out-
put. The SOFS 0 signal indicates the beginning of a
new output frame. By def ault, SOFS0 is active-high,
and a low-to-high transition (rising edge) indicates the
start of a new frame. The ac tive level and position of
the output frame sync relative to the first output data bit
can be changed via the OFSK field (SCON10[5]) and
the OFSDLY[1:0] field (SCON2[9:8]—Table 105 on
page 187), respectively. SOFS0 can be configured via
software as an input (passive, externally generated) or
an output (active, interna lly generated) via the OFSA
field (SCON10[4]) and the OFSE field (SCON3[15]).
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8 Signal Descriptions (continued)
8.4 S IU0 In ter f a ce (continued)
SCK0—External Clock Source: Input. The SCK0 pin
is an input that provides an external clock source for
generating the input and output bit clocks and frame
syncs. If enabled via the AGEXT field ( SCON12[12]—
Table 115 on page 195 ), the clock source applied to
SCK0 replaces the internal clock (CLK) for active mode
timing generation of the bit clocks and frame
syncs. The active level of the clock applied to th is pin
can be inverted by s etting the SCKK field
(SCON12[13]).
8.5 S IU1 In ter f a ce
SID1—External Serial Input Data: Input . By default,
data is latched on the SID1 pin on a falling edge of the
input bit clock, SICK1 , during a selected channel.
SOD1— Externa l Seria l Output Data: Output. By
default, data is driven onto the SOD1 pin on a rising
edge of the output bit clock, SOCK1, during a selected
and unmask ed channel. During ina ctive or masked
channel periods, SOD1 is 3-state.
SICK1—Input Bit Clock: Input/output. SICK1 can be
an input (pas sive input clock) or an output (active input
clock). The SICK1 pin is the input data bit clock. By
default, data on SID1 is latched on a falling edge of this
clock, but the active level of this clock can be change d
by the ICKK field (SCON10[3]—Table 113 on
page 191). SICK1 can be configured via software as
an input (passive, externally generated) or an output
(active, internally generated) via the ICKA field
(SCON10[ 2] ) and the ICKE field
(SCON3[6]—Table 106 on page 188).
SOCK1—Outpu t Bit Clock: I nput/output. SOCK1 can
be an input (passive output clock) or an output (active
output clock). The SOCK1 pin is the output data bit
clock. By default, data on SOD1 is driven on a rising
edge of SOCK1 durin g active channel periods, but the
active level of this clock can be changed by the OCKK
field (SCON10[ 7] ). S OCK 1 can be configured via soft-
ware as an inp ut (passive, externally generated) or an
output (acti ve, internally generated) via the OCKA field
(SCON10[ 6] ) and the OCKE field (SCON3[14]).
SI FS 1 — In put Fra m e Synch ronizat i on: In pu t/ou tp u t .
The SIFS1 s ignal indicates the beginning of a new
input frame. By default, SIFS1 is active-high, and a
low-to-high transition (rising edge) indicates the start of
a new frame. The active level and position of the input
fram e sync relative to the first input data bit can be
chan ged via the IFSK field (SCON10[1]) and the IFS-
DLY[1: 0] field (SCON1[9:8]), r e sp ec ti ve ly. SIFS1 can
be configured via software as an input (passive, exter-
nally generated) or an output (active, internally gener-
ated) via the IFSA field (SCON10[0]) and the IFSE
(SCON3[7]).
SOFS1 — Out p ut Fram e Sync hroniz at io n: Input/out-
put. The SOFS 1 signal indicates the beginning of a
new output frame. By def ault, SOFS1 is active-high,
and a low-to-high transition (rising edge) indicates the
start of a new frame. The ac tive level and position of
the output frame sync relative to the first output data bit
can be changed via the OFSK field (SCON10[5]) and
the OFSDLY[1:0] field (SCON2[9:8]—Table 105 on
page 187), respectively. SOFS1 can be configured via
software as an input (passive, externally generated) or
an output (active, internally generat ed) via the OFSA
field (SCON10[4]) and the OFSE field (SCON3[15]).
SCK1—External Clock Source: I nput. The SCK1 pin
is an input that provides an external clock source for
generat ing the input and output bit clocks and frame
syncs . I f enabled via the AGEX T field of
SCON12[12]—Table 115 on page 195), the clock
source appl ied to SCK1 replaces the internal clock
(CLK) for active mode timing generation of the bit
clocks and frame syncs . T he ac tive level of the clock
applied to this pin can be inverted by setting the SCKK
field (SCON12[13]).
Advance Data Sheet
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8 Signal Descriptions (continued)
8.6 P IU In te rf a c e
Note: The PIU data and address bu ses (PD[15:0] and
PADD[3:0]) contain internal bus ho ld circuits. If
BHPDIS (ECON1[13]—Ta ble 61 on
page 112) = 0 , these bus hold circuits are acti-
vated. If BHPDIS = 0 and neither the PIU nor an
external device is driving these buses, the bus
hold circuits hold them at their previous valid
logic level. This eliminates the need for external
pull-up or pull-down resistors on these pins. See
Section 10.1 on page 268 fo r details.
PD[15:0]—16 -B it Bidirectional, Parallel Data Bus:
Input/output. During host data reads, the DSP16411
drives the data contained in the PIU output data regis-
ter ( PDO) onto this bus. During host data writes, data
driven by the host onto this bus is latched into the PIU
input data register (PDI). If the PIU is not selected by
the host (PCSN is high), PD[15:0] is 3-state. PD[15:0]
contain internal bus hold circuits. See Section 10.1 on
page 268 for details.
PADD[3:0]—PIU 4-Bit Address and Control:
Input. Thi s 4-bit address input is driven by the host to
select between various PIU registers and to iss ue PIU
comman ds . Refer to Section 4.15.5 on page 147 for
details. If unused, these input pins should be tied low.
PADD[3:0] contain internal bus hold circuits. See
Section 10 .1 on page 268 for details.
PO BE— PIU Ou tp ut B uf fe r E mpt y Fl a g: Output. This
status pin directly reflects the state of the PIU output
data register (PDO). If POBE = 0, the PDO register
contains data ready for the host to read. If POBE = 1,
the PDO register is empty and there is no data for the
host to read. The hos t can read the state of this pin
any time PCSN is asserted low. The state of this pin is
also reflected in the PO BE field of the PCON register.
PIBF—PIU Input Buffer Full Flag: Output. Th is sta-
tus pin directly reflects the state of the PIU input data
register (PDI). If PIBF = 0, PDI is empty and the host
can safely write anoth er word to the PIU. If PIBF = 1,
PDI is full with the previous word that was writ ten by
the host. If the host issues another write to the PIU
while PIBF = 1, the previous data in PDI is
overwritten. The host can read this pin any time PCSN
is asserted low . The state of this pin is also reflected in
the PIBF field (PCON[1]—Table 75 on page 136).
PRDY—PIU Host Ready: Output . This status pin
directly reflects the stat e of the previous PIU host
transaction. It is used by the host to extend the current
access until the prev iou s a ccess is complete. The
active state of this pin is determined by the state of the
PRDYMD pin. The state of PRDY is valid only if the PIU
is activated, i.e., if PSTRN is asserted. (See
Sect ion 4.1 5.2.1 on page 140 f or a definition of
PSTRN.)
If PRDYMD = 0 , PRDY is active-low. If PRDY = 0,
the previous host read or host write is complete, and
the host can continue with the current read or write
transaction. If PRD Y = 1, the previous PIU read o r
write is still in progress (PDI is s til l full or PDO is still
empty) and the host must extend the current access
until PRDY = 0.
If PRDYMD = 1 , PRDY is active-high. If PRDY = 1,
the previous host read or host write is complete, and
the host can continue with the current read or write
transaction. If PRD Y = 0, the previous PIU read o r
write is still in progress (PDI is s til l full or PDO is still
empty) and the host must extend the current access
until PRDY = 1.
P I NT—P IU Inte r r upt: Output. Can be set by the
DSP16411 to generate a host interrupt. If a core sets
the PINT field (PCON[3]—Table 75 on page 136 ), the
PIU drives the PINT pin high to create a host interrupt.
After the host acknowledges the interrupt, it must clear
the PINT field (PCON[3]).
PRDYM D—PIU Ready Pin Mode: In p ut. D e te r min es
the active state of the PRDY pin. Refer to the PRDY
pin description above. I f unused , PRDYMD should be
tied low.
POD S—P IU Output Data Strobe: Input. Function is
dependent upon the host type (
Intel
or
Motorola
). If
unus ed, PODS must be tied high:
Intel
mode: In this mode, PODS functions as an out-
put data strobe and must be connected to the host
active-low read data strobe. The host read transac-
tion is initiated by the assertion (low) of PCSN and
PODS. I t is terminated by the deassertion (high) of
PCSN o r PODS .
Motorola
mode: In this mode, PODS functions as a
data strobe and must be connected to the host data
strobe. Th e active level of PODS (ac tive-high or
active-low) is determined by the state of the PIDS
pin. A host read or write transaction is initiated b y
the assertion of PCSN and PODS. It is terminated
by the deassertion of PCSN or PODS.
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8 Signal Descriptions (continued)
8.6 P IU In te rf a c e (continued)
PIDS—PIU Input Data Strobe: Input. Function is
dependent upon the host type (
Intel
or
Motorola
). If
unused, PIDS must be tied high:
Intel
mode: In this mod e, PIDS functions as an input
data strobe and must be connect ed to the host
active-low write data strobe. The host write transac-
tion is initiated by the assertion (low) of PCSN and
PIDS. It is term inated by the deassertion (high) of
PCSN or PIDS.
Motorola
mode: In this mode, the state of PIDS
determines th e active level of the host data strobe,
POD S. If PIDS = 0, PODS is an active-high data
strobe. If PIDS = 1, PODS is an active-low data
strobe.
PRWN—PIU Read/Write Not: Input. F unc tion is
dependent upon the host type (
Intel
or
Motorola
). In
either case, PRWN is driven high by the host during
host reads and driven low by the host during host
writes. PRWN must be stable for the entire access
(while PCSN and the appropriate data strobe are
asserted). If unused, PRWN must be tied high.
Intel
mode: In this mod e, PRWN is connecte d to the
active-low write data strobe of the host processor,
the same as the PIDS input.
Motorola
mode: In t his mode, PR WN functions as an
active read/write strobe and must be connected to
the RWN output of the
Motorola
host processor.
PCSN—PIU Chip Select: Negative-assertion input.
PCSN is the chip select from the host for shared-bus
systems. If PCSN = 0, the PIU of the selected
DSP16411 is active for transfers with the host. If
PCSN = 1, the PIU ignores any activity on PIDS,
PODS, and PRWN, and 3-states PD[15:0]. If unused,
PCSN mus t be tied high.
8.7 JTAG0 Test Interface
The JTAG0 test interface has features that allow pro-
grams and data to be downloaded into CORE0 via five
pins. This provides extensive test and di agnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Agere Systems provides hardware
and software tools to interface to the on-chip HDS via
the JTAG port.
Note: J TAG0 provides all JTAG/
IEEE
1149.1 standard
test capabilit ies including bound ary scan.
T D I0—J TAG Test Dat a Inp ut: Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO0—JT AG T est Data Output: Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS0—JTAG Test Mode Select: Mode control signal
that, combined with TCK0, controls the scan opera-
tions. T his pin has an internal pull-up resistor.
TCK0—JTAG Test Clock: Serial shi ft cl o ck. This sig-
nal clocks all data into the port through TDI0 and out of
the port through TDO 0. It also controls the port by
latchi ng the TMS0 signal inside the state-machine con-
troller.
TRST0N—JTAG TAP Controller Reset: Negative
assertion. Test reset. If asserted low, resets the
JTAG 0 TAP cont roller. In an application environ men t,
this pin must be asserted prior to or concurrent with
RST N. This pin has an internal pull-up resistor.
8.8 JTAG1 Test Interface
The JTAG1 test interface has features that allow pro-
grams and data to be downloaded into CORE1 via five
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Ag ere Systems prov ides hard-
ware and software tools to interface to the on-chip HDS
via the JTAG port.
Note: JTAG1 provides all JTAG/
IEEE
1149.1 standard
test capabilities including boundary scan.
T D I1—J TAG Test Dat a Inp ut: Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO1—JT AG T est Data Output: Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS1—JTAG Test Mode Select: Mode control signal
that, combined with TCK1, controls the scan opera-
tions. T his pin has an internal pull-up resistor.
TCK1—JTAG Test Clock: Serial shi ft cl o ck. This sig-
nal clocks all data into the port through TDI1 and out of
the port through TDO 1. It also controls the port by
latchi ng the TMS1 signal inside the state-machine con-
troller.
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8 Signal Descriptions (continued)
8.8 JTAG1 Test Interface (continued)
TRST1N—JTAG TAP Controller Reset: Negative
assertion. Test re se t. If a sserte d l o w, TRST1N re se ts
the JTAG1 TAP controller. In an application environ-
ment, this pin must be asserted prior to or concurrent
with RSTN. This pin has an internal pull-up resistor.
8. 9 Po w e r and Gr ou n d
VDD1—Core Supply Voltage: Supply voltage for the
DSP16000 cores and all internal DSP16411 circuitry.
Required voltage level is 1.0 V nominal.
VDD2—I/O Supply Voltage: Supply voltage for the I/O
pins. Required voltage level is 3.3 V nominal.
VSS—Ground: Ground for core and I/O supplies.
VDD1A—Analog Supply Voltage: Supply voltage 1 for
the PLL circuitry. Required voltage level is 1.0 V nomi-
nal.
VSS1A— A nalog Ground : Ground 1 for analog supply.
VDD2A—Analog Supply Voltage: Supply voltage 2 for
the PLL circuitry. Required voltage level is 3.3 V nomi-
nal.
VSS2A— A nalog Ground : Ground 2 for analog supply.
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9 Device Characteristics
9.1 Ab s ol u te M ax im um Rat in gs
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Funct ional operation of the device is not impli ed at these or any other conditions in
excess of those given in the operational sections of the data sheet. Expo su re to absolute maximum ratings for
extended per iods c an adv erse ly affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 220 °C.
9.2 Handl ing Prec autions
Although electr ostatic discharge (ESD) protect ion circuitry has been design ed into this device, proper precautions
must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembl y, and test
operations. Agere employs bot h a human-bo dy model (HBM) and a charged-device m odel (CDM) qualification
requirem ent in or der to determin e ESD-s usce ptibilit y limits and protec tion design ev aluation. ESD volt age thresh-
olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC’s JESD22-A114
(HBM) and JESD22-C101 (CDM) standards.
9.3 Recommended Operating Conditions
Table 179. Absol ute Maximum Ratings
Parameter Min Max Unit
Voltage on VDD1 with Respect to VSS –0.3 TBD V
Voltage on VDD1A with Respect to VSS –0.3 TBD V
Voltage on VDD2 with Respect to VSS –0.3 4.0 V
Voltage on VDD2A with Respect to VSS –0.3 4.0 V
Voltage Range on Any Signal Pin†
† During a transition, the voltage on an input pin can be outside the range of this specification for a short time duration (less tha n or equal to 1. 0 ns ). See
Table 183 on page 267 for details.
VSS – 0.3 VDD2 + 0. 3 V
VSS + 4.0
Junction Temper ature (TJ) –40 TBD °C
Storage Temperat ure Range –40 150 °C
Table 180. Minimum ESD Voltage Thresholds
Device Minimum HBM Threshold Minimum CDM Threshold
DSP16411 2000 V 1000 V
Table 181. Recom mend ed Operati ng Conditions
Maximum
Internal Clock
(CLK) Frequency†
† The r a ti o of th e in struction cy cl e rate (f CLK) to the input clock frequency (fCKI) is 1:1 without the PLL selected. With the PLL selected, the ratio of f CLK to
fCKI is the PLL output frequency (fSYN) and is determined by the programming of the PLL as defined in Section 4.18.1 on page 201. The ma ximum in p ut
clo ck (CKI input pin) frequen cy is def i ned in Ta bl e 188 on page 275.
Minimum
Internal Clock
(CLK) Period T
Junction
Temperature TJ (°C) Supply Voltage
VDD1, VDD1A ( V ) Supply Voltage
VDD2 ( V )
Min Max Min Max Min Max
240 MHz 4.2 ns –40 115 0.95 1.05 3.0 3.6
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9 Device Characteristics (continued)
9.3 Recommended Operating Conditions (continued)
9.3.1 Package The rm al Consider ations
The maximum allowable ambient temperature, TAMAX, is dependent upon the device power dissipation and is deter-
mined by the following equation:
TAMAX = TJMAX – PMAX x ΘJA
where PMAX is the maximum device power dissipat ion for the application, TJMAX is the maximum device junction
temperature specif ied in Table 182, and ΘJA is the maximum thermal resistance in still-air-ambient specified in
Table 182. See Section 10.3 on page 271 for information on determining the maximum device power diss ipation.
WARNING: Due to package thermal constraints, proper precautions in the user’ s application must be taken
to avoid exceeding the maximum junction temperature of 115 °C. Otherwise, the device perfor-
manc e and reliability is adversel y affected.
Table 182. Package Therma l Considerati on s
Device Package Param eter Value Unit
208 PBGA Maximum Junction Temperature (TJMAX) 115 °C
208 PBGA Maximum Therm al Resistanc e in St il l-Air-Am bient (ΘJA)27°C/W
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10 Electrical Characteristics and Requirements
Electrical characteristics refer to the behavior of the device under specified condition s. Elec trical requireme nts
refer to conditions imposed on the user for proper operation of the device. The parameters below are valid for the
conditions descr ibed in the previous section, Section 9.3 on page 265.
Note: The specifications in Table 183 are preliminary and subject to change.
Table 183. Electrical Characteristics and Requirements
Pins Parameter Symbol Condition Min Max Unit
All inputs except CKI Low-Input Vol tage VIL Steady State –0.3 0.3 x VDD2V
High-Input Voltage VIH 0.7 x VDD2VDD2 + 0.2 V
CKI inp ut Low -I nput Voltage VIL Steady State –0.3 0. 3 x VDD2V
High-Input Voltage VIH 2.8 VDD2 + 0.2 V
All inputs (undershoot or over-
shoot during a transiti on)†
† This specification allows for input signal voltages outside the range of the steady-state values specified in this table and outside the range of
the absolute maximum ratings (see Table 17 9 on page 265 ) for a short time duration (less than or equal to 1.0 ns).
Low-Input Vol tage VIL Time Duration
≤ 1.0 ns VSS – 1.0 — V
High-Input Voltage VIH —VDD2 + 1.0 V
All inputs except TMS0, TMS1,
TDI0, TDI1, TRST0N, TRST1N,
ED[31:0], EA[ 18:0], ESEG[3:0],
PD[15:0], and PADD[3:0]
Low-Input Leakage
Current IIL VIL =0V,
VDD2=3.6V –10 — µA
High-Input Leakage
Current IIH VIH =VDD2,
VDD2=3.6V —10µA
TMS0, TMS1, TDI0, TDI1,
TRST0N, and TRST1N Low-Input Leakage
Current IIL VIL =0V,
VDD2=3.6V –100 — µA
High-Input Leakage
Current IIH VIH =VDD2,
VDD2=3.6V —10µA
ED[31:0], EA[18 :0] , and
ESEG[3:0] with BHEDIS‡=1;
PD [15:0] and PADD[3:0] with
BHPDIS‡=1
‡ BHEDIS is ECON1[12] (Table 61 on page 112) and BHPDIS is ECON1[13]. If BHEDIS = 0 (default after reset), the bus hold circuits for
ED[31:0], EA[18:0], and ESEG[3:0] are enabled. If BHEDIS = 1, these bus hold circuits are disabled. If BHPDIS = 0 (default after reset), the
bus hold circuits for PD[15:0] and P ADD[3:0] are enabled. If BHPDIS = 1, these bus hold circuits are disabled. See Section 10.1 on page 268
for details.
Low-Input Leakage
Current IIL VIL =0V,
VDD2=3.6V –10 — µA
High-Input Leakage
Current IIH VIH =VDD2,
VDD2=3.6V —10µA
ED[31:0], EA[18 :0] , and
ESEG[3:0] with BHEDIS‡=0;
PD [15:0] and PADD[3:0] with
BHPDIS‡=0
Low-Input Bus Hold
Current§
§ T he inpu t bus hol d cur rent is the current supplied by an active bus ho ld circ uit to the bu s signal . To avoid unnecessa ry bus hold po wer co n-
s umption for active bus hold circuit s, an ex ter nal devi ce must drive the bus signal pins to valid logic levels (less than 0.8 V or greater than
2.0 V).
IKIL VIL = 0.8 V,
VDD2=3.0V –75 — µA
High-Input Bus Hold
Current§IKIH VIH =2.0V,
VDD2=3.0V 75 —µA
Low-Input Bus Hold
Toggl e Curr ent††
†† The input bus hold toggle current is the current that must be provided by an external device to change the state of a signal that is bein g held
by an active bus hold circuit.
IKTOGGLE VIL = 0 to VDD2,
VDD2=3.6V –225 225 µA
All outputs Low-Output Voltage VOL IOL = 4.0 mA — 0.4 V
IOL = 50 µA— 0.2V
High-Output Voltage VOH IOH =–4.0 mA 2.4 —V
IOH =–50 µAVDD2 – 0.2 — V
All 3-state outputs Low-Output 3-State
Current IOZL VIL =0V,
VDD2=3.6V –10 — µA
High-Output 3- State
Current IOZH VIH =VDD2,
VDD2=3.6V —10µA
All inputs Input Capacitance CI——10pF
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10 Electrical Characteristics and Requirements(continued)
10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs
Except for th e SEMI and PIU data and address bus pins, the DSP16411 does not include any internal circuitry to
maintain valid logic levels on input pins or on bidirectional pins that are not driv en. For correct device operation and
low static power dissipation, valid CMOS levels must be applied to these input and bidirectional pins. Failure to
ensure full C MO S levels (VIL or VIH) on pins that are not driven may result in high static power consumption and
possible device failure.
Any unused input pin must be pulled up to the I/O pin supply (VDD2) or pulled down to V SS according to the func-
tional requirements of the pin. The pin can be pulled up or down directly or through a 10 kΩ resistor. Any unused
bidirectional pin, statically configured as an input, should be pulled to VDD2 or VSS through a 10 k Ω resistor.
10.1.1 Maintena nce of Val id Lo gic Levels on the SE MI Interface
The SEMI data and address buses (ED[31:0], EA[18:0], and ESEG[3:0]) include internal bus hold circuits that are
enabled during reset and are enabled by default after reset. These bus hold circuits can be disabled by setting the
BHED IS fi e ld ( ECON1[12]—Table 61 on page 112). If the bus hold circuits are enabled, external pull -up/down
resistors are not needed on ED[31:0], EA[18:0], or ESEG[3:0].
If the SEMI interface is unused in the system, the EYMODE pin can be connected to VDD2 to force the inte rnal data
bus transceivers on ED[31: 0] to always be in the output mode. If the SEM I interface is used in the system, the
EYMODE pin mus t be connected to V SS.
Table 184 summarize s the effect of the EYMOD E pin and the BHEDI S field.
For pull-up or pull-down resistors, the value of the resistors sho uld be selected to avoid exceeding the dc voltage
and current characteristics of any device attached to the pin. The value of the pull-up resistors on ED[31:0]
depends on the programmed bus width, 32-bit or 16-bit, as determined by the ESIZE pin. It is recommended that
any 16-bit peripheral that is connected to the external memory interface of the DSP16411 use the upper 16 bits of
the data bus (ED[31:16]). This is r equired if the ext ernal memory interface is configur ed as a 16-bit interface. For
the following configurations, 10 kΩ pu ll-up or pull-dow n resistors can be used on the ext ernal data bus:
■32-bit SEMI with no 16-bit peripherals
■32-bit SEMI with 16-bit peripherals connected to ED[31:16]
■16-bit interface (ED[31:16] only)
Table 184. Effect of EYMODE Pin and BHEDIS Field
EYMODE
Pin BHEDIS†
Field
† B HEDIS is bit 12 of the ECON1 register (Table 61 on page 112).
Application/Description
0 0 Typical application for which the SEMI is being used with external memory devices. The bus hold cir-
cuit s are enabl ed, eliminating th e need for external pull-up or pul l-down resistors on ED[31:0],
EA[18:0], and ESEG[3 :0] . Depending on the applicat ion‡, pull- up resi stors may be needed on othe r
SEMI output pins.
‡If an external device asserts the EREQN pin to gain control of the SEMI interface, the SEMI 3-states ED[31:0], EA[18:0], ESEG[3:0], and
other SEMI output pins (see Table 53 o n page 103 for details). In this case, ED[31:0], EA[18:0], and ESEG[3:0] must be held at valid logic lev-
els, either by the bus hold circuits or by external pull-up/down resistors. The other 3-stated output pins are active-low and must be externally
pulled up to VDD2, their inact ive state. Specif ically, pull-up resistors ar e needed on ERAMN, EROMN, E IO N, and E RWN[1:0].
0 1 The SEMI is used wit h external me mory devices. Because the bus hold ci rcuits are disabled, exter nal
pull-up or pull-down resistors are needed for ED[31:0]. Depending on the application‡, pull- up or pul l-
down resistors may also be needed for EA[18:0], ESEG[3:0], and other SEMI output pins.
1 X The SEMI is not used in the system, i.e., there are no external devices attached to the SEMI pins.
External pull-up or pull-down resistors are not needed on any SEMI pins.
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10 Electrical Characteristics and Requirements(continued)
10.1 Maintenance of V alid Logic Levels for Bidirectional Signals and Unused Inputs (continued)
10.1.1 Maintena nce of Val id Lo gic Levels on the SEMI Interf ace (continued)
If the DSP16 411’s externa l memory interface is configured for 32-bit op eration with 16-bit peripherals on the lower
half of the external data bus (ED[15:0]), the external data bus (ED[31:0]) should have 2 kΩ pull-up or pull-down
resistors to meet the rise or fall time requiremen ts of th e DSP16411 1.
The different requirements for the s ize of the pull-up/pull-down resistors arise from the manner in which SEMI
treats 16-bit accesses if the inte rface is configured for 32-bit operation. If c onfigured as a 32-bit interface and a
16-bit read is performed to a dev ice on the upper half of the data bus, the SEMI latches the value on the upper
16 bits inter nally onto the lower 16 bits. This ensures that the lower half of the data bus sees valid logic levels both
in this case and also if the bus is operated as a 16-bit bus. Howeve r, if a 16-bit read operation is performed (on a
32-bit bus) to a 16-bit peripheral on the lower 16 bit s, no data is latched onto the upper 16 bits, resulting in the
upper half of th e bus floating. In this case, the smaller p ull-up resistors ensure the floating data bits transition to a
valid logic level fast enough to avoid metastability problems when t he inputs are latched by the SEMI.
10.1.2 Maintenance of Val id Lo gic Levels on the PIU Interface
The PIU data and address buses (PD[15:0] and PADD[3:0]) include internal bus hold circuits that are enabled dur-
ing reset and are enabled by default after reset. These bus hold circuits can be disabled by setting the BHPDIS
field (ECON1[13]—Table 61 on page 112). If the bus hold circuits are enabled, external pull-up/do wn resistors are
not needed on PD[15:0] and PADD[3:0]. If the bus hold circuits are disabled, external pull-up/down resistors are
needed on PD[15:0 ] and are also needed on PADD[3:0] if the external host is not driving PADD[3:0] continuously.
The value of the resistors should be selected to avoid exceeding the dc voltage and current charac teristics of any
device attached to the pin.
1. The 2 kΩ resistor value assumes a bus loading of 30 pF and also ensures IOL is not violated.
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10 Electrical Characteristics and Requirements(continued)
10.2 Analog Powe r Suppl y Decoupl ing
The PLL has two sets of analog power and ground pins (VDD1A, VDD2A, VSS1A, and VSS2A) that are separate
from t he digital power and ground pins (VDD1, VDD2, and VSS). To minimize ground bounce and s uppl y noise on
the analog supplies, addition al filtering should be provided for VDD1A and VDD2A as illustrated in Figure 62. For
each analog supply, a three-terminal EMC (electromagnetic coupling) filter is connected from the digital supply to
its corresponding analog supply. The EMC filter is TDK® part number ACF451832-332-T, or equivalent. In additi on,
two decoupling capacitors (10 µF tantalum in parallel with a 0.01 µF ceramic) ar e connec ted from each analog sup-
ply pin to its correspond ing ground pin. The EMC filter and capacitors should be placed as close to the VDD1A
(VDD2A) pin as possible. VSS1A and VSS2A are connected to the main ground plane, VSS. This recommendation is
subject to change and may nee d to be modified for specific applications dependi ng on the characteris tics of th e
supply noise.
Figu re 62 . An a lo g Su pply Dec oupling
VDD1A
10 µF
0.01 µF
VSS1A
VDD1
VDD1
EMC
FILTER
VDD2A
10 µF
0.01 µF
VSS2A
VDD2
VDD2
EMC
FILTER
DSP16411
VDD2VSSVDD1
SUPPLY SUPPLY
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10 Electrical Characteristics and Requirements(continued)
10.3 Power Diss ipation
The total device power dissipation is comprised of two components:
■The contribution from the VDD1 and VDD1A supplies, referred to as internal power dissipation.
■The contribution from the VDD2 sup ply, referred to as I/O power dissipation.
The next two sections specify power dissipation for each c omponent.
10.3.1 Internal Power Dissipation
Internal power dissipation is highly dependent on operating voltage, core program activity, internal peripheral activ-
ity, and CLK frequency. Table 185 lists the DSP 16411 typi cal internal power dissipation contribution for various
conditions. The following conditions are assumed for all cases:
■VDD1 and VDD1A are both 1.0 V.
■All memory accesses by the cores and the DMAU are to internal memory.
■SIU0 and SIU1 are operating at 30 MH z in loopback mode. An external device drives the SICK〈0—1〉 and
SOCK〈0—1〉 input pins at 30 MHz, and SIU〈0—1〉 ar e prog ra mmed to select pass ive input clocks a nd inte rn al
loopback (the ICKA field (SCON10[2]—Table 113 on page 191) and OCKA field (SCON10[6]) are cleared and
the SIOL B field (SCON10[8]) is set).
■The PLL is enabled and selected as the source of the internal clock, CLK. Table 185 specifies the internal power
dissipati on for a C LK frequency of 240 M Hz.
The internal power dissipation fo r the low- power standby and typical operating modes described in Table 185 is
representative of actual applications. The worst-case internal power dissipation occurs under an artificial condition
that is unlikely to occur for an extended period of time in an actual application. T his worst-case power should be
used for the calculation of maximum ambient operating temperature (TAMAX) defined in Section 9.3.1 on page 266.
This value should also be used for worst-case system power supply design for VDD1 and V DD1A.
Table 185. Typical Internal Power Dissipation at 1.0 V and 240 MHz
Condition Internal P ower Dissipation (W)
at CLK = 240 MHz
Type Core Operation DMAU Activity
Low-power
Standby The AWAIT field (alf[15]) is set
in both cores. The DMAU is operating the
MMT4 channel to continuously
transfer data.
0.23
Typical Both cores repetitively execute
a 20-tap FIR
filter†.
† To optimi ze exe cution speed, the core s each execu te the in ner loop of the filter from cach e and per form a double-wo rd dat a access every cycle from
separate m odules of TPRAM .
0.69
Worst-case‡
‡ Thi s is an ar tific i al condit i on tha t is unlikely to occur for an ext ended period of tim e i n an actual appl i cation bec ause the cores are not perf orm i ng any
I/O servic i ng. In a n actual appli cation , the cor es perform I/ O servi ci ng that changes pr ogram f l ow and lower s th e power dissi pation.
Both cores execute worst-case
instructions with worst-case
data patterns.
The DMAU is operating all six
channels (SWT〈0—3〉 and
MMT〈4—5〉) to continuously
transfer data.
1.26
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10 Electrical Characteristics and Requirements(continued)
10.3 Power Diss ipation (continued)
10.3.2 I/O Power Dissipation
I/O power dissipation is highly dependent on operat ing voltage, I/O loading, and I/O signal frequency. I t can be
estimated as:
where CL is the load capacitance, VDD2 is the I/O supply voltage, and f is the frequency of output signal.
Table 186 lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical appli-
cation under specific conditions. The following conditions are assumed for all cases:
■VDD2 is 3.3 V.
■The load capacit ance for each output and I/O pin is 30 pF.
For applications with values of C L, VDD2, or f that differ from those assumed for Table 186, the above formula can
be used to adjust the I/O power dissipation values in the table.
Table 186. Typica l I/O Power Dissipation at 3.3 V and 240 MHz
Internal
Peripheral Pin(s) Type No. of
Pins Signal Frequency
(MHz) I /O P ower Di s s ip a tion (m W)
ECKO = 120 MHz
(CLK/2) ECKO = 80 MHz
(CLK/3)
SEMI†
† It is assumed that the SEMI is configured for a 32-bit external data bus (the ESIZE pin is high), and that the contribution from the EACKN pin is negligi-
ble.
ED[31:0] I/O‡
‡ It i s assum ed tha t the pins s wi tch fr om inpu t t o outpu t a t a 50% duty cy cle.
32 ECKO/2 312 210
ERWN[1:0] O 2 ECKO/2 19 13
EA0 O 1 ECKO/4 10 6.8
EA[18:1] O 18 ECKO/2 350 238
ESEG[3:0] O 4 ECKO/2 82 50.2
EROMN O 1 ECKO/6 6.2 4.6
ERAMN O 1 ECKO/6 6.2 4.6
EION O 1 ECKO/6 6.2 4.6
ECKO O 1 ECKO 36.8 27.2
BIO〈0—1〉IO〈0—1〉BIT[6:0] O§
§ It i s assum ed tha t the cor respondi ng co re has c onf i gured these pins as output s.
14 1 4.6 4.6
PIU PD[15:0] I/O‡16 30 78.5 78.5
PINT O 1 1 0.33 0.33
PIBF O 1 30 9.8 9.8
POBE O 1 30 9.8 9.8
PRDY O 1 30 9.8 9.8
SIU〈0—1〉SICK〈0—1〉O2 8 5.2 5.2
SOCK〈0—1〉O2 8 5.2 5.2
SOD〈0—1〉O2 8 5.2 5.2
SIFS〈0—1〉O 2 0.03 0.02 0.02
SOFS〈0—1〉O 2 0.03 0.02 0.02
CLVDD22
×f×
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10 Electrical Characteristics and Requirements(continued)
10.3 Power Diss ipation (continued)
10.3.2 I/O Power Dissipation (continued)
Power dissipation due to the input buffers is highly dependent upon the input voltage level. At full CMOS levels,
essentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the
threshold of VDD2/2, high current can flow . See Section 10.1 on page 268 for more information.
W ARNING: The device needs to be clocked for at least seven CKI cycles during reset after powerup
(see Section 11.4 on page 278 for details). Improper reset may cause unpredictable
operation leading to device damag e.
10.4 Power Supply Sequencing Issues
The following section s describe the requirem ents for powering up and powering down the supplies .
Note: The exte rnal power sequence protection circuit d escribed in the
DSP16410B Digital Signal Processor
Data
Sheet (DS01-070W INF) is compatible with the DSP16411 and exceeds the requiremen ts specified below.
10.4.1 Powerup Sequence
During power up, the 1.0 V supplies (VDD1 and VDD1A) must not exceed the 3.3 V s upplies (VDD2 and VDD2A) by
more than 0.6 V.
10.4.2 Powerdown Sequence
During power down, the 1.0 V supplies (VDD1 and VDD1A) must not exceed the 3.3 V supplies (VDD2 and VDD2A)
by more than 0.6 V.
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11 Timing Characteristics and Requirements
Timing characteristics refer to the behavior of the device under spe cified conditions. Timing requi remen ts refer to
conditions impos ed on the user for proper operation of the device. All timing data is preliminary and subject to
change, and is valid for the following conditions:
TJ = –40 °C to +11 5 °C (See Section 9.3 on page 265.)
VDD2 = 3.3 V ± 0.3 V, VSS = 0 V (See Section 9.3 on page 265.)
Capacitance load on outputs (CL) = 30 pF, except for ECKO. Load on EC KO output is a 50 Ω transmiss ion line.
Note: Circuit design and printed circuit board (PCB) layout can have a signific ant impact on signal integrity and tim-
ing of hig h speed designs such as the DSP 16411 SEMI . For maximu m SEMI performance:
■Minimize load ing on the buses and EC KO outpu t clock.
■Keep PC B traces as short as possible.
■Add terminations where necessary to maintain signal integrity.
■Verify design perform ance through simula tion. An IBIS model for design simulation is available through
your Agere Systems field application engineer or sales representative.
Output chara cteristics can be derated as a function of load c apacitanc e (CL).
All outputs: 0.025 ns/pF ≤ dt/dCL ≤ 0 .07 ns/pF for 10 ≤ CL ≤ 100 pF.
For example, if the actual load capacitance on an output pin is 20 pF instead of 30 pF, the maximum derating for a
rising edge is (20 – 30) pF x 0.07 ns/pF = 0.7 ns less than the specified rise time or delay that includes a rise time.
The min imum derating for the same 20 pF load would be (20 – 30) pF x 0 .025 ns/pF = 0.25 ns.
Test conditions for inputs:
■Rise and fall times of 4 ns or less.
■Timing reference levels for CKI, R STN, TRST 0N, TRST1N, TCK0, and TCK1 are VIH and VIL.
■T i ming reference level for all other inputs is VM (see Table 187).
Test conditions for outputs (unless noted otherwise):
■Capac itance load on outputs except for ECKO (CL) = 30 pF.
■The load on EC KO is a 50 Ω transmission line.
■Timing reference level for all other outputs is VM (see Table 187).
■3-state delays measured to the high-impedance state of the output driver.
Unless otherwise noted, ECKO in the timing diagrams is the free-running CLK (ECON1[3:0] (Table 61 on
page 112) = 0x1).
Figure 63 . Referen ce Vo ltage Level for Timing Characteri sti cs and Requirements for Inputs and Outputs
Table 187. Referen ce Voltage Level for Timing Characteristi cs and Requiremen ts for Inputs and Outputs
Abbreviat ed Reference Param eter Value Unit
VMReference Voltage Level for Timing Charact eristi cs and
Requirements for Inputs and Outputs 1.5 V
V
M
–
5-8215 (F)
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11 Timing Characteristics and Requirements (continued)
11.1 Phase -Loc k Loop
Table 188 specifies the timing requirements and characteristics of t he phase-lock loop (PLL) clock synthesizer . See
Section 4.18, beginning on page 201, for g eneral information on the PLL. The PLL must be programm ed so that
the timing requirements in Table 188 are m et .
Table 188. PLL Requi remen ts
Symbol Parameter Min Max Unit
fSYN PLL Output Frequenc y Range 125 500 MHz
— Input Jitter at CKI — 200 ps-rms
fVCO VCO Output Frequency Range (V DD1A = 1.0 V) 500 1000 MHz
fPD Phase Detector Input Frequ ency 10 50 MHz
tLLock Time — 0.5 ms
fCKI CKI Frequency with PLL Enabled†
† T he PLL is di sabled (po wered down) if the PLLEN field (pllcon[1]—Table 124 on page 202) is clear ed, wh i ch is th e defau l t af t er res et. The PLL is
ena bl ed (po wered up) if the PLLEN fi el d (pllcon[1]) is set.
10 50 MHz
fCKI CKI Frequency with PLL Disabled†050 MHz
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11 Timing Characteristics and Requirements (continued)
11.2 Wake-Up Latency
Table 189 specifies the wake-up latency for the low-power standby mo de. The w ake-up latency is the delay
between exiting low-power standby mode and resumption of normal execution. See Section 4.20 on page 205 for
an explanation of low-power standby mode and wake-up latency.
Table 189. Wake-Up Latency
Condition Wake-Up Latency
PLL Deselected† During
Norma l Execut ion
† T he PLL is deselected if the PLLSEL field (pllcon[0]) is cleared, which is the default after reset. The PLL is selected if the PLLSEL field
(pllcon[0]) is set.
PLL Enabled‡ and Selected†
During Nor mal Executio n
Low-power Standby Mode
(AWAIT (alf[15]) = 1) PLL Disabled ‡
During Sta ndby
‡ T he PLL is disabled (power ed dow n) if the PLLEN field (pllcon[1]) is cleared, which is the default after reset. The PLL is enabled (powered
up ) if the PLLEN field (pllcon[1]) is set.
3T§
§ T = C LK clock cycle (fCLK = fCKI if PLL deselected; fCLK = fCKI x ((M + 2)/((D + 2) x f(OD))) if PLL enabled and selected).
3T§ + tL††
†† tL = PLL lock-in time (see Table 18 8 on page 2 75).
PLL Enabled‡
During Sta ndby 3T§3T§
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11 Timing Characteristics and Requirements (continued)
11.3 DSP Clock Generation
Figu re 64. I/ O Cl oc k Timi ng Diag ra m
Table 190. Timi ng Requiremen ts for Input Clock
Abbreviated Reference Parameter Min Max Unit
t1 Clock In Peri od (high to high) 20 —†
† The device is fully static. t1 is tested at 100 ns input clock. The memory hold time is tested at 0.1 s. If the PLL is selected, the maximum CKI
per io d is 100 ns .
ns
t2 Clock In Low Ti me (low to high) 10 —ns
t3 Clock In High Time (hi gh to low) 10 — ns
Table 191. Timi ng Characteristi cs for Output Clock
Abbreviated Reference Parameter Min Max Unit
t4 Clock Out High Delay (low to low) — 10 ns
t5 Clock Out Low Delay (h igh to high) — 10 ns
t6 Clock Out Peri od (high to high) T†
† T = internal clock period (CLK).
—ns
5-4009(F).i
t4
t6
t1
t2
CKI
t5
ECKO
t3
VIH–
VIL–
VOH–
VOL–
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11 Timing Characteristics and Requirements (continued)
11.4 Reset Circuit
The DSP16411 has three external reset pins: RSTN, TRST0N, T RST1N. At initial powerup or if any supply voltage
(VDD1, VDD1A, or VDD2) falls below VDD MIN1, a device reset is required and RSTN, TRST0N, TRS T1N must be
asserted simultaneously to init ialize the device.
Note: The TRST0N and TRST1N pin s must be asserted even if the JTAG controller is not used by the application.
† When both INT0 an d RSTN are asserted , all output and bidirectional pins (except TDO, which 3-st ates by JTAG control) are put in a
3-st ate condition. With RST N asserted and INT0 not asserted, EION, ERAMN, EROMN, EACKN, ERWN0, and ER WN1 output s are driven
high. EA[18:0], ESEG[3:0], and ECKO are driven low .
Figure 65. Powerup and Device Reset Timing Diagram
Note: The device needs to be clocked for at least seven CKI cycles during reset after powerup. Otherwise, high
cu rr e nts ma y flow.
1. Se e Tabl e 181 on page 265.
Table 192. Timing Requiremen ts for Poweru p and Device Reset
Abbreviated Reference Parameter Min Max Unit
t8 RSTN, TRST0N, and TRST1N Reset Pulse ( low t o high ) 7T†
† T = internal clock period (CKI).
—ns
t146 VDD1, VDD1A MIN to RSTN, TRST0N, and TRST1N Low 2T†—ns
t153 RSTN, TRST0N, and TRST1N Rise (low t o high) — 60 ns
Table 193. Timi ng Characteristi cs for Device Reset
Abbrev iated Reference Paramet er Min Max Unit
t10 RST N Disable Time (low to 3- state) — 50 ns
t11 RSTN Enable Time (high to valid) — 50 ns
VDD1,
VDD1A
RSTN,
TRST0N,
CKI
t11
VOH
VOL
VIH
VIL
t146
t10
t153
t8
VDD MIN
TRST1N
RAMP
OUTPUT
PINS†
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11 Timing Characteristics and Requirements (continued)
11.5 Re set Synchr onization
Note: See S ec tio n 11.9, be gi nning on pa ge 283 , for timing charac teris tics of the E ROMN pin.
Figure 66. Reset Synch ronization Timing
Table 194. Timing Requirements for Reset Synchronization Timing
Abbreviat ed Reference Parameter Min Max Unit
t126 Res et Setup (high t o high) 3 T/2 – 1†
† T = internal clock period (CKI).
ns
t24 CKI to Enable Vali d 4T + 0.5 4T + 4 ns
5-4011(F).i
CKI
EROMN
t126
t24
RSTN
(EXM = 1)
VIH–
VIL–
VIH–
VIL–
FETCH OF FIRST
I NSTRU CT ION BEG INS
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11 Timing Characteristics and Requirements (continued)
11.6 JTAG
Figure 67. JTAG I/O Timing Diagram
Table 195. Timing Requiremen ts for JTAG I/O
Abbreviated Reference Param eter Min Max Unit
t12 TCK Period (high to high) 50 —ns
t13 TCK High Time (high to low) 22.5 — ns
t14 TCK Low Time (low to high) 22.5 — ns
t155 TCK Rise Transition Tim e (l ow to hi gh) 0.6 — V/ns
t156 TCK Fall T ransition Time ( high to low) 0.6 — V/ns
t15 TMS Setup Time (valid to high) 7.5 — ns
t16 TMS Hold Time (high to invalid) 5 — ns
t17 TDI Setup Ti me (val id to high) 7.5 — ns
t18 TDI Hold Time (high to invalid) 5 — ns
Table 196. Timi ng Characteristi cs for JTAG I/O
Abbreviat ed Reference Parameter Min Max Unit
t19 TDO Delay (low to val id) — 15 ns
t20 TDO Hold (low to invalid) 0 — ns
5-4017(F).d
t12
t14t13
t15 t16
t17 t18
t19
t20
TCK 0, TCK1
TMS0, TMS1
TDI0, TDI1
TDO0, TD01
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
t155
t156
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11 Timing Characteristics and Requirements (continued)
11.7 Interrupt an d Trap
† ECKO is the fr ee-running CLK , i.e., ECON1[3:0] = 0x1.
‡ INT is one of INT[3:0] or TRAP.
Figu re 68 . I nt erru pt and Trap Timing Diagram
Table 197. Timi ng Requiremen ts for Interrupt and Trap
Abbreviated Reference Parameter M in Max Unit
t21 Inter rupt Setup (high to low) 8 —ns
t22 INT/TRAP Assertion Time (high to low) 2T†
† T = internal clock period (CLK).
—ns
INT‡
t21
t22
ECKO†
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11 Timing Characteristics and Requirements (continued)
11.8 Bit I/O
Figure 69. Write Outp uts Follow ed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics
Table 198. Timi ng Requiremen ts for BIO Input Read
Abbreviated Reference Parameter Min Max Unit
t27 IOBIT Input Setup Time (valid to low) 10 —ns
t28 IOBIT Input Hold Time (low to invalid) 0 — ns
Table 199. Timi ng Characteristi cs for BIO Output
Abbreviated Reference Parameter Min M ax Unit
t29 IOBIT O utput Valid Tim e (hi gh to valid) — 9 ns
t144 IOBIT Output Hold Time (high to invalid) 1 — ns
ECKO
IOBIT
(INPUT)
t28
t27
VALID OUTPUT
DATA INPUT
t29
t144
IOBIT
(OUTPUT)
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface
In the following timing diagrams and associate d tables:
■The designat ion
ENABLE
refers to one of the following pins: EROMN, ERAMN, or EION. The designation
ENABLES
refers to all of the following pins: ERO MN, ERAM N, and EION.
■The designat ion
ERWN
refers to:
— The ERWN0 pin if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic low.
— The ERWN1 and ERW N0 pins if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic
high.
— The ERWN1, ERWN0, and EA0 pins if the exte rnal data bus is configured as 32 bits, i.e., if the ESIZE pin is
logic high, and if the me mory acce ss is synchronous .
■The designat ion
EA
refers to:
—The ext ernal a ddres s pi ns EA[ 18:0 ] and the exte rnal segme nt address p ins ESEG [3:0] if th e exte rnal da ta bus
is configured as 16 bits, i.e., if the ESIZE pin is lo gic low.
—The ext ernal a ddres s pi ns EA[ 18:1 ] and the exte rnal segme nt address p ins ESEG [3:0] if th e exte rnal da ta bus
is configured as 32 bits, i.e., if the ESIZE pin is lo gic high.
■The designat ion
ED
re fe r s to:
— The external data pins ED[31:16] if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic
low.
— The external data pins ED[31:0] if the external data bus is co nfigured as 32 bits, i.e., if the ESIZE pin is logic
high.
■The designat ion
ATIME
refers to IATIME (ECON0[11:8]) for accesses to the EIO space, YATIME (ECON0[7:4])
for accesses to the ERAM space, or XATIME (ECON0[3:0]) for accesses to the EROM space.
† ECKO reflects CLK, i.e., ECON1[3:0] = 0x1.
Figure 70 . En ab le and Write Strobe Transition Timing
Table 200. Timing Characteristi cs for
ERWN
and Memory Enables
Abbreviated Reference Parameter Mi n Max Unit
t102 ECKO to
ENABLE
Active (high to low) 0.8 3 ns
t103 ECKO to
ENABLE
Inacti ve (high to high) 0.8 3 ns
t112 ECKO to
ERWN
Active (high to low) 0. 8 3 ns
t113 ECKO to
ERWN
Inacti ve (high to high) 0.8 3 ns
ENABLE
t102
ERWN
t113
t112
t103
ECKO†
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
11.9 .1 Asynchro no us Interface
† ECKO reflects CLK, i.e., ECON1[3:0] = 0x1.
Figure 71. Timing Diagram for EREQN and EACKN
Table 201. Timing Requiremen ts for EREQN
Abbreviated Reference Para meter Min Max Uni t
t122 EREQN Setup (low to high or high to high) 5 —ns
t129 EREQN Deassertion (high to low)
ATIME
MAX†
†
ATIME
MAX = the greatest of IATIME(ECON0[11:8] ), YATIME (ECON0[7:4]), and XA TIME (ECON0[3:0]}.
—ns
Table 202. Timi ng Characteristi cs for EACKN and SEMI Bus Disable
Abbreviated Reference Parameter Min Max Unit
t123 Memory Bus Disable Delay (high to 3-state) — 6 ns
t124 EACKN Assertion Delay† (high to low)
† If an y
ENABLE
is as serted (low) when EREQN is asserted ( low ), then the delay occurs fr om the tim e that
ENABLE
is deasserted (high).
(The SE M I does not ackno wle dge the requ est by asserting EACKN u ntil it has compl eted any pendin g memory accesses.)
4T‡—ns
t125 EACKN Deassertion Delay (hi gh to high) 4T‡
‡ T = internal clock period (CLK).
4T‡ + 3 ns
t127 Memor y Bus Enabl e Delay (high to active) 5 —ns
t128 EACKN Delay (high to low) — 3 ns
ECKO†
EREQN
ENABLES
EA
EACKN
t122
t123
t124
t122
t125
t129
t128
t127
ED
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
11.9 .1 Asynchro no us Interface (continued)
† ECKO reflects CLK, i.e., ECON1[3:0] = 0x1.
Figure 72. Asynch ron ous R ead Timing Diagram (RHOLD = 0 and RSETUP = 0)
Note: The exte rnal memory acce ss time from th e asserting of
ENABLE
can be calculated as t90 – (t91 + t92) .
Table 203. Timing Requiremen ts for Asynchron ou s Memo ry Read Operation s
Abbreviated Reference Paramet er Min Max Unit
t92 Read Data Setup (valid to
ENABLE
hi g h) 5 —ns
t93 Read Data Hold (
ENABLE
high to invalid) 0 — ns
Table 204. Timing Characteristi cs for Async hrono us Me mory Read Oper ations
Abbreviated Refe rence Parameter Mi n Max Unit
t90
ENABLE
Width (low to high) (T † ×
ATIME
) – 3
† T = internal clock period (CLK).
—ns
t91 Addre ss Dela y
(
ENABLE
low to valid) —2 – (T
† × RSETUP‡)
‡ RSETUP = ECON0[12].
ns
t95
ERWN
Activation
(
ENABLE
high to
ERWN
lo w) T† × (1 + RHOLD§ +
WSETUP††) – 3
§ RHOLD = ECON0[14].
†† WSE TU P = ECON0[13].
——
ENABLE
ED
ECKO†
EA
t91
READ ADDRESS
ATIME
= 3
t90
t92 t93
READ DATA
ERWN
t95
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
11.9 .1 Asynchro no us Interface (continued)
† ECKO reflects CLK, i.e., ECON1[3:0] = 0x1.
‡ The idle cycle is caused by t he read following the write.
Figure 73. As ynch ronou s Write Timing Diagram (WHO LD = 0, WSETUP = 0)
Table 205. Timing Characteristi cs for Async hrono us Me mory Write Operati on s
Abbreviated
Reference Parameter Min Max Unit
t90
ENABLE
Width (low to high) (T† ×
ATIME
) – 3
† T = internal clock period (CLK).
—ns
t96 Enable Delay (
ERWN
high to
ENABLE
low) T† × (1 + WHOLD‡ + RSETUP§) – 3
‡WHOLD = ECON0[15].
§ RSETUP = ECON0[12].
—ns
t97 Write Data Setup (valid to
ENABLE
high) (T† ×
ATIME
) – 3 — n s
t98 Write Data Deactivation (
ERWN
high to 3-s tate) — 3 ns
t99 Write Address Setup (valid to
ENABLE
low ) T† × (1 + WSETUP††) – 3
†† WSE TU P = ECON0[13].
—ns
t100 Write Data Activation (
ERWN
low to low-Z) T† – 2 — ns
t101 Address Ho ld T ime (
ENABLE
high to invalid) T† × (1 + WHOLD‡) – 3 — n s
t114 Write Data Hold Time (
ENABLE
high to invalid) T – 3 — ns
ECKO†
WRITE DATA READ DATA
t98
t100
ATIME
= 2
t90
t97
t96
WRITE ADDRESS READ ADDRESS
ENABLE
ED
ERWN
t99
t114
IDLE‡
t101
ATIME
= 2
EA
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
11.9.2 S ync h ronou s In te rfa ce
† ECKO reflects CLK/2, i.e., ECON1[3:0] = 0x0.
Figure 74. Syn chro no us Read Timing Diagram (Read -R ead-Write Sequenc e)
Table 206. Timing Requirements for Synchronous Read Operations
Abbreviated Reference Parameter Min Max Unit
t104 Read Data Setup (valid to high) 3.5 —ns
t105 Read Data Hold (high to invali d) 1 — ns
Table 207. Timing Characteristi cs for Synch ronou s Read Ope rations
Abbreviated Reference Parameter Min Max Unit
t102 ECKO to
ENABLE
Acti ve (high to low) 0.8 3 ns
t103 ECKO to
ENABLE
Inactive (hi gh to high ) 0.8 3 ns
t106 Addre ss Delay (high to valid) — 3.5 ns
t107 Addre ss Hold (high to i nvalid) 0.8 — ns
t108 Write Data Active (high to low-Z) T† – 3
† T = internal clock period (CLK).
—ns
ENABLE
ED
ECKO†
EA
READ DATA
ERWN
WRITE DATA
t102
t106
t103
t104
t107
t108
t105
READ ADDRESS WRITE ADDRESSREAD ADDRESS
READ DATA
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
11.9.2 S ync h ronou s In te rfa ce (continued)
† ECKO reflects CLK/2, i.e., ECON1[3:0] = 0x0.
Figure 75. Synch ronou s Write Timin g Diagram
Table 208. Timing Characteristi cs for Synch ronou s Write Operation s
Abbreviated Reference Paramete r Min Max Unit
t102 ECKO to
ENABLE
Active (h igh to low) 0.8 3 ns
t103 ECKO to
ENABLE
Ina ct iv e (hi g h to hi gh ) 0.8 3 ns
t106 Address Delay (h igh to valid) —3.5ns
t107 Address Hold (high to inva li d) 0.8 — ns
t109 Write Data Delay (high to valid) — 3.5 ns
t110 Write Data Hold (high to invalid) 0.8 — ns
t111 Write Data Deactivation Delay (high to 3-state) — 2.5 ns
t112 ECKO to
ERWN
Active (high to low) 0.8 3 ns
t113 ECKO to
ERWN
Ina ct iv e (hi g h to hi gh ) 0.8 3 ns
t109 t110
DATA
ENABLE
ED
EA
ERWN
t102 t103
t111
t107
t106
t112 t113
ECKO†
ADDRESS
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11 Timing Characteristics and Requirements (continued)
11.9 System and Extern al Memory Interface (continued)
1 1.9.3 ERDY Interface
†
ATIME
mus t be pr ogrammed as gr eater than or equal t o five CLK cycles. Otherwise, th e SEM I ignores the s tate of ERDY.
‡ T = internal clock period (CLK).
N
must be greater than or equal to one, i.e., ERDY must be hel d low for at least one CLK cycle af ter the
SEMI samples ERDY.
§ ECKO reflects CLK, i.e., ECON1[1:0] = 1.
Figure 76. ERDY Pin T iming Diagram
As indicated in the drawing, the SEMI:
■Samples th e state of ERDY at 4T prior to the end of the access (unstalled). (The end of the access (unstalled)
occurs at
ATIME
cycles after
ENABLE
goes low.)
■Ignores the state of ERDY before the ERDY sample point.
■Stalls the external memory access by
N
× T cycles, i.e ., by the num ber of cycl es th a t E R DY is held low following
the ERDY sample point.
Table 209. Timi ng Requiremen ts for ERDY Pin
Abbreviated Reference Parameter Min Max Uni t
t115 ERDY Setup To any ECKO (low t o high or high to high) 5 —ns
t121 ERDY Setup To ECKO at End of Unstalled Access (low to high) 4T + 5 — ns
ENABLE
ERDY
t115
4T‡
t115
N
× T‡
SEMI
SAMPLES
ERDY PIN
ECKO§
ATIME
†
END OF
ACCESS
(UNSTALLED)
N
× T‡
4T‡
END OF
ACCESS
(STALLED)
t121
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11.10 PIU
† PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e.,
PSTRN = PCSN |(PIDS ^ PODS).
‡ It is assumed that the PR DYMD pin is logic l ow, configur ing the PR DY pin as acti ve-low.
Figure 77. Host Data Write to PDI Timing Diagram
Table 210. Timing Requirements for PIU Data Write Operations
Abbreviated Reference Param eter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
† T is t he period of the int ern al clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡ Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
5 —ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t63 PD Setup Time§ (valid to high)
§ Tim e to the rising edge of PIDS, PO DS, or PCSN, whichev e r occu rs firs t.
6—ns
t64 PD Hold Time§ (high to inv a lid ) 5 —ns
t65 PSTRN Re quest Period (low to low) max ( 5T†, 30) —ns
t66 PRWN Setup Time‡ (low to low) 0 —ns
t67 PRWN Hold Time§ (high to high) 0 —ns
t74 PSTRN Ho ld (low t o high ) 1 — ns
Table 211. Timing Char acteristics for PIU Data Write Operati ons
Abbreviated Reference Parameter Mi n Max Unit
t68 PIBF Delay† (high to high)
† Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t69 PRDY Delay (low to valid) 1 7 ns
PSTRN
†
PADD[3:0]
PRWN
PD[15:0]
PIBF
PRDY
‡
t65
t60 t60
t61 t62
t74
t67
t64t63
t68
t69
t66
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11.10 PIU (continued)
† PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e.,
PSTRN = PCSN | (PIDS ^ PODS).
‡ It is assume d that the PRDYMD pin i s logic l ow, c onfiguri ng the PRDY pin as active -lo w.
Figure 78. Host Data Read from PDO Timing Diagra m
Table 212. Timing Requirements for PIU Data Read Operations
Abbreviat ed Reference Parameter Mi n Max Unit
t60 PSTRN Pulse Width (hi gh to low or low to high) max (2T†, 15)
† T is t he period of the int ern al clock (CLK).
—ns
t61 PADD Setup Time‡ (va lid to low)
‡ Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
5 —ns
t62 PADD Hold Ti me‡ (low to invalid) 5 —ns
t65 PSTRN Request Per iod (low to low) max ( 5T†, 30) —ns
t74 PSTRN Hold (low to high) 1 — ns
Table 213. Timi ng Characteristi cs for PIU Data Read Operations
Abbreviat ed Reference Parameter Min Max Unit
t69 PRDY Delay (low to valid) 1 7 ns
t70 POBE, PRDY Delays (valid to low) 0.5T – 1 0.5T + 2.5 ns
t71 PD Activ a tion Del a y † (low to lo w -Z )
† Delay from the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
18ns
t72 POBE Delay‡ (hig h to high) 1 12 ns
t73 PD Deactivat ion Delay‡ (high t o 3-state)
‡ Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
PSTRN†
PADD[3:0]
PD[15:0]
POBE
PRDY‡
t65
t60 t60
t61 t62
t73t71
t72t70
t74
t69
Advance Data Sheet
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292 A gere System s— P rop rietary Agere Systems Inc.
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11 Timing Characteristics and Requirements (continued)
11.10 PIU (continued)
† PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e.,
PSTRN = PCSN |(PIDS ^ PODS).
‡ It is assumed that the PR DYMD pin is logic l ow, configur ing the PR DY pin as acti ve-low.
Figure 79. Ho st Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram
Table 214. Timi ng Requiremen ts for PIU Register Write Oper ations
Abbreviated Reference Param eter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
† T is t he period of the int ern al clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡ Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
5—ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t63 PD Setup Time§ (valid to high)
§ Tim e to the rising edge of PIDS, PO DS, or PCSN, whichev e r occu rs firs t.
6—ns
t64 PD Hold Time§ (high to inv a lid ) 5 —ns
t65 PSTRN Re quest Period (low to low) max ( 5T†, 30) —ns
t66 PRWN Setup Time‡ (low to low) 0 —ns
t67 PRWN Hold Time§ (high to high) 0 —ns
t74 PSTRN Ho ld (low t o high ) 1 — ns
Table 215. Timing Characteristi cs for PIU Register Write Operations
Abbreviated Reference Parameter Mi n Max Unit
t68 PIBF Delay† (high to high)
† Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t69 PRDY Delay (low to valid) 1 7 ns
PSTRN†
PADD[3:0]
PRWN
PD[15:0]
PIBF
PRDY‡
t65
t60 t60
t61 t62
t74
t67
t64t63
t68
t69
t66
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11 Timing Characteristics and Requirements (continued)
11.10 PIU (continued)
† PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e.,
PSTRN = PCSN | (PIDS ^ PODS).
Figure 80. Host Register Read (PAH, PAL, PCON, or DSCRATCH) T iming Diagram
Table 216. Timi ng Requiremen ts for PIU Register Read Operation s
Abbreviated Reference Parameter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2 T†, 15)
† T is t he period of the int ern al clock (CLK).
—ns
t61 PADD Setu p Ti me‡ (valid to low)
‡ Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
5—ns
t62 PADD Hold T ime‡ (low to inva lid) 5 —ns
t65 PSTRN Request Perio d (l ow to lo w) max (5T†, 30) —ns
Table 217. Timi ng Characteristi cs for PIU Register Read Opera tions
Abbreviated Reference P aram eter Min Max Unit
t7 1 PD Activation De lay† (low to low-Z)
† Delay from the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
18ns
t73 PD Deactivati on Delay‡ (high to 3-state)
‡ Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t7 5 PD Delay† (low to valid) —16ns
t75
5-7853 (F)
PSTRN†
PADD[3:0]
PD[15:0]
t65
t60 t60
t61 t62
t73t71
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU
Note : It is assumed that the SIU is configured with ICKA(SCON10[2]) = 0 for passive mode input clock, ICKK(SCON10[3 ]) = 0 for no in ve rsio n
of SICK, IFSA(SCON10[0]) = 0 for passive m ode inpu t frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS,
IMSB(SCON0[2]) = 0 for LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay.
Figure 81. SIU Passive Frame and Channel Mode Input T iming Diagram
Table 218. Timi ng Requiremen ts for SIU Passive Frame Mo de Input
Abbreviated Reference Parame ter Min Max Unit
t30 SICK Bit Clock Period (high t o high ) 19.2 —ns
t31 SICK Bit Clock High T ime (high t o low) 9 — ns
t32 SICK Bit Clock Low Time (low to high) 9 — ns
t33 SIFS Hold Time (high to low or high to high) 9 — ns
t34 SIFS Setup Time (low to high or high to high) 9 — ns
t35 SID Setup T ime (valid to low) 0.5 — ns
t36 SID Hold Time (low to invalid) 8 — ns
Table 219. Timi ng Requiremen ts for SIU Passive Chann el Mode Input
Abbreviated Reference Parame ter Min Max Unit
t30 SICK Bit Clock Period (high t o high ) 19.2 — ns
t31 SICK Bit Clock High T ime (high t o low) 9 — ns
t32 SICK Bit Clock Low Time (low to high) 9 — ns
t33 SIFS Hold Time (high to low or high to high) 9 — ns
t34 SIFS Setup Time (low to high or high to high) 9 — ns
t35 SID Setup T ime (valid to low) 0.5 — ns
t36 SID Hold Time (low to invalid) 8 — ns
5-8033 (F)
t30
t31 t32
t34
SICK
SIFS
SID B0 B1 B2
t34 t33 t35
t36
t33
B0
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passi ve mod e outp ut cl ock, O CKK (SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for
no output frame sync delay.
Figure 82. SIU Passive Frame Mode Output Timing Diagram
Table 220. Timing Requiremen ts for SIU Passive Fram e Mode Ou tpu t
Abbreviat ed Reference Parameter Min Max Unit
t37 SOCK Bit Clock Period (high to high) 19.2 —ns
t38 SOCK Bit Clock High Time (high to low) 9 — ns
t39 SOCK Bit Clock Low Time (low to hi gh) 9 — ns
t40 SOFS Hold Time (high to low or high t o high) 9 — ns
t41 SOFS Setup Ti me (low to high or high to high) 9 — ns
Table 221. Timi ng Characteristi cs for SIU Passive Frame M ode Output
Abbreviated Reference Paramet er Mi n Max Unit
t42 SOD Delay (high to valid) 1 7.5 ns
t43 SOD Hold (high to invalid) 0 — ns
5-8034 (F)
t37
t38 t39
t42
SOCK
SOFS
SOD B0 B1
t43
B0
t40
t41
t40
t41
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passi ve mod e outp ut cl ock, O CKK (SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 0 for channel mode output, and OFSDLY[1:0](SCON2[9:8]) = 00
for no output frame sync delay.
Figure 83. SIU Passive Channel Mo de Ou tput Timing Diagram
Table 222. Timi ng Requiremen ts for SIU Passive Chann el Mode Output
Abbreviat ed Reference Parameter Min Max Unit
t37 SOCK Bit Clock Period (high to high) 19.2 —ns
t38 SOCK Bit Clock High Time (high to low) 9 — ns
t39 SOCK Bit Clock Low Time (low to hi gh) 9 — ns
t40 SOFS Hold Time (high to low or high t o high) 9 — ns
t41 SOFS Setup Ti me (low to high or high to high) 9 — ns
Table 223. Timi ng Characteristi cs for SIU Passive Channel Mode Output
Abbreviated Reference Paramet er Mi n Max Unit
t42 SOD Delay (high to valid) 1 7.5 ns
t43 SOD Hold (high to invalid) 0 — ns
t44 SOD Deactivati on Delay (high to 3-stat e) — 12 ns
5-8032 (F)
t37
t38 t39
t42
SOCK
SOFS
SOD B0 B1
t43
B0
t40
t41
t40
t41
t44
B1
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Figure 84. SCK External Clock Source Input Timing Diagram
Table 224. Timi ng Requiremen ts for SCK External Clock Source
Abbreviat ed Reference Paramet er Min Max Unit
t76 SCK Bit Clock Period (high to high) 25 —ns
t77 SCK Bit Clock High Time (high to low) 10 — ns
t78 SCK Bit Clock Low Ti me (low to high) 10 — ns
t76
t77 t78
SCK
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Note: It is assumed that the SIU is configured with ICKA(SCON10[2]) = 1 for active mode input clock, ICKK(SCON10[3]) = 0 for no inversion
of SICK, IFSA( SCON10[0]) = 1 for active mode input frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS, IMSB(SCON0[2]) = 0
for LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay.
Figure 85. SIU Active Frame and Ch annel Mod e Input Timing Diagra m
Table 225. Timi ng Requiremen ts for SIU Active Frame Mode Input
Abbreviated Reference Parameter M in Max Unit
t45 SICK Bit Clock Period (high t o high) 19.2†
† The active c lock source is programm ed as eit her the intern al clock CLK or the SC K pin, depending on the AGE XT field (SCON12[12]). The
period of SICK is dependent on the period of the active clock sou rce and the pr ogramming of the A GCKL IM[7:0] field (SCON11[7:0 ]). Th e
application must ensure that the period of SICK is at least 19.2 ns.
—ns
t49 SID Setup Time (valid to low) 5 — ns
t50 SID Hold Time (low to invalid) 8 — ns
Table 226. Timi ng Characteristi cs for SIU Active Frame Mode Input
Abbreviated Reference Parameter Min Max Unit
t46 SI CK Bit Clock High Tim e (high to low) TAGCKH†–2
†TAGCKH and TAGCKL are dependent on the progr amming of the AGCK LIM[7:0] f ield (SCON11[7:0]) and the peri od of the active clock source.
TCKAG is the period o f the ac tive c lock source. The active clock source is pr ogrammed as eit her the internal clock CLK or the SCK pi n,
depending on the AGEXT field (SCON12[12]).
TAGCKH†+2 ns
t47 SI C K Bit Clock Low T ime (l ow to high) TAGCKL†–2 TAGCKL†+2 ns
t48 SI FS Delay (high to high) TCKAG†–2 TCKAG†+2 ns
5-8029 (F)
t45
t46 t47
t48
SICK
SIFS
SID B0 B1 B2
t49
t50
B0
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Table 227. Timing Requirements for SIU Active Channel Mode Input
Abbreviat ed Reference Paramet er Min Max Unit
t45 SICK Bit Clock Period (high t o high) 19.2†
† The active c lock source is programm ed as eit her the intern al clock CLK or the SC K pin, depending on the AGE XT field (SCON12[12]). The
period of SICK is dependent on the period of the active clock source and the pro gramming of the AGC KLI M[7:0] field (SCON11[7:0]). Th e
application must ensure that the period of SICK is at least 19.2 ns.
—ns
t49 SID Setup T ime (valid to low) 5 — ns
t50 SID Hold Time (low to invalid) 8 — ns
Table 228. Timi ng Characteristi cs for SIU Active Channel Mode Input
Abbreviated Reference Parameter Min Max Unit
t46 SICK Bit Clock High Time (high to low) TAGCKH†–2
†TAGCKH and TAGCKL are dependent on the progr amming of the A GCK LIM[7:0] f ield (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. Th e ac t ive clock s our ce i s prog r am med as ei the r the in te r na l cloc k C LK or th e SC K pin , de pe nd-
ing on the AGEXT field (SCON12[12]).
TAGCKH†+2 ns
t47 SICK Bit Clock Low Tim e (l ow to hi gh) TAGCKL†–2 TAGCKL†+2 ns
t48 SIFS Delay (high to high) TCKAG†–2 TCKAG†+2 ns
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for
no output frame sync delay.
Fi gure 86. SI U Ac t ive Frame Mod e Output Timi ng Diagra m
Table 229. Timi ng Requiremen ts for SIU Active Frame Mode Ou tput
Abbreviated Reference Parameter Min Max Unit
t51 SOCK Bit Clock Period (high to high) 19.2†
† The ac tive cl ock source is programmed as ei ther the internal clock CLK or the SC K pin, depending on the AGEXT field (SCON12[12]). The
period of SOCK is depe ndent on the per iod of the active clock source and th e programming of the AGCK LIM[7 :0] field (SCON11[ 7:0 ]). Th e
application must ensure that the period of SOCK is at leas t 19.2 ns.
—ns
Table 230. Timi ng Characteristi cs for SIU Active Frame Mode Outpu t
Abbreviated Reference Parameter Min Max Unit
t52 SOCK Bit Clock High Time (high to low) TAGCKH†–2
†TAGCKH and TAGCKL are depen dent on the pr ogramming of the A GCKL IM[7:0] field (SCON11[7: 0]) and the p eriod of the ac tive clock source.
TCKAG is the period of the active clock s ource. The a c tive cl ock source is p rogrammed a s either the inter nal clock CLK or t he SCK pin,
dependin g on the AGEXT field (SCON12[12]).
TAGCKH†+2 ns
t53 SOCK Bit Clock Low Ti me (l ow to hi gh) T AGCKL†–2 TAGCKL†+2 ns
t54 SOFS Delay (high to hi gh) TCKAG†–2 TCKAG†+2 ns
t55 SOD Data Delay (high to valid) 0 5 ns
t56 SOD Data Hold (high to invalid) –3 — ns
5-8030 (F)
t51
t52 t53
t55
SOCK
SOFS
SOD B0 B1
t56
B0
t54
B2
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for
no output frame sync delay.
Figu re 8 7. SIU Acti ve C hannel Mo de Ou t put Timi ng Diagr a m
Table 231. Timing Requirements for SIU Active Channel Mode Output
Abbreviated Reference Par ameter Min Max Unit
t51 SOCK Bit Clock Period (high to hi gh) 19.2†
† The ac tive cl ock source is programmed as ei ther the internal clock CLK or the SC K pin, depending on the AGEXT field (SCON12[12]). The
period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0 ]). Th e
applicat ion must en sure th at the period of SOC K is at l east 19.2 ns.
—ns
Table 232. Timing Characteristics for SIU Active Channel Mode Output
Abbreviated
Reference Parameter Min Max Unit
t52 SOCK Bit Clock High T ime (high t o low) T AGCKH†–2
†TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the p eriod of the ac tive clock source.
TCKAG is the period of the active c lock source. The active clock sour ce is pro grammed as eith er the inter nal clock CLK or th e SCK pin,
dependin g on the AGEXT field (SCON12[12]).
TAGCKH†+2 ns
t53 SOCK Bit Clock Low Time (low to high) TAGCKL†–2 TAGCKL†+2 ns
t54 SOFS Delay (high to high) TCKAG†–2 TCKAG†+2 ns
t55 SOD Data Delay (high to valid) 0 5 ns
t56 SO D D at a Hold (h ig h to in v a lid ) –3 — ns
t57 SOD Deactivation Delay (high to 3-stat e) — 5 ns
5-8028 (F)
t51
t52 t53
t55
SOCK
SOFS
SOD B0 B1
t56
B0
t54
t57
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
† ICK is the internal active generated bit clock shown for reference purposes only.
Note: It is assumed that the SIU is configured with ICKA (SCON10[2]) = 1 for active mode input clock, I2XDLY (SCON1[11]) = 1 for extension
of active input bit clock, IFSA (SCON10[0]) = 1 and AGSYNC (SCON12[14]) = 1 to configure SIFS as an input and to synchronize the
active bit clocks and active frame syncs to SIFS, IFSK (SCON10[1]) = 1 for inversion of SIFS, IMSB (SCON0[2]) = 0 for LSB-first input,
IFSDLY[1:0] (SCON1[9 :8]) = 00 for no input frame sync delay, AGEXT (SCON12[12]) = 1 for SCK pin as active clock source, SCKK
(SCON12[13]) = 1 for invers ion of SCK, and AG CKLIM[ 7:0] (SCON11[7:0]) = 1 for an active clock divide ratio of 2.
Figure 88. ST-Bus 2x Input Timing Diagram
Table 233. ST-Bus 2x Input Timing Requirements
Abbreviated Reference Parameter Min M ax Unit
t80 SCK Clock Peri od (low to low) 60 —ns
t81 SCK Clock Low Ti me (l ow to hi gh) 30 — ns
t82 SCK Clock High T ime ( hig h to low) 30 — ns
t83 SIFS Hold (low to low or low to high) 30 — ns
t84 SIFS Setup (low to low) 20 — ns
t85 SID Setup (valid to high) 5 — ns
t86 SID Hold (high to valid) 20 — ns
t80
t81 t82
t84
SCK
SIFS
SID B0 B2
t83
t86
t83
B4
ICK
†
B
N – 1
t85
Advance Data Sheet
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11 Timing Characteristics and Requirements (continued)
11 .11 SIU (continued)
† OCK is the i nter nal act ive generated bit clock sho wn for refer ence purposes only.
Note : It is assumed that the SIU is configured w ith OCKA (SCON10[6]) = 1 for active mode output clock, IFSA(SCON10[0]) = 1 and AGSYNC
(SCON12[14]) = 1 to configure SIFS as an input and to synchronize the active bit clocks and active frame syncs to SIFS,
OFSA(SCON10[4]) = 1 for active output frame sync, IFSK(SCON10[1]) = 1 for inversion of SIFS, OMSB(SCON0[10]) = 0 for LSB-first
input, OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay, AGEXT (SCON12[ 12]) = 1 for SC K pi n as active clock source,
SCKK (SCON12[13]) = 1 for invers ion of SCK, and AG CKLIM[ 7:0] (SCON11[7:0]) = 1 for an active clock divide ratio of 2.
Figure 89. ST-Bus 2x Output Timing Diagram
Table 234. ST-B us 2x Output Timing Requirements
Abbreviated Reference Parameter Mi n Max Unit
t80 SCK Clock Per iod (low to low) 60 —ns
t81 SCK Clock Low Ti m e (l ow to hi gh) 30 — ns
t82 SCK Clock High Ti me (hi gh to l ow) 30 — ns
t83 SIFS Hold (low to low or low to high) 30 — ns
t84 SIFS Setup (low to low) 20 — ns
Table 235. ST-B us 2x Output Timing Characteristics
Abbreviated Reference Parameter Mi n Max Unit
t89 SOD Delay (low to val id) 1 25 ns
t58 SOD Hold (high to invalid) 0 — ns
t83
t80
t81 t82
t84
SCK
SIFS
SOD B0 B2
t89
t58
t83
B4
OCK
†
B
N – 1
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
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any instructions
12 Appendix—Naming Inconsistencies
Table 236 lists the inconsistencies for pin names between this docum ent and the
LUxWORKS
debugger.
Table 237 lists the inconsistencies for register names between this document and the
LUxWORKS
debugger.
Table 236. Pin Name Inconsistenc ies
Data Sheet Debugger
PRDY PREADY
PRDYMD PREADYMD
ERDY EREADY
Table 237. Register Name Incon sistencies
Data Sheet Debugger
ECON0 ECN0
ECON1 ECN1
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April 2002 DSP16411 Digital Signal Processor
Agere Systems Inc. A gere S ystems—Prop rietary 305
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13 Outline Diagram—208-Ball PBGA
All dimensions are in millimeters.
5-7809 (F).b
0.80 ± 0.05
SEATING PLANE
SOLDER BALL
0.50 ± 0.1 0 0.20
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
15 SPACES @ 1.00 = 15.00
A1 B ALL
CORNER
15 SPACES
@ 1 .00 = 15 .00
17.00 ± 0.20
17.00 ± 0.20
15.00 + 0.70
– 0.05
+ 0.70
– 0.05
A1 BALL
IDENTI FIER ZO NE
1.56
0.61 ± 0.06 1.91 ± 0.2 1
2 3 4 6 7 8 9 10 11 12 13 14 15 1615
1.00
0.63 + 0.07
– 0.13
15.00
Advance Data Sheet
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14 Index
Symbols
– 218
–– 218
& 218
( ) 218
* 218
**2 218
+ 218
++ 218
: 218
<< 218
<<< 218
>> 218
>>> 218
[ ] 14
^ 218
_ (underscore) 218
{ } 218
| (pipe) 218
~ 218
± 218
〈 〉 218
218
A
absolute value (see function, abs)
ACS 19
ALU/ACS 223
arithmetic unit control registers (see register, auc0; reg-
ister, auc1)
auc0 (see register, auc0)
auc1 (see register, auc1)
B
BMU 223
boot pr ogram 23
busXAB 38
XDB 38
YAB 38
YDB 38
ZEAB 38
ZEDB 38
ZIAB 38
ZIDB 38
C
cache 210
instruction 19
circular buffers 20
clock
bit 154, 159, 161
phase-lock loop (see clock, PLL)
PLL 200
clock synthesi zer (see clock, PLL)
code
boot 39
HDS 39
control block 19
control registers (see registers, control)
counters 20
D
DAU 19, 20
DMAU channel
bypass 86, 135
DMAU channels
MMT 64, 86, 90
mem ory-map ped registers 91
SWT 64, 83, 84, 87, 154
mem ory-map ped registers 88
E
exponent computation 225
F
flagALLF 50, 52, 226
ALLT 50, 52, 226
LOCK 226
MGIBE 47, 48, 226
MGOBF 47, 48, 226
SOMEF 50, 52, 226
SOMET 50, 52, 226
flags
cond itional instruction 226
PIUPIBF 136
POBE 136
function
cmp0 20, 225
cmp1 20, 225
cmp2 20, 225
min 225
functions
side effects 20
G
guard bits 229
H
h (see register, h)
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14 Index (continued)
H(continued)
holding register (see register, c2)
I
i (see register, i)
instruction
di 25, 30, 31
ei 25, 30, 31
ic all IM6 25, 34
ireturn 25, 30, 32
treturn 25, 32
instructi o n cache 19
instruction set 210
instructions
ALU g r oup 210
ALU/ACS 223
BMU 223
BMU group 210
cac he group 210
conditional 226
control group 210
data move and pointer arithme tic group 210
MAC 223
MAC group 210
not cachable 211
notation conve ntions 14, 218
F titles 218
lower-case 218
UPPER-CASE 218
special function group 210
interrupt
DMINT4 49
DMINT5 49
MGIBF 47, 48
PHINT 30, 153
PINT 30
priority
assigning 31
SIGINT 47
SIINT 160
software 34
SOINT 161
inte r ru pt mu lt iplexe r (IM U X ) 28
interrupts 25
hardware 27, 28
PIU 153
ireturn (see instruction, ireturn)
J
j (see register, j)
K
k (see register, k)
M
macro
SLEEP_ALF () 205
memory
addressing
register-indirect 20
CACHE1 39
EIO 39, 111
ERAM 39, 111
EROM 39, 111
IROM0 39, 208
IROM1 39, 208
shared local (SLM) 39, 43, 45
TPRAM0 39, 44
TPRAM1 39, 44
X- space 38
Y- space 38
Z- space 38
memory-to-memory channels (see DMAU channels,
MMT)
MGU0 46
MGU1 46
modes of operation
channel 154
frame 154
N
notation (see instructions not ation conv entions )
P
PC (see register, PC)
pi (see register, pi)
pin CKI 257
EA0 107, 258
EACKN 103, 260
ECKO 205, 257
EION 104, 124, 138, 259
ERAMN 104, 124, 138, 259
ERDY 103, 120, 259
EREQN 103, 259
EROMN 106, 108, 124, 138, 259
ERTYPE 102, 116, 124, 260
ESIZE 102, 107, 109, 124, 260
EXM 23, 102, 208, 260
PCSN 139, 140, 143, 145, 263
PIBF 139, 142, 148, 262
PIDS 139, 140, 143, 145, 263
PINT 30, 139, 142, 153, 262
POBE 139, 142, 143, 148, 262
Advance Data Sheet
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14 Index (continued)
P(continued)
pin (continued)
PODS 139, 140, 143, 145, 262
PRDY 139, 142, 143, 148, 262
PRDYMD 139, 142, 262
PRWN 139, 140, 145, 263
RSTN 23, 208, 257
SCK0 261
SCK1 261
SICK0 260
SICK1 261
SID0 260
SID1 261
SIFS0 260
SIFS1 261
SOCK 160
SOCK0 260
SOCK1 261
SOD0 260
SOD1 261
SOFS0 260
SOFS1 261
TCK0 263
TCK1 263, 264
TDI0 263
TDI1 263
TDO0 263
TDO1 263
TMS0 263
TMS1 263
TRAP 25, 34, 47, 257
TRST0N 23, 263
TRST1N 23, 264
pins 267
EA[18:0] 107, 124, 138
EA[18:1] 258
ED[31:0] 107, 124, 257
ERWN[1:0] 106, 108, 124, 258
ESEG[3:0] 39, 107, 108, 114, 124, 258
INT[3:0] 34, 257
IO0BIT[6:0] 50, 257
IO1BIT[6:0] 50, 257
PADD[3:0] 139, 141, 143, 145, 262
PD[15:0] 139, 141, 143, 145, 262
PIUaddress and data 141
enable and strobe 140
external interface 139
flags, interrupt, and ready 142
SCK[1:0] 156
SEMI 101
SICK[1:0] 156, 159, 161
SID[1:0] 156, 159, 168
SIFS[1:0] 156, 159, 162
SIU 156
SOCK[1:0] 156, 160, 161
SOD[1:0] 156, 160, 168
SOFS[1:0] 156, 160, 162
postincrem ent (see registers, postincreme nt)
powerup rese t 249
pr (see register, pr)
psw0 (see register, psw0)
psw1 (see register, psw1)
pt0 (see registers, pointer, coefficient (X space ,
(pt0—pt1)))
pt1 (see registers, pointer, coefficient (X space ,
(pt0—pt1)))
ptrap (see register, ptrap)
R
rb0 (see registers, circular buffer)
rb1 (see registers, circular buffer)
re0 (see registers, circular buffer)
re1 (see registers, circular buffer)
register
alf 51, 235
AWAIT field 205
auc0 20, 236
auc1 20, 237
c0 20
c1 20
c2 20
cbit 51, 52, 238
DATA[6:0]/PAT[6:0] field 50
MODE[6:0]/MASK[6:0] field 50
cloop 239
csave 239
cstate 239
CTL〈0—3〉 74, 83, 84
SIGCON[2:0] field 87
CTL〈4—5〉 76, 86
SIGCON[2:0] field 90
DADD〈0—3〉 83, 84
DADD〈0—5〉 77
DADD〈4—5〉 86
DBAS〈0—3〉 81, 83, 84
DCNT〈0—3〉 79, 83, 85
DCNT〈4—5〉 79, 86
DMAU
memory-mapped
status 69
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
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14 Index (continued)
R(continued)
register (continued)
DMCON0 71, 83, 85, 86
DRUN[1:0] field 87, 88
HPRIM field 93
MINT field 93
SRUN[1:0] fi eld 87
TRIGGER[5:4] field 94
TRIG GE R4 fi e ld 90
TRIG GE R5 fi e ld 90
XSIZE4 field 90
XSIZE5 field 90
DMCON1 72
PI UD IS fiel d 86
RESET[5:0] field 94
DSCRATCH 137, 145
DSTAT 69, 92
DTAT
ERR[5:0] field 94
ECON0 111
IATIME field 116, 120, 128
RHOLD field 116, 128
RSETUP field 116, 128
SLKA fields 128
WHOLD field 116, 128
WSETUP field 116, 128
XATIME fi e ld 116, 120, 128
YATIME fi e ld 116, 120, 128
ECON1 112
ECKO[1:0] field 105
ECKOB[1:0] and ECKOA[1:0] fields 126, 204,
205
EREADY field 120
ITYPE field 124, 126
WEROM field 39
YTYPE field 116, 124, 126
EXSEG0 114
EXSEG1 114
EYSEG0 115
EYSEG1 115
FSTAT 197
h 20
holding (see register, c2)
HSCRATCH 137
i 20
ICIX〈0—3〉 198
ID 57, 241
imux 25, 28, 240
XIOC[1:0 ] fiel d 49
inc0 31, 49, 241
inc1 31, 48, 49, 241
ins 32, 37, 242
PHINT interrupt condition field 208
interrupt return (see register, pi)
j 20
k 20
LIM〈0—3〉 80, 83, 85
LIM〈4—5〉 80, 86
mgi 46, 47, 242
mgo 46, 47, 48, 242
OCIX〈0—3〉 198, 198
PA 138
ADD[19:0] field 138
CMP[2:0] field 138
ESEG[3:0 ] field 138
PAH 138, 145
PAL 138, 145
PC 20, 227
PCON 136, 145
HINT field 30, 153, 209
PINT field 30, 153
PDI 137, 143, 145
PDO 137, 143
pi 20, 25
pid 209, 242
pllcon 200, 201, 202, 243
PLLEN field 203, 205
PLLSEL field 200, 205
plldly 200, 201, 202, 243
pllfrq 200, 201, 202, 243
pllfrq1 200, 201, 202, 243
pr 20
psw0 20, 244
psw1 20, 35, 245
IEN field 30
ptrap 20, 25
rb0 (see registers, circular buffer)
rb1 (see registers, circular buffer)
re0 (see registers, circular buffer)
re1 (see registers, circular buffer)
RI〈0—3〉 82, 85
SADD〈0—3〉 83, 84
SADD〈4—5〉 77, 86
SBAS〈0—3〉 81, 83, 84
sbit 50, 52, 246
DIREC[6:0] fi eld 50
VALUE[6:0] field 50
SCNT〈0—3〉 78, 83, 85
SCNT〈4—5〉 78, 86
SCON0 185
IFORMAT[1:0] field 160
IMSB field 159
ISIZE[1:0] field 159
OFORMAT[1:0] field 161
OMSB field 161
OSIZE field 161
Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
310 Agere System s—P roprietary Agere Systems Inc.
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14 Index (continued)
R(continued)
register (continued)
SCON1 186
I2XD L Y fie l d 162
IFLIM[6:0] field 168
IFSDL Y[1:0 ] fiel d 159, 162
SCON10 191
ICKA fi el d 161
ICKK fi el d 159, 161
IF SA fiel d 162
IF SK fiel d 159, 162
IINTSE L [1:0] fi e l d 160
OCKA field 161
OCKK field 160, 161
OFSA fi eld 162
OFSK fi eld 160, 162
OINTSEL[1:0] field 161
SIOLB field 168
SCON11 194
AGCKLIM[7: 0] field 162
SCON12 195
AGEXT field 162
AGFSLIM[10:0] field 162
AGRESET fie ld 162
AGSYNC field 162
SCON2 187
OFLIM[ 6:0] field 168
OFSDLY[1:0] field 160, 162
SCON3 188
ICKE fi el d 162
IF SE fiel d 162
OCKE field 162
OFSE fi eld 162
SCON4 189
SCON5 189
SCON6 190
SCON7 190
SCON8 190
SCON9 190
SIDR 87, 160, 196
signal 47, 47, 246
SODR 87, 161, 196
sp 20
STAT 197
IO F L OW fi eld 160
OUFLOW field 161
SI BV fl a g 159
SIDV flag 160
SODV flag 161
STR〈0—3〉 82, 85
subroutine return (see register, pr)
timer〈0, 1〉 53, 56, 205, 248
timer〈0, 1〉c 53, 55, 247
COUNT field 53
PRESCALE[3 :0 ] fiel d 53
PWR_DWN field 53
RELOAD field 53
trap return (see register, ptrap)
vbase 20, 32
vector base offset (see register, vbase)
Viterbi support wor d (see register, vsw)
vsw 20, 248
registers
arithmetic unit control
(See also register, auc0; register, auc1) 20
auxiliary 20
circular buffer 20
control 20
counter (See register, c0; register, c1; register, c2)
data 227
DMAU
memory-mapped 67
address 77
base address 81
chan nel control 73
destination counter 79
limit 80
master control 71
reindex 82
source count er 78
stride 82
PIUmemory-mapped 135
address 138
Data 137
scratch 137
pointer 227
coefficient (X space, (pt0—pt1)) 20
data (Y space, (r0—r7)) 20, 210
postincrement 20
(see also register, h; re gister, i; register, j; reg-
ister, k)
processor status word (see register, psw0; register,
psw1)
SEMI
memory-mapped
control 110
external segm ent 114
SIUmemory-mapped 184
status 227
reset
device 23
JTAG controller 24
pin 23
RSTN (see reset, device and r eset, pin)
14 Index (continued)
Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
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S
shuffling of accumulat ors (see operations, shuffling of
accumulators)
signal
PTRAP 47
single-cycle squaring (see squaring, single-cycle)
single-word transfer channels (see DMAU channe ls,
SWT)
SLM 100
squaring
single-cycle 20
status regist ers (see registers, status)
sync
frame 154, 161
T
TDM 154
TIMER0_0 53
TIMER0_1 53
TIMER1_0 53
TIMER1_1 53
traceback encoder 20
traps 25
treturn (see instruction, treturn)
TRST0N (see reset, device and reset, JTAG controller)
TRST1N (see reset, device and reset, JTAG controller)
V
vbase (see register, vbase)
vectors
accumulator 229
Viterbi
decoding 19, 20
side effects 19, 20
support word (see re gister, vsw)
vsw (s ee register, vsw)
X
XAAU 19, 20, 38
XAAU conte ntion 222
Y
YAAU 20, 38
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, the Agere logo,
LUxWORKS
,
and
TargetView
are trademarks of Agere Systems Inc.
Copyright © 2002 Agere Systems Inc.
All Rights Reserved
Ap ril 20 02
DS02-037WINF
For additio nal information, contac t your A ger e Systems Account Manager or the following:
INTERNET: http://www.agere.com
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Tel. (852 ) 3129- 2000, FAX (8 52) 3129- 2020
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IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
ZBT
and
Zero Bus Turnaround
are t rade marks of Integrated Device Tech nology, Inc., and the architecture is support ed by Micron Technology,
Inc., and Motorola, I nc.
3M
is a regi stered trademark of Minnesota Mining an d Manufac turing Company.
Intel
is a registered trademark of Intel Corporation.
Motorola
is a registered trademark of Motorola, Inc.
MITEL
is a reg istered trademark of Mi tel Cor por ation.
TDK is a re gistered trademark of TDK Electronics Co., L td. Cor poration
The DSP16411 is based on the DSP16410B and DSP1 6410CG devices, desc ribed in the
DSP16410B Digital Sig-
nal Processor
Data Sheet dated June 2001 (DS01-070WI NF) and in the
DSP16410CG Digital Signal Processor
Preliminary
Data Addendum dated Novem ber 2001 (DS0 2-001WINF). The following set of tables compare s the
DSP16411, DSP16410 B, and DSP16 410CG devices.
Note: The procedure for nesting interrupts described in Section 4.4.11 on page 36 of this data sheet is different
than that described in Section 4.4.11 on page 36 of the
DSP16410B Digital Signal Processor
Data Sheet
and in Section 5.4. 9 of the
DSP16000 Digi tal Signal Processor Core
Information Manual. This updated pro-
cedure applies to the DSP16410 family of devices and to the DSP16411.
Comparison of the DSP1641X Fami ly Devi ces
DSP16410B DSP16410CG DSP16411 Page(s)
The maximum internal clock
(CLK) fre quency is 185 MHz. The maximum internal clock
(CLK) frequency is 200 MHz. The m aximum int ernal clock (CLK) fre-
quency i s 240 MHz. 1, 265,
271—272
The nominal operating voltage
for t he VDD1 and VDD1A power
supplies is 1.8 V.
The nominal operating voltage
for t he VDD1 and VDD1A power
supplies is 1.575 V.
The nominal opera ti ng voltage for the
VDD1 and VDD1A power supplies is 1.0 V. 1, 264, 265,
271
The size of i nternal RAM is as
follows (194 Kwords total):
■96 Kwords TPRAM0
■96 Kwords TPRAM1
■2Kwords SLM
The size of interna l RAM is as
follows (194 Kwords total):
■96 Kwords TPRAM0
■96 Kwords TPRAM1
■2Kwords SLM
The size of intern al RAM is as f oll ows
(322 Kwords total):
■160 Kwords TPRAM0
■160 Kwords TPRAM1
■2Kwords SLM
1, 15, 17, 38,
40—42, 44
The boot ROM (IROM) is
located at address 0x20000. The boot ROM (I RO M) is
located at address 0x20000 . The boot ROM (IROM) is located at
address 0x30000. 40—41, 102,
208—209,
250, 260
The cache is l ocated at
address 0x1FFC0. The cache is l ocated at
address 0x1FFC0. The cache is located at address 0x3FFC0. 40—41
The package option s are a
208-ball PBGA a nd a 256-ball
EBGA.
The package optio ns are a
208-ball PBGA and a 2 56-bal l
EBGA.
The DSP16411 is of fer ed in a 208-ball
PBGA package. 1, 253, 266,
305
The PLL has a singl e power
supply (VDD1A/VSS1A).
The PLL output f requency is
control led by t he pllfrq re giste r.
The G3 and G4 balls on the
PBGA package are a ssigned to
VDD2 and VSS.
The PLL has a singl e power
supply (VDD1A/VSS1A).
The PLL output frequency is
controlled by the pllfrq r egist er.
The G3 and G4 balls on the
PBGA package are assigned to
VDD2 and VSS.
The PLL has a two power supplies
(VDD1A/VSS1A and VDD2A/VSS2A).
The PLL output frequency is controlled by
the pllfrq and pllfrq1 registers.
The G3 and G4 balls on the PBGA pack-
age are assigned to the new VDD2A and
VSS2A pins.
The timi ng requirem ents and char acteris-
tics for the PLL have cha nged.
201, 256, 264,
270
15, 200—203,
220, 228,230,
243, 250, 252
253, 255
275
The following is the contents of
the JTAG ID registers for each
core:
JTAG0: 0x2C81403B
JTAG1: 0x3C81403B
The foll owing is the content s of
the JTAG ID registers for each
core:
JTAG0: 0x4C81403B
JTAG1: 0x5C81403B
The foll owing is the contents of the JTAG
ID regi sters for each core :
JTAG0: 0x1C815321
JTAG1: 0x0C815321
57, 241
The ECKO pin of t he SEMI can
be configured as logic 0, CKI,
CLK, or CLK/2.
The ECKO pin of t he SEMI can
be configured as logic 0, CKI,
CLK, or CLK/2.
The ECKO pin of the SEMI can be config-
ured as logic 0, CKI, CLK, CLK/2, CLK/3,
or CLK/4. An additional field (ECKOB[1:0]
was added to the ECON1 register in t he
SEMI to select the additional options.
101, 104,
112—113,
124, 126,
131—134,
204, 205, 206,
257
- 2 -
The SEMI data and address
bus pins (ED[ 31:0], EA[18:0],
ESEG[3:0]) do not include
inter nal bus hold cir cuits.
The SEMI data and address
bus pins (ED[ 31:0], EA[18:0],
ESEG[3:0]) do not include
internal bus hold circuits.
The SEMI data and address bus pins
(ED[31: 0], EA[18:0], ESEG[3: 0]) inc lude
inter nal bus hold circuits that hol d the bus
pins at t heir previous level if they are not
drive n. A new field was added to the
ECON1 r egister (bit 12, BHEDIS) t o
enable/disabl e these bus hold circ uits,
which el iminate the need for exter nal pull-
up or pull -down resistors.
101, 106, 112,
256,
257—258,
267, 268
The PIU data and addr ess bus
pins (PD[15:0] and PADD[3: 0])
do not i nclude i nter nal bus h old
circuits.
The PIU data and addr ess bus
pins (PD[ 15:0] and PA DD[3:0])
do not i nclude inter nal bus hol d
circuits.
The PIU data and addr ess bus pin s
(PD[15: 0] and PADD[3:0]) include internal
bus hold ci rcuits that hold the bus pins at
their previous l evel if th ey are not dri ven. A
new field was added to the ECON1 regi ster
(bit 13, BHPDIS) to enable/disable these
bus hold ci rcuits, which eli m inate the need
for ext ernal pull-up or pul l-down resistors.
112, 139, 141,
256, 262, 267,
269
The processor type code,
found at IROM address
0x20FFE, is 0x00000003.
The processor type code,
found at I ROM addr ess
0x20FFE, is 0x00000004.
The processor type code, found at IROM
address 0x30FFE, is 0x00000005. 208
The maximu m operating junc-
tion temperature (TJMAX) is
120 °C.
The absolute maximu m junc-
tion temperature is 125 °C.
The maxim um ope rating junc-
tion t emp erature (TJMAX) is
120 °C.
The absolute maxim um junc-
tion t emp erature is 125 °C.
The maxim um operating junction tempera-
tu re (T JMAX) is 115 °C.
The absolute maximum junction tempera-
ture is TBD °C.
265, 266, 274
— — The elect ri cal character istics and require-
ments for the DSP16411 are di fferent than
the DSP16410 family.
267
— — The power dissipation values for the
DSP16411 are di ffer ent tha n the value s for
the DSP16410 family.
271—272
— — The power suppl y sequenci ng require-
ments described i n Section 10.4 are less
stri ngent th an the r equirements for the
DSP16410 family. The external power
sequence prot ection circuit r ecom m ended
in the DSP16410 documentation is com-
patib le wi th the DSP16411.
273
For the tim ing requirements
and character istics, the load
assumed for the ECKO pin is
30 pF.
For the timing requirements
and characteristics, the load
assume d for the ECKO pin is
30 pF.
For the tim ing requirement s and character-
istics, the load assumed for the ECKO pin
is a 5 0 Ω transmission line.
274
Compari son of SEMI Timing Requirements and Cha racteristics
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t102 0.5 4 0.5 4 0.8 3 ns 283, 287, 288
t103 0.5 4 0.5 4 0.8 3 ns 283, 287, 288
t104 4 — 3.75 — 3.5 — ns 287
t106 —2.5—3.9—3.5ns287, 288
t107 0.5 — 0.5 — 0.8 — ns 287, 288
t109 —2.5—4.3—3.5ns 288
t110 0.5 — 0.5 — 0.8 — ns 288
t112 0.5 4 0.5 4 0.8 3 ns 283, 288
Comparison of the DSP1641X Family Devices (continued)
DSP16410B DSP16410CG DSP16411 Page(s)
- 3 -
t113 0.5 4 0.5 4 0.8 3 ns 283, 288
Comparison of PIU Timing Characteristics
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t69 112112 1 7ns290, 291, 292
t70 T – 3 T T – 3 T 0.5T – 1 0.5T + 2.5 ns 291
t71 1 6 1 6 1 8 ns 291
Compari son of SIU Passive Frame Mode Inpu t Timing Requireme nts
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t30 25 — 25 — 19.2 — ns 294
t31 10 — 10 — 9 — ns 294
t32 10 — 10 — 9 — ns 294
t33 10 — 10 — 9 — ns 294
t34 10 — 10 — 9 — ns 294
t35 5 — 5 — 0.5 — ns 294
Compa riso n of SIU P assive Channe l Mode I npu t T i m ing Requ i re m e nts
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t30 61.035 — 61.035 — 19.2 — ns 294
t31 28 — 28 — 9 — ns 294
t32 28 — 28 — 9 — ns 294
t33 10 — 10 — 9 — ns 294
t34 10 — 10 — 9 — ns 294
t35 5 — 5 — 0.5 — ns 294
Comparison of SIU Passive Frame Mode Output Timing Requirements
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t37 25 — 25 — 19.2 — ns 295
t38 10 — 10 — 9 — ns 295
t39 10 — 10 — 9 — ns 295
t40 10 — 10 — 9 — ns 295
t41 10 — 10 — 9 — ns 295
t42 1 16 1 16 1 7.5 ns 295
t43 0 4 0 4 0 — ns 295
Compari son of SIU Passive Channel Mode Ou tput Timing Requireme nts
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t37 61.035 — 61.035 — 19.2 — ns 296
t38 28 — 28 — 9 — ns 296
t39 28 — 28 — 9 — ns 296
t40 10 — 10 — 9 — ns 296
t41 10 — 10 — 9 — ns 296
Compari son of SEMI Timing Requirements and Cha racteristics (continued)
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
- 4 -
t42 1 16 1 16 1 7.5 ns 296
t43 0 4 0 4 0 —ns 296
Compari son of SIU Active Frame Mode Input Timing Requirements and Characteristi cs
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t45 25 — 25 — 19.2 — ns 298
t49 9 — 9 — 5 — ns 298
t46 TAGCKH –3 TAGCKH +3 TAGCKH –3 TAGCKH +3 TAGCKH –2 TAGCKH +2 ns 298
t47 TAGCKL –3 TAGCKL +3 TAGCKL –3 TAGCKL +3 TAGCKL –2 TAGCKL +2 ns 298
t48 TCKAG –5 TCKAG +5 TCKAG –5 TCKAG +5 TCKAG –2 TCKAG +2 ns 298
Comparison of SIU Ac tive Channel Mode Input Timing Requiremen ts and Characteri stics
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t45 61.035 — 61.035 — 19.2 — ns 299
t49 9 — 9 — 5 — ns 299
t46 TAGCKH –3 TAGCKH +3 TAGCKH –3 TAGCKH +3 TAGCKH –2 TAGCKH +2 ns 299
t47 TAGCKL –3 TAGCKL +3 TAGCKL –3 TAGCKL +3 TAGCKL –2 TAGCKL +2 ns 299
t48 TCKAG –5 TCKAG +5 TCKAG –5 TCKAG +5 TCKAG –2 TCKAG +2 ns 299
Compar ison of SIU Active Frame Mode Output Timin g Requirem ents and Charac teristics
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t51 25 — 25 — 19.2 — ns 300
t52 TAGCKH –3 TAGCKH +3 TAGCKH –3 TAGCKH +3 TAGCKH –2 TAGCKH +2 ns 300
t53 TAGCKL –3 TAGCKL +3 TAGCKL –3 TAGCKL +3 TAGCKL –2 TAGCKL +2 ns 300
t54 TCKAG –5 TCKAG +5 TCKAG –5 TCKAG +5 TCKAG –2 TCKAG +2 ns 300
t550160160 5ns300
t56–35–35–3—ns300
Compari son of SIU Active Channel Mode Output Timing Requirements and Characteristi cs
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t51 61.035 — 61.035 — 19.2 — ns 301
t52 TAGCKH –3 TAGCKH +3 TAGCKH –3 TAGCKH +3 TAGCKH –2 TAGCKH +2 ns 301
t53 TAGCKL –3 TAGCKL +3 TAGCKL –3 TAGCKL +3 TAGCKL –2 TAGCKL +2 ns 301
t54 TCKAG –5 TCKAG +5 TCKAG –5 TCKAG +5 TCKAG –2 TCKAG +2 ns 301
t550160160 5ns301
t56–35–35–3—ns301
t57 — 15 — 15 — 5 ns 301
C om paris on of S T-Bus 2x Output Timi ng Cha ract eristi c s
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
t5804040—ns303
Compari son of SIU Passive Channe l Mode Outpu t Timing Requirements (continued)
Abbreviated
Reference DSP16410B DSP16410CG DSP16411 Unit Page(s)
Min Max Min Max Min Max
